JP2786665B2 - Charge transfer device - Google Patents

Description

The present invention relates to a charge transfer device, and more particularly, to a charge transfer device used for a low-voltage driven CCD image sensor and the like, and particularly relates to an output portion of the charge transfer device. Regarding the configuration.

(Prior Art) An embedded channel type CCD register is known as a typical charge transfer device used for a solid-state imaging device or the like. The power supply and drive voltage of such a charge transfer device are currently 12
V system is mainstream. However, due to demands for lower power consumption and lower cost, low voltage driving is required in the future, and it is expected that the power supply voltage will shift to a 5V system of 5V and a driving pulse of 0-5V.

However, when the voltage is reduced to 5V, the operating voltage margin of the CCD register is reduced.
The reset voltage of the output section becomes low, and the dynamic range of the output signal becomes small or reset becomes impossible.
There are two problems.

In the case of a two-phase drive CCD, the problem similar to that of the related art can be dealt with by controlling the potential step under the transfer electrode to be small in the manufacturing process.

On the other hand, there is known a method of solving the above problem by increasing the reset voltage.

7 to 10 explain the structure and operation for boosting the reset voltage in the conventional example.

FIG. 7 is a cross-sectional view showing a cross-sectional structure near an output section of the CCD register. In the figure, the CCD is of a buried channel type and adopts a two-phase drive structure using two-phase drive electrodes formed of polysilicon electrodes formed in two layers. An n-type buried channel region 2 is formed in a desired surface region of a p-type silicon substrate 1. In the buried channel region 2, an n ⁻ -type region 3 having a lower concentration than that of the channel region 2 is formed, and forms a potential barrier for preventing a backflow of charges in the transfer electrode.

An output gate to which a constant voltage OG is applied is formed at the last stage of the CCD register, and an n ⁺ -type floating diffusion region 4 is formed adjacent to the output gate. The floating diffusion region 4 accumulates the electric charge transferred from the CCD register in the capacitance of the floating diffusion region, receives the potential change by an output circuit 11 formed by a source follower circuit or the like, and outputs it. A reset gate 6 is provided adjacent to the floating diffusion region 4. When a reset pulse RS is applied to the reset gate 6, a predetermined reset voltage V _RD applied to the reset drain 5 is set in the floating diffusion region 4. Is done.

The reset drain 5 is connected to a reset voltage generation circuit 12 for supplying a reset voltage _VRD . This reset voltage generation circuit 12 is connected to a power supply voltage V _DD as described later.
And a reset voltage _VRD is generated.

FIG. 8 is a diagram showing a potential distribution of each part in FIG. The minimum value of the potential under the CCD registers 8 and 9 needs to be 3 V or more in order to prevent charges from being lost due to surface defects during transfer. In addition, in order to drive with a voltage of 5V, it is necessary to add a potential step in the electrode of 1 to 2V. As a result, the deeper potential of the transfer electrodes 8 and 9 becomes 4 to 5 V when the pulse is at a low level, and the potential of the output gate 7 requires 6 to 7 V. In such a state, the reset voltage V _RD
Is set to the power supply voltage V _DD (5 V), resetting becomes impossible, so that the reset voltage V _RD needs to be boosted.

FIG. 9 is a timing chart for operating the circuit of FIG. The first phase pulse phi ₁ and the reset pulse RS
With Outputs the output V _OUT as shown in FIG.
_sig is obtained.

FIG. 10 is a circuit diagram showing a configuration of a reset voltage generation circuit 12 for generating a boosted reset voltage _VRD .
First, a circuit 13 composed of a combination of a MOSFET and a capacitor applies a two-phase clock signal φ, φ to charge the power supply V _DD.
Generating a boosted voltage V ₀ by the by pumping successively deeper voltage. Then obtain the reset voltage V _RD low output impedance from the circuit 14 to the boosted voltage V ₀ to the power supply. Note that the current flowing through the circuit 14 is
Extracted by _DD .

(Problems to be Solved by the Invention) In such a conventional booster circuit, the frequency of the applied clock signal φ is , The minimum capacity of the applied clock signal cannot be reduced too much. That is, 1
Since the amount of current that can be extracted by one transfer is determined, if the clock frequency is reduced, the amount of signal current becomes larger than the amount of current that can be extracted, and the reset current changes.
Therefore, when the applied clock signals φ, φ are also used as the clock signals φ1, φ2 applied to the CCD register, the frequency is restricted to the lowest frequency. Therefore, there is a problem that the use range of a CCD linear image sensor or the like having a wide use frequency is limited by the restriction of the lowest frequency.

Further, when the applied clock φ is internally generated as a high-speed clock by a ring oscillator or the like, there is a possibility that the S / N ratio may be reduced due to noise wrapping around the output signal.

Furthermore, when the circuit 13 of the booster is formed on-chip, there is a problem that the chip area increases because the capacitance value needs to be sufficiently large.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and can obtain a boosted reset voltage by a simple method, and further, there is no limitation on the operating frequency and the circuit scale can be reduced. An object of the present invention is to provide a low-voltage power supply system charge transfer device.

[Configuration of the invention]

(Means for Solving the Problems) A charge transfer device according to the present invention comprises a CCD register, a floating diffusion region adjacent to an output stage of the CCD register via an output gate, and a first reset circuit provided in the floating diffusion region. An adjacent reset drain via a gate, one end connected to the reset drain, and a capacitance that boosts a reset voltage applied to the reset drain by applying a pulse voltage to the other end at a predetermined timing; A drain, which is adjacent to the reset drain via a second reset gate and which is held at a power supply voltage, and a pulse applied to the second reset gate are input, and a pulse having an arbitrary amplitude synchronized with the pulse is input. And a pulse generating circuit for outputting to the other end of the capacitance, and opening and closing the first reset gate at a predetermined timing. Accordingly, the potential of the floating diffusion region is set to be equal to the reset voltage.

The pulse generation circuit includes a series connection between a power supply and a ground.
Consisting of two diode-connected MOS transistors,
It is preferable that the connection midpoint is connected to the other end of the capacitance and is lowered to the ground potential via a switch controlled by a pulse applied to the second reset gate.

(Operation) In the present invention, in order to boost the reset voltage, the reset drain is set to the power supply voltage without using a high-speed clock signal, and then the floating state is set, and the voltage at one end of the capacitance connected to the reset drain is increased. This boosts the reset drain by capacitive coupling. And
The voltage applied to this reset drain is internally generated by two series-connected diode-connected MOS transistors based on a reset pulse applied to the gate between the drain adjacent to the reset drain. Therefore, it can be generated at an arbitrary voltage by adjusting the circuit constant. When boosting is performed by controlling a single switch by using the opening and closing of the reset gate, there is no need to generate a high-speed clock signal with the internal oscillation circuit, so the circuit configuration is simplified and the chip area is reduced. .

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a cross-sectional structure in the vicinity of an output portion of an example of a charge transfer device which is a premise of the present invention. .

FIG. 2 is a timing chart for explaining the operation of FIG.

This embodiment is different from the conventional one in structure.
A second reset gate 15 and a drain 16 connected to the power supply voltage V _DD are added to reset the reset drain 5 to the power supply voltage V _DD , and a reset drain (RD)
5 is connected to one end of the capacitance 17. Note that a pulse φ3 is applied to the other end of the capacitance 17 at a predetermined timing.

Next, the operation in the configuration of FIG. 1 will be described with reference to FIG. At the timing indicated by (1) in the figure, the gate
The pulse RS2 is applied to 15 to set the reset drain 5 to the power supply voltage _VDD .

The pulse φ3 applied to the capacitor 17 at the next timing
At a high level to boost the reset drain 5.

At the last timing, the reset pulse RS1 applied to the reset gate 6 is turned on / off and the floating diffusion region (J
F) 4 is reset to the potential of the reset drain 5.

At the subsequent timing, the drive pulse φ1 is set to low level, and signal charges are caused to flow from the CCD registers 7 and 8 into the floating diffusion region 4. Here, the final reset voltage of the floating diffusion region 4 slightly fluctuates depending on the voltage of the floating diffusion region 4 before resetting. However, if the size of the capacitor 17 is set to be larger than that of the floating diffusion region 4, , That variation can be ignored.

FIG. 3 is an explanatory view showing an embodiment of the present invention.
The figure is a timing chart showing the operation. FIG. 3 differs from FIG. 1 in that a voltage generating circuit 18 and a switch 19 are connected to one end of a capacitance 17. That is, the voltage generating circuit 18 has two MOS transistors each diode-connected between the power supply _VDD and the ground power supply, which are connected in series. Grounded. This switch is a MOS switch, and a pulse RS2 is applied to the gate thereof together with the second reset gate 15.

With such a configuration, the pulse φ3 is generated internally based on the pulse φ1, and the number of externally applied pulses is reduced.

That is, as shown in FIG. 4, when the reset pulse RS2 goes high at the first timing, the gate 15
Is turned on, and the reset drain 5 is reset to the power supply voltage _VDD . At the same time, the gate 19 conducts, and the pulse φ3 becomes low level.

Next, when the reset pulse R2 goes low, the gate
15 and 19 become non-conductive, and subsequently, the pulse φ3 goes high and the reset drain 5 is boosted.

At the last timing, the reset pulse RS1 is applied to the reset gate, and the floating diffusion region 4 is reset to the potential of the reset drain 5.

As described above, in this embodiment, the boosting is performed by using the opening and closing of the two series-connected transistors and the reset gate, and there is no need to generate a high-speed clock signal in the internal oscillation circuit. This simplifies the process, reduces the chip area, and eliminates the need for an external input for providing a pulse for charging the capacitor. Further, the voltage generation circuit can be shared with another output circuit or the like by using transistors of the same conductivity type.

In this embodiment, an arbitrary value can be obtained for the voltage of the pulse φ3 by appropriately selecting the circuit constant of the transistor of the voltage generating circuit 18, that is, the size, the material, and the like.

FIG. 5 shows another example related to the present invention. Here, the capacitance 20 is directly connected to the floating diffusion region 4 to boost the voltage.

Therefore, in this example, the reset drain 23 is adjacent to the floating diffusion region 4 via the gate 22, and the power supply voltage V _DD is connected to the reset drain 23. Further, a pulse φ4 is applied to the other end of the capacitance 20 via the gate 21 at a predetermined timing. Reset pulses RS4 and RS3 are applied to gates 21 and 22, respectively.

FIG. 6 is a timing chart for explaining the operation of FIG. Reset pulse at first timing
Set RS3 and RS4 to high level and set floating diffusion region 4 to power supply voltage.
One end of the capacitor 20 is set to the low level of the pulse φ4 at V _DD .

At the next timing, the reset pulse RS3 is set to the low level to make the floating diffusion region 4 floating, and at the timing, the pulse φ4 is set to the high level to boost the floating diffusion region 4.

At the last timing, the reset pulse RS4 is set to the low level to make the floating diffusion region 4 and the capacitance 20 floating.

Note that, in the example of FIG.
It is necessary to increase the capacitance and the capacitance of the floating diffusion region 4.

〔The invention's effect〕

As described above in detail based on the embodiments, according to the present invention, a capacitance is connected to the reset drain, and a pulse generated by a simple internal circuit is applied to the other end at a predetermined timing to directly apply a voltage. As in the conventional booster circuit, it is not necessary to apply a high-speed clock pulse from the outside, so that the operating frequency can be widened and the area efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional structural view showing an example on which the present invention is based, and FIG.
FIG. 3 is a timing chart for explaining the operation in FIG. 1, FIG. 3 is a sectional structural view showing an embodiment of the present invention, FIG. 4 is a timing chart for explaining the operation in FIG.
FIG. 5 is a sectional structural view showing an example related to the present invention, FIG. 6 is a timing chart for explaining the operation of the example of FIG. 5, and FIG. 7 is a sectional structure of an output section of a conventional charge transfer device. FIG. 8 is a diagram showing potential distribution of each part of the circuit of FIG. 7,
FIG. 9 is a timing chart for explaining the operation of FIG. 7, and FIG. 10 is a circuit diagram of a booster circuit used in a conventional charge transfer device. 1 ... p-type silicon substrate, 2 ... n-type buried channel region, 4 ... floating diffusion region, 5 ... reset drain,
6 ... Reset gate, 8-10 ... CCD register, 11 ...
... Output circuit, 12 ... Reset voltage generation circuit (boost circuit), 15 ... Second reset gate, 16 ... Drain, 17
... capacitance, 18 ... voltage generation circuit, 19 to 22 ... gate, 23 ... drain.

Claims (2)

(57) [Claims] 1. A CCD register, a floating diffusion region adjacent to an output stage of the CCD register via an output gate, a reset drain adjacent to the floating diffusion region via a first reset gate, and the reset drain One end is connected to the other end, and a capacitance that boosts a reset voltage applied to the reset drain by applying a pulse voltage to the other end at a predetermined timing, and is adjacent to the reset drain via a second reset gate. A pulse applied to the drain held at the power supply voltage and the second reset gate, and output a pulse having an arbitrary amplitude synchronized with the pulse to the other end of the capacitance. A pulse generating circuit, which opens and closes the first reset gate at a predetermined timing to reset the potential of the floating diffusion region to the reset level. Charge transfer device is characterized in that so as to set to be equal to Tsu G Voltage. 2. The pulse generating circuit comprises two diode-connected MOS transistors connected in series between a power supply and a ground, and a connection midpoint thereof is connected to the other end of the capacitance. 2. The charge transfer device according to claim 1, wherein the potential is lowered to a ground potential via a switch controlled by a pulse applied to the second reset gate.