JPS58111371A - Inputting method for charge transfer element - Google Patents
Inputting method for charge transfer elementInfo
- Publication number
- JPS58111371A JPS58111371A JP56209220A JP20922081A JPS58111371A JP S58111371 A JPS58111371 A JP S58111371A JP 56209220 A JP56209220 A JP 56209220A JP 20922081 A JP20922081 A JP 20922081A JP S58111371 A JPS58111371 A JP S58111371A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- charge transfer
- charges
- transfer element
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 241000272201 Columbiformes Species 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
- H01L29/76808—Input structures
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
本′発明は、Ｃ−ＭＯ８構造を持つ電荷移送素子におい
て、１段あた９１層類以上の・（イアスミ荷を１時、蓄
積する場合に好適なバイアス電荷入力方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a bias charge input method suitable for storing 91 or more layers of Iasumi charges per stage in a charge transfer element having a C-MO8 structure. Regarding.
従来の電荷移送素子、例えば２相駆動ＣＯＤの入力方法
では、１段あたＤ２１１類の電荷を蓄積する事は不可能
であった。４相駆動ＣＯＤにおいて、特殊な駆動を行な
えは可能でおる（ＴＶ学会、１９層０全国大会予稿集ｐ
２７〜）。With the input method of a conventional charge transfer element, for example, a two-phase drive COD, it is impossible to accumulate D211 type charges per stage. It is possible to perform special drives in 4-phase drive COD (TV Society, Proceedings of the 19th Layer 0 National Conference, p.
27~).
本発明の目的は、電荷移送素子において、ノ（イアスミ
荷を１段あたり１種類以上入力する方法を提供する事に
ある。An object of the present invention is to provide a method for inputting one or more types of insulator charges per stage in a charge transfer element.
従来、電荷移送素子は単一基板上に形成されておシ、バ
イアス電荷は入力段より注入していた。Conventionally, charge transfer devices have been formed on a single substrate, and bias charges have been injected from the input stage.
そのため、１段あたり１種のバイアス電荷しか蓄積でき
なかった。最近のプロセス技術の向上により、浅いウェ
ル内に電荷移送素子を形成する事が可能となった。その
結果、縦方向のバイポーラトランジスタ効果を利用して
、１段あた９１種以上のバイアス電荷を入力する拳が可
能となった。Therefore, only one type of bias charge could be accumulated per stage. Recent improvements in process technology have made it possible to form charge transport elements within shallow wells. As a result, it has become possible to input more than 91 types of bias charges per stage by utilizing the vertical bipolar transistor effect.
本発明の入力法について説明する。The input method of the present invention will be explained.
第１図はりｐツク、φ１、φ２で駆動する電荷移送素子
ＣＯＤの断面を示したものである。１はＮ形Ｂｉ基板、
２はＰ形ワエル層、３は２９層、４はゲート絶縁膜（Ｓ
ｉα１．５は蓄積電極（Ｐｏｌｙ＠８ｉ）、６は転送電
極（ｐｏｌｙ −Ｓｉ ）である。７は電荷の転送方向
を示す。このＣＯＤに電圧を印加し九時のφ１の蓄積ゲ
ート部、Ａ−Ａ’力方向電位分布を第２図に示す。１１
は蓄積ゲート領域、１２はゲート絶縁膜領域、１３はＰ
形りエル領域、１４はＮ形Ｓｉ基板領域である。今、Ｐ
形つェル電位ｖｗＮＬＸ、ｔ−０マとし蓄積ゲートに正
電圧φＩＭを印加し、基板に正電圧’Ｖ’５ｖｓｈを印
加すると、表面にポテンシャルの井戸ができる。この井
戸を利用して電荷を転送するものがＣＯＤである。この
時、表面からの空乏層幅Ｗｄ１５は【１）式％式％
Ｎム ：Ｐ形りエル層不純物濃度
ｇ３ｉ：３ｉの誘電率
φＳ ：フエルミ電圧
第３図は（１）式をグラフに示したものである。FIG. 1 shows a cross section of a charge transfer element COD driven by p, φ1, and φ2. 1 is an N-type Bi substrate,
2 is a P-type Wael layer, 3 is a 29 layer, and 4 is a gate insulating film (S
iα1.5 is a storage electrode (Poly@8i), and 6 is a transfer electrode (poly-Si). 7 indicates the direction of charge transfer. FIG. 2 shows the potential distribution in the A-A' force direction at the storage gate portion of φ1 at 9 o'clock when a voltage is applied to this COD. 11
is a storage gate region, 12 is a gate insulating film region, and 13 is a P
The shaped L region 14 is an N-type Si substrate region. Now, P
When a positive voltage φIM is applied to the storage gate, and a positive voltage 'V'5vsh is applied to the substrate, a potential well is created on the surface. A COD uses this well to transfer charges. At this time, the depletion layer width Wd15 from the surface is determined by the formula (1). It is something that
Ｎｍ＝１０”ｃｒｎ−烏、φＩＭ＝２０Ｖとすると、Ｗ
ｄは約５μｍである。この時、Ｐ形つェル層Ｏ深さｘｌ
を５μｍ以下とすると、ウェル層はすべて空乏化してし
まう。このような状態では、表面とＮ形Ｓｉ基板間にパ
ンチスルー電流が流れる。その結果、表面チャネル部に
電荷が注入され、電位はＶａｍｈとなる。本発明はこの
パンチスルー電流を利用して、基板側より電荷を注入す
る事である０次に実施例を用いて説明する。If Nm=10"crn-karasu and φIM=20V, W
d is approximately 5 μm. At this time, the P-type well layer O depth xl
If it is less than 5 μm, the well layer will be completely depleted. In such a state, a punch-through current flows between the surface and the N-type Si substrate. As a result, charges are injected into the surface channel portion, and the potential becomes Vamh. The present invention will be explained using a zero-order embodiment in which charge is injected from the substrate side using this punch-through current.
Ｗ４１図の２相駆動ＣＯＤにおいて、ｘ１＝４ｐｍＮム
＝ １０”ａｎ−”とし、第４図のクロックパルスを用
いてバイアス電荷を注入する。φＩＨ＝１５Ｖ、１６１
Ｍ＝１２Ｍ＝９Ｖ、＄１Ｌ＝＄２Ｌ＝ＯＶ、Ｖ−ｈ＝１
３■とする。入力期間１６時のポテンシャルを第５図の
点線で示す。Ｐ形９エル層１３は全て空乏化しているた
め、パンチスルー電流によシ、Ｎｓｍｂ１４から電荷が
注入され表面に斜線部のバイアス電荷１９が入力できる
。この時表面チャネル電位ＦｉＶ−ｈ電位となる。次に
転送期間１７に移ると第５図の実線のようなポテンシャ
ルとなり、Ｐ形つェル層の一部しか空乏化しなくなる。In the two-phase drive COD shown in FIG. W41, x1=4pmN=10"an-", and bias charges are injected using the clock pulse shown in FIG. φIH=15V, 161
M=12M=9V, $1L=$2L=OV, V-h=1
3■. The potential during the 16 o'clock input period is shown by the dotted line in FIG. Since the P-type 9L layer 13 is completely depleted, charges are injected from the Nsmb 14 by the punch-through current, and the bias charges 19 shown in the shaded area can be input to the surface. At this time, the surface channel potential becomes FiV-h potential. Next, in the transfer period 17, the potential becomes as shown by the solid line in FIG. 5, and only a portion of the P-type well layer becomes depleted.
そのた 。That's it.
め、表面チャネル部とＮ形基板とが電気的に分離される
。その後１８の期間ではφ１、φ２を用いて電荷を順次
転送する。Therefore, the surface channel portion and the N-type substrate are electrically isolated. After that, in the 18th period, charges are sequentially transferred using φ1 and φ2.
他の駆動方法として、第６図のようなりロックパルスを
用いると、各々の蓄積ゲー）Ｈｌ、Ｈ２にバイアス電荷
を１時的に蓄積する動作も可能である。As another driving method, by using a lock pulse as shown in FIG. 6, it is also possible to temporarily accumulate bias charges in each of the storage gates H1 and H2.
本発明の入力方法は電荷移送素子の１１類（例えは表面
形ＣＯＤ、埋め込み形ＣＯＤ％ＢＢＤ）に依らず適用で
きる。The input method of the present invention can be applied regardless of the type 11 type of charge transfer device (for example, surface type COD, buried type COD%BBD).
本発明によれば、電荷移送素子の段数によらず、一度に
バイアス電荷を蓄積ゲート下に入力する事が可能であり
、電荷移送素子機能が拡大できる。According to the present invention, it is possible to input bias charges under the storage gate at one time regardless of the number of stages of charge transfer elements, and the function of the charge transfer element can be expanded.
第１図Ｆｉ２相駆動ＣＯＤの断面図、第２図および第５
図ｔｉｃｃｎ内部のポテンシャル図、第３図は空乏層幅
の電圧依存性を示す図、第４図および第６図はパルスタ
イミングチャートである。
１・・・Ｎ形３ｉ基板、２・・・Ｐ形つェル鳩、３・・
・１０層、４・・・ゲート絶縁膜、５・・・蓄積ゲート
電極、６第 １ 口
第 ２Ｉ２１１
ｙｆＪ３ ｔ￥１
Ｍ４１￥ｌ
／４／７／８
聞 ５ＵｆＵ
！ｆＪ ６ 図
鴫１頁の続き
０発 明 者 青木正和
国分寺市東恋ケ窪１丁目２８０番
地株式会社日立製作所中央研究
所内
０発 明 者 今出宅哉
横浜市戸塚区吉田町２９２番地株
式会社日立製作所家電研究所内
０発 明 者 高橋健二
国分寺市東恋ケ窪１丁目２８０番
地株式会社日立製作所中央研究
所内
０発 明 者 秋山俊之
国分寺市東恋ケ窪１丁目２８０番
地株式会社日立製作所中央研究
所内
０発 明 者 長原脩策
国分寺市東恋ケ窪１丁目２８０番
地株式会社日立製作所中央研究
所内Figure 1: Cross-sectional view of Fi two-phase drive COD, Figures 2 and 5
ticcn, FIG. 3 is a diagram showing the voltage dependence of the depletion layer width, and FIGS. 4 and 6 are pulse timing charts. 1...N-type 3i board, 2...P-type swell pigeon, 3...
・10 layers, 4... Gate insulating film, 5... Storage gate electrode, 6 1st port 2I211 yfJ3 t￥1 M41￥l /4/7/8 5UfU! fJ 6 Illustration continued on page 10 Author Masakazu Aoki 1-280 Higashikoigakubo, Kokubunji City, Hitachi, Ltd. Central Research Laboratory Author: Takuya Imade Home Appliance Research, Hitachi, Ltd. 292 Yoshida-cho, Totsuka-ku, Yokohama City 0 within the facility Author: Kenji Takahashi, 1-280 Higashi-Koigakubo, Kokubunji City, Hitachi, Ltd. Central Research Laboratory, 0 author: Toshiyuki Akiyama, 1-280 Higashi-Koigakubo, Kokubunji City, Hitachi, Ltd., 0 publications Author: Shusaku Nagahara, Kokubunji City Hitachi, Ltd. Central Research Laboratory, 1-280 Higashi Koigakubo
Claims (1)
アス電荷を基板側よりウェルを介し、電荷移送素子内に
注入する事を特徴とする電荷移送素子の入力方法。1. An input method for a charge transfer element, which is characterized in that, in a charge transfer element formed in a well, bias charges are injected into the charge transfer element from the substrate side through the well.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56209220A JPS58111371A (en) | 1981-12-25 | 1981-12-25 | Inputting method for charge transfer element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56209220A JPS58111371A (en) | 1981-12-25 | 1981-12-25 | Inputting method for charge transfer element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58111371A true JPS58111371A (en) | 1983-07-02 |
Family
ID=16569330
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56209220A Pending JPS58111371A (en) | 1981-12-25 | 1981-12-25 | Inputting method for charge transfer element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58111371A (en) |
-
1981
- 1981-12-25 JP JP56209220A patent/JPS58111371A/en active Pending
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