JPS6238868B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge coupled device.
It concerns an input structure that produces complementary signals on two channels of a device, and in particular incorporates a transversal filter in such a device, thereby obviating the need for a combination of operational amplifiers. Regarding input structure.

In the July 1971 issue of IEEE Spectrum, pages 18-27, WS Boyle and GE Smith published ``Charge Coupled Devices - A New Approach to MIS Structures''.
-Coupled Device-A New Approach to MIS
In an article titled ``Device Structure'', he describes a new information processing structure, the charge-coupled device (CCD). This device accumulates a minority carrier charge in a potential well made on the surface of a semiconductor and transfers this charge along the surface by applying a bias voltage to a control electrode. move the potential well.

Various applications have been proposed for CCDs. International Conference on Applications of Charge-Coupled Devices
Conference on the Application of Charge−
"Multiple Filter Characteristics Using a Single CCD Structure" on pages 245-249 of the October issue of Coupled Devices.
a Single CCD Structure)”.
as a transverse filter, or ISSCC, as described in the article by Ibrahim et al.
“Dual differential analog CCD for time-divided cursive filters” on pages 152-153 of the February 1975 issue.
(A Dual Differential Analog CCD For Time
−Shared Recursive Filters)”
It can be used as a recursive filter as described in the article by Seale and MF Tompsett. One drawback of this type of conventional device is that two charge signals had to be subtracted at each delay stage to produce the positive and negative coefficients of the sampled signal. this is,
This is generally done using a differential amplifier. However, for this method to be successful, it is necessary to integrate a MOST (metal oxide silicon transistor) operational amplifier on the same chip as the CCD.

The present invention provides a unique input structure for supplying complementary charges to the two channels of a CCD, making it possible to weight the detected signals and to add them directly, thus making it possible to To provide an input structure that eliminates the need for a dynamic amplifier.

In accordance with the present invention, a multi-channel charge-coupled device includes a charge storage substrate, an insulating layer disposed on the substrate, and sequential transfer of mobile charges along the substrate in response to an applied clock voltage. A complementary input structure for a multi-channel charge coupled device is provided comprising a pair of channels each having a plurality of electrodes disposed on the insulator for controlling a charge coupled device. The input structure includes a common input electrode provided on the insulator at a location adjacent to the head of each channel to control a constant amount of charge entering the substrate from an adjacent charge source. have Further, the input structure is provided at the top of each channel adjacent to the common input electrode to transfer a selected proportion of the fixed amount of charge to one channel and transfer the remaining charge. control electrodes each adapted to be responsive to separate control signals for transfer to the other channel, such that the charge in the other channel is complementary to the charge in the one channel; It's starting to happen.

Further, in accordance with the invention, selected electrodes in each channel are divided by a gap extending along the length of the channel to divide the charge transferred on the underside into predetermined proportions. has been done. One part of each of the split electrodes is connected in common, so that the total charge under the common connection part of the split electrodes is transferred along both channels. and the relative division of each electrode in both channels.

An embodiment of the present invention will be described below with reference to the accompanying drawings.

The manufacture of the charge coupled devices described herein utilizes techniques well known in the semiconductor art. Therefore, it will not be necessary to describe in detail the individual steps of manufacturing this device. However, Canadian Patent No. 941072, issued January 29, 1974, to James J. White, describes one method for making a dual level polysilicon charge coupled device, which is the basic structure of the device described herein. It should also be understood that the shapes shown in the accompanying drawings are merely examples of the configuration of the present invention, and are not necessarily drawn to scale.

In the following detailed description and accompanying drawings, individual elements of the device are provided with basic reference numerals. When it is necessary to distinguish between elements that occur repeatedly in the same column, an additional reference character is added to the base number. Generally, the description refers only to the base number.

1 and 2, the two-phase charge-coupled device has a charge storage substrate 1 made of p-type silicon.
0, on which an insulating layer 11 made of silicon dioxide (SiO ₂ ) of various thicknesses is provided. On the insulating layer 11, elongated upper electrodes 12 and lower electrodes 13 made of polysilicon are arranged alternately in the lateral direction so that adjacent electrodes overlap each other, forming a row of electrodes. As will become clear later, the lower electrode 13 functions as an accumulation control electrode and the upper electrode 12 functions as a transfer gate in a well-known manner.

In this example, the lower electrode 13 is the electrode 13
A, 13B, 13C, 13D, 13E, 13J,
13K, 13L, 13M, 13R, 13V, 13
W, 13X, 13Y and 13Z, and the upper electrode 12 includes electrodes 12A, 12B, 12C, 12D,
12E, 12R, 12V, 12W, 12X, 12
Contains Y and 12Z.

As shown in FIGS. 1, 2 and 4, silicon dioxide insulating layer 11 is formed by gate oxide region 15 defined by channels 15A and 15B.
, and a bundle of charges covers the bottom of this region,
Under the control of clock voltages applied to electrodes 12 and 13, n-channels are transferred along the column.

The lower electrodes 13 are all arranged in the insulating layer 11 on the charge storage substrate 10 . In the gate oxide region 15, the lower electrode 13 and the charge storage substrate 1
The thickness of the insulating layer 11 between 0 and 0 is all the same,
For example, about 1100 Å. That is, the lower electrode 13
are all in the same plane. All upper electrodes 12 are arranged on the insulating layer 11. In the gate oxide region 15, the thickness of the insulating layer 11 between the upper electrode 11 and the charge storage substrate 10 is all the same, for example about 3000 Å. That is, upper electrode 1
2 are all in the same plane. As shown in FIG. 2, the lower electrodes 13 and the upper electrodes 12 are arranged alternately. For this reason, the insulating layer 11 between the electrodes (lower electrode 13 and upper electrode 12) and the substrate 10
The thickness becomes thicker and thinner alternately. The thicker parts around these electrodes are formed as field oxide regions 26 and have a sufficient thickness (approximately 1.2 μm).
, so that the portion of substrate 10 immediately below it will not invert in response to the application of a clock voltage to electrodes 12 and 13. Minority carrier charge is therefore only transported along the portion of substrate 10 adjacent gate oxide region 15.

At the top of channels 15A and 15B is an n ⁺ diffusion source 20 of mobile charge or carrier. This is followed by a transfer gate 12R and a first storage electrode 13R, common to both channels 15A and 15B. Immediately adjacent to this common electrode 13R is a control electrode 12A and 12V, respectively, in each channel 15A and 15B. These electrodes 12
R, 13R, 12A and 12V are channel 1
Unlike the other electrodes in 5A and 15B, they are controlled by separate clocks as described below.

Furthermore, every other storage electrode 13 is connected to channel 1.
A gap is formed along the length of 5A and 15B, and the two parts 13B and 13J, 1
It is divided into 3L, 13W, etc. The inner parts of the divided electrodes 13J, 13K, 13L
It can be seen that 13M and 13M are commonly connected. These divided electrodes are connected to channel 15A.
and a weighting factor for non-destructive detection of the magnitude of the analog charge transferred along 15B.

In FIGS. 1 and 2, the clock drives are designated by the reference characters φ ₁ , φ ₂ , φ _s , φ _s1 and φ _s2 . These clock drives have voltage waveforms as shown in FIG. Referring to these figures, at time t ₁ the clock drives φ ₁ and φ _s go high, and a mobile charge consisting of electrons is transferred from the charge source 20 to the lower side of the storage electrode 13R to which a constant reference voltage V _RR is applied. will be forwarded to. Reference voltage V _RR
is chosen to produce a charge Q _RR of a preselected magnitude on the underside of electrode 13R, which acts as a de facto charge source for the two channels 15A and 15B. At time t ₂ , φ _s becomes low, and φ _s1
becomes higher. This signal φ _s1 is the DC bias voltage V
_B and the alternating current signal _Vs , which comes from, for example, a transfer line (not shown). Since electrode 13A was already driven high by clock φ ₁ at time t ₁ , clock φ _s1
A signal under the control of transfers a preselected portion of the charge Q _Rs to the underside of storage electrode 13A.

At time _t3 , φ _s1 becomes low and φ _s2 becomes high. For this purpose, a sufficient voltage is applied to the transfer gate 12V, and the remaining part of the charge under the electrode 13R is transferred to the underside of the storage electrode 13V, which is already driven to a high state. Therefore, the charge Q _RR −Q _Rs accumulated under the electrode 13V has a complementary relationship with the charge accumulated under the electrode 13A. At time _t4 , clock _φ2 goes high, followed by clock _φ1 . For this purpose, the charge on the lower side of electrodes 13A and 13V is divided into electrodes 13B and 13B, as is well known.
Transferred to the lower side of J, 13L and 13W.

Since the magnitude of the voltage applied to each portion of the divided electrodes is the same, the charge is divided between each portion according to their relative lengths.

The relative magnitude of the total charge on the underside of electrodes 13J, 13L, 13K and 13M is determined by A. above.
The floating gate detection circuit 16 was tested using non-destructive testing techniques such as those described in the paper of Ibrahim et al.
monitored by.

In a typical application example of a CCD transverse filter, an AC signal V _s superimposed on a DC bias voltage V _B is applied to the gate electrode 12A via a clock φ _s1 , and is stored in advance under the storage electrode 13R. A previously selected portion Q _Rs of the current charge Q _RR is transferred to the lower side of the electrode 13A. Next, the complement of this charge Q _RR -Q _Rs is transferred to the lower side of the storage electrode 13V under the control of the clock φ _s2 . Both charges are then simultaneously transferred along channels 15A and 15B under the control of clocks _φ1 and _φ2 . The relative length of each divided electrode 13 determines the load factor here. The output of electrode 17 is obtained by repeatedly non-destructively sampling the charge under the various divided storage electrodes 13 and summing these outputs in circuit 16. This output is proportional to the magnitude of the charge transferred along both channels 15A and 15B and a weighting factor determined by the location of the electrode splits. channel 1
The complement of the charge transferred along 5A is channel 1
5B, the detected signals may be summed directly without the need for a differential amplifier. This creates a DC offset on the detected signal on the electrode 17, which is caused by the detection circuit 1.
It is easily removed within 6 seconds.

Floating gate detection circuits use semiconductor amplifiers, and these amplifiers are made using MOS (metal-oxide-silicon) technology, similar to how CCDs are made. The entire structure can also be fabricated using p-channel technology on an n-type silicon substrate.

[Brief explanation of the drawing]

FIG. 1 is a top view of a bi-channel charge-coupled device including an input structure according to the present invention. Second
The figure is a sectional view taken along the line - in FIG. 1.
FIG. 3 shows representative waveforms of various clock voltages applied to the elements shown in FIGS. 1 and 2. FIG.
FIG. 4 is a sectional view taken along the line - in FIG. 1. DESCRIPTION OF SYMBOLS 10...Substrate, 11...Insulating layer, 12...Transfer gate electrode, 13...Storage control electrode, 15...
Gate oxide region, 16... floating gate detection circuit, 20... charge source.

Claims (1)

[Scope of Claims] 1. A charge storage substrate; an insulating layer provided on the substrate; and controlled sequential transfer of mobile charges along its length in response to an applied clock voltage. a pair of channels, each having a plurality of electrodes provided on the insulating layer; and a channel adjacent to the head of each of the pair of channels, controlling the input of a certain amount of charge from an adjacent charge source. a common input electrode disposed in parallel to the common input electrode, each of the pair of channels being disposed in parallel with the common input electrode and each responsive to a separate control signal to select one of the predetermined amounts of charge; a control electrode for transferring an amount of charge to one channel and a remaining charge to the other channel, the at least one electrode of each of the pair of channels extending along the length of the channel; divided into two discontinuous portions by an extending gap, said two portions having a selected amount of charge or a remainder of said amount of charge transferred through each of said channels; is divided according to the ratio of the respective lengths of the two parts, one of each of the two parts being interconnected, whereby the bottom of said interconnected parts is characterized in that the total amount of charge transferred to the side is a function of the amount of charge transferred along each of the pair of channels and the ratio of the lengths of the two portions of each of the pair of channels. charge-coupled device.