JPH0123880B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge transfer circuit, and particularly to a technique suitable for use in a charge-coupled quantization circuit that quantizes an analog signal amount based on a charge transfer principle. Conventionally, as a circuit for quantizing an analog signal amount, a circuit that treats the analog signal amount as a charge amount, divides the charge amount into a desired unit amount, and performs quantization is often used. This is because by treating the amount of charge as an amount of charge, voltage noise can be prevented from being mixed in, and a high-speed processing circuit with a high S/N ratio (signal-to-noise ratio) can be obtained. FIG. 1a shows a cross-sectional structural diagram of a conventional charge transfer type quantization circuit.
1 is a p-type semiconductor board, 2 is a low concentration n ^- type impurity layer forming a buried channel, 3 is a p-type impurity layer for forming an asymmetric potential in the transfer channel and enabling two-phase drive, and 4 is a p ^- type impurity layer. MOS( M etal Oxide
5 is a charge injection barrier electrode, and 6 is a charge input transfer electrode, which is a barrier potential formed under the charge injection barrier electrode 5 by pushing up the potential formed under the same electrode. Beyond that, charge is input into the potential well below the storage electrode. 7 is a dividing electrode for dividing the analog signal charge stored in the charge storage well into unit amounts and pumping it to the transfer register;
8 receives the quantized signal charge flux from 7;
Transfer electrode for transferring to the left side toward the paper surface, 1
5 indicates an insulating film. That is, the charge input electrode 5,
The analog signal charge injected from the channel below the storage electrode 4 to the channel below the storage electrode 4 fills that channel by applying a high voltage to the divided electrode 7 having an asymmetric potential, and by applying a low voltage to the difference in the asymmetric potential. It is divided into corresponding unit charges and pumped out. This situation is shown in Figure 1 b-f.
This is specifically shown in the potential distribution diagram shown in . The broken line 10 shows the channel potential distribution under the divided electrode, 11 the analog signal charge, 12
denote the divided quantized signal charge fluxes, respectively. 1st
Figure g is a timing diagram of the applied pulses, where pulse φ ^* indicates the voltage pulse applied to the dividing electrode 7, pulse φ ₁ indicates the voltage pulse applied to the transfer electrode 8, and pulse φ ₂ indicates the voltage pulse applied to the transfer electrode 8.
It shows voltage pulses of opposite phases applied to two-phase drive electrodes that are adjacent on the left and have the same structure. b to f in FIG. 1 are t=t ₁ , t ₂ , and g in FIG. 1, respectively.
FIG. 7 is a diagram showing the potential distribution under each electrode formed at times corresponding to t ₃ , t ₄ , and t ₅ . By repeating the quantum operation of the follow signal in FIG. 1g, the quantized time-series signal is sequentially transferred to the left on the paper. These quantized signal sequences are outputted after being processed as necessary or directly through a well-known charge-voltage conversion circuit. As explained above, in the conventional example, it is possible to quantize analog signals, but when the amount of signals to be handled becomes large or high speed is required, the following drawbacks arise. That is, when quantizing a large amount of signal charge, the amount of charge stored in the charge storage section must be increased accordingly. Specifically, the area of the storage electrode 4 is increased to expand the storage region. Along with this, the distance from the quantization division electrode 7 to the farthest region of the storage electrode 4 increases. In the conventional example, since a constant voltage is applied to the storage electrode 4, the storage region is kept at a substantially constant potential, and therefore the signal charge flowing under the divided electrode 7 mainly moves as a diffusion current. do. In other words, if the travel time increases in proportion to the square of the distance to the divided electrode 7 and the amount of charge in the storage region decreases, the travel speed will fatally decrease, making high-speed and high-precision quantization impossible. It becomes possible. The present invention has been made in view of the above points, and includes at least one conductive electrode disposed on a first conductivity type semiconductor substrate with an insulating film interposed therebetween, and selectively disposed on the surface of the first conductivity type semiconductor substrate. a charge storage section formed, a charge input section for injecting signal charges into the charge storage section, and charges for dividing the injected signal charges into predetermined unit charge fluxes and converting them into a time-series quantized signal charge flux sequence. By including a dividing section and a bias means for forming a channel potential so that the signal charge injected into the charge storage section constantly moves from the charge input section toward the charge dividing section, it is possible to generate a large signal. It is an object of the present invention to provide a charge-coupled quantization circuit that is high-speed and has high performance with respect to the amount of charge. Hereinafter, the present invention will be described in detail based on examples with reference to the drawings. FIG. 2 shows a plan configuration diagram of the first embodiment of the present invention. The input barrier electrode 16 corresponds to the charge injection electrode 5 in the conventional example, and is followed by charge storage electrode groups 17 to 23 to which different voltages are applied, and divided electrodes 24 and 25 for quantization. Transfer pulse φ ₁ connects to transfer electrodes 26, 27, transfer pulse φ ₂
is applied to transfer electrodes 28 and 29, respectively. In this case, a two-phase transfer electrode is shown. Reference numeral 30 denotes a dividing resistor for dividing the voltage of the power supply 31, and in this case, an ion-implanted layer formed in the same chip and having a conductivity type opposite to that of the substrate is used as a resistive element. In the first embodiment of the present invention, different voltages divided by a dividing resistor 30 are applied to each of a plurality of stacked electrodes (7 electrodes in this case) using two-layer polysilicon. 19, 20, 21, 22, 23
A voltage that gradually increases from a low voltage is applied in the order of , forming a stepped potential in the channel of the opposing storage region, and analog signal charges injected into the storage region through the input barrier electrode as in the conventional example, Accumulation is performed from the channel below the storage electrode 23 that moves through the stepped potential and has the lowest potential. Next, in Figure 3a,
The operating principle will be explained by showing a cross-sectional structure diagram cut along X′.
Note that the same parts as in FIG. 2 will be described with the same reference numerals. In this embodiment, 34 is a p-type semiconductor substrate, 35 is an n-type buried channel layer 36 is a CCD (Charge C
The p ^- type low concentration impurity layers 32 and 33 provide the directionality of the potential necessary for two-phase driving of the oupled device.
A transfer electrode is shown for receiving the image from the image and transferring it to the left side of the page. In the first embodiment, signal charge accumulation, quantization, and transfer are all performed within the embedded channel 35. FIGS. 3b to 3g are channel potential distribution diagrams corresponding to each region of FIG. 3a, and are for explaining the operating principle of the present invention. Fig. 3b shows the state in which the analog signal charge flux is input to the storage region, 39 shows the signal charge, 37 shows the potential distribution of the storage region which is distributed stepwise when there is no signal charge, and 38 shows the division. potential under the electrode,
Reference numeral 40 indicates the potential under the transfer electrodes 26 and 27, respectively. FIG. 3h shows the pulse φ ^* applied to the divided electrodes 24, 25, the transfer pulse _φ1 applied to the transfer electrodes 26, 27, 32, the transfer electrodes 28, 29,
FIG. 3b is a timing diagram of the transfer pulse φ ₂ applied to the timing 33, and the potential distribution diagram formed at time t ₁ in the diagram corresponds to FIG. 3b. That is, in FIG. 3b, all analog signal charges 39 are held in the storage region. Next, at time _t2 , a high voltage is applied to the divided electrodes, the potential under the divided electrodes decreases as shown in FIG.
Flowing down to below 25. At t= _t3 , there is a transient state in which φ ^* again falls to a low voltage, leaving behind a charge flux 41 corresponding to the potential difference between the divided electrodes 24 and 25, and as the potential increases, the accumulation region returns again. causing reflux to. The charge flux 41 left under this time division electrode 25 becomes a quantized unit charge. t
At = _t4 , the first quantized charge flux is transferred to the two-phase drive charge transfer register and transfer begins. Quantization is performed by repeating similar operations, and as the quantization operation progresses, the signal charge held in the storage region decreases. In the present invention, since the potential distribution 37 in the storage region is formed in a stepwise manner, the center of gravity thereof moves toward the divided electrodes 24 and 25 as the charge decreases. For example, the last quantized charge is localized only under the storage electrode 23 adjacent to the divided electrode 24, and therefore, as shown in f, when the potential under the divided electrode falls, it instantly moves under the divided electrode and moves at high speed. quantization becomes possible. This is a major feature of the present invention. Figure 3g
is the last (nth) quantized unit load, and 43
represents the (n-1)th quantized charge flux. In this way, even if the analog signal charge amount decreases, a stable and high-speed quantization circuit can be realized. In theory, the total charge in the storage region is quantized, but in reality the transfer efficiency (transfer efficiency is
Not all charges are necessarily quantized, and a small amount of charge may remain in the storage region. However, the amount of such residual charges is generally very small compared to the amount of quantized signal charges, and virtually all charges are quantized. Therefore, in this application, even if there is some residual charge in the storage region after quantization, it is expressed that all signal charges have been quantized. In order to achieve high speed more effectively, in the first embodiment of the present invention, the storage region (channel region) 44 indicated by the broken line in FIG. The effective channel length is made as small as possible, and the signal charge density under the storage electrodes 21 to 23 increases, resulting in higher speed. In addition, as shown in FIG. 2, storage electrodes 17 to 23
The length in the direction of the divided electrodes 24 and 25 is shortened, and as mentioned above, this increases the signal charge density under the storage electrode in the direction of the divided electrodes 24 and 25, resulting in more stable and high-speed operation. Operation is possible. Next, a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 4a shows a cross-sectional structural diagram of a second embodiment of the present invention. Hereinafter, the same parts as in FIGS. 2 and 3 will be described with the same reference numerals. Storage electrodes 45 to 51 are provided on the semiconductor substrate 34 via an insulating film, and the buried channel layer 35 is connected to the storage electrodes 45, 4.
However, unlike the first embodiment, this region is a surface channel. That is, in the second embodiment, in forming the channel potential of the storage region in a stepped manner, the phenomenon is utilized that the buried channel and the surface channel have different potentials for the same electrode voltage, and the former is deeper. are doing.
This allows the number of voltages to be applied to each storage electrode to be reduced, making it possible to downsize the circuit. 53 is an equivalent circuit of a divided resistance element with reduced branches. In this way, a potential distribution equivalent to that of the first embodiment shown in FIG. 4b can be realized. Reference numeral 55 indicates a potential distribution when there is no charge, and 54 indicates an analog signal charge flux. FIG. 5 is a cross-sectional structural diagram of a third embodiment of the present invention, in which 61 to 67 are storage electrodes, in which a low concentration is placed in an n-type buried channel under an even-numbered electrode.
P ^- type impurities are ion-implanted, and even if the same voltage is applied to storage electrodes 62 and 63, 64 and 65, and 66 and 67, a stepped potential is formed. In other words, the same structure as the two-phase CCD structure is formed, and therefore the effective number of electrodes is halved. 56,5
7 and 58 are the p ^- type impurity implanted regions. Therefore, the divided resistive element 59 becomes very small, and the wiring on the chip can be simplified, making it more suitable for fine technology. In addition, in carrying out the present invention, various structures other than the above-mentioned structure can be considered. That is, any means that can form the channel potential of the storage region in a stepped manner may be used. In addition, in the example,
All explanations have been made considering electrons as signal charges, but of course holes may also be used, and the transfer means can be CCD, BBD ( Bucket Brigade Device ).
There are many other possibilities. Furthermore, the quantized time series output may be extracted externally as a time series voltage signal using well-known means, but in combination with a counter circuit, 2
It can also be output as digital output in decimal, octal, hexadecimal, etc. In the above embodiment, the accumulation channel potential is formed in a step-like manner, but the channel potential of the accumulation region for holding and accumulating the analog signal charge to be quantized is lowered from the signal charge input section to the dividing section. It is also possible to form it so that it has an inclination. The cross-sectional structural diagrams of the fourth embodiment in this case are shown in Fig. 6a, Fig. 7, and Fig. 8a, and the potential distribution diagrams are shown in Fig. 6b, Fig. 8b.
Shown below. Further, by combining the above embodiments, the channel potential can be made into a stepped or inclined shape. As described above, according to the present invention, the channel potential is formed such that the accumulated signal charge in the charge storage section always moves in the direction from the charge input section to the region close to the charge division section, so that a large It is possible to provide a charge-coupled quantization circuit with high speed and high performance even for signal charge amounts.

[Brief explanation of drawings]

FIG. 1a is a cross-sectional structural diagram of a conventional charge-coupled quantization circuit, and FIGS. 1b to 1f are potential distribution diagrams for explaining the operating principle of the conventional charge-coupled quantization circuit. g is a diagram showing timing pulses for explaining the potential distributions in FIGS. 1a to 1f, and FIG. 2 is a planar structural diagram of a charge-coupled quantization circuit for explaining the first embodiment of the present invention. , 3rd
Figure a is a cross-sectional structural diagram taken along the line X-X' in Figure 2, Figures 3 b to g are potential distribution diagrams for explaining the operating principle of the first embodiment of the present invention, and Figure 3
Figure h is a diagram showing the timing and pulses in the first embodiment of the present invention, Figure 4 a is a cross-sectional structural diagram showing the second embodiment of the present invention, and Figure 4 b is the potential of Figure 4 a. Distribution diagram, Figure 5 is a sectional structural diagram showing the third embodiment of the present invention, Figure 6a, Figure 7, Figure 8.
Figure a is a cross-sectional structural diagram showing a fourth embodiment of the present invention,
6b and 8b are potential distribution diagrams of FIGS. 6a, 7, and 8a. In the figure, 16...input barrier electrode, 17-23...charge storage electrode, 24, 25...divided electrode, 26-29,
32, 33... Transfer electrode, 34... P-type semiconductor substrate, 35... N-type buried channel layer, 36...
p ^- type low concentration impurity layer, 37...Channel potential of storage section, 38...Potential under divided electrode, 39...Analog signal charge flux, 40...Potential under signal electrode, 41...Quantization unit charge bundle.

Claims (1)

[Claims] 1. An electrode array including first and second electrodes formed on a charge storage portion of a semiconductor substrate with an insulating film interposed therebetween;
a charge dividing section provided adjacent to the first electrode and dividing the signal charge accumulated in the charge storage section into predetermined unit charge fluxes and converting the signal charge into a time-series quantized signal charge flux sequence; biasing means for applying a predetermined voltage to the charge storage section to form a potential that becomes deeper toward the charge splitting section, such that the area of the charge storage section corresponding to the first electrode is larger than the area of the charge storage section corresponding to the first electrode. A charge-coupled quantization circuit characterized in that the area is smaller than the area of a charge storage section corresponding to an electrode, and all signal charges accumulated in the charge storage section are quantized. 2. The charge-coupled quantization circuit according to claim 1, wherein the width of the charge storage section becomes shorter toward the charge division section. 3. The charge-coupled quantization circuit according to claim 1 or 2, wherein the length of the first electrode in the electrode column direction is shorter than the length of the second electrode.