JPS6167963A - Charge coupling element - Google Patents
Charge coupling elementInfo
- Publication number
- JPS6167963A JPS6167963A JP59190301A JP19030184A JPS6167963A JP S6167963 A JPS6167963 A JP S6167963A JP 59190301 A JP59190301 A JP 59190301A JP 19030184 A JP19030184 A JP 19030184A JP S6167963 A JPS6167963 A JP S6167963A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- electrodes
- potential
- potential well
- electrical resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000008878 coupling Effects 0.000 title 1
- 238000010168 coupling process Methods 0.000 title 1
- 238000005859 coupling reaction Methods 0.000 title 1
- 238000005036 potential barrier Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000000969 carrier Substances 0.000 abstract description 9
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 230000001105 regulatory effect Effects 0.000 abstract 1
- 238000001444 catalytic combustion detection Methods 0.000 description 13
- 230000004044 response Effects 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 230000015654 memory Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000003384 imaging method Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42396—Gate electrodes for field effect devices for charge coupled devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
ｊ−発明は電荷結合素子（以下ＣＯＤと称す）に関する
。DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field j--The invention relates to a charge-coupled device (hereinafter referred to as COD).
（ロ）従来の技術
この種ＣＣＤは遅延素子、アナログメモリの他に例えば
特公昭５７−３２５４８号公報に示諮れている如く固体
撮像装置としての利用゛が注目されており、テレビカメ
ラの小型化に寄与するものである。(B) Prior Art This type of CCD is attracting attention for its use as a solid-state imaging device in addition to delay elements and analog memories, as proposed in Japanese Patent Publication No. 57-32548, and has been used in compact television cameras. This contributes to the
第２図〈イ）、（ロ）にこの種従来ＣＯＤの平面図、及
びそのＡ−Ａ線断面図を示す、これ等の図に於いて、（
１）はシリコン基板、（２）はシリコン酸化膜、（３１
）（３２）（３１）（３２）・・・は多結晶シリコンか
らなる第１１に極、（４１）（４２＞（４１）（４２）
・・・は同じく多結晶シリコンからなる第２電極である
。これ等第１電極と第２７Ｆ極とが交互に配置きれた電
極列は、連続した多数の電極対（４１）（３１）、 （
４２）（３２）。Figures 2 (a) and (b) show a plan view of this kind of conventional COD and a cross-sectional view taken along the line A-A.
1) is a silicon substrate, (2) is a silicon oxide film, (31
)(32)(31)(32)... is the 11th pole made of polycrystalline silicon, (41)(42>(41)(42)
. . . is a second electrode also made of polycrystalline silicon. These electrode rows in which the first electrode and the 27th F pole are arranged alternately are a large number of consecutive electrode pairs (41), (31), (
42) (32).
（４１）（３１）、・・・を構成し、奇数番目の電極対
（４１）（３１）、 （４１）（３１）、・・・にはク
ロックパルスφ１が供給され、偶数番目の電極対（４２
）（３２）、 （４２）（３２）。(41) (31), . . . , the odd numbered electrode pairs (41) (31), (41) (31), . . . are supplied with a clock pulse φ1, and the even numbered electrode pairs (42
)(32), (42)(32).
・・・にクロックパルスφ２が供給されている。これ等
電極（４１）（３１）（４２）（３２）・・・下のＰ型
のシリコン基板（１）表面部には、燐あるいは砒素を導
入した埋込みチャンネル層（１４１）（１３１）（１４
２）（１３２）・・・が設けられており、第２電極（４
２）（３２）・・・下の埋込みチャンネル層（１４２）
（１３２）・・・のＮ型化された領域は逆にＰ型化させ
るような硼素を導入する事に依って第１電極（４１）（
３１）・・・下のＮ型不純物領域の埋込みチャンネル層
（１４１）＜１３１）・・・よりＮ型化の弱められたＮ
−型不純物領域となっている。... is supplied with clock pulse φ2. These electrodes (41) (31) (42) (32)... On the surface of the P-type silicon substrate (1) below, there are buried channel layers (141) (131) (14) doped with phosphorus or arsenic.
2) (132)... are provided, and the second electrode (4
2) (32)... Lower buried channel layer (142)
The N-type region of (132)... is transformed into a P-type region by introducing boron to the first electrode (41) (
31)...Buried channel layer in the lower N-type impurity region (141)<131)...N with weaker N-type conversion
− type impurity region.
尚、同図（イ）の平面図に於ける領域（ａ）（ａ）・・
・は並列配置された同図（ロ）の断面図に示す如きチャ
ンネル領域であり、これ等領域（ａＨａ）・・・間はＰ
゛型不純物からなるチャンネルストッパ領域（ｂ）（ｂ
）・が設けられている。In addition, area (a) (a) in the plan view of figure (a)...
・are channel regions arranged in parallel as shown in the cross-sectional view of the same figure (b), and these regions (aHa)...are spaced apart by P.
Channel stopper region (b) made of ゛ type impurity (b
)・is provided.
斯様な従来ＣＣＤに於いては第３図に示す如き２相のク
ロックパルスΦ１．Φ２にて駆動され第１ＴＬ極（３１
）（３２）（３１）（３２）・・とこれと電極対をなす
第２電極（４１）（４２）（４１）（４２）・・とには
同一のクロックパルスΦ１又はφ２が印加される事とな
るが、上述の如くテ〜ンネル層の不純物濃度が異なる為
に第１を極（３１）（３２）（３１）（３２）・・・下
のポテンシャルが第２電極（４１）（４２）（４１）（
４２）・・・下のそれよりも深く形成きれる。即ち、第
３図の時刻ｔ１（φ１−Ｈ１φ２−Ｌ）でのポテンシャ
ル形態は第４図ｔ１で示す如く、偶数番目の電極対の第
２電１ｍ （４２＞（４２）・・・下のポテンシャルが
ポテンシャル障壁を形成するべく最も浅くなり、奇数番
目の電極対の第１電極（３１）（３１）・・・下のポテ
ンシャルがポテンシャル井戸を形成するべく最も深くな
る。In such a conventional CCD, two-phase clock pulses Φ1. as shown in FIG. The first TL pole (31
)(32)(31)(32)... and the second electrodes (41)(42)(41)(42)... that form an electrode pair with these are applied with the same clock pulse Φ1 or φ2. However, as mentioned above, since the impurity concentration of the tunnel layer is different, the potential below the first electrode (31) (32) (31) (32)... is the second electrode (41) (42). )(41)(
42)...It can be formed deeper than the one below. That is, the potential form at time t1 (φ1-H1φ2-L) in FIG. 3 is as shown in t1 in FIG. becomes the shallowest to form a potential barrier, and the potential below the first electrodes (31) (31) of the odd-numbered electrode pairs becomes the deepest to form a potential well.
又時刻１２（Φｓ−Ｌ、Φ２−Ｈ）でのポテンシャル形
態は第４図ｔ２で示−す如く、奇数番目の電極対の第２
′ｒｔ極（４１）（４１＞・・・下のポテンシャルがポ
テンシャル障壁を形成すると共に偶数番目の電極対の第
１ｉｔ極（３２）（３２）・・・下のポテンシャルがポ
テンシャル井戸を形成する事となる。この様に同図のｔ
ｌの状態とｔ２の状態とがくり返されるとキャリアであ
る電子がポテンシャル井戸の移動に従って同図の矢印で
示す如く左から右へと転送きれるのである。Also, the potential form at time 12 (Φs-L, Φ2-H) is the second one of the odd-numbered electrode pairs, as shown at t2 in Figure 4.
'rt pole (41) (41>...The lower potential forms a potential barrier, and the 1st it pole of even-numbered electrode pairs (32) (32)...The lower potential forms a potential well. In this way, t in the same figure
When the state 1 and the state t2 are repeated, electrons, which are carriers, are transferred from left to right as shown by the arrow in the figure, following the movement of the potential well.
斯様な従来のＣＯＤを多数ビットを必要とする固体撮像
素子あるいはメモリとして用いる場合、多数ピノ）・即
ち多数チャンネルとなる為に、大面積化を招き、多結晶
シリコンからなる各電極（３１）（３２）（４１）（４
２）・−の長さが１ｃｍ近くなり、又この電極数も増加
するので、１本の電極巾も数μｍと細くなり、斯る電極
（３１）（３２）（４１＞（４２）・・・１本１本の電
気抵抗が無視できない程大きな値となっているのが現状
である。When such a conventional COD is used as a solid-state image sensor or memory that requires a large number of bits, it becomes a large number of pins (i.e., a large number of channels), which leads to a large area and the need for each electrode (31) made of polycrystalline silicon. (32) (41) (4
2) As the length of ・- becomes close to 1 cm and the number of electrodes increases, the width of each electrode becomes thinner to several μm, and such electrodes (31) (32) (41>(42)...・The current situation is that the electrical resistance of each wire is too large to be ignored.
一方、上述の如き２相駆動方式のＣＣＤに於いては、第
２を極（ａｔ）（４２）自・はキャリアである電子の逆
流を妨止する目的を達成する為のポテンシャル障壁を形
成できればよいので、電極巾は極力細く設定してＣＣＤ
全体の小型集積化を図るのが一般的であるが、この場合
第２電極（４１）（４２＞・・・の電気抵抗値が第１電
極＜３１）＜３２）・・・のそれよりもさらに大きくな
ってしまう欠点が生じる。On the other hand, in the two-phase drive type CCD as described above, the second pole (at) (42) can form a potential barrier to prevent the reverse flow of electrons, which are carriers. Therefore, set the electrode width as thin as possible and use the CCD.
It is common to aim for miniaturization of the whole, but in this case the electrical resistance value of the second electrodes (41) (42>... is higher than that of the first electrodes <31) <32)... This creates an even bigger drawback.
即ち、この場合第２電極（４１）（４２）・・・の電気
抵抗値が第１電極（３１）（３２）・・・のそれより大
きいので、第５図に示す如くクロックパルスΦ１及びφ
２に依る第２電極（４１）（４２）・・・位置への印加
電圧ΦＩｔ 、及びφセの立上り又は立下り時の時定数
がクロックパルスΦ１及びΦ２に依る第１を極（３１）
（３２）・・・位置への印加電圧Φ１１及びΦｔＫのそ
れよりも長くなる。従って第２電極（４１）（４２）・
・・下に形成されるポテンシャル障壁の応答時間が第１
電極（３１）（３２）・・・下に形成されるポテンシャ
ル井戸の応答時間より遅くなるので、ポテンシャル井戸
の移動が完了してからポテンシャル障壁の移動が完了す
るまでの間の遅延差時間にキャリアである電子が逆流し
てしまう不都合があった。この様子は第６図に示してお
り、同図に依れば第５ｒＩＡの時刻ｔ１でのポテンシャ
ル形態から時刻ｔ３でのポテンシャル形態に移る途中の
上記遅延差時間に於ける時刻ｔ３での電子の逆流現象が
理解できる。この様にクロックパルスの変形に依って、
電子の逆流転送が生じるとただ単に転送効率の低下を来
たすだけでなくこの逆流電子がノイズとなり、ＣＯＤ固
体撮像装置に於いては再生画像のフントラストの劣化を
招いたり、ＣＯＤメモリに於いては記憶内容の破壊を引
き起こす原因となっていた。That is, in this case, since the electrical resistance value of the second electrodes (41), (42), etc. is larger than that of the first electrodes (31, (32),..., the clock pulses Φ1 and φ
The applied voltage ΦIt to the position and the time constant at the rise or fall of φSe depend on the clock pulses Φ1 and Φ2.
(32)...It is longer than that of the voltages Φ11 and ΦtK applied to the position. Therefore, the second electrodes (41) (42)・
...The response time of the potential barrier formed below is the first
Electrodes (31) (32)...Since the response time is slower than the response time of the potential well formed below, carriers are There was an inconvenience that some electrons would flow backwards. This situation is shown in FIG. 6, which shows that the electrons at time t3 during the delay difference time during the transition from the potential form at time t1 to the potential form at time t3 in the fifth rIA. Understand the reflux phenomenon. In this way, depending on the deformation of the clock pulse,
When reverse flow transfer of electrons occurs, it not only causes a decrease in transfer efficiency, but also the reverse flow electrons become noise, causing deterioration of the image quality of reproduced images in COD solid-state imaging devices, and in COD memory. This caused the destruction of memory contents.
（ハ） 発明が解決しようとする問題点本発明は上述の
点に鑑みてなされたものであり、キャリアの逆流現象を
解消したＣＯＤを提供するものである。(c) Problems to be Solved by the Invention The present invention has been made in view of the above-mentioned points, and provides a COD that eliminates the carrier backflow phenomenon.
（ニ） 問題点を解決するための手段本発明のＣＯＤ
は半導体基板上に絶縁膜を介して電極列を配置した電荷
結合素子に於いて、該電棚列は共通の電圧源がらの印加
電圧に依って半導体基板中にポテンシャル井戸を形成す
る為の第１電極とこれと隣接してポテンシャル障壁を形
成する為の第２を極とからなる２枚１組の電極対からな
り、上記第１電極の電気抵抗を第２に極の電気抵抗より
大ならしめたものである。(d) Means for solving the problem COD of the present invention
In a charge-coupled device in which an electrode array is arranged on a semiconductor substrate with an insulating film interposed therebetween, the electric shelf array is used to form a potential well in the semiconductor substrate by applying a voltage from a common voltage source. It consists of a pair of electrodes consisting of one electrode and a second electrode adjacent to it to form a potential barrier, and if the electrical resistance of the first electrode is greater than the electrical resistance of the second electrode. It is closed.
（ホ） 作用
本発明に依ればポテンシャル井戸を形成する為の第１Ｔ
Ｌ極の電気抵抗をポテンシャル井戸を形成する為の第２
を極のそれよりも大ならしめる事やこ依り、ポテンシャ
ル障壁形成の為の応答時間をポテンシャル井戸形成の為
の応答時間より短くしてこのポテンシャル＃壁にてキャ
リアの逆流現象を解消する事ができる。(E) Function According to the present invention, the first T for forming a potential well
The electrical resistance of the L pole is the second to form a potential well.
By making it larger than that of the pole, the response time for forming a potential barrier is shorter than the response time for forming a potential well, and the backflow phenomenon of carriers can be eliminated at this potential wall. .
（へ）実施例
第１図（イ）（ロ）に本発明のＣＯＤの一実施例の平面
図、及びそのＡ−Ａ線断面図を示す、同図に於いて、第
２図（イ）（ロ）の従来ＣＯＤと同一部分には第１図（
イバｏ）と同一符号を付している。本発明実施例ＣＣＤ
が従来ＣＣＤと異なるところは、第２ ’ｔａｉ （４
１’） （４２’） ・・ノ膜厚を第１電極（３１）（
３２）・・のそれより大きくする事に依って、第１電極
（３１）（３２）・・・の電気抵抗を第２電極（ａｔ’
）（４２’）・・・のそれより大ならしめた点にある。(f) Embodiment Figures 1 (a) and (b) show a plan view of an embodiment of the COD of the present invention, and a sectional view thereof taken along the line A-A. The same parts as the conventional COD in (b) are shown in Figure 1 (
The same reference numerals as ``Ibao'' are given. Example CCD of the present invention
differs from conventional CCDs in that the second 'tai (4
1') (42') ... film thickness of the first electrode (31) (
By making the electrical resistance of the first electrode (31), (32)... larger than that of the second electrode (at'
) (42')...
断る実施例ＣＣＤは、ポテンシャル障壁を形成する為の
第２電極（４１’） ＜４２’）・・・の電極巾をポテ
ンシャル井戸を形成する為の第１１１：極（３１）＜３
２）・の電極巾の約２７３に狭めてＣＣＤ全体の集積化
を図ったものに於いて、電極巾の短縮に依る電気抵抗の
増大分を電極の膜厚を約２倍にまで厚くする事に依って
、ポテンシャル井戸を形成する為に電極巾が大きく形成
されている第１電極（３１）（３２）・の断面積を上記
第２電極（４１’） （４２’）のそれよい小きく設定
しているのである。In the example CCD, the electrode width of the second electrode (41') <42') for forming a potential barrier is the 111th electrode width for forming a potential well: (31) <3
2) In an attempt to integrate the entire CCD by narrowing the electrode width to approximately 273 cm, the electrode film thickness is increased to approximately twice as much to compensate for the increase in electrical resistance due to the shortening of the electrode width. According to It is set.
従って、同一の多結晶シリコン材料（比抵抗的１０−Ｉ
ΩｃｌＴｌ）からなる第１及び第２電極（３１）（３２
）。Therefore, the same polycrystalline silicon material (resistivity 10-I
The first and second electrodes (31) (32
).
、 （４１’）（４２’）であっても第１電極（３１
）（３２）の電気抵抗が第２電極（４１’） （４２’
）のそれよりも大きくなるので、Ｔｌｔ粍対（３１）（
４１’）に共通の電圧源である第３図図示のりａツクパ
ルスΦ１が、又電極対（３２）（４２’）に共通の’ｔ
ＪＥ源である第３図図示のクロックパルスφ２が印力ｒ
Ｊされた場合、各電極（４１’）（３１）（４２’）
＜３２）には第７図に示す如き遅延現象を有する電圧Φ
′１２．Φ’ＩＩ 、Φ′ｎ、φ’ｚｔが印加される事
となる。, (41') (42'), the first electrode (31')
) (32) is the second electrode (41') (42'
) is larger than that of (31) (
41') is a voltage source common to the electrode pairs (32) and (42'), as shown in FIG.
The clock pulse φ2 shown in FIG. 3, which is the JE source, is the output r
J, each electrode (41') (31) (42')
<32), there is a voltage Φ with a delay phenomenon as shown in Figure 7.
'12. Φ'II, Φ'n, and φ'zt are applied.
第８図に第７図に於ける時刻ｔ１．ｔ２゜ｔ３．ｔ４時
の印加電圧Φ−１φ′１１．φ′ｎ・φ′１１に応答す
るポテンシャル形態の状態変化を示す。FIG. 8 shows time t1 in FIG. t2゜t3. Applied voltage Φ-1φ'11 at time t4. The state change of the potential form in response to φ′n·φ′11 is shown.
同図に依れば、印加電圧Φ′け、Φ′セ、の立上り時又
は立下り時（時刻ｔｓ、ｔｚ）の時定数、即ち遅延時間
が印加電圧φ’ＩＩ 、Φ’１１のそれよりも小さいの
で、時刻ｔｌから時刻ｔ４に至るポテンシャル井戸の移
動形成に常に先んしてポテンシャル障壁の移動形成が行
なわれる事がわかる。従ってキャリアである電子は上述
のポテンシャル障壁に依って常に転送方向が規制される
事となり、この電子の逆流転送はない。According to the figure, the time constants at the rise or fall (times ts, tz) of the applied voltages Φ', Φ', i.e., the delay times are longer than those of the applied voltages Φ'II, Φ'11. It can be seen that the moving formation of the potential barrier always takes place prior to the moving formation of the potential well from time tl to time t4. Therefore, the transfer direction of electrons, which are carriers, is always restricted by the above-mentioned potential barrier, and there is no reverse flow transfer of the electrons.
上述の実施例のＣＯＤは第１及び第２電極として同一の
多結晶シリフン材料で構成したものであるが、この多結
晶シリフン材料は燐のドープ量に依っである程度比抵抗
を設定できるものであるので、これを利用してポテンシ
ャル井戸を形成する為の第ｉｔ極（３１）（３２）・・
・の比抵抗を２Ｘ１０−”９口とし、ポテンシャル障壁
を形成する為の第２電極（４１’） （４２’）・・の
比抵抗を１０１Ωｍとする事ができる。この場合には第
２を極の膜厚を第１電極のそれよりも大きくする必要は
なく、これ等膜厚を従来通り等しく設計しても本発明は
実施できる。In the COD of the above embodiment, the first and second electrodes are made of the same polycrystalline silicon material, but the specific resistance of this polycrystalline silicon material can be set to a certain degree depending on the amount of phosphorus doped. Therefore, using this to form a potential well, it is the it-th pole (31) (32)...
The specific resistance of the second electrode (41') (42') for forming a potential barrier can be set to 101 Ωm. It is not necessary to make the thickness of the electrode larger than that of the first electrode, and the present invention can be carried out even if these thicknesses are designed to be equal in the conventional manner.
さらに、上述の実施例に於いては、集積化を図る為に、
第２電極の電極巾を狭くした場合について説明したが、
第２電極と第１を極の電極巾がほぼ等しいＣＯＤに於い
ても、ポテンシャル井戸を形成する為の第１電極の電気
抵抗をポテンシャルｗｔ壁を形成する為のｖｇ２電極の
それより大きく設定しておれば、上述の如く電荷の逆流
転送の惧れは皆無となる。Furthermore, in the above embodiment, in order to achieve integration,
Although we have explained the case where the electrode width of the second electrode is narrowed,
Even in a COD where the electrode widths of the second electrode and the first electrode are approximately equal, the electrical resistance of the first electrode for forming a potential well is set larger than that of the vg2 electrode for forming a potential wt wall. If this is the case, there will be no fear of reverse charge transfer as described above.
（ト〉 発明の効果
本発明のＣＣＤは共通電圧源からの印加電圧に依って半
導体基板中にポテンシャル井戸を形成する為の第１電極
とこれと隣接してボテンノヤル障壁を形成する為の第２
電極とからなる２枚１組の電極対からなる電極列を備え
、第１！極の電気抵抗庖第２Ｎ、極の電気抵抗より大な
らしめているので、第１ＴＩＬ極に依って形成されるポ
テンシャル井戸よりも第２［ｍに依って形成きれるポテ
ンシャル障壁の方が応答時間が短くなり、このポテンシ
ャル障壁にて転送方向が決定されるキャリアの逆流転送
を解消する事ができる。従って本発明に係るＣＣＤ固体
撮像装置に於いては、逆流キャリアの解消に依って再生
画像のフントラストの劣化を防止でき、ＣＣＤメモリに
於いては記憶内容が破壊きれる惧れはない。(G) Effects of the Invention The CCD of the present invention has a first electrode for forming a potential well in a semiconductor substrate by a voltage applied from a common voltage source, and a second electrode for forming a potential well adjacent thereto.
The first ! Since the electric resistance of the pole is made larger than the electric resistance of the pole, the response time of the potential barrier formed by the second TIL is shorter than that of the potential well formed by the first TIL pole. Therefore, reverse flow transfer of carriers in which the transfer direction is determined by this potential barrier can be eliminated. Therefore, in the CCD solid-state imaging device according to the present invention, deterioration of the fundus of the reproduced image can be prevented by eliminating backflow carriers, and there is no fear that the stored contents in the CCD memory will be destroyed.
第１図（イ）、（ロ）は本発明のＣＣＤの一実施例の平
面図、及び断面図、第２図（イ）、（ロ）は従来のＣＣ
Ｄの平面図、及び断面図、第３図及び第４図はクロック
パルスの波形図、及びそれに伴う理論的なポテンシャル
図、第５図及び第６図は従来ＣＯＤに於ける各電極の電
圧波形図、及びそれに伴う実際のボテンシへ・ル図、第
７図及び第８図は本発明ＣＣＤに於ける各電極の電圧波
形図、及びそれに伴う実際のポテンシャル図である。
（１）・・・シリコン基板、（２）・・・シリコン酸化
膜、（３１）（３２）・・・第１電極、（４１）（４２
＞（４１つ（４２’）・・第２電極。Figures 1 (a) and (b) are a plan view and a sectional view of an embodiment of the CCD of the present invention, and Figures 2 (a) and (b) are a conventional CC
A plan view and a sectional view of D, FIGS. 3 and 4 are clock pulse waveform diagrams and accompanying theoretical potential diagrams, and FIGS. 5 and 6 are voltage waveforms of each electrode in conventional COD. 7 and 8 are voltage waveform diagrams of each electrode in the CCD of the present invention, and actual potential diagrams associated therewith. (1)... Silicon substrate, (2)... Silicon oxide film, (31) (32)... First electrode, (41) (42
>(41 (42')...second electrodes.
Claims (1)
荷結合素子に於いて、該電極列は共通の電圧源からの印
加電圧に依って半導体基板中にポテンシャル井戸を形成
する為の第１電極とこれと隣接してポテンシャル障壁を
形成する為の第２電極とからなる２枚１組の電極対から
なり、上記第１電極の電気抵抗を第２電極の電極抵抗よ
り大ならしめた事を特徴とする電荷結合素子。1) In a charge-coupled device in which an electrode array is arranged on a semiconductor substrate with an insulating film interposed therebetween, the electrode array is used to form a potential well in the semiconductor substrate by applying a voltage from a common voltage source. It consists of a pair of electrodes consisting of a first electrode and a second electrode adjacent to it to form a potential barrier, and the electrical resistance of the first electrode is made greater than the electrode resistance of the second electrode. A charge-coupled device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59190301A JPH0697669B2 (en) | 1984-09-11 | 1984-09-11 | Charge coupled device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59190301A JPH0697669B2 (en) | 1984-09-11 | 1984-09-11 | Charge coupled device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6167963A true JPS6167963A (en) | 1986-04-08 |
| JPH0697669B2 JPH0697669B2 (en) | 1994-11-30 |
Family
ID=16255880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59190301A Expired - Lifetime JPH0697669B2 (en) | 1984-09-11 | 1984-09-11 | Charge coupled device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0697669B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0496357A2 (en) * | 1991-01-23 | 1992-07-29 | Sony Corporation | Charge coupled device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5178179A (en) * | 1974-12-27 | 1976-07-07 | Sony Corp | |
| JPS5330282A (en) * | 1976-09-01 | 1978-03-22 | Hitachi Ltd | Semiconductor device |
| JPS575361A (en) * | 1980-06-11 | 1982-01-12 | Toshiba Corp | Charge transfer device |
-
1984
- 1984-09-11 JP JP59190301A patent/JPH0697669B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5178179A (en) * | 1974-12-27 | 1976-07-07 | Sony Corp | |
| JPS5330282A (en) * | 1976-09-01 | 1978-03-22 | Hitachi Ltd | Semiconductor device |
| JPS575361A (en) * | 1980-06-11 | 1982-01-12 | Toshiba Corp | Charge transfer device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0496357A2 (en) * | 1991-01-23 | 1992-07-29 | Sony Corporation | Charge coupled device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0697669B2 (en) | 1994-11-30 |
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