JPH0760895B2 - Charge coupled device and driving method thereof - Google Patents

Charge coupled device and driving method thereof

Info

Publication number
JPH0760895B2
JPH0760895B2 JP17343685A JP17343685A JPH0760895B2 JP H0760895 B2 JPH0760895 B2 JP H0760895B2 JP 17343685 A JP17343685 A JP 17343685A JP 17343685 A JP17343685 A JP 17343685A JP H0760895 B2 JPH0760895 B2 JP H0760895B2
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor region
conductivity type
diffusion layer
floating diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP17343685A
Other languages
Japanese (ja)
Other versions
JPS6233463A (en
Inventor
英嗣 織田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17343685A priority Critical patent/JPH0760895B2/en
Publication of JPS6233463A publication Critical patent/JPS6233463A/en
Publication of JPH0760895B2 publication Critical patent/JPH0760895B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は電荷結合素子及びその駆動方法に関し、特に、
出力部の高密度化を可能とする電荷結合素子及びその駆
動方法に関する。
Description: TECHNICAL FIELD The present invention relates to a charge-coupled device and a driving method thereof, and in particular,
The present invention relates to a charge-coupled device capable of increasing the density of an output section and a driving method thereof.

(従来技術) 電荷結合素子(以下CCDと記す)は、従来からの高度の
集積回路技術を基盤とし、その発展とともに急速な開発
が進められ、近年固体撮像,メモリ等の各種の応用がな
されるようになった。特にCCDを用いた固体撮像素子
は、低消費電力,小型,軽量など多くの特徴を有し近年
その開発が盛んである。現在、固体撮像素子は、多画
素,高密度化されるが一般的傾向である。これにともな
い、ダイナミックレンジの低下,S/Nの劣化等が問題とな
っている。
(Prior Art) Charge-coupled devices (hereinafter referred to as CCDs) are based on the conventional high-level integrated circuit technology, and are rapidly developed along with their development. In recent years, various applications such as solid-state imaging and memory have been made. It became so. In particular, a solid-state image sensor using a CCD has many features such as low power consumption, small size, and light weight, and its development has been brisk in recent years. At present, the solid-state image sensor has a large number of pixels and a high density, but it is a general tendency. Along with this, there are problems such as a decrease in dynamic range and deterioration of S / N.

第2図は従来の電荷結合素子の出力部の模式的断面図を
示す。なお、以下の説明では便宜上N型半導体基板を用
いたNチャネルの素子について説明する。第2図におい
て、1はN型の半導体基板2,3はこの半導体基板上に形
成される反対導電型すなわちP型の第1および第2の半
導体領域で、ここでは第1および第2のPウエルと呼
ぶ。4はこれらPウエル内に形成されるN型の半導体層
(Nウエル)で、埋込みチャネルCCDを構成する。5お
よび6は高濃度のN型不純物を拡散した領域で、とくに
5は浮遊拡散層としてCCDの出力構造の一部を構成し、
転送電荷の検出を行なうのに用いられる。7はP型の高
濃度拡散層でチャネルストッパーを形成している。8は
絶縁膜,9はリセット電極,10は出力ゲート電極、11,12は
転送ゲート電極である。本素子の動作においては通常前
記第1,第2のPウエル2,3と前記N型半導体基板1との
間には逆バイアス電圧VSUBが印加されている。本素子に
おける第2のPウエルはNウエル4直下に形成され、CC
Dの転送電荷量の増大あるいは固体撮像におけるスミア
の抑制に有効に作用する。また本素子のCCDは便宜上4
相駆動パルスφ〜φによって駆動されるものと仮定
し、図では出力付近のφ3に対応する転送ゲート電
極11,12のみが示されている。出力ゲート電極10には通
常電圧VOGが印加されている。またリセット電極9には
周期的なリセットパルスφが印加され、リセット電極
直下のチャネルを導通させ、浮遊拡散層5の電位を周期
的に基準電位VRDにセットする。以下に本素子の動作に
ついて説明する。CCDのチャネルを転送されてきた信号
電荷は出力ゲート電極10直下を経由して浮遊拡散層5へ
と流入する。このとき浮遊拡散層5の電位は、信号電荷
量に比例、浮遊拡散層の容量に反比例して変化する。こ
の電位変化が、浮遊拡散層と結合された出力アンプ(図
示せず)を介して外部にとり出される。この後、リセッ
ト電極9にリセットパルスφが印加され浮遊拡散層5
の電位は基準電位VRDにセットされ、再び、信号電荷検
出可能な状態となる。
FIG. 2 shows a schematic cross-sectional view of the output part of a conventional charge coupled device. In the following description, an N-channel element using an N-type semiconductor substrate will be described for convenience. In FIG. 2, reference numeral 1 is an N-type semiconductor substrate 2, 3 is first and second semiconductor regions of opposite conductivity type, that is, P-type, formed on the semiconductor substrate. Call it well. Reference numeral 4 denotes an N type semiconductor layer (N well) formed in these P wells, which constitutes a buried channel CCD. 5 and 6 are regions in which high-concentration N-type impurities are diffused, and particularly 5 is a floating diffusion layer which constitutes a part of the output structure of the CCD.
Used to detect transfer charge. 7 is a P-type high-concentration diffusion layer forming a channel stopper. Reference numeral 8 is an insulating film, 9 is a reset electrode, 10 is an output gate electrode, and 11 and 12 are transfer gate electrodes. In the operation of this element, a reverse bias voltage V SUB is normally applied between the first and second P wells 2 and 3 and the N-type semiconductor substrate 1. The second P well in this device is formed immediately below the N well 4, and CC
It effectively acts to increase the transfer charge amount of D or suppress smear in solid-state imaging. Also, the CCD of this device is 4 for convenience.
Was assumed to be driven by a phase drive pulses phi 1 to [phi] 4, the drawings show only the transfer gate electrodes 11 and 12 corresponding to phi 3, phi 4 near the output. A normal voltage V OG is applied to the output gate electrode 10. Further, a periodic reset pulse φ R is applied to the reset electrode 9, the channel immediately below the reset electrode is made conductive, and the potential of the floating diffusion layer 5 is periodically set to the reference potential V RD . The operation of this element will be described below. The signal charge transferred through the CCD channel flows into the floating diffusion layer 5 directly below the output gate electrode 10. At this time, the potential of the floating diffusion layer 5 changes in proportion to the signal charge amount and in inverse proportion to the capacitance of the floating diffusion layer. This potential change is taken out to the outside through an output amplifier (not shown) coupled to the floating diffusion layer. After that, the reset pulse φ R is applied to the reset electrode 9 and the floating diffusion layer 5
The potential of is set to the reference potential V RD , and the signal charge can be detected again.

(従来技術の問題点) 以上述べた一連の動作から、本素子の信号電荷の検出感
度は、浮遊拡散層容量が小さいほど大きいことがわか
る。浮遊拡散層5の容量は、第1,第2のPウエルに対す
る容量,リセット電極9に対する容量,出力ゲート電極
10に対する容量,出力アンプ(図示せず)の入力容量等
の合成容量となる。
(Problems of Prior Art) From the series of operations described above, it is understood that the detection sensitivity of the signal charge of this element is larger as the floating diffusion layer capacitance is smaller. The floating diffusion layer 5 has a capacitance for the first and second P wells, a capacitance for the reset electrode 9 and an output gate electrode.
It is the combined capacitance of the capacitance for 10 and the input capacitance of the output amplifier (not shown).

通常、第2のPウエル3は比較的高濃度である。このた
め従来素子では浮遊拡散層からPウエルに向って空乏層
があまり延びず、対Pウエルの容量が比較的大きくな
り、結果的に浮遊拡散層の容量が大となり、信号検出感
度の劣化あるいはS/N比の低下等の問題が生じていた。
Usually, the second P well 3 has a relatively high concentration. For this reason, in the conventional device, the depletion layer does not extend so much from the floating diffusion layer toward the P well, the capacitance of the P well is relatively large, and as a result, the capacitance of the floating diffusion layer is large, and the signal detection sensitivity is deteriorated. There was a problem such as a decrease in S / N ratio.

(発明の目的) 本発明の目的は、このような従来の問題点を解消するこ
とにより、信号検出感度が高く、S/N比のより電荷結合
素子とその駆動方法を提供することにある。
(Object of the Invention) It is an object of the present invention to provide a charge-coupled device having a high signal detection sensitivity and a higher S / N ratio and a method for driving the same by solving the problems of the related art.

(発明の構成) 本発明の第1の発明の電荷結合素子は、一導電形の半導
体基板と、該半導体基板の表面部に形成された該半導体
基板と反対導電形の第1の半導体領域と、該第1の半導
体領域の表面部にその所定箇所を除き形成された前記第
1の半導体領域と同一導電形でこれより高濃度の第2の
半導体領域と、前記所定箇所および前記第2の半導体領
域の表面部に形成された一導電形の埋込みチャネルの半
導体層と、該半導体層の前記所定箇所に対応する部分と
その近傍に浮遊拡散層として形成された一導電形の半導
体拡散層を備えた出力構造を有するというものである。
(Structure of the Invention) A charge-coupled device according to a first invention of the present invention includes a semiconductor substrate of one conductivity type, and a first semiconductor region of a conductivity type opposite to the semiconductor substrate formed on a surface portion of the semiconductor substrate. A second semiconductor region which has the same conductivity type as that of the first semiconductor region and has a higher concentration than that of the first semiconductor region, which is formed on the surface portion of the first semiconductor region except for the predetermined region, and the predetermined region and the second semiconductor region. A semiconductor layer of a buried channel of one conductivity type formed on the surface portion of the semiconductor region, and a semiconductor diffusion layer of one conductivity type formed as a floating diffusion layer in the portion corresponding to the predetermined portion of the semiconductor layer and in the vicinity thereof. It has a built-in output structure.

また本発明の第2の発明の電荷結合素子の駆動方法は、
一導電形の半導体基板と、該半導体基板の表面部に形成
された該半導体基板と反対導電形の第1の半導体領域
と、該第1の半導体領域の表面部にその所定箇所を除き
形成された前記第1の半導体領域と同一導電形でこれよ
り高濃度の第2の半導体領域と、前記所定箇所および前
記第2の半導体領域の表面部に形成された一導電形の埋
込みチャネルの半導体層と、該半導体層の前記所定箇所
に対応する部分とその近傍に浮遊拡散層として形成され
た一導電形の半導体拡散層を備えた出力構造を有する電
荷結合素子の駆動方法であって、前記半導体基板と前記
第1の半導体領域との間に逆バイアス電圧を印加すると
いうものである。
The charge-coupled device driving method of the second invention of the present invention is
A semiconductor substrate of one conductivity type, a first semiconductor region of an opposite conductivity type to the semiconductor substrate formed on a surface portion of the semiconductor substrate, and a surface portion of the first semiconductor region except a predetermined portion thereof. A second semiconductor region having the same conductivity type as that of the first semiconductor region and having a higher concentration than that of the first semiconductor region, and a semiconductor layer of a buried channel of one conductivity type formed in the predetermined portion and the surface portion of the second semiconductor region. And a driving method of a charge-coupled device having an output structure including a portion corresponding to the predetermined portion of the semiconductor layer and a semiconductor diffusion layer of one conductivity type formed as a floating diffusion layer in the vicinity thereof. A reverse bias voltage is applied between the substrate and the first semiconductor region.

(構成の詳細な説明) 本発明の第1の発明の電荷結合素子は、従来浮遊拡散層
直下にあった二つのPウエルの一方を除去することによ
り浮遊拡散層直下のPウエルの不純物濃度を低下させ空
乏層がより広がりやすくさせていることに特徴がある。
(Detailed Description of Configuration) In the charge-coupled device of the first invention of the present invention, by removing one of the two P wells which are located immediately below the floating diffusion layer, the impurity concentration of the P well immediately below the floating diffusion layer is removed. It is characterized by lowering the depletion layer so that it can spread more easily.

そして、本発明の第2の発明の電荷結合素子の駆動方法
により以下の動作を行わしめることにより本発明の目的
を達成するものである。すなわち、PウエルとN型基板
との間に印加する逆バイアス電圧を充分に大きくし、浮
遊拡散層直下のPウエルが完全に空乏化されるように
し、浮遊拡散層直下の空乏層をN型基板まで達せしめる
ようにする。
Then, the object of the present invention is achieved by performing the following operations by the method for driving a charge coupled device according to the second aspect of the present invention. That is, the reverse bias voltage applied between the P-well and the N-type substrate is sufficiently increased so that the P-well directly under the floating diffusion layer is completely depleted, and the depletion layer immediately under the floating diffusion layer is N-type. Try to reach the substrate.

かくして、本発明によれば、浮遊拡散層直下の空乏層を
大きくすることができ、もって浮遊拡散層の容量の低下
が可能となり、信号検出感度の向上,S/N比の向上等がは
かれる。
Thus, according to the present invention, the depletion layer immediately below the floating diffusion layer can be enlarged, and the capacitance of the floating diffusion layer can be reduced, and the signal detection sensitivity and the S / N ratio can be improved.

(実施例) 以下、本発明の実施例について図面を参照して説明す
る。
(Example) Hereinafter, the Example of this invention is described with reference to drawings.

第1図は、本発明の第1の発明による一実施例の模式的
断面図を示し、素子出力部の要部について示している。
第1図において、第2図と同一番号は同一対象物を示
す。第1図において、13,14は第2のPウエルであり、
浮遊拡散層5直下は欠除して構成されている。15は浮遊
拡散層5直下の第1のPウエル領域を示す。本素子の構
成において領域15は、素子主要部のPウエル領域よりも
全体としてその不純物濃度がより低濃度となっている。
また、Pウエル15とN型基板1との間には逆バイアス電
圧VSUBが印加されている。この逆バイアス電圧は、浮遊
拡散層5直下の領域15が完全に空乏化されるように充分
にバイアスされていることに特徴がある。この領域15
は、本発明の素子においては、前記したように素子主要
部よりも低濃度となっているため、比較的容易に空乏化
され得る。この空乏層は、浮遊拡散層5からPウエルへ
向って延びる空乏層とN型基板1からPウエルへ向って
延びる空乏層とが直列に結合された構成となっている。
したがって浮遊拡散層5直下の空乏層幅は、従来素子と
比べて極めて大きくなる。すなわち、従来素子において
は、空乏層は浮遊拡散層5と第1および第2のPウエル
2,3との間に形成されその幅はせいぜい2〜5μm程度
であった。これに対して本発明による素子およびその駆
動方法によれば空乏層は浮遊拡散層5とN型基板1との
間に形成されるためその幅は15μmあるいは20μm以上
に容易になし得る。このため本発明による素子の浮遊拡
散層直下の空乏層容量は極めて小さくなり信号検出感度
の向上、S/N比の向上等が達成される。
FIG. 1 is a schematic cross-sectional view of one embodiment according to the first aspect of the present invention, showing a main part of an element output section.
In FIG. 1, the same numbers as in FIG. 2 indicate the same objects. In FIG. 1, 13 and 14 are second P wells,
The portion directly below the floating diffusion layer 5 is omitted. Reference numeral 15 indicates a first P well region directly below the floating diffusion layer 5. In the structure of this device, the region 15 has a lower impurity concentration as a whole than the P well region of the main part of the device.
A reverse bias voltage V SUB is applied between the P well 15 and the N type substrate 1. This reverse bias voltage is characterized by being sufficiently biased so that the region 15 immediately below the floating diffusion layer 5 is completely depleted. This area 15
In the device of the present invention, since the concentration is lower than that of the main part of the device as described above, it can be depleted relatively easily. The depletion layer has a configuration in which a depletion layer extending from the floating diffusion layer 5 toward the P well and a depletion layer extending from the N-type substrate 1 toward the P well are connected in series.
Therefore, the width of the depletion layer immediately below the floating diffusion layer 5 becomes extremely large as compared with the conventional element. That is, in the conventional device, the depletion layer is the floating diffusion layer 5 and the first and second P wells.
It was formed between 2 and 3 and its width was at most about 2 to 5 μm. On the other hand, according to the element and the driving method thereof according to the present invention, the depletion layer is formed between the floating diffusion layer 5 and the N-type substrate 1, so that the width thereof can be easily set to 15 μm or 20 μm or more. Therefore, the capacitance of the depletion layer just below the floating diffusion layer of the device according to the present invention is extremely small, and the signal detection sensitivity and the S / N ratio are improved.

(発明の効果) 以上、詳細に述べたように、本発明によれば、上記の構
成および駆動方法により、信号検出感度が高く、S/N比
のよい電荷結合素子及びその駆動方法が実現できる。
(Effects of the Invention) As described in detail above, according to the present invention, a charge coupled device having a high signal detection sensitivity and a good S / N ratio and a driving method thereof can be realized by the above configuration and driving method. .

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の第1の発明の一実施例の要部を示す模
式的断面図、第2図は従来の電荷結合素子の要部の模式
的断面図である。 1……N型半導体基板、2……第1のPウエル、3,13,1
4……第2のPウエル、4……埋込みチャネル、5……
浮遊拡散層、6……高濃度N型不純物拡散層、7……チ
ャネルストッパー、8……絶縁膜、9……リセットゲー
ト電極、10……出力ゲート電極、11,12……転送ゲート
電極。
FIG. 1 is a schematic sectional view showing an essential part of an embodiment of the first invention of the present invention, and FIG. 2 is a schematic sectional view of an essential part of a conventional charge coupled device. 1 ... N-type semiconductor substrate, 2 ... first P well, 3,13,1
4 …… Second P well, 4 …… Embedded channel, 5 ……
Floating diffusion layer, 6 ... High-concentration N-type impurity diffusion layer, 7 ... Channel stopper, 8 ... Insulating film, 9 ... Reset gate electrode, 10 ... Output gate electrode, 11, 12 ... Transfer gate electrode.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】一導電形の半導体基板と、該半導体基板の
表面部に形成された該半導体基板と反対導電形の第1の
半導体領域と、該第1の半導体領域の表面部にその所定
箇所を除き形成された前記第1の半導体領域と同一導電
形でこれより高濃度の第2の半導体領域と、前記所定箇
所および前記第2の半導体領域の表面部に形成された一
導電形の埋込みチャネルの半導体層と、該半導体層の前
記所定箇所に対応する部分とその近傍に浮遊拡散層とし
て形成された一導電形の半導体拡散層を備えた出力構造
を有することを特徴とする電荷結合素子。
1. A semiconductor substrate of one conductivity type, a first semiconductor region of a conductivity type opposite to that of the semiconductor substrate formed on a surface portion of the semiconductor substrate, and a predetermined portion on a surface portion of the first semiconductor region. A second semiconductor region of the same conductivity type as that of the first semiconductor region formed except for a portion and having a higher concentration than that of the first semiconductor region; and one conductivity type formed on the predetermined portion and the surface portion of the second semiconductor region. A charge coupling having a semiconductor layer of a buried channel, an output structure including a semiconductor diffusion layer of one conductivity type formed as a floating diffusion layer in a portion corresponding to the predetermined portion of the semiconductor layer and in the vicinity thereof. element.
【請求項2】一導電形の半導体基板と、該半導体基板の
表面部に形成された該半導体基板と反対導電形の第1の
半導体領域と、該第1の半導体領域の表面部にその所定
箇所を除き形成された前記第1の半導体領域と同一導電
形でこれより高濃度の第2の半導体領域と、前記所定箇
所および前記第2の半導体領域の表面部に形成された一
導電形の埋込みチャネルの半導体層と、該半導体層の前
記所定箇所に対応する部分とその近傍に浮遊拡散層とし
て形成された一導電形の半導体拡散層を備えた出力構造
を有する電荷結合素子の駆動方法であって、前記半導体
基板と前記第1の半導体領域との間に逆バイアス電圧を
印加することを特徴とする電荷結合素子の駆動方法。
2. A semiconductor substrate of one conductivity type, a first semiconductor region of a conductivity type opposite to that of the semiconductor substrate formed on a surface portion of the semiconductor substrate, and a predetermined portion on the surface portion of the first semiconductor region. A second semiconductor region of the same conductivity type as that of the first semiconductor region formed except for a portion and having a higher concentration than that of the first semiconductor region; and one conductivity type formed on the predetermined portion and the surface portion of the second semiconductor region. A method for driving a charge-coupled device having a semiconductor layer of a buried channel, an output structure including a portion corresponding to the predetermined portion of the semiconductor layer and a semiconductor diffusion layer of one conductivity type formed as a floating diffusion layer in the vicinity thereof is provided. A charge-coupled device driving method, characterized in that a reverse bias voltage is applied between the semiconductor substrate and the first semiconductor region.
JP17343685A 1985-08-06 1985-08-06 Charge coupled device and driving method thereof Expired - Fee Related JPH0760895B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17343685A JPH0760895B2 (en) 1985-08-06 1985-08-06 Charge coupled device and driving method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17343685A JPH0760895B2 (en) 1985-08-06 1985-08-06 Charge coupled device and driving method thereof

Publications (2)

Publication Number Publication Date
JPS6233463A JPS6233463A (en) 1987-02-13
JPH0760895B2 true JPH0760895B2 (en) 1995-06-28

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JP17343685A Expired - Fee Related JPH0760895B2 (en) 1985-08-06 1985-08-06 Charge coupled device and driving method thereof

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JP5706212B2 (en) * 2011-03-29 2015-04-22 シャープ株式会社 Solid-state imaging device, manufacturing method thereof, and electronic information device
JP6399301B2 (en) 2014-11-25 2018-10-03 セイコーエプソン株式会社 Solid-state imaging device and manufacturing method thereof

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JPS6233463A (en) 1987-02-13

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