JPS5965470A - Output structure of charge coupled device - Google Patents

Output structure of charge coupled device

Info

Publication number
JPS5965470A
JPS5965470A JP57175013A JP17501382A JPS5965470A JP S5965470 A JPS5965470 A JP S5965470A JP 57175013 A JP57175013 A JP 57175013A JP 17501382 A JP17501382 A JP 17501382A JP S5965470 A JPS5965470 A JP S5965470A
Authority
JP
Japan
Prior art keywords
well
output
diffusion layer
density
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57175013A
Other languages
Japanese (ja)
Inventor
Hidetsugu Oda
織田 英嗣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57175013A priority Critical patent/JPS5965470A/en
Publication of JPS5965470A publication Critical patent/JPS5965470A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/762Charge transfer devices
    • H01L29/765Charge-coupled devices
    • H01L29/768Charge-coupled devices with field effect produced by an insulated gate
    • H01L29/76816Output structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE:To enable to simplify the entire system of the titled output structure by a method wherein the semiconductor region, where a floating diffusion layer will be formed, is constituted in such a manner that it is completely deplated by an invertedly biasing means, thereby enabling to control the value of maximum output signal voltage in the interior of the device and to unnecessitate a clipping operation. CONSTITUTION:The point differing from the conventional structure is that the device is formed on the two P-wells 22 and 23 provided on an N type substrate 21. Also, the P-well 22 is formed relatively in shallow depth and in thin density, and the P-well 23 is formed relatively deeply and in thick density. The density of the P-well 23 is almost same as that of the conventional P-substrate 1, and the density of the P-well 22 is approximately 10<15>/cm<3> and the depth is 1-5mum or thereabout. An inverted bias voltage Vsub is applied between the P-wells 21 and 23 and the substrate 21, and the P-well 22 is formed in such a manner that it is depleted completely.

Description

【発明の詳細な説明】 本発明は電荷結合素子(以後CODと記す)の出力構造
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output structure of a charge coupled device (hereinafter referred to as COD).

CODは!970年、に発表されて以来、従来からの高
度の集積回路技術を基盤とし、その発展とともに急速な
開発が進められ、近年固体撮像、アナログ遅延線、メモ
リ等の各種の応用がなされるようになった。特にCOD
を用いた固体撮像−子はMOS型の固体撮像素子と同様
、低消費電力、小型軽量、高集積化が可能など、多くの
特徴を有し近年その開発が盛をである。ところでCC,
Dを用いた単板カラーカメラにおいては水平方向解像度
向上のため、湧常CCD遅延線を用いて垂直方向に画素
補間を行なっている。このときCOD固体固体素像素子
の出力信号は遅延線でのS/N劣化を防ぐため、いった
ん増幅されたのち、遅延縁へ入力されて−る。このとき
の増幅度は通常10dB程度である。ところでCCD撮
像素子からの出力信号電圧は光入射強度に応じて数mV
から約1■まで変化する。このためこの信号電圧を増幅
してそのままCC])遅延線へ入力するとCC1)遅延
線でのダイナミックレンジによる制約を受け、信号電圧
の大きなところでビデオ信号にひずみを生じるなど不都
合をひきおこす。このため従来は撮像素子からの出力信
号電圧を増幅した後に、いったんクリップ回路を通[7
て信号電圧が必要以上に太きくならないように遅延線へ
入力するなど複雑な周辺回路を必要とした。
COD is! Since it was announced in 1970, it has been rapidly developed based on conventional advanced integrated circuit technology, and in recent years has been used for various applications such as solid-state imaging, analog delay lines, and memory. became. Especially COD
Similar to MOS type solid-state image sensors, solid-state image sensors using MOS image sensors have many features such as low power consumption, small size and light weight, and can be highly integrated, and their development has been active in recent years. By the way, CC,
In a single-chip color camera using D, pixel interpolation is performed in the vertical direction using a CCD delay line in order to improve the resolution in the horizontal direction. At this time, the output signal of the COD solid-state image element is once amplified to prevent S/N deterioration in the delay line and then input to the delay edge. The amplification degree at this time is usually about 10 dB. By the way, the output signal voltage from the CCD image sensor varies by several mV depending on the incident light intensity.
It varies from about 1■. Therefore, if this signal voltage is amplified and input directly to the CC1) delay line, it will be restricted by the dynamic range of the CC1) delay line, causing problems such as distortion of the video signal at large signal voltages. For this reason, conventionally, after amplifying the output signal voltage from the image sensor, it is first passed through a clip circuit [7
This required complex peripheral circuitry, such as inputting it into a delay line to prevent the signal voltage from becoming unnecessarily thick.

第1図は従来のCOD固体撮像素子の出力部近傍の断面
図を示す。1は一導電型を有する半導体基板、2は半導
体基板1と反対導電型を有する半導体層であり、埋込み
チャネルを形成する。3はチャネルストッパー、4は酸
化膜、5は半導体基板1と反対導電型を有する出力浮遊
拡散層、6は半導体基板1と反対導電型を有する拡散層
でリセットドレインと称する。7〜9はCCDの転送電
極、lOは出力ゲート電極、11はリセットゲート電極
、12はリセットドレイン6の端子、13ハリセツトゲ
ート電極11の端子、14は出力ゲート電極10の端子
、15−17はCCDの転送電極7〜9の端子群である
。第2図はこの素子に印加されるパルス波形01〜04
,0 の代表的な例および出几 力信号波形■。UTについて示している。つぎにこの素
子の動作について説明する。まず、リセットゲート11
にバルスダ を印加する。これによりり几 セラトゲ−)11直下は導通状態となり出力浮遊拡散層
5はリセットドレイン6と同一の電位に設定され、出力
波形v  ld第2図■l’LDで示されOUT る電位となる。つぎにリセットパルスタ11.はオフ状
態となるが、このときのリセットパル入への過渡的な変
化がリセットゲー)11と出力浮遊拡散層5との間に存
在する寄生容量を介して出力浮遊拡散層5にフィードス
ルーとして現われ出力波形V  は第2図V で示され
る′電極と、なる。
FIG. 1 shows a cross-sectional view of the vicinity of the output section of a conventional COD solid-state image sensor. 1 is a semiconductor substrate having one conductivity type, and 2 is a semiconductor layer having a conductivity type opposite to that of the semiconductor substrate 1, forming a buried channel. 3 is a channel stopper, 4 is an oxide film, 5 is an output floating diffusion layer having a conductivity type opposite to that of the semiconductor substrate 1, and 6 is a diffusion layer having a conductivity type opposite to that of the semiconductor substrate 1, which is called a reset drain. 7 to 9 are transfer electrodes of the CCD, IO is an output gate electrode, 11 is a reset gate electrode, 12 is a terminal of the reset drain 6, 13 is a terminal of the reset gate electrode 11, 14 is a terminal of the output gate electrode 10, 15-17 is a terminal group of transfer electrodes 7 to 9 of the CCD. Figure 2 shows pulse waveforms 01 to 04 applied to this element.
, 0 representative example and output power signal waveform■. It shows about UT. Next, the operation of this element will be explained. First, reset gate 11
Apply Barsuda to . As a result, the area immediately below the conductor 11 becomes conductive, and the output floating diffusion layer 5 is set to the same potential as the reset drain 6, and the output waveform becomes the potential shown by 1'LD in FIG. Next, reset pulser 11. is in the off state, but the transient change to the input of the reset pulse at this time is a feedthrough to the output floating diffusion layer 5 via the parasitic capacitance existing between the reset gate 11 and the output floating diffusion layer 5. The resulting output waveform V 1 becomes the 'electrode shown in FIG. 2 as V 2 .

OUT           R この電位がCCDの出力の基準電位となる。OUT R This potential becomes the reference potential for the output of the CCD.

つぎに信号電荷である・成子が第2図に示される/ぐル
スグ、〜グ。によって第1図右方から左方へと転送され
、出力浮遊拡散層5へ導かれると、出力浮遊拡散層5の
電位は信号電荷の量に比例して変化し、出力波形■。t
JTは■0となる。
Next, the signal charge, Nariko, is shown in Figure 2. When the signal charge is transferred from the right side to the left side in FIG. 1 and guided to the output floating diffusion layer 5, the potential of the output floating diffusion layer 5 changes in proportion to the amount of signal charge, and the output waveform . t
JT becomes ■0.

このときのVoとV との差■0が信号出力となる。The difference between Vo and V at this time (■0) becomes the signal output.

一般にCCDを用いた個体撮惨米子では、と、の■0の
値は数mVから1■〈らいまで変化する。
In general, in individual imaging using a CCD in Yonago, the value of 0 varies from several mV to 1 〈.

前記したようにとのVoを増幅【7て直接CCD遅延線
へ入力するとCCD遅延線でのダイナミックレンジによ
る制約を受けるため、増’I’iil シた信号電圧を
、いったんり1)ツブ回路を通す処理をしている。この
だめ複雑な前処理回路を必要とドアていた。
As mentioned above, if you amplify Vo and directly input it to the CCD delay line, you will be limited by the dynamic range of the CCD delay line. Processing to pass. This door required a complicated preprocessing circuit.

本発明の目的は前記従来の欠点を除去した新しい電荷結
合素子の出力構造を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a new charge-coupled device output structure that eliminates the above-mentioned drawbacks of the prior art.

本発明によれば、−導電型を有する半導体基板上に形成
され、該半導体基板と反対導電型を有する半導体領域内
に該半導体領域と反対導電型を有する浮遊拡散層と該拡
散層に隣接して設けられたゲート′邂極と、該ゲート電
極に隣接して設けられたイアスする手段とを含む電荷結
合素子の出力構造において、前記浮遊拡散層が形成され
る前記半導体領域が前記逆バイアスする手段によって完
全に空乏化されるように構成されていることを特徴とす
る電荷結合素子の出力構造が得られる。
According to the present invention, - a floating diffusion layer formed on a semiconductor substrate having a conductivity type, in a semiconductor region having a conductivity type opposite to that of the semiconductor substrate, and a floating diffusion layer having a conductivity type opposite to that of the semiconductor region; In the output structure of a charge-coupled device, the semiconductor region in which the floating diffusion layer is formed is reverse-biased. An output structure of a charge-coupled device is obtained, which is characterized in that it is configured to be completely depleted by the means.

以下、本発明について図面を用いて詳細に説明する。Hereinafter, the present invention will be explained in detail using the drawings.

第3図は本発明による一実施例を示し素子出力部の断面
図を示す。第3図において第1図と異なる点は、素子が
N型基板21の上に形成きれた二つのP−wel 12
2.23上に形成されていることである。他の番号は第
1図に示すものと同一である。
FIG. 3 shows an embodiment according to the present invention and shows a sectional view of an element output section. The difference in FIG. 3 from FIG. 1 is that the elements are two P-wells 12 completely formed on the N-type substrate 21
2.23. Other numbers are the same as shown in FIG.

まだ第3図におけるP−wel122は比較的浅く濃度
も薄くなるように形成され、P−wel123は比較的
深く濃度も濃くなるように形成される。
The P-well 122 in FIG. 3 is formed relatively shallow and has a low concentration, and the P-well 123 is formed relatively deep and has a high concentration.

P−wel123の濃度は第1図のP基板1と、はぼ深
さは1〜5μm程度である。P−well 22.23
と基板21との間には逆バイアス亀圧■subが印加さ
れP−wel122は完全に空乏化されるように設定さ
れる。つぎに本素子の動作について説明する。
The concentration of the P-well 123 is the same as that of the P substrate 1 in FIG. 1, and the depth is about 1 to 5 μm. P-well 22.23
A reverse bias torque sub is applied between the substrate 21 and the P-well 122, and the P-well 122 is set to be completely depleted. Next, the operation of this device will be explained.

第4図は楠々の動作状態における出力浮遊拡散層5直下
のポテンシャル分布を示す。
FIG. 4 shows the potential distribution directly under the output floating diffusion layer 5 in the operating state of Kusunoki.

カーブAは前記リセットパルス〆 によって出力部 浮遊拡散層5の電位がリセットされ■ となった几 状Itsを示す。すなわち出力浮遊拡散層5がCCDの
出力電圧の基準′電位となった状態である。
Curve A shows a truncated Its shape in which the potential of the output floating diffusion layer 5 is reset by the reset pulse. That is, the output floating diffusion layer 5 is at the reference potential of the output voltage of the CCD.

カーブBは転送されてきた信号電荷が出力浮遊拡散層5
に蓄積された状rc<を示す。このとき信号電荷量は比
較的少ない状態を示し、全て出力浮遊拡散層に蓄積され
ている。信号電荷の蓄積にともなって全体のポテンシャ
ル分布は浅くなり、カーブAとカーブBとのポテンシャ
ル差差■、が、と−のとき蓄積された信号電荷量に比例
する。したがってこの値を通常の出力バッファアンプに
より検知すれば、出力′電圧を得ることができる。さら
シこ信号電荷が蓄積されるとポテンシャル分布はカーブ
Cのように浅くなる。このとき出力浮遊拡散層直下のP
−wellの濃度および深さを前記したような値に設定
すると、P−wel122の電位と出力浮遊拡散層5の
電位との差が小さくなり過剰な信号電荷は基板へ掃きだ
されてします。このと1!蓄積される信号電荷の量は、
第4図に示すポテンシャル差v2に対応する。したがっ
てCCDから転送されてくる信号電荷の量が、この■2
を越える桂度に大きければ、そrし以上の電荷は出力浮
遊拡散層に蓄積されず、全てv2に対ル6する値にクリ
ップされる。さらに前記過剰なな荷が基板へ掃き出され
るために必要なP−wel122の電位の値は前記基板
に印加される逆バイアス電圧vsubによって制御する
ことができる。”  −”      sub′丁  
−°       したがって、とのVsubの埴を変
えることにより前記最大Ye QSI ”J能な電荷の
ロチるいはV2の値を制御することもできる。このよう
に本発明てよれば、素子内部において最大出力信号電圧
の値を制御できるために従来のような外部周辺回路によ
るり、リップ操作を必要とせず、CCD固体撮像素子を
用いたカメラ装置を作ろうとする場合にシステム全体を
簡略化できる。
Curve B shows that the transferred signal charge is transferred to the output floating diffusion layer 5.
The accumulated state rc< is shown. At this time, the amount of signal charge is relatively small, and all of it is accumulated in the output floating diffusion layer. As signal charges are accumulated, the overall potential distribution becomes shallower, and when the potential difference (2) between curve A and curve B is and -, it is proportional to the amount of accumulated signal charges. Therefore, by detecting this value with a normal output buffer amplifier, the output voltage can be obtained. As more signal charges are accumulated, the potential distribution becomes shallower as shown by curve C. At this time, P directly below the output floating diffusion layer
If the concentration and depth of the -well are set to the values described above, the difference between the potential of the P-well 122 and the potential of the output floating diffusion layer 5 will become smaller, and excess signal charges will be swept out to the substrate. This and 1! The amount of signal charge accumulated is
This corresponds to the potential difference v2 shown in FIG. Therefore, the amount of signal charge transferred from the CCD is
If the magnitude is greater than V2, no more charge will be accumulated in the output floating diffusion layer, and it will all be clipped to a value equal to v2. Furthermore, the value of the potential of the P-well 122 necessary for sweeping out the excess load to the substrate can be controlled by the reverse bias voltage vsub applied to the substrate. ”-” sub′d
-° Therefore, by changing the value of Vsub, it is possible to control the amount of charge that can be achieved by the maximum Ye QSI, or the value of V2.As described above, according to the present invention, the maximum output inside the element can be controlled. Since the value of the signal voltage can be controlled, there is no need for conventional external peripheral circuits or lip operations, and the entire system can be simplified when creating a camera device using a CCD solid-state image sensor.

(以 下 余 白)(Hereafter, extra white)

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のCCD固体撮像素子の出力部近傍の断面
図、第2図は本素子の駆動波形の一例、第3図は本発明
による電荷結合素子の出力構造の一実施例、第4図は出
力浮遊拡散層直下のポテンシャル分布を示す。 図において、1は一導電に型を有する半導体基板2は1
と反対導電型を有する半導体領域、3はチャネルストッ
パー、4は酸化膜、5.6は半導体基板1と反対導電型
を有する心敗層、7〜10はCCDの転送電極、11は
リセットゲート電極、12は拡散層6の端子、13は4
+七ツトゲー)11の端子、14〜17は転送・成極7
〜10の端子、21は一導電型を有する半導体基板、2
2.23は半導体基板21と反対導電型を有する半導体
領域である。 第1図
FIG. 1 is a cross-sectional view of the vicinity of the output part of a conventional CCD solid-state image sensor, FIG. 2 is an example of the driving waveform of this device, FIG. 3 is an example of the output structure of the charge-coupled device according to the present invention, and FIG. The figure shows the potential distribution directly under the output floating diffusion layer. In the figure, 1 is a semiconductor substrate 2 having a conductivity type.
3 is a channel stopper, 4 is an oxide film, 5.6 is a failure layer having a conductivity type opposite to that of the semiconductor substrate 1, 7 to 10 are CCD transfer electrodes, and 11 is a reset gate electrode. , 12 is the terminal of the diffusion layer 6, 13 is the terminal of 4
+ Seven Toge) 11 terminals, 14 to 17 are transfer/polarization 7
~10 terminals, 21 is a semiconductor substrate having one conductivity type, 2
2.23 is a semiconductor region having a conductivity type opposite to that of the semiconductor substrate 21; Figure 1

Claims (1)

【特許請求の範囲】[Claims] 一導電型を有する半導体基板上に形成され、該半導体基
板と反対導電型を有する半導体領域内に該半導体領域と
反対導電型を有する浮遊坪赦層と該拡散層に隣接して設
けられたゲート電極と、該ゲート電極に隣接して設けら
れた前記半導体領域と反対導電型を有する拡散層とを具
え、前記半導体基板と前記半導体領域とを逆バイアスす
る手段とを含む電荷結合素子の出力構造において、前記
浮遊拡散層が形成される前記半導体領域が前記逆バイア
スする手段によって完全に空乏化されるように構成され
ていることを特徴とする電荷結合素子の出力構造。
A floating layer formed on a semiconductor substrate having one conductivity type and having a conductivity type opposite to that of the semiconductor region in a semiconductor region having a conductivity type opposite to that of the semiconductor region, and a gate provided adjacent to the diffusion layer. An output structure for a charge coupled device, comprising: an electrode; and a diffusion layer having a conductivity type opposite to that of the semiconductor region provided adjacent to the gate electrode; and means for reverse biasing the semiconductor substrate and the semiconductor region. An output structure of a charge coupled device according to claim 1, wherein the semiconductor region in which the floating diffusion layer is formed is completely depleted by the reverse biasing means.
JP57175013A 1982-10-05 1982-10-05 Output structure of charge coupled device Pending JPS5965470A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57175013A JPS5965470A (en) 1982-10-05 1982-10-05 Output structure of charge coupled device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57175013A JPS5965470A (en) 1982-10-05 1982-10-05 Output structure of charge coupled device

Publications (1)

Publication Number Publication Date
JPS5965470A true JPS5965470A (en) 1984-04-13

Family

ID=15988685

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57175013A Pending JPS5965470A (en) 1982-10-05 1982-10-05 Output structure of charge coupled device

Country Status (1)

Country Link
JP (1) JPS5965470A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5068736A (en) * 1988-09-20 1991-11-26 Sony Corporation Solid state imaging device which has a short time constant which is shorter than the application of a pulse voltage until the end of the blanking period
US5103278A (en) * 1989-02-11 1992-04-07 Nec Corporation Charge transfer device achieving a high charge transfer efficiency by forming a potential well gradient under an output-gate area
US5192990A (en) * 1986-09-18 1993-03-09 Eastman Kodak Company Output circuit for image sensor
US5221852A (en) * 1991-02-01 1993-06-22 Fujitsu Limited Charge coupled device and method of producing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5724576A (en) * 1980-07-22 1982-02-09 Toshiba Corp Solid state image pick up device
JPS5755672A (en) * 1980-09-19 1982-04-02 Nec Corp Solid-state image pickup device and its driving method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5724576A (en) * 1980-07-22 1982-02-09 Toshiba Corp Solid state image pick up device
JPS5755672A (en) * 1980-09-19 1982-04-02 Nec Corp Solid-state image pickup device and its driving method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5192990A (en) * 1986-09-18 1993-03-09 Eastman Kodak Company Output circuit for image sensor
US5068736A (en) * 1988-09-20 1991-11-26 Sony Corporation Solid state imaging device which has a short time constant which is shorter than the application of a pulse voltage until the end of the blanking period
US5103278A (en) * 1989-02-11 1992-04-07 Nec Corporation Charge transfer device achieving a high charge transfer efficiency by forming a potential well gradient under an output-gate area
US5221852A (en) * 1991-02-01 1993-06-22 Fujitsu Limited Charge coupled device and method of producing the same

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