JPS5965470A - Output structure of charge coupled device - Google Patents

Abstract

PURPOSE:To enable to simplify the entire system of the titled output structure by a method wherein the semiconductor region, where a floating diffusion layer will be formed, is constituted in such a manner that it is completely deplated by an invertedly biasing means, thereby enabling to control the value of maximum output signal voltage in the interior of the device and to unnecessitate a clipping operation. CONSTITUTION:The point differing from the conventional structure is that the device is formed on the two P-wells 22 and 23 provided on an N type substrate 21. Also, the P-well 22 is formed relatively in shallow depth and in thin density, and the P-well 23 is formed relatively deeply and in thick density. The density of the P-well 23 is almost same as that of the conventional P-substrate 1, and the density of the P-well 22 is approximately 10<15>/cm<3> and the depth is 1-5mum or thereabout. An inverted bias voltage Vsub is applied between the P-wells 21 and 23 and the substrate 21, and the P-well 22 is formed in such a manner that it is depleted completely.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output structure of a charge coupled device (hereinafter referred to as COD).

COD is! Since it was announced in 1970, it has been rapidly developed based on conventional advanced integrated circuit technology, and in recent years has been used for various applications such as solid-state imaging, analog delay lines, and memory. became. Especially COD
Similar to MOS type solid-state image sensors, solid-state image sensors using MOS image sensors have many features such as low power consumption, small size and light weight, and can be highly integrated, and their development has been active in recent years. By the way, CC,
In a single-chip color camera using D, pixel interpolation is performed in the vertical direction using a CCD delay line in order to improve the resolution in the horizontal direction. At this time, the output signal of the COD solid-state image element is once amplified to prevent S/N deterioration in the delay line and then input to the delay edge. The amplification degree at this time is usually about 10 dB. By the way, the output signal voltage from the CCD image sensor varies by several mV depending on the incident light intensity.
It varies from about 1■. Therefore, if this signal voltage is amplified and input directly to the CC1) delay line, it will be restricted by the dynamic range of the CC1) delay line, causing problems such as distortion of the video signal at large signal voltages. For this reason, conventionally, after amplifying the output signal voltage from the image sensor, it is first passed through a clip circuit [7
This required complex peripheral circuitry, such as inputting it into a delay line to prevent the signal voltage from becoming unnecessarily thick.

FIG. 1 shows a cross-sectional view of the vicinity of the output section of a conventional COD solid-state image sensor. 1 is a semiconductor substrate having one conductivity type, and 2 is a semiconductor layer having a conductivity type opposite to that of the semiconductor substrate 1, forming a buried channel. 3 is a channel stopper, 4 is an oxide film, 5 is an output floating diffusion layer having a conductivity type opposite to that of the semiconductor substrate 1, and 6 is a diffusion layer having a conductivity type opposite to that of the semiconductor substrate 1, which is called a reset drain. 7 to 9 are transfer electrodes of the CCD, IO is an output gate electrode, 11 is a reset gate electrode, 12 is a terminal of the reset drain 6, 13 is a terminal of the reset gate electrode 11, 14 is a terminal of the output gate electrode 10, 15-17 is a terminal group of transfer electrodes 7 to 9 of the CCD. Figure 2 shows pulse waveforms 01 to 04 applied to this element.
, 0 representative example and output power signal waveform■. It shows about UT. Next, the operation of this element will be explained. First, reset gate 11
Apply Barsuda to . As a result, the area immediately below the conductor 11 becomes conductive, and the output floating diffusion layer 5 is set to the same potential as the reset drain 6, and the output waveform becomes the potential shown by 1'LD in FIG. Next, reset pulser 11. is in the off state, but the transient change to the input of the reset pulse at this time is a feedthrough to the output floating diffusion layer 5 via the parasitic capacitance existing between the reset gate 11 and the output floating diffusion layer 5. The resulting output waveform V 1 becomes the 'electrode shown in FIG. 2 as V 2 .

OUT R This potential becomes the reference potential for the output of the CCD.

Next, the signal charge, Nariko, is shown in Figure 2. When the signal charge is transferred from the right side to the left side in FIG. 1 and guided to the output floating diffusion layer 5, the potential of the output floating diffusion layer 5 changes in proportion to the amount of signal charge, and the output waveform . t
JT becomes ■0.

The difference between Vo and V at this time (■0) becomes the signal output.

In general, in individual imaging using a CCD in Yonago, the value of 0 varies from several mV to 1 〈.

As mentioned above, if you amplify Vo and directly input it to the CCD delay line, you will be limited by the dynamic range of the CCD delay line. Processing to pass. This door required a complicated preprocessing circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a new charge-coupled device output structure that eliminates the above-mentioned drawbacks of the prior art.

According to the present invention, - a floating diffusion layer formed on a semiconductor substrate having a conductivity type, in a semiconductor region having a conductivity type opposite to that of the semiconductor substrate, and a floating diffusion layer having a conductivity type opposite to that of the semiconductor region; In the output structure of a charge-coupled device, the semiconductor region in which the floating diffusion layer is formed is reverse-biased. An output structure of a charge-coupled device is obtained, which is characterized in that it is configured to be completely depleted by the means.

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 3 shows an embodiment according to the present invention and shows a sectional view of an element output section. The difference in FIG. 3 from FIG. 1 is that the elements are two P-wells 12 completely formed on the N-type substrate 21
2.23. Other numbers are the same as shown in FIG.

The P-well 122 in FIG. 3 is formed relatively shallow and has a low concentration, and the P-well 123 is formed relatively deep and has a high concentration.

The concentration of the P-well 123 is the same as that of the P substrate 1 in FIG. 1, and the depth is about 1 to 5 μm. P-well 22.23
A reverse bias torque sub is applied between the substrate 21 and the P-well 122, and the P-well 122 is set to be completely depleted. Next, the operation of this device will be explained.

FIG. 4 shows the potential distribution directly under the output floating diffusion layer 5 in the operating state of Kusunoki.

Curve A shows a truncated Its shape in which the potential of the output floating diffusion layer 5 is reset by the reset pulse. That is, the output floating diffusion layer 5 is at the reference potential of the output voltage of the CCD.

Curve B shows that the transferred signal charge is transferred to the output floating diffusion layer 5.
The accumulated state rc< is shown. At this time, the amount of signal charge is relatively small, and all of it is accumulated in the output floating diffusion layer. As signal charges are accumulated, the overall potential distribution becomes shallower, and when the potential difference (2) between curve A and curve B is and -, it is proportional to the amount of accumulated signal charges. Therefore, by detecting this value with a normal output buffer amplifier, the output voltage can be obtained. As more signal charges are accumulated, the potential distribution becomes shallower as shown by curve C. At this time, P directly below the output floating diffusion layer
If the concentration and depth of the -well are set to the values described above, the difference between the potential of the P-well 122 and the potential of the output floating diffusion layer 5 will become smaller, and excess signal charges will be swept out to the substrate. This and 1! The amount of signal charge accumulated is
This corresponds to the potential difference v2 shown in FIG. Therefore, the amount of signal charge transferred from the CCD is
If the magnitude is greater than V2, no more charge will be accumulated in the output floating diffusion layer, and it will all be clipped to a value equal to v2. Furthermore, the value of the potential of the P-well 122 necessary for sweeping out the excess load to the substrate can be controlled by the reverse bias voltage vsub applied to the substrate. ”-” sub′d
-° Therefore, by changing the value of Vsub, it is possible to control the amount of charge that can be achieved by the maximum Ye QSI, or the value of V2.As described above, according to the present invention, the maximum output inside the element can be controlled. Since the value of the signal voltage can be controlled, there is no need for conventional external peripheral circuits or lip operations, and the entire system can be simplified when creating a camera device using a CCD solid-state image sensor.

(Hereafter, extra white)

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the vicinity of the output part of a conventional CCD solid-state image sensor, FIG. 2 is an example of the driving waveform of this device, FIG. 3 is an example of the output structure of the charge-coupled device according to the present invention, and FIG. The figure shows the potential distribution directly under the output floating diffusion layer. In the figure, 1 is a semiconductor substrate 2 having a conductivity type.
3 is a channel stopper, 4 is an oxide film, 5.6 is a failure layer having a conductivity type opposite to that of the semiconductor substrate 1, 7 to 10 are CCD transfer electrodes, and 11 is a reset gate electrode. , 12 is the terminal of the diffusion layer 6, 13 is the terminal of 4
+ Seven Toge) 11 terminals, 14 to 17 are transfer/polarization 7
~10 terminals, 21 is a semiconductor substrate having one conductivity type, 2
2.23 is a semiconductor region having a conductivity type opposite to that of the semiconductor substrate 21; Figure 1

Claims (1)

[Claims] A floating layer formed on a semiconductor substrate having one conductivity type and having a conductivity type opposite to that of the semiconductor region in a semiconductor region having a conductivity type opposite to that of the semiconductor region, and a gate provided adjacent to the diffusion layer. An output structure for a charge coupled device, comprising: an electrode; and a diffusion layer having a conductivity type opposite to that of the semiconductor region provided adjacent to the gate electrode; and means for reverse biasing the semiconductor substrate and the semiconductor region. An output structure of a charge coupled device according to claim 1, wherein the semiconductor region in which the floating diffusion layer is formed is completely depleted by the reverse biasing means.