JP2986752B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit for transmitting and amplifying an analog signal, particularly to a signal output circuit in a CCD type solid-state image pickup device, and an improvement of a MOS transistor suitable for the circuit.

[0002]

2. Description of the Related Art Conventionally, a CCD solid-state imaging device has been widely used as a solid-state imaging device used in a home video camera or the like. Regarding this kind of CCD type solid-state imaging device, see “ISSC Digest”.
Pages 96 to 97 (1985) of ISSCC DIGEST OF TECHNICAL PAPERS, p.
pp. 96-97, 1985) and "Preprints of the National Convention of the Institute of Television Engineers of Japan 3-11, pp. 57-58; July 1983.
Moon ". The CCD type solid-state imaging device described in the above document has an element configuration called an interline type shown in FIG. 15, and its output circuit comprises a two-stage source follower circuit shown in FIG. Has a sectional structure shown in FIG.

In FIG. 15, reference numeral 151 denotes a photodiode for performing photoelectric conversion; 152 and 153, vertical and horizontal CCDs for transferring signal charges photoelectrically converted by the photodiodes; and 154, an output circuit for detecting and outputting signal charges. It is. The signal charges photoelectrically converted by the photodiode 151 are collectively sent to the vertical CCD 152, and then transferred to the horizontal CCD 153 line by line.
The data is sequentially transferred in the CD 153, converted into a voltage by the output circuit 154, and output to the outside of the element.

In FIG. 16, reference numerals 110 and 111 denote a driver transistor constituting a first-stage source follower, load transistors 112 and 113 denote a driver transistor constituting a next-stage source follower, respectively, and a load transistor 114 denotes a signal charge from the horizontal CCD 153. This is a reset transistor for resetting the transmitted floating diffusion layer 115 every transfer cycle of the horizontal CCD. VRD and ΦR are the floating diffusion layers 11 respectively.
5, reset voltage, reset pulse, VG is the gate voltage of the load transistor, VD is the power supply voltage of the output circuit, and the ground of the output circuit is equal to the voltage of the well in which the element is formed.

The signal charge is supplied from the horizontal CCD to the floating diffusion layer 11.
5 and the resulting potential change of the floating diffusion layer 115 is detected by the first-stage source follower including the transistors 110 and 111, and the transistors 112 and 11
3 is output to the outside by a next-stage source follower. Next, the reset pulse ΦR is input to the gate of the reset transistor 114, and the floating diffusion layer 115 is reset to the reset voltage VRD. The above operation is repeated, and signals are sequentially output.

FIG. 17 is a sectional view showing a BB ′ portion of the first-stage source follower driver transistor 110 of FIG. 16, and shows a p-well 2 formed on an n-type substrate 27.
A polysilicon gate 116 is formed on 6, and an n + diffusion layer 24 serving as a drain and an n + diffusion layer 23 serving as a source are formed in self-alignment with the polysilicon gate 116.

[0007]

In the prior art, since the power supply voltage of the output circuit 154 is high, a transistor having a short channel length cannot be used from the viewpoint of the withstand voltage of the transistors constituting the circuit. Therefore, there is a problem that the output circuit has a lot of noise and consumes a large amount of power. That is, the vertical CCD 15 used in the above prior art is used.
The horizontal CCD 153 and the horizontal CCD 153 form a well having a potential lower than the potential of the semiconductor substrate on the surface of the semiconductor substrate structurally connected to the p well 26 in FIG. 17 and sequentially transfer signal charges through the well. The principle. Therefore, the reset voltage VR of the floating diffusion layer 115 of the output circuit is transferred to transfer the electric charge from the potential well of the horizontal CCD 153.
D and the power supply voltage VD of the output circuit having the floating diffusion layer 115 as an input terminal are about 13 V. Since the ground potential of the output circuit is the same as that of the substrate (p well 26 in FIG. 17), a high voltage of 13 V is applied between the source and drain of each transistor constituting the output circuit when the power is turned on or off. In some cases. Further, even during the operation of the element, a high voltage of about 7 V is applied between the source and the drain of each transistor constituting the output circuit.

On the other hand, the withstand voltage characteristics between the source and the drain of the driver transistor of such a CCD output circuit are shown in FIG.
As shown in FIG. That is, FIG. 18 illustrates the withstand voltage characteristics between the source and the drain with the channel length of the gate electrode as the horizontal axis and the voltage between the source and drain as the vertical axis. In the figure, a characteristic (1) is a withstand voltage characteristic determined by the reliability. In order to obtain a normal reliability intended by this characteristic, it is necessary to operate with a source-drain voltage below the characteristic curve for each channel length. Indicates that it is necessary to The characteristic (2) is an instantaneous maximum allowable breakdown voltage characteristic between the source and the drain, and indicates that the transistor may be destroyed when a voltage exceeding the characteristic curve is instantaneously applied between the source and the drain. Further, FIG. 5 shows the level of the above-mentioned operating voltage of 7 V and the maximum voltage of 13 V which is instantaneously applied when the power is turned on, as the voltage applied between the source and drain of the driver transistor. As can be seen from this figure, the channel length of the transistor must be 3 μm or more in order to prevent a breakdown voltage failure due to the characteristic (2) and to prevent long-term reliability degradation due to the characteristic (1). there were.

Returning to FIGS. 15 and 16, the noise of the conventional example is mainly generated in the output circuit 154.
The noise of the output circuit includes reset noise generated by the thermal noise of the reset transistor 114, 1 / f noise of the transistors included in the output circuit, and thermal noise. Of these three components, the reset noise and 1 / f noise can be reduced to a negligible value compared to the thermal noise by the correlated double sampling method. The component of the thermal noise generated in the next-stage source follower can be designed to have a negligible value compared to the component generated in the first-stage source follower. On the other hand, according to the knowledge of the authors, the signal-to-noise ratio due to the thermal noise of the first-stage source follower is best when the gate capacitance of the driver transistor 110 is equal to the parasitic capacitance associated with the floating diffusion layer 115. On the other hand, under this condition, the signal-to-noise ratio is almost inversely proportional to the channel length of the driver transistor 110. That is, from this viewpoint, it is better to shorten the channel length.
However, for the reason of the withstand voltage described above, there is a lower limit to the shortening of the channel, and thus an upper limit of the signal-to-noise ratio of the element has been generated.

In addition, the power consumption of the above-mentioned prior art is a horizontal C
It is generated by the CD 153 and the output circuit 154. Output circuit 15
In No. 4, it mainly occurs in the next-stage sofollower which needs to drive a large capacity of about 10 pf outside the element at high speed.
The cutoff frequency of this circuit is inversely proportional to the 乗 power of the channel length of the next-stage source follower driver transistor 112, and is proportional to the 幅 power of the channel width and the through current. The power consumption is proportional to a value obtained by subtracting the ground voltage 0v from the power supply voltage VD and the through current. By the way, the next-stage source follower driver transistor 112 is a load of the first-stage source follower, and an upper limit is imposed on the gate area in order to obtain required frequency characteristics. As a result, using the minimum channel length that can be tolerated from the breakdown voltage,
The upper limit of the channel width is determined. Therefore, in order to obtain a desired frequency characteristic, the through current must be increased, and the power consumption was large.

In the above-mentioned prior art, an example of a CCD type solid-state imaging device has been described. However, two problems concerning noise and power consumption due to the above-described restriction on withstand voltage are the conventional charge transfer devices requiring low noise and low power consumption. This was a problem for the entire output circuit. Further, in the above conventional example, the example of the source follower circuit has been described, but a similar problem occurs regardless of the circuit form as long as the voltage change of the floating detection node due to the signal charge is detected and output by the MOS transistor. .

Further, in an analog integrated circuit using a power supply voltage of 5 V, when the channel length is shortened, the influence of the voltage on the drain side affects the source side, so that the drain conductance increases and the gain of the amplifier decreases. There was a problem.

An object of the present invention is to provide a CCD solid-state imaging device,
More generally, it is to improve the signal to noise ratio of the output circuit of the charge transfer device. Another object of the present invention is to provide a CCD
An object of the present invention is to reduce power consumption of an output circuit of a solid-state imaging device, more generally, a charge transfer device. Still another object of the present invention is to improve the gain of an amplifier constituting an analog integrated circuit. In addition, M
An object is to provide an OS transistor.

[0014]

In order to achieve the above object, according to the present invention, a charge transfer device and a floating detection node to which signal charges are sequentially transferred from the charge transfer device are provided on the same semiconductor substrate. In a semiconductor device provided with reset means for resetting the floating detection node every transfer cycle of each signal, and an output circuit connected to the floating detection node, the output circuit may be connected to an input of the floating detection node. Source follower circuit, a coupling capacitor having one end connected to the output of the source follower circuit, an inverting amplifier circuit having an input connected to the other end of the coupling capacitor, and an input terminal connected to the input of the inverting amplifier circuit. And bias setting means.

The bias setting means is a switching element connected between the input and the output of the inverting amplifier circuit. The bias setting means sets a bias voltage of the input of the inverting amplifier circuit immediately before the signal charge is transferred to the floating detection node in each transfer cycle of the signal charge. The above configuration corresponds to, for example, an eighth embodiment shown in FIG. 10 described later.

According to the above arrangement, it is possible to provide an output circuit of a charge transfer device (CCD type solid-state imaging device) having a large signal voltage amplitude outputted to the outside of the device. As a result, the signal to noise ratio of the output circuit is improved. I can do it. According to a third aspect of the present invention, there is provided a conventional device in which the input bias voltage of the inverting amplifier circuit is set immediately before the signal charge is transferred to the floating detection node in each transfer cycle of the signal charge. The clamping function of the correlated double sampling method, which was performed externally, can be performed in the element.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
3 will be described with reference to FIG. In this embodiment, in a MOS transistor, a gate electrode is used as a first gate electrode, a second gate electrode is provided on the drain side, and the first gate electrode and the second gate electrode are partially formed as an insulating layer. This is an example in which an MOS transistor is provided with an overlap via a gate, and an example in which the MOS transistor is used in a CCD type solid-state imaging device output circuit. FIG.
FIG. 2 is a cross-sectional structural view of a MOS transistor according to the first embodiment, FIG. 2 is a circuit configuration diagram of an output circuit according to the first embodiment,
FIG. 3 is a diagram showing a proper operation range of the gate voltage of the buffer transistor 1 of FIG. In addition, FIG. 1 is FIG.
This is also the cross-sectional structure of the portion.

In the MOS transistor of FIG. 1, a first-layer polysilicon gate electrode 22 as a first gate electrode is provided on a p-well 26 and a p + well 25 on an n-type substrate 27.
A second-layer polysilicon gate electrode 21 serving as a second gate electrode is formed so as to partially overlap with this via an insulating layer, and further an n + diffusion layer 24 serving as a drain and an n + diffusion layer 23 serving as a source are formed. Is provided.

The channels under the polysilicon gate electrodes of the first layer and the second layer are formed so as to be in contact with each other between the source and the drain. L in the drawing indicates the channel length on the first layer polysilicon gate electrode side. Therefore, the distance between the gate electrode and the drain diffusion layer corresponds to the channel length on the side of the second-layer polysilicon gate electrode. Each MOS transistor is formed below these gate electrodes. The source-drain voltage is shared by these two channel length regions. Therefore, the drain electric field can be easily reduced by setting the interval between the source and the drain to a desired value.

In FIG. 2, similarly to FIG. 15, the output circuit is composed of two stages of source followers, 2 and 3 are driver transistors and load transistors which constitute the first stage source follower, and 4 and 5 are the next stage source followers, respectively. A driver transistor and a load transistor 6 constituting a follower are reset transistors for resetting the floating diffusion layer 115 to which the signal charge is sent from the horizontal CCD 153 every transfer cycle of the horizontal CCD. Also,
VRD, ΦR, VG, and VD are the same as those in FIG. Reference numeral 1 denotes a buffer transistor for weakening the electric field on the drain side of the first-stage source follower driver transistor 2;
Is a DC gate voltage of the buffer transistor 1.
Further, a thick line in the drawing indicates that the transistor is a depletion type. The operation of this circuit is the same as in FIG. The gate electrode of the first stage source follower driver transistor of FIG. 2 is the first layer polysilicon gate electrode 22 of FIG. 1, and the gate electrode of the buffer transistor of FIG. 2 is the second layer polysilicon gate electrode 21 of FIG.

FIG. 3 is a diagram showing an appropriate operating range of the DC gate voltage VTG of the buffer transistor 1. In the figure, V
thTG and VthD are the threshold voltages of the buffer transistor 1 and the first-stage source follower driver transistor 2, respectively, β, L, and W are the drain conductance constant, channel length, and channel width of the buffer transistor 1, respectively, and I is the through current of the first-stage source follower. It is. In order to prevent the first-stage source follower driver transistor 2 from saturating and deteriorating the transconductance of the first-stage source follower driver transistor 2, the DC voltage of the buffer transistor 1 is changed with respect to the reset voltage which is the gate voltage of the first-stage source follower driver transistor 2. The voltage VTG is a voltage higher than the straight line A in the figure. In addition, the DC gate voltage VTG of the buffer transistor 1 is set to be lower than the power supply voltage VD than the straight line B in the figure so that the buffer transistor 1 operates in saturation and a strong relaxation effect of the drain electric field is obtained.

According to the present embodiment, the drain electric field of the first-stage source follower driver transistor 2 is reduced,
Therefore, the withstand voltage of the transistor can be improved. Therefore, the first-stage source follower driver transistor 2 can be shortened, thereby realizing a CCD solid-state imaging device having a high signal-to-noise ratio. In addition, the drain conductance of the first-stage source follower driver transistor can be reduced by relaxing the drain electric field, and an output circuit of a CCD solid-state imaging device having a high voltage gain can be provided.

In this embodiment, the case where both the buffer transistor 1 and the first-stage source follower driver transistor 2 are n-channel transistors has been described, but the same applies to the case of p-channel transistors. Further, in the present embodiment, the case where both the buffer transistor 1 and the first-stage source follower driver transistor 2 are of the enhancement type has been described, but the same applies to both of the depletion type and the depletion type.

In the present embodiment, a case where the buffer transistor 1 of the first-stage source follower driver transistor 2 and the first-stage source follower driver transistor 2 are formed on the p-well 26 and the p + well 25 on the n-type substrate 27 is described. As described above, it goes without saying that the present invention can be implemented regardless of the substrate structure. Although the case of the source follower has been described in the present embodiment, the present invention has the same effect even with another circuit configuration such as an inverter. Further, the present embodiment is effective not only for the output circuit of the CCD type solid-state imaging device but also for the noise reduction and the high voltage gain of the output circuit of the charge transfer device. Further, by using a MOS transistor having a first gate electrode, a first gate electrode, and a second gate electrode whose channels are connected by a depletion layer, the gain of the analog integrated circuit can be increased.

(Second Embodiment) FIG. 4 is a sectional structural view of another embodiment of a MOS transistor. In FIG. 4, a small gap is provided between the first gate electrode and the second gate electrode as compared with the length of the gate electrode, and channels below both electrodes are formed so as to be connected between the source and the drain. If the gap is very small, such a channel can be formed. The effect of weakening the drain electric field is the same as that of FIG. Note that L in the drawing indicates the channel length on the first-layer polysilicon gate electrode side. When this embodiment is used for the first-stage source follower in FIG. 2 as an example of a semiconductor device, the cross-sectional view in FIG. 4 is also a cross-sectional structural view of a portion corresponding to AA ′ in FIG. In this case, in FIGS. 4 and 2, 22 to 27 are the same as in FIG. 2, and 28 is a first-layer polysilicon 2 serving as a gate electrode of the first-stage source follower driver transistor 2.
2 and a first-layer polysilicon gate electrode provided as a gate electrode of the buffer transistor 1 provided through a minute gap. No diffusion layer is formed between the two polysilicon electrodes.

According to the present embodiment, the same effect as in the first embodiment can be obtained only by forming one polysilicon layer without overlapping the polysilicon layers as in the first embodiment. Can be obtained, and the manufacturing process can be simplified.

(Third Embodiment) The embodiment shown in FIG. 5 is an output circuit of a CCD solid-state imaging device in which a second gate electrode is connected to a drain point in the first embodiment. 1 to 6, 153, 115 in the figure, VRD, Φ
R, VG, and VD are the same as in FIG. The gate terminal of buffer transistor 1 is connected to power supply voltage VD. As a result, the number of pins can be reduced. In order to satisfy the condition of the straight line B described in FIG.
Has a positive threshold voltage.

(Fourth Embodiment) FIG. 6 shows that a second gate electrode is provided on the drain side of a MOS transistor whose gate electrode is connected to a floating detection node whose voltage changes according to a signal charge. FIG. 4 is an output circuit configuration diagram of a CCD solid-state imaging device in which is connected to an output point in an output circuit where a voltage change having the same polarity as a voltage change due to a signal charge of a floating detection node occurs. The reference numerals in the figure are the same as those in FIG. In the present embodiment, the potential change of the floating diffusion layer 115 due to the signal charge is detected by the first-stage source follower including the transistors 2 and 3 and is output to the outside of the element by the next-stage source follower including the transistors 4 and 5 and the buffer transistor It is transmitted to Gate 1. The change in the potential under the gate of the buffer transistor 1, which becomes the drain voltage of the first-stage source follower driver transistor 2, and the change in the potential of the output C of the first-stage source follower, which become the source voltage, have the same polarity. Can be prevented. As a result, even if the channel length of the first-stage source follower driver transistor 2 is shortened, long-term reliability does not deteriorate and the noise of the output circuit can be reduced. I can do it. Further, since the voltage between the source and the drain of the first-stage source follower driver transistor 2 can be kept substantially constant, the drain conductance on the circuit can be reduced and an output circuit of a CCD type solid-state imaging device having a high gain can be obtained.

In this embodiment, as in the first embodiment, the second gate electrode is partially connected to the first gate electrode connected to the floating detection node whose voltage changes due to the signal charge. Although the case where there is an overlap has been described, a similar effect can be obtained when both gates have no overlap and there is a diffusion layer between the two gates.

Further, also in the present embodiment, it is necessary to satisfy the condition of the straight line A described in FIG. For this,
In order to increase the output voltage VOUT of the next-stage source follower, which is the input voltage to the gate of the buffer transistor 1, the next-stage source follower driver transistor 4
It consists of a depletion transistor. In addition,
Such an operating point is set by setting the buffer transistor 1 to a depletion type, the first-stage source follower driver transistor 2 to an enhancement type, and setting VthTG-VthD
Can also be realized by setting a large negative value. Further, the present invention can be applied not only to the output circuit of the CCD solid-state imaging device but also to the reduction in noise, the increase in voltage and the gain of analog integrated circuits in the output circuit of the charge transfer device.

(Fifth Embodiment) In the fourth embodiment, the output voltage VOUT of the next-stage source follower becomes a high voltage, and a high voltage is applied between the source and the drain of the next-stage source follower load 5. Withstand voltage may be a problem. FIG. 7 shows that a next-stage high withstand voltage transistor 61 having a gate and a drain connected between a next-stage source follower driver transistor 4 serving as a driving stage of the buffer transistor 1 and a load transistor 5 is provided. FIG. 3 is a configuration diagram of an output circuit of a CCD solid-state imaging device with reduced voltage. Load transistor 5
Of the drain D is lower than VOUT by the gate-source voltage of the high breakdown voltage transistor 61. As a result, the withstand voltage of the load 5 does not matter.

Further, in the fourth embodiment, the C level is reduced due to the substrate effect of the driver transistor of the next-stage source follower.
The point and the voltage change of VOUT are not equal, and the voltage between the source and drain of the first-stage source follower driver transistor 2 is not completely constant. In the present embodiment,
Next stage source follower driver transistor 4 and next stage high breakdown voltage transistor 61 are replaced by next stage high breakdown voltage transistor 6
In the P-well connected to one source D, the substrate effect of the next-stage source follower driver transistor is reduced. As a result, the point C and the voltage change of VOUT become almost equal, and furthermore, the withstand voltage is improved and the drain conductance is reduced.

The present invention in which a high breakdown voltage transistor having a gate and a drain connected between a driver transistor and a load transistor is provided to reduce the voltage between the source and the drain of each transistor is described in the present embodiment. The present invention can be applied not only to the output circuit of the solid-state imaging device but also to an increase in the breakdown voltage of the analog integrated circuit of the output circuit of the charge transfer device.

(Sixth Embodiment) FIG. 8 shows a CCD type solid-state device in which a gate electrode and a second gate electrode whose channel is connected by a depletion layer are provided on the drain side of a MOS transistor for driving the outside of the device. FIG. 2 is an output circuit configuration diagram of an image sensor. The output circuit is composed of three stages of source followers commonly used in high-vision devices of about 2 million pixels, and includes 1 to 6, 153, 115, VRD, ΦR, V
G and VD are the same as those in FIG. 2, and reference numerals 71, 72, and 73 denote a buffer transistor, a driver transistor, and a load transistor, respectively, forming a final-stage source follower.
In the present embodiment, the next-stage source follower including the transistors 4 and 5 serves as a level shift for raising the low voltage level of the first-stage source follower to a voltage level appropriate for the operation of the last-stage source follower, and also has a large input capacitance. It is a buffer for driving the last-stage source follower. Due to the level shift, the next-stage source follower driver transistor 4 is a depletion type transistor.

According to the present embodiment, the buffer transistor 71 having the gate electrode provided on the drain side of the final driver transistor 72 for driving the outside of the element and the second gate electrode connected to the channel by the depletion layer. As a result, the drain electric field is weakened, the channel length of the final stage driver transistor 72 can be shortened, and an output circuit of a low power consumption CCD solid-state imaging device can be realized.

(Seventh Embodiment) In the three-stage source follower configuration described in the sixth embodiment, unnecessary power consumption occurs in the next-stage source follower. FIG.
This problem is caused by providing a next-stage source follower output transistor 81 having a gate and a drain connected between the next-stage source follower driver transistor 4 and the load transistor 5 and using the source of the next-stage source follower output transistor 81 as an output terminal. FIG. 4 is an output circuit configuration diagram of a CCD type solid-state imaging device that solves the above problem. 1 to 6, 15 in the figure
Reference numerals 3, 115, VRD, ΦR, VG, and VD are the same as those in FIG. 2, and reference numeral 81 denotes a next-stage source follower output transistor that drives the outside of the element. As in the fourth embodiment, the source of the next stage source follower driver transistor 4 is connected to the gate of the buffer transistor 1. Also,
As in the fifth embodiment, the next-stage source follower driver transistor 4 and the next-stage source follower output transistor 81 are formed in a P-well connected to VOUT.

The first-stage source follower including the transistors 1 to 3 first drives the next-stage source follower driver transistor 4 having a small gate capacitance, and then the next-stage source follower output transistor 81 drives a load external to the element. As a result, the next source follower
It is possible to have both a small input capacitance and a low impedance for driving the outside of the device, and it is possible to realize an output circuit of a low power consumption CCD solid-state imaging device with a two-stage source follower configuration. Note that the next-stage source follower output transistor 81 has the same effect as the next-stage high breakdown voltage transistor 61 in the fourth embodiment.

(Eighth Embodiment) In the three-stage source follower configuration described in the sixth embodiment, since the voltage gain of each source follower cannot be 1 or more, the signal voltage amplitude at the element output terminal Is small, which may cause a problem in signal processing outside the element. FIG. 10 is an output circuit configuration diagram of a CCD solid-state imaging device in which the signal voltage amplitude at the device output terminal is increased by using an inverter at the next stage. 1 to 3, 6, 153, 115 in the figure, VRD, Φ
R, VG, and VD are the same as those in FIG. 2, and reference numerals 91 and 92 denote driver transistors constituting a next-stage inverter, and load transistors 93, 94, and 95 denote driver transistors, output transistors, and loads constituting a final-stage source follower. A transistor 96 is an auto-bias transistor for self-biasing the next-stage inverter, and a reference numeral 97 is a coupling capacitance for transmitting the signal output of the first-stage source follower to the next-stage inverter. Also, a P-stage in which the last-stage source follower driver transistor 93 and the last-stage source follower output transistor 94 are connected to VOUT
Formed in the well to reduce the substrate effect.

Before the horizontal CCD 153 starts scanning one horizontal line (horizontal blanking period), the bias pulse Φ
B becomes a high voltage, the auto-bias transistor 96 conducts, and the next-stage inverter is self-biased to a high gain region. Next, when scanning starts, the signal output of the first-stage source follower is transmitted to the next-stage inverter via the coupling capacitor 97, the voltage amplitude is amplified, and the level is shifted by the last-stage source follower driver transistor 93. The output transistor 94 outputs the signal to the outside of the device. According to the present embodiment, it is possible to provide an output circuit of a CCD solid-state imaging device having a large signal voltage amplitude output to the outside of the device.

It should be noted that the bias pulse φB is a horizontal CCD
After the reset pulse ΦR is input for each transfer cycle, the voltage may be set to a high voltage immediately before the signal charge is transferred from the horizontal CCD 153 to the floating diffusion layer 115. By this operation, the clamping function of the correlated double sampling method conventionally performed outside the element can be performed inside the element.

(Ninth Embodiment) FIG. 11 is an output circuit configuration diagram of a CCD solid-state imaging device in which the ground potential of the output circuit is lower than the substrate potential on which the charge transfer device is formed. In the figure, 1 to 6, 153, 115, VRD, Φ
R, VG, VD, and VTG are the same as in FIG. The ground voltage VS of the output circuit is set to a potential higher than the P-well voltage 0v formed on the horizontal CCD 153.
As a result, the voltage applied to the first-stage source follower driver transistor 1 at the time of power-on, power-off, or operation is reduced, the electric field on the drain side is weakened, and even if the channel length is shortened, the withstand voltage between the source and drain and the long-term operation of the transistor become longer. The output circuit can be reduced in noise without deterioration in reliability.

(Tenth Embodiment) This embodiment is different from the tenth embodiment in that
At least a drain-side diffusion layer of a MOS transistor whose gate electrode is connected to a floating detection node whose voltage changes due to signal charge is formed at a certain distance from the gate electrode, and is the same as the diffusion layer between the diffusion layer and the gate electrode. 5 is an example of an output circuit of a CCD solid-state imaging device provided with a polar impurity layer having a lower concentration. FIG. 12 is a diagram showing a sectional structure view of a portion corresponding to BB ′ in FIG. 16, and FIG. 13 is a diagram showing a process for producing the structure of FIG. In FIG. 12, 2
3, 25 to 27 and 116 are the same as in FIG.
Is an offset drain diffusion layer formed at a fixed distance from the polysilicon gate 116, and 102 is a diffusion layer 1
01 and a lower concentration impurity layer having the same polarity as the diffusion layer provided between the polysilicon gate 116. For example, 1
01 has a concentration of 10 ²⁰ / cm ³ and a depth of 0.2 μm.
The impurity is As, and the concentration of the diffusion layer 102 is 5
× 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ , depth about 0.15 μm, and impurities are P.

The structure shown in FIG. 12 is a high withstand voltage structure of a MOS transistor widely used in a MOS memory or the like, but is not used in a conventional CCD solid-state imaging device. One reason is that the polysilicon gate 116
From since the offset drain diffusion layer is formed at a distance, it conventionally had with SIO ₂ film remains on the sidewalls of polysilicon gate 116 after dry-etched to form a uniform SIO ₂ film on the element It is in. That is, image quality deteriorates due to an increase in dark current and minute defects due to damage to the surface of the photodiode 151 due to dry etching, and the output circuit 154 of the CCD type solid-state image pickup device has not achieved the above structure. In this embodiment, the polysilicon gate 11 is formed by a photomask.
6, the above problem is solved by forming the offset drain diffusion layer 101 at a certain distance from the CC.
The above structure is realized by the output circuit 154 of the D-type solid-state imaging device. Hereinafter, the creation process will be described with reference to FIG.

After the polysilicon gate 116 is formed, the photoresist film 10 is formed on the drain side of the transistor.
3 and the polysilicon gate 116 as a mask, phosphorus is ion-implanted to form the low-concentration impurity layer 102.
(FIG. 13A) Next, on the drain side of the transistor, the photoresist film 92 formed between the polysilicon gate 116 and the distance X only and the photoresist 104 formed on the source side at a position as shown in the figure are used as masks. A
s is ion-implanted and the offset drain diffusion layer 101
And source diffusion layer 23 are formed. (FIG. 13 (b)) As described above, without any dry etching,
The above structure can be realized.

According to this embodiment, the electric field on the drain side of the MOS transistor whose gate electrode is connected to the floating detection node whose voltage changes by the signal charge of the output circuit of the CCD solid-state imaging device can be reduced. Even if the channel length of the MOS transistor is shortened, the breakdown voltage between the source and the drain and the long-term reliability of the transistor do not deteriorate, and the noise of the output circuit can be reduced.

In the method of the present embodiment,
The distance X must be increased in order to allow a margin for mask alignment. As a result, a large resistance of the low-concentration impurity layer occurs in the current path. However, in the present embodiment, by providing the offset structure only on the drain side, it is possible to avoid adverse effects such as deterioration of the transconductance.

Further, the present structure has a
It can also be realized by performing dry etching only in the output circuit section. Further, in this embodiment, the case of the n-channel transistor has been described, but the same applies to the case of the p-channel transistor. Furthermore, in the present embodiment, the case of the enhancement type has been described, but the same applies to the depletion type. In the case of the depletion type, the n− layer below the polysilicon gate 116 is provided so as to be connected to the offset drain diffusion layer 101, so that the low concentration impurity layer 102 may not be provided. Further, in the present embodiment, the case where the transistor is formed on the p well 26 and the p + well 25 on the n-type substrate 27 has been described.
It goes without saying that the present invention can be implemented without depending on the substrate structure.

(Eleventh Embodiment) FIG. 14 shows a MOS transistor having a gate electrode connected to a floating detection node whose voltage changes due to a signal charge, at least around a diffusion layer on the drain side of the MOS transistor having the same polarity as the diffusion layer. FIG. 17 is a sectional structural view of a portion corresponding to BB ′ of FIG. 16 of the output circuit of the CCD solid-state imaging device provided with a lower concentration impurity layer.
23 to 27 and 116 are the same as those in FIG.
Is a lower concentration double drain layer having the same polarity as the diffusion layer 24 provided around the drain diffusion layer 24. Here, for example, the concentration of 24 diffusion layers is 10 ²⁰ / cm ³ , and the depth is 0.2.
0.3 μm, the impurity is As, the concentration of the diffusion layer 105 is 5 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ , and the depth is 0.3 to
0.5 μm, the impurity is P.

According to the present embodiment, it is possible to reduce the electric field on the drain side of the MOS transistor whose gate electrode is connected to the floating detection node whose voltage changes by the signal charge of the output circuit of the CCD solid-state imaging device. Even if the channel length of the MOS transistor is shortened, the breakdown voltage between the source and the drain and the long-term reliability of the transistor do not deteriorate, and the noise of the output circuit can be reduced.

[0050]

According to the present invention, it is possible to provide an output circuit of a charge transfer device (CCD type solid-state imaging device) having a large signal voltage amplitude outputted to the outside of the device, and as a result, it is possible to improve a signal-to-noise ratio. The effect is obtained. Also,
By configuring the input bias voltage of the inverting amplifier circuit to set the bias voltage immediately before the signal charge is transferred to the floating detection node in each transfer cycle of the signal charge, the correlated double sampling method conventionally performed outside the element is used. The clamping function can be performed in the device.

Further, the CCD-type solid-state imaging device, generally, weakens the electric field on the drain side of the MOS transistor whose gate electrode is connected to the floating detection node where the voltage changes due to the signal charge of the output circuit of the charge transfer device, and reduces the electric potential between the source and the drain. , The channel length of the MOS transistor can be shortened from 3 μm or more to 1 μm or less, and the noise of the output circuit can be reduced to 1/3 or less.

Also, the electric field on the drain side of the MOS transistor for driving the outside of the element is weakened, and the channel length of the MOS transistor is reduced to 3 μm in the conventional MOS transistor without causing a withstand voltage defect between the source and the drain and deterioration of the long-term reliability of the transistor. From the above, it can be shortened to 1 micron or less, and the power consumption of the output circuit can be reduced to 1/3 or less.

Further, in an analog integrated circuit, the drain conductance of a transistor constituting the circuit can be reduced, and an amplifier having a high gain can be realized. In addition, a MOS transistor with a reduced drain electric field can be realized as a transistor suitable for reducing noise, reducing power consumption, or increasing gain in a semiconductor device having such a circuit.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of a MOS transistor according to a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a first embodiment of the semiconductor device of the present invention.

FIG. 3 is a characteristic diagram showing an optimum operation range of the circuit of FIG. 2;

FIG. 4 is a sectional view of a MOS transistor according to a second embodiment of the present invention.

FIG. 5 is a circuit configuration diagram of a third embodiment of the semiconductor device of the present invention.

FIG. 6 is a circuit diagram of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 7 is a circuit configuration diagram of a fifth embodiment of the semiconductor device of the present invention.

FIG. 8 is a circuit diagram of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 9 is a circuit diagram of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 10 is a circuit configuration diagram of an eighth embodiment of a semiconductor device according to the present invention.

FIG. 11 is a circuit configuration diagram of a ninth embodiment of the semiconductor device of the present invention.

FIG. 12 is a structural sectional view of a semiconductor device according to a tenth embodiment of the present invention;

FIG. 13 is a view showing a formation process of the structure shown in FIG. 12;

FIG. 14 is a structural sectional view of an eleventh embodiment of the semiconductor device of the present invention.

FIG. 15 is a block diagram showing an element configuration of a conventional example.

FIG. 16 is a circuit configuration diagram of an output circuit in FIG. 15;

FIG. 17 is a cross-sectional structural view of a conventional BB ′ part of FIG. 16;

FIG. 18 is a characteristic diagram for explaining a source-drain breakdown voltage characteristic with respect to a channel length of a driver transistor of a CCD output circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... First stage source follower buffer transistor 2 ... First stage source follower driver transistor 3 ... First stage source follower load transistor 4 ... Next stage source follower driver transistor 5 ... Next stage source follower load transistor 6 ... Reset transistor 21 ... Second layer polysilicon Gate electrodes 22, 28: first-layer polysilicon gate electrodes 23, 24: n + diffusion layer 25: p +
Well 26 p-well 27 n-type substrate VD output circuit power supply voltage VS output circuit ground voltage VOUT output voltage 61 next-stage high breakdown voltage transistor 71 final-stage source follower buffer transistor 81 next-stage source Follower output transistor 91 ... Next stage inverter load transistor 92 ... Next stage inverter driver transistor 94 ... Last stage source follower output transistor 96 ... Auto bias transistor 101 ... Offset drain diffusion layer 102 ... Low concentration impurity layer 104 ... photoresist film 105 ... double drain layer 115 ... floating diffusion layer 151 ... photodiode 152 ... vertical CCD 153 ... horizontal CCD 154 ... output circuit

Continuation of the front page (51) Int.Cl. ⁶ Identification symbol FI H04N 5/335 (72) Inventor Hideyuki Ono 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor Haruhiko Tanaka Tokyo 1-280 Higashi-Koigakubo, Tokyo-Kokubunji-shi Hitachi Central Research Laboratory, Inc. . ^6, DB name) H01L 27/14 - 27/148 H01L 29/762 - 29/768

Claims (3)

(57) [Claims] 1. A charge transfer device, a floating detection node to which signal charges are sequentially transferred from the charge transfer device, and reset means for resetting the floating detection node for each signal transfer cycle on the same semiconductor substrate. An output circuit connected to the floating detection node, wherein the output circuit is connected to a source follower circuit having an input connected to the floating detection node, and one end is connected to an output of the source follower circuit. A coupling capacitor, an inverting amplifier circuit having an input connected to the other end of the coupling capacitor, and bias setting means connected to an input of the inverting amplifier circuit. 2. The semiconductor device according to claim 1, wherein said bias setting means is a switching element connected between an input and an output of said inverting amplifier circuit. 3. The apparatus according to claim 1, wherein said bias setting means sets a bias voltage of an input of said inverting amplifier circuit immediately before a signal charge is transferred to a floating detection node in each transfer cycle of the signal charge. 3. The semiconductor device according to claim 1.