JP3302834B2 - Charge transfer method and device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer method and a device therefor, and is particularly suitable for a charge transfer section of a CCD image sensor.

[0002]

2. Description of the Related Art In recent years, a drive pulse of a CCD image sensor has been reduced in voltage.

FIG. 8A shows a longitudinal sectional structure of a signal charge transfer section in a conventional CCD image sensor. An n-type buried channel layer 1 is formed on the surface of p-type semiconductor substrate 50.
2 are provided. This n-type buried channel layer 12
A CCD register for sequentially transferring signal charges generated in a photosensitive pixel (not shown) is provided on the upper surface of the inside.

As a register two stages before the last stage, a p-type impurity region 11 formed as a barrier portion for preventing the stored signal charges from moving to another register, and storing the transferred signal charges. An n-type buried channel layer 12 formed as a storage portion to be formed, and a transfer electrode 6 formed on these regions via an insulating film (not shown) are provided.

Similarly, as a register one stage before the last stage, a p-type impurity region 10 formed as a barrier portion,
N-type buried channel layer 12 formed as a storage unit
And a transfer electrode 5 are provided. further,
A p-type impurity region 9, an n-type impurity region 51, and a transfer electrode 4 are formed as a final stage register.

An output gate electrode 3 is provided above the n-type impurity region 51 via an insulating film, adjacent to the final stage register. This output gate electrode 3 is grounded.
In the surface portion of the n-type buried channel layer 12, the charge detection section 7 and the reset drain 1 are formed at a fixed interval, and the n-type impurity between the charge detection section 7 and the reset drain 1 is formed. The reset gate 2 is provided above the region 51 via an insulating film. Here, the charge detection unit 7 and the reset drain 1 are formed as n ⁺ -type impurity regions in which n-type impurity ions are further implanted into the surface of the n-type impurity region 51. A positive power supply voltage is applied to the reset drain 1.

FIG. 8B shows a potential distribution in each region.
A drive pulse φ1 is applied to the transfer electrode 6 of the register two stages before the last stage, and the potential 62 of the n-type buried channel layer 12 and the potential 63 of the p-type impurity region 11 change as illustrated. The potential 62 of the n-type buried channel layer 12 corresponds to the potential in the storage section, and the potential 63 of the p-type impurity region 11 corresponds to the potential in the barrier section.

The transfer electrode 5 of the register immediately before the last stage
Is applied with a drive pulse φ2, and the potential 26 of the n-type buried channel layer 12 and the potential 27 of the p-type impurity region 10 are
It changes as shown in FIG.

A drive pulse φ1 is applied to the transfer electrode 4 of the last stage register. The potential 24 of the n-type impurity region 51 and the potential 61 of the p-type impurity region 52 of this final stage register
Changes as shown in FIG.

The ground voltage is applied to the output gate electrode 3 as described above. The potential 23 of the n-type impurity region 51 provided below the output gate electrode 3 is
It is fixed as shown in FIG.

A reset pulse RS is applied to the reset gate 2, and the potential 20 of the n-type impurity region 51 provided below the reset gate 2 changes as shown in FIG. Further, the potential 21 of the reset drain 1 adjacent to the reset gate 2 corresponds to a positive power supply voltage, and the potential 22 of the charge detection unit 7 changes according to the signal charge 100 or the potential of the reset gate electrode 2. That is, when the signal charge 100 is given to the charge detection unit 7, the potential 22 of this portion changes to a low level. When a positive reset pulse RS is applied to the reset gate electrode 2, the potential 22 of the charge detection unit 7 becomes equal to the potential 21 of the reset drain 1 and is initialized.

In such a potential distribution, the driving pulse φ
In order to lower the voltage of 1 and φ2, the potential 26 of the storage unit in the register one stage before the last stage, the potential 24 of the storage unit and the potential 61 of the barrier unit of the last stage register, and the potential 23 of the output gate unit Needs to be set so that the signal charge 100 can be transferred. As a result, as shown in FIG. 8B, when the potential 23 of the output gate section is set higher than the potentials 26 and 62 of the storage section when the CCD register is at a low level before the final stage. There is.

In such a case, as shown in FIG.
Drive pulse φ applied to transfer electrode 4 of the last stage register
If the time T2 required for the rise of 1 is shorter than the time T1 required for the fall of the drive pulse φ2 applied to the transfer electrode 5 of the register immediately before the last stage, the following problem occurs.

As shown in FIG. 10, before the potential 61 of the barrier section of the last stage register goes high, the potential 26 of the storage section of the register one stage before the last stage goes low first. As a result, the signal charge 100 stored in the storage unit of the register immediately before the last stage flows into the charge detection unit 7 through the barrier unit and the storage unit of the last stage register and the output gate unit. That is, the signal charge 100 is read forward by one pixel.

[0015]

As described above, an abnormal operation has conventionally occurred in which signal charges are advanced by one pixel and read out.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a charge transfer method and a device capable of normally transferring signal charges while reducing the voltage of a drive pulse. I do.

[0017]

According to the present invention, there is provided a charge transfer device, comprising: a storage section for receiving and storing a signal charge; and a barrier for preventing the signal charge stored in the storage section from moving to another adjacent area. A CCD register provided with a plurality of registers for transferring a signal charge by applying a drive pulse, a charge detection unit for receiving and detecting the signal charge transferred from the CCD register, and a reset pulse. And a reset gate for setting the charge detection unit to a predetermined state when the reset pulse is supplied to the barrier unit of the last stage register in the CCD register. It is characterized in that a short pulse is applied.

Here, an impurity region of the same conductivity type as the barrier portion of the last stage register is formed between the last stage register in the CCD register and the register one stage before the last stage register. A pulse having the same period as the reset pulse and a shorter high-level period than the drive pulse may be applied.

[0019]

According to the charge transfer method of the present invention, there is provided a register having a storage section for storing a given signal charge, and a barrier section for preventing the signal charge stored in the storage section from moving to another adjacent area. Is provided with a drive pulse to a CCD register provided with a plurality of stages to transfer signal charges,
A method for detecting a signal charge transferred from a register by a charge detection unit and applying a reset pulse to a reset gate to set the charge detection unit to a predetermined state;
Only in the barrier section of the last register in the D register,
A pulse having the same cycle as the reset pulse and having a shorter high-level period than the drive pulse is applied.

Alternatively, an impurity region of the same conductivity type as the barrier portion of the last stage register is formed between the last stage register in the CCD register and the register one stage before the last stage register. A method may be employed in which a pulse having the same cycle as the reset pulse and having a shorter high-level period than the drive pulse is applied.

[0022]

[0023]

When the signal charge stored in the storage unit of the register immediately before the last stage is transferred to the storage unit of the last stage register, the potential of the storage unit of the register immediately before the last stage becomes low. , The potential of the storage section of the last stage register increases.
At this time, if the potential of the barrier section of the last-stage register becomes high similarly to the potential of the storage section, there is a possibility that the signal charge jumps over the storage section of the last-stage register and is forwarded to the charge detection section. On the other hand, in the present invention, a pulse having the same cycle as the reset pulse and having a shorter high-level period than the drive pulse is applied only to the barrier section of the final register in the CCD register, so that the barrier section of the final register is The potential is set to a low potential, and the barrier portion serves as a wall to prevent signal charges from being transferred to the charge detection portion. Next, the potential of the barrier section of the final stage register changes as high as the accumulation section, and the signal charges accumulated in the accumulation section of the register immediately before the final stage are transferred to the accumulation section of the final stage register. You.

An impurity region of the same conductivity type as the barrier portion of the last stage register is formed between the last stage register and the register one stage before the last stage in the CCD register. When a pulse having a period and a high-level period shorter than the driving pulse is applied, the potential of the impurity region formed between the final stage register and the register immediately before the final stage is equal to the reset pulse. It changes according to a pulse having a period and a high-level period shorter than the drive pulse. As a result, when the potential of the storage unit of the last stage before the last stage decreases and the potential of the storage unit of the last stage register changes to a high level, the potential is formed between the last stage register and the register immediately before the last stage. The potential of the impurity region is in a low state, and this region serves as a wall, thereby preventing an operation in which the signal charge jumps over the accumulation section of the last stage register and is forward-transferred.

[0025]

[0026]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1A shows a sectional structure of a charge transfer device according to a first embodiment of the present invention. The structure of this embodiment is
It differs from the conventional structure shown in FIG. 8A in the following point.

A reset pulse RS is applied to the transfer electrode 16 provided on the p-type impurity region 10 corresponding to the barrier section of the final stage register, instead of the drive pulse φ1.
A drive pulse φ1 is applied to the transfer electrode 4 provided above the n-type buried channel layer 12 corresponding to the storage section of the final register. The other same components are denoted by the same reference numerals and description thereof is omitted.

FIG. 1 (b) shows a change in potential in each region as a potential distribution diagram. The change of the potential 25 of the barrier portion of the final register is different from that of FIG. This potential 25 changes with the reset pulse RS as described above. The potentials of the other regions are the same as those shown in FIG.

FIG. 2 shows a time chart of the drive pulses φ1 and φ2 and the reset pulse RS. The drive pulse φ1 and the drive pulse φ2 have a complementary relationship. The reset pulse RS is the same as that applied to the reset gate electrode 2. The high-level period of the reset pulse RS is set shorter than the period of the drive pulses φ1 and φ2.

The potential of each region is determined by driving pulses φ1 and φ2
3A to 3E in accordance with the reset pulse RS. Here, the potential distributions shown in FIGS. 3A to 3E respectively correspond to the times t1 to t in FIG.
5.

At time t1, the driving pulse φ1 is at a low level, the driving pulse φ2 is at a high level, and the reset pulse RS is at a low level. As shown in FIG. 3A, a high-level driving pulse φ2 is applied to the transfer electrode 5 of the register one stage before the last stage, and the potential 26 of the storage unit and the potential 27 of the barrier unit are both high. In state. Signal charge 10
0 is stored in the storage section of this register. A low-level drive pulse φ1 is applied to the transfer electrode 4 on the accumulation unit of the last-stage register, and a low-level reset pulse RS is applied to the transfer electrode 16 on the barrier unit of the last-stage register. As a result, the potential 24 of the storage section of the final stage register and the potential 25 of the barrier section are both low.

At time t2, the driving pulse φ1 changes to the high level, the driving pulse φ2 changes to the low level, and the reset pulse RS maintains the low level. As shown in FIG. 3B, a low-level drive pulse φ2 is applied to the transfer electrode 5 of the register one stage before the last stage, and the high-level drive pulse 4 is applied to the transfer electrode 4 on the storage unit of the last stage register. Drive pulse φ1
Is applied. The potential 26 of the storage unit and the potential 27 of the barrier unit of the register one stage before the last stage are both low. Further, the transfer electrode 16 on the barrier section of the last stage register
, A low-level reset pulse RS is applied, and the potential 25 at this portion remains low. A high-level drive pulse φ1 is applied to the transfer electrode 4 on the storage section of the last stage register.
Is applied, and the potential 24 of the storage section changes to a high level. At time t2, the potential 26 of the storage unit of the register one stage before the last stage becomes low, but the potential 25 of the barrier unit of the last stage register is lower than this potential 26. Therefore, the signal charge 1
00 does not move.

At time t3, drive pulse φ1 and drive pulse φ2 do not change from time t2. Reset pulse RS
Goes to a high level. As shown in FIG.
The potentials 26 and 27 of the storage unit and the barrier unit of the register one stage before the last stage maintain a low level. The potential 25 of the barrier section of the last-stage register changes high. The potential 24 of the storage section of this register is maintained at a high level. As a result, the signal charge 100 moves to the accumulation section of the final stage register.

When the reset pulse RS goes high, this high level voltage is applied to the reset gate electrode 2 in FIG. As a result, the potential 22 of the charge detection unit 7 becomes the same level as the positive power supply voltage of the reset drain 1.

At time t4, the driving pulse φ1 and the driving pulse φ2 do not change from time t2 and t3. The reset pulse RS changes to a low level. As shown in FIG. 3D, the potentials 26 and 27 of the storage unit and the barrier unit of the register one stage before the last stage continue to maintain a low level. The potential 24 of the storage section of the final stage register maintains a high level, and the potential 25 of the barrier section changes to a low level.

At time t5, the driving pulse φ1 changes to low level and the driving pulse φ2 changes to high level. The reset pulse RS maintains a low level. As shown in FIG. 3E, the potentials 26 and 27 of the storage unit and the barrier unit of the register immediately before the last stage change to a high level. The potential 24 of the storage section of the final stage register changes low, and the potential 25 of the barrier section maintains a low level. The signal charge 100 stored in the storage section of the last stage register moves to the charge detection section 7 and is read.

When the signal charge 100 is transferred from the storage unit of the register one stage before the last stage to the storage unit of the last stage register, the potential 26 of the storage unit of the register one stage before the last stage
Changes to low, and the potential 24 of the storage section of the final stage register changes to high. However, at this point, as shown in FIG.
Since RS is applied and the potential 25 at this portion is at a low level, an abnormal operation in which the signal charge 100 jumps over the accumulation section of the last-stage register and is transferred to the charge detection section 7 in advance is prevented. Thereafter, as shown in FIG. 3C, the potential 25 of the barrier section of the final stage register changes to a high level, and the signal charge 100
Is transferred to the storage section of the last stage register without any trouble.

Next, a second embodiment of the present invention will be described. In the first embodiment, the driving pulse φ1 is applied to the accumulation section of the final stage register, and the driving pulse φ1 is applied to the barrier section.
It is characterized in that a reset pulse RS is applied instead of. On the other hand, in the second embodiment, a barrier unit is provided between the register one stage before the last stage and the last stage register,
It is characterized in that a reset pulse RS is applied to this barrier section.

FIG. 4A shows a sectional structure of the charge transfer device according to the present embodiment. An n-type impurity region 31 is formed in the accumulation section of the final stage register, and a p-type impurity region 32 is formed in the barrier section. A drive pulse φ1 is applied to the transfer electrode 4 provided on the storage unit and the barrier unit.

A p-type impurity region 3 is provided in a barrier portion provided between the last stage register and the register immediately before the last stage.
2 are formed, and the transfer electrode 16 is formed on this region 32.
Is provided. A reset pulse RS is applied to the transfer electrode 16. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

FIG. 4B is a potential distribution diagram showing a change in potential of each region in this embodiment. Compared with the potential distribution in the first embodiment shown in FIG. 1B, the potential 25 of the barrier section of the final stage register changes with the drive pulse φ1 similarly to the potential 24 of the storage section, and The difference is that the potential 28 of the barrier section between the last stage register and the register one stage before the last stage changes according to the reset pulse RS. The time chart of the drive pulses φ1 and φ2 and the reset pulse RS is shown in FIG. 2 as in the case of the first embodiment.

The potential of each region in the second embodiment changes as shown in FIGS. 5 (a) to 5 (e). This figure 5
The potential distributions shown in (a) to (e) respectively correspond to those at times t1 to t5 in FIG.

At time t1, as shown in FIG. 5A, a high-level drive pulse φ2 is applied to the transfer electrode 5 of the register immediately before the last stage, and the potential 26 of the storage unit and the barrier unit Are both in a high state. The signal charge 100 is stored in the storage section of this register.
A low-level reset pulse RS is applied to the barrier section between the last-stage register and the register immediately before the last-stage register, and the potential 28 in this region is at a low level. A low-level drive pulse φ1 is applied to both the storage section and the barrier section of the last-stage register, and the respective potentials 24 and 25 are low.

At time t2, as shown in FIG. 5B, a low-level drive pulse φ2 is applied to the register immediately before the last stage, and the potentials 26 and 27 of the storage unit and the barrier unit are both set. Change low. However, a low-level reset pulse RS is applied to the barrier section between the last stage register and the register one stage before the last stage, and the potential 28 in this region maintains a low level. Therefore, the signal charges 100 stored in the storage unit of the register one stage before the last stage are not transferred. A high-level drive pulse φ1 is applied to the last-stage register, and the potential 24 of the storage section and the potential 25 of the barrier section both change high.

At time t3, as shown in FIG. 5 (c), the potentials 26 and 27 of the storage section and the barrier section of the register immediately before the last stage maintain a low level. A high-level reset pulse RS is applied to a barrier section between the last-stage register and the register one stage before the last stage,
The potential 28 in this region changes high. A high-level drive pulse φ1 is applied to the final stage register, and the potentials 24 and 25 of the storage unit and the barrier unit maintain a high level. The signal charge 100 stored in the storage unit of the register one stage before the last stage moves to the barrier unit between the last stage register and the register one stage before the last stage.

At the time t4, as shown in FIG.
And 27 continue to maintain a low level, and the potential 24 of the storage section and the potential 25 of the barrier section of the final stage register maintain a high level. A low-level reset pulse is applied to the area between the last register and the register one step before the last register.
RS is applied, and the potential 28 in this region changes low. The signal charge 100 moves from the barrier portion between the last stage register and the register one stage before the last stage to the storage portion of the last stage register.

At time t5, as shown in FIG. 5E, the potentials 26 and 27 of the storage section and the barrier section of the register immediately before the last stage change to a high level. A low-level reset pulse RS is applied to the barrier section between the last-stage register and the register immediately before the last-stage register, and the potential 28 in this region maintains the low-level. A low-level drive pulse φ1 is applied to the final stage register, and the potential 24 of the storage portion and the potential 25 of the barrier portion in this portion are applied.
Change to low level. The signal charge 100 stored in the storage unit of the last-stage register moves to the charge detection unit 22 and is read.

According to the second embodiment, when the signal charge 100 is transferred from the register one stage before the last stage to the accumulation unit of the last register, as shown in FIG.
The potentials 26 and 27 of the register immediately before the last stage change to low level, and the potentials 24 and 25 of the last register change to high level. However, the potential 28 of the barrier section between the last stage register and the register one stage before the last stage is at a low level, and the advance of the signal charge 100 is prevented. Thereafter, as shown in FIG. 5C, the potential 28 of the barrier section between the last stage register and the register one stage before the last stage changes to a high level, and the signal charge 100 is changed to the last stage. Transferred to register.

Next, a third embodiment of the present invention will be described with reference to the drawings. As described above, the second embodiment is characterized in that the barrier section is provided between the register one stage before the last stage and the last stage register, and the reset pulse RS is applied to this barrier portion. On the other hand, the third embodiment is characterized in that a register having a storage unit and a barrier unit is provided immediately before the last stage and a reset pulse RS is applied to this register.

FIG. 6A shows a vertical sectional structure of the charge transfer device according to the present embodiment. In the final register, an n-type impurity region 31 is formed as a storage portion, and a p-type impurity region 34 is formed as a barrier portion. A drive pulse φ1 is applied to the transfer electrode 4 provided on the storage section and the barrier section.
Is applied. In the register one stage before the last stage,
An n-type buried channel layer 12 is formed as a charge storage portion, and a p-type impurity region 35 is formed as a barrier portion. A reset pulse RS is applied to the charge storage section and the barrier section via the transfer electrode 16. The same components as those in the first or second embodiment are denoted by the same reference numerals, and description thereof is omitted.

FIG. 6B shows a change in potential for each region in the third embodiment. The potential 41 of the charge storage section and the potential 42 of the barrier section of the final stage register are reset pulses RS
It changes according to. The changes in the waveforms of the drive pulses φ1 and φ2 and the reset pulse RS are the same as those shown in the time chart of FIG. 2 as in the first and second embodiments.

In the third embodiment, the potential of each region changes as shown in FIGS. 7A to 7E with the passage of time t1 to t5. The potential distributions shown in FIGS. 7A to 7E correspond to those at times t1 to t5 in FIG.

At time t1, as shown in FIG. 7A, a high-level driving pulse φ2 is applied to the transfer electrode 5 of the register two stages before the last stage, and the potential 26 and the potential 26 Both potentials 27 of the barrier section are in a high state.
The signal charge 100 is stored in the storage section of this register. A low-level reset pulse RS is applied to the register one stage before the last stage, and the potential 41 of the storage unit and the potential 42 of the barrier unit are both at a low level. A low-level drive pulse φ1 is applied to both the accumulation section and the barrier section of the last-stage register, and the respective potentials 24 and 25 are both at the low level.

At time t2, as shown in FIG. 7 (b), a low-level drive pulse φ2 is applied to the register two stages before the last stage, and the potentials 26 and 27 of the storage unit and the barrier unit are both changed. Also vary low. A low-level reset pulse RS is applied to the register one stage before the last stage,
The potential 41 of the storage section and the potential 42 of the barrier section maintain a low level. As a result, the signal charges 100 stored in the storage unit of the register two stages before the last stage are not transferred. The high-level drive pulse φ1 is stored in the last stage register.
Is applied, and the potential 24 of the storage portion and the potential 25 of the barrier portion both change high.

At time t3, as shown in FIG. 7C, the potential 26 of the storage section and the barrier section of the register two stages before the last stage.
And 27 maintain a low level. A high-level reset pulse RS is applied to the register one stage before the last stage, and the potential 41 of the storage unit and the potential 42 of the barrier unit change high. Thus, the signal charge 100 stored in the storage unit of the register two stages before the last stage is transferred to the storage unit of the register one stage before the last stage. A high-level drive pulse φ1 is applied to the final stage register, and the potentials 24 and 25 of the storage unit and the barrier unit maintain a high level.

At time t4, as shown in FIG.
The potentials 26 and 27 of the storage unit and the barrier unit of the register two stages before the last stage continue to maintain a low level, and the potential 24 of the storage unit and the potential 25 of the barrier unit of the last stage register maintain a high level. A low-level reset pulse RS is applied to the register one stage before the last stage, and the potential 41 of the storage unit and the potential 42 of the barrier unit change low. The signal charge 100 moves from the storage portion of the register one stage before the last stage to the storage portion of the last stage register.

At time t5, as shown in FIG. 7 (e), the potentials 26 and 27 of the storage section and the barrier section of the register two stages before the last stage both change to a high level. A low-level reset pulse RS is applied to the register one stage before the last stage, and the potential 4 of the storage unit of this register is applied.
1 and the potential 42 of the barrier section maintain the low level. A low-level drive pulse φ1 is applied to the final stage register, and the potential 24 of the storage portion and the potential 25 of the barrier portion in this portion are applied.
Change to low level. The signal charge 100 stored in the storage unit of the last stage register is transferred to the charge detection unit 22 and read.

According to the third embodiment, when the signal charge 100 is transferred from the register two stages before the last stage to the storage part of the register one stage before the last stage, it is shown in FIG. 7B. As described above, the potentials 26 and 27 of the register two stages before the last stage are at the low level, and the potentials 24 and 25 of the last stage register are changed to the high level. However, at this time, the potentials 41 and 42 of the register one stage before the last stage are at the low level. Therefore, the signal charge 100 is not transferred to the charge detection unit 22 by skipping over the last-stage register, and an abnormal operation is prevented.

Thereafter, as shown in FIG. 7C, the potentials 41 and 42 of the registers one stage before the last stage change to the high level, and the signal charge 100 becomes one stage before the last stage. Is transferred to the storage section of the register. Further, FIG.
As shown in (d), the potential 41 of the register immediately before the last stage is obtained.
And 42 change to low level, and the signal charge 100 is transferred to the final stage register without any trouble.

The above embodiments are merely examples, and do not limit the present invention. For example, in the first embodiment, the reset pulse RS shown in FIG. 2 is applied to the barrier section of the last stage register. This reset pulse RS
It is the same as that applied to the reset gate electrode 2, but it is not necessary to be the same. That is, it is only necessary to apply, to the barrier section of the final stage register, a transistor having the same cycle as that applied to the reset gate electrode and having a high-level period shorter than the drive pulse. Similarly, in the second embodiment, the reset pulse RS is applied to the barrier section provided between the last stage register and the register one stage before the last stage. In the third embodiment, the reset pulse RS is applied from the last stage. The reset pulse RS is applied to the storage unit and barrier unit of the register one stage before, but it is necessary to apply the reset pulse RS whose period is the same as that applied to the reset gate electrode and whose high-level period is shorter than the drive pulse. I just need.

[0061]

As described above, according to the charge transfer method and device of the present invention, when signal charges are transferred to the accumulation section of the final register in the CCD register, only the barrier section of the final register is transferred. By applying a pulse having the same cycle as the reset pulse and having a high-level period shorter than the drive pulse, or between the last-stage register and the register one stage before the last-stage register, Impurity regions of the same conductivity type are formed,
By applying a pulse having the same period as the reset pulse and a high-level period shorter than the drive pulse to this impurity region, an abnormal operation of jumping over the accumulation section of the final stage register and being forward-transferred to the charge detection section is prevented. You.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing a vertical sectional structure and a potential distribution of a charge transfer device according to a first embodiment of the present invention.

FIG. 2 is a time chart showing changes in waveforms of a drive pulse and a reset pulse used in the first to third embodiments of the present invention.

FIG. 3 is a potential distribution diagram showing a change in potential of each region in the charge transfer device according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram showing a vertical sectional structure and a potential distribution of a charge transfer device according to a second embodiment of the present invention.

FIG. 5 is a potential distribution diagram showing a change in potential of each region in the charge transfer device according to the same embodiment.

FIG. 6 is an explanatory diagram showing a vertical sectional structure and a potential distribution of a charge transfer device according to a third embodiment of the present invention.

FIG. 7 is a potential distribution diagram showing a change in potential of each region in the charge transfer device according to the same embodiment.

FIG. 8 is an explanatory diagram showing a vertical cross-sectional structure and a potential distribution of a conventional charge transfer device.

FIG. 9 is a time chart showing a change in a drive pulse waveform in the same charge transfer device.

FIG. 10 is a potential distribution diagram showing a change in potential of each region in the same charge transfer device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 reset drain 2 reset gate electrode 3 output gate electrode 4,5 transfer electrode 7 charge detector 8,31 n-type impurity region 10,11,34,35 p-type impurity region 12 n-type buried channel layer 20-27,41, 42 potential 50 p-type semiconductor substrate 100 signal charge

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/339 H01L 29/762 H04N 5/335

Claims (4)

(57) [Claims] An accumulator for receiving and accumulating signal charges, and a barrier for preventing the signal charges accumulated in the accumulator from moving to another adjacent area, wherein a driving pulse is applied. C provided with a plurality of registers for transferring signal charges
A charge transfer device comprising: a CD register; a charge detection unit that receives and detects a signal charge transferred from the CCD register; and a reset gate that receives a reset pulse and sets the charge detection unit to a predetermined state. A charge transfer device, wherein a pulse having the same cycle as the reset pulse and having a shorter high-level period than the drive pulse is applied only to the barrier section of the last register in the CCD register. 2. An accumulator for accumulating a given signal charge;
A drive pulse is applied to a CCD register provided with a plurality of registers having a barrier section for preventing the signal charges accumulated in the accumulation section from moving to another adjacent area, and the signal charges are transferred. In the charge transfer method of detecting a signal charge transferred from a register by a charge detection unit and applying a reset pulse to a reset gate to set the charge detection unit to a predetermined state, only the barrier unit of the last stage register in the CCD register And applying a pulse having the same period as the reset pulse and a shorter high-level period than the drive pulse. 3. A storage section for receiving a signal charge and storing the signal charge, and a barrier section for preventing the signal charge stored in the storage section from moving to another adjacent area. C provided with a plurality of registers for transferring signal charges
A charge transfer device comprising: a CD register; a charge detection unit that receives and detects a signal charge transferred from the CCD register; and a reset gate that receives a reset pulse and sets the charge detection unit to a predetermined state. An impurity region of the same conductivity type as a barrier portion of the last stage register is formed between the last stage register and the register one stage before the last stage in the CCD register. A charge transfer device, wherein pulses having the same cycle and a shorter high-level period than the driving pulse are applied. 4. An accumulator for accumulating a given signal charge;
A drive pulse is applied to a CCD register provided with a plurality of registers having a barrier section for preventing the signal charges accumulated in the accumulation section from moving to another adjacent area, and the signal charges are transferred. In a charge transfer method for detecting a signal charge transferred from a register by a charge detection unit and applying a reset pulse to a reset gate to set the charge detection unit in a predetermined state, An impurity region of the same conductivity type as that of the barrier unit of the last stage register is formed between the last stage register and the impurity region. A charge transfer method comprising applying a short pulse.