JP2846513B2 - Solid-state imaging device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device using a charge transfer device and a method of manufacturing the same.

[0002]

2. Description of the Related Art A charge detection circuit called a floating diffusion amplifier (hereinafter referred to as an FD amplifier) for performing charge-voltage conversion is used for a charge-coupled device (hereinafter referred to as a CCD) and the like. FIG. 6 is a diagram showing a configuration in the case where this FD amplifier is used in a CCD output circuit. The n ⁻ layer 2 formed on the p-type semiconductor substrate 1 has C
A CD channel, an FD section, and a reset drain are configured. A predetermined gate electrode 3 and a potential barrier forming gate electrode 4 of the CCD are arranged at predetermined positions on the n ⁻ layer 2. Φ _H, which is one of the drive clocks for charge transfer, is applied to the gate electrode 3, and a DC voltage V _OG is applied to the gate electrode 4.

In a region adjacent to the gate electrode 4, a MOS transistor Tr1 including a gate electrode 5 and impurity regions 6 and 7 is formed. This MOS transistor T
r1 reset clock phi _R is applied to the gate electrode 5 of, if the reset clock phi _R to the high level,
The MOS transistor Tr1 turns on. The impurity region 6 is called a floating diffusion (FD portion) and is connected to a gate of an output source follower transistor Tr2 formed on the same semiconductor substrate. The impurity region 7 is called a reset drain, and is connected to a reset power supply V _RD . Since each drive voltage is applied to the FD section 6 and the reset drain 7, it is necessary to secure an ohmic contact with the aluminum wiring, and the central portion of each region is formed as a high concentration impurity layer ( n ⁺ layer ). . Also,
Reference numeral 8 denotes a channel stopper.

Next, the operation of the conventional device will be described.
FIG. 7A shows a cross-sectional structure along CC ′ in FIG.
FIGS. 7B to 7D are diagrams showing the potentials of the respective parts in FIG. 7A at times corresponding to the clock timings t1 to t3 in FIG. First, at time t1 in FIG. 4, the drive clock φ _H is at a high level, and a potential well is formed below the gate electrode 3 as shown in FIG. Has become reset clock phi _R is a high level at the same time, MOS transistor Tr1 is turned on, the gate potential of the FD portion 6 and a transistor Tr2 connected thereto is reset to the reset power source V _RD.

At time t2 in FIG. 4, reset clock φ
_R goes low, turning off the MOS transistor Tr1. When reset clock phi _R is changed from high level to low level, the capacitive coupling between the gate electrode 5 and the FD section 6, the potential of the FD portion 6 is reduced. Node connected to the FD section 6 reset clock phi _R is the duration of the low level in the floating.

At time t3 in FIG. 4, when the driving clock φ _H goes low, the signal charge Q stored in the potential well below the gate electrode 3 is read out to the FD section 6, and the node of the FD section 6 , And this change in potential is output through the source follower circuit.

[0007]

The conventional solid-state imaging device is
It operates and operates as described above, except that the reset clock φ
_RBecomes high level, and the potential of the FD section 6 is reset to the reset potential V.
_RDIs fixed, the thermal noise of the reset channel is FD
Because it is superimposed on the section 6, it exists in the FD section 6 immediately after reset
The number of generated electrons fluctuates and reset noise is generated. this
To eliminate, reset the electrons of FD section 6 at reset
Transfer completely to the drain 7 and deplete the FD section 6
However, as described above, the FD section 6 is
Contact must be made, forming a high-concentration impurity layer.
Must be able to achieve complete electron transfer.
There was a problem that it was not possible.

Further, if a high concentration p ⁺ layer is formed on the FD portion 6, the FD portion 6 can be depleted. However, if the p ⁺ layer is formed so as to cover the FD portion 6, ^{The +} layer is connected to the channel stopper, and the potential is fixed. Further, when the p ⁺ layer is formed smaller than the FD section 6, the potential of the FD section becomes shallow in a region covered by the p ⁺ layer, and signal charges flow into a region not covered by the p ⁺ layer. Can not be done. In any case, the FD section 6 cannot be surely depleted.

Accordingly, an object of the present invention is to provide a solid-state imaging device having an FD amplifier that does not generate reset noise, and an object of the invention to provide a manufacturing method capable of easily manufacturing this device.

[0010]

In order to solve the above-mentioned problems, the present invention employs the following configuration. That is,
According to a first aspect of the present invention, there is provided a solid-state imaging device comprising: a first diffusion region of another conductivity type formed on a semiconductor layer of one conductivity type; a potential barrier forming gate electrode provided adjacent to the first diffusion region ; and the final gate electrode of the position charge transfer device disposed adjacent to the barrier forming a gate electrode, a first <br/> MOS transistor for diffusion reset with the first diffusion region as a source electrode, a first expansion A solid-state imaging device including a floating diffusion amplifier-type charge detection unit including a source follower circuit for detecting a potential of a diffusion region , wherein a first diffusion region is provided.
Low impurity concentration is high end at the center portion of the first diffusion region
And forming as Ku becomes, and wherein the forming the second diffusion region of the one conductivity type in a central portion a surface of the first diffusion region.

According to a second aspect of the present invention, there is provided a method of manufacturing a solid-state imaging device.
A first diffusion region of the other conductivity type formed on a semiconductor layer of the one conductivity type, a photodiode consisting of a second <br/> diffusion region of the one conductivity type formed in the first diffusion region, a third diffusion region of the other conductivity type formed in the semiconductor layer, the third diffusion and the potential barrier formed gate electrode provided adjacent to the region, a charge transfer device provided adjacent to the conductive position barrier formed gate electrode A third diffusion region resetting MOS transistor using the third diffusion region as a source electrode, and a source follower circuit for detecting the potential of the third diffusion region And the third
A method of manufacturing a solid-state imaging device and a fourth floating diffusion amplifier type charge detecting section constituted by <br/> the diffusion region of the one conductivity type formed on the surface of the diffusion region, a charge detection The third diffusion region of the portion is a photodiode
Formed simultaneously with the first diffusion region of
The fourth diffusion region of the photodiode to the second diffusion region of the photodiode.
It is characterized by being formed simultaneously with the region .

[0012]

According to the structure of the first aspect, the floating
Since a one-conductivity-type high-concentration diffusion layer is formed in the other-conductivity-type diffusion region forming the diffusion, the reset M
When the OS transistor is turned on, the diffusion layer is completely depleted, and the signal charge transferred from the imaging unit flows into the floating diffusion and is completely transferred to the drain of the reset transistor. When the reset MOS transistor is in the off state, the potential is in a floating state, so that the potential does not fluctuate during the reset operation and no reset noise is generated.

According to the structure of the second invention, the charge detection section of the solid-state imaging device of the first invention can be formed in the same step as the photodiode of the imaging section, so that the number of photomasks and the number of times of photolithography can be reduced. A solid-state imaging device can be easily manufactured without increasing the number.

[0014]

FIG. 1 is a diagram showing the configuration of an FD amplifier of a solid-state imaging device according to an embodiment of the present invention. The same reference numerals as those in FIG. In the n ⁻ layer 2 formed on the substrate 1, a CCD channel, an FD section 6 and a reset drain 7 are formed, and a final gate electrode 3 of the CCD, a potential barrier forming gate electrode 4, a reset gate electrode 5, an FD section 6 The reset drain 7 constitutes a charge detection unit D. As shown in FIG. 2A showing a cross-sectional structure along AA ′ in FIG. 1 and FIG. 3A showing a cross-sectional structure along BB ′ in FIG. The diffusion layer 6a at the portion has a higher impurity density than the diffusion layer 6b at the end, and a high concentration p ⁺ layer 10 is formed above the central diffusion layer 6a.

Since the impurity concentration of the high-concentration p ⁺ layer 10 is sufficiently high, an ohmic contact with the aluminum wiring is ensured. The diffusion layer 6a is formed at a concentration approximately twice that of the diffusion layer 6b. FIG. 2B shows a potential diagram when a voltage is applied. The diffusion layer 6a is higher than the diffusion layer 6b by the potential P. As described above, if the concentration of the diffusion layer 6a is about twice the concentration of the diffusion layer 6b, depletion easily occurs under the normal driving condition of V _RD = 15V.
Therefore, when the reset transistor is turned on in the reset clock phi _R to the high level, the diffusion layer 6
Both a and 6b are completely depleted, and the diffusion layer 6a has a higher potential than the diffusion layer 6b. This allows CC
The signal charge transferred from D flows into the FD section 6 and is completely transferred to the reset drain 7 by the reset operation, so that noise due to the reset operation does not occur. 3 (b) to 3 (d) are diagrams showing the potentials of the respective portions of FIG. 3 (a) at times corresponding to t1 to t3 in the clock timing diagram of FIG. 4, respectively, and the electric charge Q is completely transferred to the reset drain. This is shown.

FIGS. 5A to 5C are cross-sectional views showing the steps of the method of manufacturing the above-described embodiment device. In FIG. 5A, the left side shows an image pickup section, and the right side shows a step of forming an FD section. First, as shown in FIG. 5A, phosphorus or arsenic is implanted into the p-type substrate 1 to form n ⁻ layers 22 and 6. The n ⁻ layer 22 forms the photodiode of the imaging unit, and is the same process as in the related art. The difference from the related art is that the n ⁻ layer 6a is simultaneously formed in the FD portion. Next, FIG.
As shown in, by implanting phosphorus or arsenic n ^- layer 23,
6b is formed. The n ⁻ layer 23 forms a vertical CCD channel of the imaging unit, and the n ⁻ layer 25 forms a channel from the horizontal CCD to the FD. This is the same process as the conventional one.
Therefore, phosphorus or arsenic is implanted twice in the FD portion. Next, as shown in FIG. 5C, boron is implanted on the n ⁻ diffusion layers 22 and 6a to form p ⁺ layers 24 and 10. The p ⁺ layer 24 is formed to reduce the dark current on the photodiode, which is also the same as the conventional case. The difference from the related art is that the p ⁺ layer 10 is formed in the FD portion at the same time, thereby realizing low noise as described above.

As described above, since the FD portion can be manufactured according to the conventional method of manufacturing a solid-state imaging device, it is not necessary to increase the number of photomasks or the number of photolithography. Further, by adding an n ⁻ layer having the same concentration as that of the photodiode to the FD portion, the magnitude of the potential difference P in FIG. 2B can be made substantially equal to the potential of the photodiode. Therefore, if the area of the FD portion is made larger than that of the photodiode, the charge storage capacity of the diffusion layer 6a becomes larger than that of the photodiode, so that the charge does not leak to the diffusion layer 6b, and stable driving can be performed. it can.

[0018]

As described above, according to the solid-state imaging device of the present invention, a high-concentration diffusion layer of an anti-conductive type is formed in the charge detection portion of the floating diffusion, thereby completely depleting the channel. can do. Also,
When the reset transistor is in the off state, the potential is in a floating state, so that the potential fluctuation at the time of the reset operation is eliminated, and the occurrence of reset noise can be prevented.
The S / N ratio can be significantly improved.

Further, according to the method of manufacturing a solid-state imaging device of the present invention, the photodiode of the imaging section and the floating diffusion can be formed at the same time. Therefore, stable driving can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a solid-state imaging device according to an embodiment of the present invention.

FIG. 2A is a cross-sectional view taken along the line AA ′ of FIG. 1;
(B) is a diagram showing a potential when a voltage is applied.

FIG. 3A is a cross-sectional view taken along the line BB ′ of FIG. 1;
(B), (c), and (d) are diagrams showing potentials when a voltage is applied to each part shown in (a).

FIG. 4 is a timing chart showing the timing of a clock applied to each electrode.

FIGS. 5A, 5B, and 5C are views showing steps of a method for manufacturing a solid-state imaging device according to the present invention; FIGS.

FIG. 6 is a diagram showing a configuration of a conventional example.

FIG. 7A is a cross-sectional view taken along the line CC ′ of FIG. 6;
(B), (c), and (d) are diagrams showing potentials when a voltage is applied to each part shown in (a).

[Explanation of symbols]

REFERENCE SIGNS LIST 1 P-type substrate 2 n ^- layer 3 CCD final gate electrode 4 potential barrier forming gate electrode 5 reset gate electrode 6 floating diffusion (FD section) 7 reset drain 10 p ⁺ layer D charge detection section

Claims (2)

(57) [Claims] 1. A a first diffusion region of the other conductivity type formed on the semiconductor layer of the one conductivity type, said a potential barrier formed gate electrode provided adjacent to the first diffusion region, the potential barrier formed gate and the final gate electrode of the charge transfer device disposed adjacent to an electrode, the first of said first diffusion region and a source electrode
And MOS transistor for diffusion regions resetting, the first
And a source follower circuit for detecting a potential of the first diffusion region .
The first diffusion region is formed so that the impurity concentration is high at the center of the first diffusion region and low at the end thereof .
A solid-state imaging apparatus characterized by forming a second diffusion region of the one conductivity type in a central portion a surface of the first diffusion region. 2. A photo diode comprising: a first diffusion region of another conductivity type formed on a semiconductor layer of one conductivity type; and a second diffusion region of one conductivity type formed on the first diffusion region.
And de, the third diffusion region of the other conductivity type formed before Symbol semiconductors layer, and the potential barrier formed gate electrode provided adjacent to the third diffusion region, adjacent to the potential barrier formed gate electrode and the final gate electrode of the charge transfer device provided with the said third MOS transistor for diffusion reset the third expansion <br/> dispersion region of the source electrode, the potential of the third diffusion region Source follower circuit for detecting the third diffusion region
And a floating diffusion amplifier type charge detection section comprising a fourth diffusion region of one conductivity type formed on the surface of the solid-state imaging device . The diffusion region of
Forming at the same time as the first diffusion region of the ode
The fourth diffusion region of the charge detection unit is
A method for manufacturing a solid-state imaging device , wherein the diode is formed simultaneously with the second diffusion region .