JPH05121459A - Solid-state image sensing device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a solid-state image sensing device wherein reset noise is not generated and a charge detection part of floating-diffusion amplifier type is provided, and to provide the simple manufacturing method of the device. CONSTITUTION:A region 6a whose impurity concentration becomes dense in the central part of a diffusion region and a region 6b whose impurity concentration becomes thin at its end parts are formed additionally in one part of an n<-> layer 2 for a floating diffusion 67 a high-concentration p<-> layer 10 is formed on the high-concentration region in the added n<-> layer. Thereby, a charge detection part D of floating-diffusion amplifier type is constituted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device using a charge transfer device and a manufacturing method thereof.

[0002]

2. Description of the Related Art A charge detection device called a floating diffusion amplifier (hereinafter referred to as FD amplifier) for performing charge-voltage conversion is used for a charge coupled device (hereinafter referred to as CCD) and the like. FIG. 6 is a diagram showing a configuration in the case where this FD amplifier is used in an output circuit of a CCD, in which an n ⁻ layer 2 formed on a p-type semiconductor substrate 1 has a C
The CD channel, the FD portion, and the reset drain are configured. The final gate electrode 3 and the potential barrier forming gate electrode 4 of the CCD are arranged at predetermined positions on the n ⁻ layer 2. Φ _H, which is one of the drive clocks for charge transfer, is applied to the gate electrode 3, and the DC voltage V _OG is applied to the gate electrode 4.

In the region adjacent to the gate electrode 4, the gate
MOS transistor consisting of electrode 5 and impurity regions 6 and 7
The data Tr1 is formed. This MOS transistor T
Reset clock φ is applied to the gate electrode 5 of r1._RIs applied
This reset clock φ _RTo high level,
The MOS transistor Tr1 turns on. Also, the impurity region
Area 6 is a floating diffusion (FD part)
Called source for output formed on the same semiconductor substrate
It is connected to the gate of the follower transistor Tr2. Not
The pure material region 7 is called a reset drain and is a reset power supply.
V_RDAre connected. For the FD section 6 and the reset drain 7,
Ohmic with aluminum wiring because each drive voltage is applied
It is necessary to secure contacts, and the central part of each area is high.
Concentration impurity layer (n^-Layers). Also,
8 indicates a channel stopper.

Next, the operation of the conventional device will be described.
FIG. 7A shows a cross-sectional structure taken along the line CC ′ of FIG.
7B to 7D are diagrams showing the potential of each portion of FIG. 7A at times corresponding to t1 to t3 of the clock timing of FIG. 4, respectively. First, at time t1 in FIG. 4, the drive clock φ _H is at a high level, a potential well is formed under the gate electrode 3 as shown in FIG. 7B, and the charge Q is accumulated. At the same time, the reset clock φ _R is at high level, the MOS transistor Tr1 is turned on, and the gate potentials of the FD portion 6 and the transistor Tr2 connected thereto are reset to the reset power supply V _RD .

At time t2 in FIG. 4, the reset clock φ
_R becomes low level, and the MOS transistor Tr1 is turned off. When the reset clock φ _R changes from the high level to the low level, the potential of the FD portion 6 decreases due to the capacitive coupling between the gate electrode 5 and the FD portion 6. While the reset clock φ _R is at the low level, the node connected to the FD section 6 becomes floating.

At time t3 in FIG. 4, when the drive clock φ _H becomes low level, the signal charge Q stored in the potential well under the gate electrode 3 is read out to the FD section 6 and the node of the FD section 6 is read. Is changed, and the change in this potential is output through the source follower circuit.

[0007]

A conventional solid-state image pickup device is
Although configured and operated as described above, reset clock φ
_RBecomes the high level, and the potential of the FD section 6 is reset to the reset potential V.
_RDThe thermal noise of the reset channel is FD
Since it is overlapped with the part 6, it exists in the FD part 6 immediately after reset.
The number of electrons generated fluctuates and reset noise is generated. this
To eliminate, reset the electrons in the FD section 6 at reset
Complete transfer to the drain 7 and deplete the FD section 6
However, as mentioned above, the FD section 6 is ohmic with the aluminum wiring.
Form a high-concentration impurity layer.
It is necessary to achieve complete transfer of electrons
There was a problem that I could not.

Further, if a high-concentration p ⁺ layer is formed on the FD portion 6, the FD portion 6 can be depleted. If this p ⁺ layer is formed so as to cover the FD portion 6, p ^{The +} layer is connected to the channel stopper and the potential is fixed. Further, when the p ⁺ layer is formed smaller than the FD portion 6, the potential of the FD portion becomes shallow in the region covered by the p ⁺ layer, and the signal charges flow into the region not covered by the p ⁺ layer, so that potential detection is performed. Can not be. In any case, the depletion of the FD portion 6 could not be surely achieved.

Therefore, it is an object of the present invention to provide a solid-state image pickup device having an FD amplifier that does not generate reset noise, and a manufacturing method capable of easily manufacturing this device.

[0010]

In order to solve the above problems, the present invention adopts the following configuration. That is,
A solid-state imaging device according to a first aspect of the invention is a diffusion region of another conductivity type formed on a semiconductor layer of one conductivity type, a potential barrier forming gate electrode provided adjacent to this diffusion region, and this potential barrier forming gate electrode. And a MOS transistor for resetting the diffusion region formed by using the diffusion region as a source electrode, and a source follower circuit for detecting the potential of the diffusion region. A solid-state imaging device comprising a floating diffusion amplifier type charge detection unit, wherein the diffusion region of the other conductivity type is formed such that its impurity concentration is high at the center of the diffusion region and thin at the end, A diffusion region of one conductivity type is formed on a central portion of the diffusion region of another conductivity type.

The manufacturing method of the solid-state image pickup device of the second invention is
An image pickup section including a photodiode including a diffusion region of another conductivity type formed on a semiconductor layer of one conductivity type and a diffusion region of one conductivity type formed on the diffusion region of another conductivity type; Region of another conductivity type formed on the semiconductor layer of the V type, a potential barrier forming gate electrode provided adjacent to the diffusion region, and a final gate of the charge transfer device provided adjacent to the potential barrier forming gate electrode An electrode and an MO for resetting the diffusion region formed by using the diffusion region as a source electrode
A method of manufacturing a solid-state imaging device comprising an S-transistor and a source-follower circuit for detecting the potential of the diffusion region, the method comprising: a floating-diffusion-amplifier-type charge detection unit; It is characterized in that the detection portion is formed at the same time as the impurity layer forming the photodiode.

[0012]

According to the structure of the first invention, the floating
Since the one-conductivity-type high-concentration diffusion layer is formed in the other-conductivity-type diffusion region forming the diffusion, the reset M
When the OS transistor is turned on, the diffusion layer is completely depleted, and the signal charges transferred from the imaging unit flow into the floating diffusion and are completely transferred to the drain of the reset transistor. Further, when the reset MOS transistor is in the off state, the potential is in a floating state, so that the potential fluctuation does not occur during the reset operation and the reset noise does not occur.

According to the structure of the second invention, since the charge detecting portion of the solid-state image pickup device of the first invention can be formed in the same step as the photodiode of the image pickup portion, the number of photomasks and the number of times of photolithography can be reduced. The solid-state imaging device can be easily manufactured without increasing the number.

[0014]

1 is a diagram showing the structure of an FD amplifier of a solid-state image pickup device according to an embodiment of the present invention. The same reference numerals as those in FIG. 6 showing a conventional example indicate the same, and a p-type semiconductor. A CCD channel, an FD portion 6 and a reset drain 7 are formed on the n ⁻ layer 2 formed on the substrate 1, and a final gate electrode 3, a potential barrier forming gate electrode 4, a reset gate electrode 5, an FD portion 6 of the CCD are formed. The reset drain 7 constitutes the charge detection unit D. As shown in FIG. 2A showing a sectional structure taken along the line AA ′ of FIG. 1 and FIG. 3A showing a sectional structure taken along the line BB ′ of FIG. The diffusion layer 6a in the central portion has a higher impurity density than the diffusion layer 6b in the end portion, and the high-concentration p ⁺ layer 10 is formed in the upper layer of the central diffusion layer 6a.

Since the high-concentration p ⁺ layer 10 has a sufficiently high impurity density, ohmic contact with the aluminum wiring is ensured. Further, the diffusion layer 6a is formed to have a concentration about twice that of the diffusion layer 6b. FIG. 2B shows a potential diagram when a voltage is applied, and the diffusion layer 6a is higher than the diffusion layer 6b by the potential P. As described above, if the diffusion layer 6a has a concentration about twice that of the diffusion layer 6b, it is easily depleted under the normal driving condition of V _RD = 15V.
Therefore, when the reset clock φ _{R is set} to the high level to turn on the reset transistor, the diffusion layer 6
Both a and 6b are completely depleted, and the potential of the diffusion layer 6a is higher than that of the diffusion layer 6b. This allows CC
Since the signal charge transferred from D flows into the FD section 6 and is completely transferred to the reset drain 7 by the reset operation, noise due to the reset operation does not occur. 3 (b) to 3 (d) are diagrams showing the potential of each portion of FIG. 3 (a) at times corresponding to t1 to t3 of the clock timing diagram of FIG. 4, respectively, and the charge Q is completely transferred to the reset drain. The situation is shown.

5 (a) to 5 (c) are sectional views showing the steps of the method for manufacturing the above-described apparatus, in which the left side shows the imaging section and the right side shows the FD section. First, as shown in FIG. 5A, phosphorus or arsenic is implanted into the p-type substrate 1 to form the n ⁻ layers 22 and 6. The n ⁻ layer 22 forms a photodiode of the image pickup section, which is the same process as the conventional process. What is different from the conventional technique is that the n ⁻ layer 6a is simultaneously formed in the FD portion. Next, FIG. 5 (b)
As shown in, by implanting phosphorus or arsenic n ^- layer 23,
6b is formed. The n ⁻ layer 23 forms a vertical CCD channel of the image pickup section, and the n ⁻ layer 25 forms a channel from the horizontal CCD to the FD. This is also the same process as the conventional one.
Therefore, phosphorus or arsenic is implanted twice in the FD portion. Next, as shown in FIG. 5C, boron is implanted into the n ⁻ diffusion layers 22 and 6a to form p ⁺ layers 24 and 10. The p ⁺ layer 24 is formed to reduce the dark current on the photodiode, which is also the same as the conventional one. What is different from the conventional technique is that the p ⁺ layer 10 is simultaneously formed in the FD portion, which realizes the low noise as described above.

As described above, since the FD portion can be manufactured according to the conventional method for manufacturing a solid-state image pickup device, it is not necessary to increase the number of photomasks or photolithography. Further, by adding an n ⁻ layer having the same concentration as the photodiode to the FD portion, the magnitude of the potential difference P in FIG. 2B can be made substantially equal to the potential of the photodiode. Therefore, if the area of the FD portion is made larger than that of the photodiode, the charge storage capacity of the diffusion layer 6a becomes larger than that of the photodiode, so that the charges do not leak to the diffusion layer 6b and stable driving is possible. it can.

[0018]

As described above, according to the solid-state image pickup device of the present invention, since the anti-conduction type high-concentration diffusion layer is formed in the charge detection portion of the floating diffusion, the channel is completely depleted. can do. Also,
When the reset transistor is in the off state, the potential is in a floating state, so that the potential fluctuation during the reset operation is eliminated and the reset noise can be prevented from occurring.
The S / N ratio can be significantly improved.

Further, according to the method of manufacturing the solid-state image pickup device of the present invention, since the photodiode of the image pickup portion and the floating diffusion can be formed at the same time, the number of times of mask alignment is not increased and the manufacturing is facilitated. Since a potential for the amount can be secured, stable driving can be performed.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a solid-state imaging device which is an embodiment of the present invention.

2A is a sectional view taken along the line AA ′ of FIG.
(B) is a diagram showing a potential when a voltage is applied.

FIG. 3A is a cross-sectional view taken along the line BB ′ of FIG.
(B) (c) (d) is a figure which shows the potential when a voltage is applied to each part shown to (a).

FIG. 4 is a timing chart showing the timing of the clock applied to each electrode.

5A, 5B, and 5C are diagrams showing steps of a method for manufacturing a solid-state imaging device according to the present invention.

FIG. 6 is a diagram showing a configuration of a conventional example.

7A is a cross-sectional view taken along the line CC ′ of FIG.
(B) (c) (d) is a figure which shows the potential when a voltage is applied to each part shown to (a).

[Explanation of symbols]

1 P-type substrate 2 n ^- layer 3 CCD final gate electrode 4 Potential barrier forming gate electrode 5 Reset gate electrode 6 Floating diffusion (FD part) 7 Reset drain 10 p ⁺ layer D Charge detection part

Claims (2)

[Claims] 1. A diffusion region of another conductivity type formed on a semiconductor layer of one conductivity type, a potential barrier forming gate electrode provided adjacent to the diffusion region, and a potential barrier forming gate electrode provided adjacent to the potential barrier forming gate electrode. Floating diffusion amplifier type including a final gate electrode of the charge transfer device, a MOS transistor for resetting the diffusion region formed by using the diffusion region as a source electrode, and a source follower circuit for detecting the potential of the diffusion region. In the solid-state imaging device including the charge detection unit, the diffusion region of the other conductivity type is formed such that the impurity concentration thereof is high in the central portion of the diffusion region and thin in the end portion, and A solid-state imaging device comprising a diffusion region of one conductivity type formed on a central portion of the diffusion region. 2. An image pickup device comprising a photodiode including a diffusion region of another conductivity type formed on a semiconductor layer of one conductivity type and a diffusion region of one conductivity type formed on the diffusion region of another conductivity type. A portion, a diffusion region of another conductivity type formed on the semiconductor layer of one conductivity type, a potential barrier forming gate electrode provided adjacent to the diffusion region, and a potential barrier forming gate electrode provided adjacent to the potential barrier forming gate electrode. A final gate electrode of the charge transfer device and an MO for resetting the diffusion region formed by using the diffusion region as a source electrode.
A method of manufacturing a solid-state imaging device comprising an S-transistor and a source-follower circuit for detecting a potential of the diffusion region, the floating-diffusion amplifier-type charge detection unit comprising: A method of manufacturing a solid-state imaging device, comprising forming a charge detection unit at the same time as an impurity layer forming the photodiode.