JPH11274450A - Solid-state image pick up device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To read out the signal charge of a photodiode with a low voltage in the case of using a CMOS type solid-state image pick up device. SOLUTION: In a first conductivity type P well 11, a second conductivity type photodiode (n) region 12 is formed for photoelectric conversion, a gate electrode 15 is formed, with its one edge adjoining to the photodiode (n) region 12, and a second conductivity type drain region 22 is formed, adjoining to the other edge of the gate electrode 15. On the surface of the photodiode (n) region 12, a first conductivity type photodiode p<++> region 13 having a first concentration is formed at a prescribed distance from the one edge of the gate electrode 15, and a first conductivity type photodiode p<+> region 18 having a second concentration is formed, with its one edge adjoining to the one edge of the gate electrode 15 and the other edge contacting a photodiode p<++> region 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device for reading out signal charges of a photodiode at a low voltage in a CMOS solid-state imaging device.

[0002]

2. Description of the Related Art FIG. 9 is a sectional view of a cell portion of a conventional solid-state imaging device. In FIG. 9, the first conductivity type P well 1 is shown.
Is formed, an n region 2 of a photodiode (PD) portion of the second conductivity type is formed, and signal electrons subjected to photoelectric conversion are accumulated. On the silicon / oxide film interface of the photodiode part having the photoelectric conversion function and the storage function, the p ⁺ type surface shield layer 3 of the photodiode part of the first conductivity type is provided.
Are formed. Then, a second conductive type drain 5 of the transistor, which is a signal detection region, is formed on the surface portion of the P well 1 with the ion implantation region 4 of the MOS transistor being sandwiched from the surface shield layer 3.

A LOCOS region 6 is formed above the photodiode portion, the ion-implanted region 4 and the drain 5.
Are formed. A read gate 7 of the transistor is formed on the ion implantation region 4 with the LOCOS region 6 interposed therebetween, and ap ⁺ layer 8 for element isolation of the first conductivity type is formed between the LOCOS region 6 and the P well 1. I have.

The interface state formed at the silicon / oxide film interface is filled with holes by the surface shield layer 3 of the high-concentration first conductivity type region formed so as to shield the upper part of the photodiode. It is possible to eliminate the influence of the interface state, which is caused by disordered crystal arrangement, minute crystal defects, and heavy metal contamination. The signal electrons photoelectrically converted and accumulated in the photodiode PD-n region 2 are read out to the drain region 5 serving as a detection unit by applying a “high level (HIGH)” voltage to the readout gate 7.

FIG. 10 is a top view of a conventional cell corresponding to the structure of FIG. The n region 2 of the photodiode portion, which is an active region, is formed in the element isolation region (LOCOS element isolation in this example, but there are other methods) by a self-alignment step of ion implantation. By this method, the end surface of the read gate 7 is separated from the element isolation region 6.
The n-region 2 of the photodiode portion is formed up to the end face of.

Thereafter, in order to prevent the influence of the interface state, a first conductivity type surface shield layer 3 is formed on the front surface of the upper part of the n region 2 of the photodiode by the same self-alignment process. Adjacent pixels (cells) are separated from each other by an element isolation region 6. Although not shown, a plurality of transistors are formed adjacent to the photodiode portion, and the signal charges read here are amplified and read.

[0007]

As described above, conventionally,
Since the very high concentration surface shield layer 3 of about 5 × 10 ¹⁸ to 2 × 10 ¹⁹ was formed adjacent to the read gate 7, a channel was formed even when a voltage was applied to the read gate 7. Therefore, the signal of the photodiode could not be read.

Further, with such a buried photodiode structure called a pnp type, the photodiode has a potential bottom, and signal charges in the n region 2 of the photodiode portion can be completely read. This structure is described, for example, in N. Teranishi et al. , "An
interline CCD image sensor
or with reduced image la
g, "IEEE Trans. Electron
Devices, vol. ED-31, no. 12,
1984.

Particularly, in CCDs, a very high voltage of 15 V is used to read signals from such embedded photodiodes. However, from the viewpoint of low power consumption of LSIs and miniaturization of elements, a low voltage is used. A photodiode structure from which a signal can be read has been desired.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a CMOS solid-state imaging device capable of reading out signal charges of a photodiode at a low voltage. I do.

[0011]

That is, a first aspect of the present invention is to provide a semiconductor device of the first conductivity type on a semiconductor substrate or inside a well.
A plurality of photodiode regions of a second conductivity type opposite to the first conductivity type for photoelectric conversion, a gate electrode portion formed with one end adjacent to the photodiode region,
In a solid-state imaging device having a second conductivity type drain region formed adjacent to the other end of the gate electrode, the second conductivity type photodiode region has a surface portion from one end of the gate electrode. A first region having a first concentration of a first conductivity type and a first region having a first concentration and a surface portion of the photodiode region of the second conductivity type, one end of which is formed at a predetermined distance from the gate electrode. Close to one end and the other end is the first
And a second region having a second concentration of a first conductivity type having a different concentration from the first region.

According to a second aspect, in the first aspect,
The semiconductor device may further include a third region of the second conductivity type formed below the second region. The third invention is
In the first aspect, the second density of the second area is lower than the first density of the first area.

According to a fourth aspect of the present invention, a plurality of photodiode regions of the second conductivity type opposite to the first conductivity type for photoelectric conversion are provided on the semiconductor substrate of the first conductivity type or inside the well, and In a solid-state imaging device having a gate electrode portion formed with one end adjacent to the diode region and a second conductivity type drain region formed adjacent to the other end of the gate electrode, And a fourth region of the second conductivity type formed at least in part below.

By adopting this photodiode structure,
A solid-state imaging device that operates with a very low power supply voltage of 5 V, 3.3 V, or 2.0 V can be integrated with other peripheral circuits. In addition, by adopting the embedded photodiode structure, a high-quality solid-state imaging device with extremely low dark current (leakage current) can be provided. Further, since other peripheral circuits can be on-chip, the image processing can be made on-chip with the signal processing circuit on-chip.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a main part according to a first embodiment of a solid-state imaging device of the present invention.
(A) is a cross-sectional view of a cell portion of the solid-state imaging device, and (b) is a potential diagram corresponding to when the gate voltage is off and on.

In FIG. 1A, a first conductivity type P well 11 on a first conductivity type P substrate (not shown) or a second conductivity type N substrate (not shown) is shown. Next, a photodiode n (PD
-N) The region 12 is formed. Above the photodiode n region 12, a first conductivity type photodiode p ⁺⁺ (P
Dp ⁺⁺ ) region 13 is formed.

Here, the first conductivity type photodiode p
The edge of the ⁺⁺ region 13 is in contact with the LOCOS element isolation region 14 on one side, but is not in contact with the edge of the gate electrode 15 on the other side. That is, LOCOS
At the end of the element isolation region 14, the LOCOS element isolation region 14
Is connected to the first conductivity type p ⁺ region 17 for element isolation formed below the gate electrode 15, and contacts the first conductivity type photodiode p ⁺ region 18 on the gate electrode 15 side.

Generally, the concentration A of the photodiode p ⁺⁺ region 13 of the first conductivity type is about 5 × 10 ^{18 to} 5 × 10 ¹⁹ , but the concentration B of the photodiode p ⁺ region 18 is
Must be lower than the concentration A, for example, 5 × 10 ¹⁸ to 2 × 10 ¹⁷ is desirable.

Below the photodiode p ⁺ region 18 of the first conductivity type, an ion implantation region 19 of the second conductivity type may be formed. Also, the read gate electrode 15
An ion implantation region 21 for setting the threshold value of the MOS transistor is formed below the insulating film 20 via an insulating film 20. On the other side of the readout gate electrode 15, a drain region 22, which is a signal detection region, is formed, and receives a signal charge of the photodiode n region 12. At the end of the drain region 22, a LOCOS element isolation region 14 is formed via a first conductivity type p ⁺ region 17 for element isolation. The gate length of the gate electrode 15 is, for example, 0.7 μm.

In such a configuration, the gate electrode 15
, 3.3 V, which is a voltage smaller than the CCD read voltage of 15 V, is applied. That is, the signal charge of the photodiode n region 12 must be read to the drain region 22 of the read gate at 3.3 V. For that purpose, the channel potential of the readout gate must be modulated by the gate electrode 15.

[0021] However, the concentration of the P-well 11 which is actually used, 1 × a 10 ¹⁵ approximately to 2 × 10 ^17, the photodiode p ⁺⁺ regions are further electrically shielded silicon / oxide film interface 13 is 5 × 10 ^{18 to} 5 × 1
It is a very large value of about 0 ^19. Depending on the relationship between the concentration A of P well 1 and the concentration of the photodiode p ⁺⁺ region 13, if the density difference is about two orders of magnitude, if photodiode p ⁺⁺ region 13 is to the bottom of the readout gate electrode 15 If extended, the channel cannot be opened even when 3.3 V is applied to the gate electrode 15.

However, as shown in FIG. 1A, the concentration A of the photodiode p ⁺⁺ region 13 having a high concentration is high.
If the photodiode p ⁺ region 18 having a lower concentration is formed adjacent to the gate electrode 15, the silicon / oxide film interface can be shielded by the region of the first conductivity type, and further modulates the channel of the read gate. And be able to. This is indicated by a and b in the potential diagram of FIG. Here, a is a potential design value of the silicon / oxide film interface, and b is a potential design value of a portion to be a channel.

Since the concentration B is relatively lower than the concentration A, the potential at the silicon / oxide film interface becomes lower due to the concentration B of the photodiode p ⁺ region 18 as shown in FIG. This is a region between the gate electrode 15 indicated by a and the photodiode n region 12 where the potential is low.

However, this photodiode p ⁺ region 1
8 is the concentration A of the photodiode p ⁺⁺ region 13.
Therefore, modulation can be performed by the gate electrode 15. That is, the signal charges in the n region 12 of the photodiode portion can be read out and read out to the drain region 22.

Further, a potential gradient can be provided in the direction from the photodiode shown in FIG. 1A to the readout gate electrode 15 by the two types of concentration differences of the concentration A and the concentration B. This potential gradient not only enables signal readout but also serves to eliminate signal charges remaining in the photodiode region. Further, since the potential of this portion is shielded by the photodiode p ⁺ region 18, generation of a leak current from the silicon / oxide film interface can be suppressed.

That is, with such two or more types of interface shield structures, signal charges in the n region 12 of the photodiode are completely read out to the drain region 22 of the MOS transistor while the potential of the silicon / oxide film interface is shielded. It becomes possible.

Further, the photodiode p ⁺ region 18
By controlling the density B, the degree of modulation of the read gate electrode 15 can be reduced. When the readout gate is turned on by the reduced modulation degree, a signal can be read out as shown by c in FIG. This is because the concentration B of the photodiode p ⁺ region 18 has become smaller than the concentration A of the photodiode p ^{+ +} region 13.

Here, c indicates the potential value of the read gate portion when the ion implantation region 21 is turned on. Gate electrode 1 read from photodiode section 2
The potential gradient that becomes deeper in the direction of 5 is the photodiode p ⁺⁺
Although it can be formed only by the region 13, the photodiode p ⁺ region 18 and the ion implantation region 19 located thereunder are formed.
It can also be achieved in combination with

Next, a second embodiment of the present invention will be described. In the embodiment described below, the same parts as those in the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted.

FIGS. 2A and 2B show a configuration of a main part of a solid-state imaging device according to a second embodiment of the present invention. FIG. 2A is a sectional view of a cell portion of the solid-state imaging device, and FIG. FIG. 4 is a potential diagram corresponding to when the voltage is off and when it is on.

In the second embodiment, the ion implantation region 19 of the second conductivity type in the first embodiment shown in FIG. 1 is replaced with the ion implantation region 25 of the second conductivity type. I have. The ion implantation region 25 is formed below the readout gate electrode 15 and further below the ion implantation region 21. The ion implantation region 25
Are formed to protrude from both ends of the read gate electrode 15 by about 0.2 μm, for example.

In FIG. 2B, d is a potential design value at the silicon / oxide film interface, e is a potential design value of a portion to be a channel, and f is the ion implantation regions 21 and 25 turned on. The potential value of the read gate portion at the time.

By forming the ion implantation region 25 of the second conductivity type, the read gate can be changed from 0.0V to-
It can be a depletion type of about 0.6V.
This depletion type uses the photodiode n region 12
Is read through the inside of silicon, so that M
The effect of 1 / f noise or thermal noise generated at the interface of the OS transistor can be reduced.

FIGS. 3A and 3B show a configuration of a main part of a solid-state imaging device according to a third embodiment of the present invention. FIG. 3A is a sectional view of a cell portion of the solid-state imaging device, and FIG. FIG. 4 is a potential diagram corresponding to when the voltage is off and when it is on.

In the third embodiment, the ion implantation region 25 shown in FIG. 2 is formed only as a part of the ion implantation region 27 below the readout gate electrode. The signal charges in the photodiode n region 12 can pass through the ion implantation region 27.

The region indicated by X in the figure is the gate electrode 1
5 can be changed. Therefore, when the signal charges are read from the photodiode n region 12 to the ion implantation region 27, the signal charges can be read immediately to the drain region 22 by turning on the gate electrode 15.

Further, in FIG. 3B, g is a potential design value at the silicon / oxide film interface, h is a potential design value at a portion to be a channel, and i is the ion implantation regions 21 and 27 turned on. The potential value of the read gate portion at the time.

What is important here is that the concentration B of the photodiode p ⁺ region 18 in the interface shield region of the first conductivity type can be read with a low voltage of 3.3 V so that the signal charge of the photodiode n region 12 can be read out. Is made smaller than the concentration A of the photodiode p ⁺⁺ region 13 which is another interface shield.

Further, by forming an ion implantation region 27 of the second conductivity type in a part below the readout gate electrode 15, the signal charge accumulation region extends to a region X that can be modulated by the gate electrode 15. be able to. As a result, the signal charges in the photodiode n region 12 can be read out to the drain region 22.

FIG. 4 is a top view showing an example of the arrangement inside the cell of the solid-state imaging device of the present invention. The signal charge inside the photodiode n region 12 is read by the read gate electrode 15 to the drain region 22 which is a signal detection unit. Adjacent photodiode n regions 12 are electrically isolated by element isolation regions 14, respectively. In this example, the element isolation region 14 is separated by a LOCOS region having a thick oxide film, but may be separated by another method.

Above the photodiode n region 12,
High-concentration photodiode p ⁺⁺ region 13 of first conductivity type
Then, a photodiode p ⁺ region 18 of the first conductivity type is formed. First conductivity type photodiode p ⁺ region 1
8 is the first conductivity type photodiode p ⁺⁺ region 1
3 and the readout gate electrode 1
5, a concentration gradient is formed.

With this configuration, by applying a low voltage to the readout gate electrode 15, the signal charges of the photodiode n region wet 2 can be read out to the drain region 22, which is a signal detection unit.

FIG. 5 is a top view showing an example of the arrangement inside the cell shown in FIG. 1 described above. In FIG. 5, a low-concentration photodiode p ⁺ region 18 of the first conductivity type is formed on the front surface of the photodiode n region 12. Further, the photodiode p ⁺⁺ region 13 of the first conductivity type overlaps with the photodiode p ⁺ region 18 and is formed to be separated from the read gate electrode 15.

The ion implantation region 19 of the second conductivity type is used.
Are formed on the read gate electrode 15 by self-alignment. FIG. 6 is a top view showing another arrangement example inside the cell shown in FIG. The difference between FIG. 6 and FIG. 5 is that the photodiode p ⁺⁺ region 13 of the first conductivity type and the ion implantation region 19 of the second conductivity type are formed separately. Thereby, inside the photodiode n region 12,
A concentration gradient in the P region can be provided toward the direction of the read gate electrode 15.

FIG. 7 is a top view showing an example of the arrangement inside the cell shown in FIG. In FIG. 7, a second conductivity type ion implantation region 25 is formed in a channel portion of the read gate electrode 15 so that signal charges in the photodiode n region 12 can be easily read. By the ion implantation region 25, the transistor of the read gate electrode 15 can be operated as a depletion type of -0.6 V or less.

As a result, the signal charges in the photodiode n region 12 can be read out to the drain region 22 which is a signal detecting portion even at a low voltage. FIG. 8 is a top view showing an example of the arrangement inside the cell shown in FIG.

In FIG. 8, the photodiode n region 1
2, a first conductivity type photodiode p ⁺⁺ region 1
3 and a photodiode p ⁺ region 18 are formed.
Further, by forming the ion implantation region 27 of the second conductivity type before forming the readout gate electrode 15, the signal charges of the photodiode n region 12 can be read out to the drain region 22 which is a signal detection unit. .

The present invention is not limited to the embodiment described above. For example, the silicon / oxide film interface is
Shielding with a conductive region can suppress the influence of irregularities in crystal defects, minute crystal defects, and interface states generated by heavy metal impurities and the like.

[0049]

As described above, according to the present invention, the CMO
In the S-type solid-state imaging device, it is possible to provide a solid-state imaging device capable of reading out signal charges of a photodiode at a low voltage.

[Brief description of the drawings]

FIGS. 1A and 1B show a configuration of a main part of a solid-state imaging device according to a first embodiment of the present invention, wherein FIG. 1A is a cross-sectional view of a cell portion of the solid-state imaging device, and FIG. FIG. 4 is a potential diagram corresponding to the time and the ON state.

FIGS. 2A and 2B show a configuration of a main part of a solid-state imaging device according to a second embodiment of the present invention, wherein FIG. 2A is a cross-sectional view of a cell portion of the solid-state imaging device, and FIG. FIG. 4 is a potential diagram corresponding to the time and the ON state.

FIGS. 3A and 3B show a configuration of a main part of a solid-state imaging device according to a third embodiment of the present invention, wherein FIG. 3A is a cross-sectional view of a cell portion of the solid-state imaging device, and FIG. FIG. 4 is a potential diagram corresponding to an off state and an on state.

FIG. 4 is a top view showing an example of an arrangement inside a cell of the solid-state imaging device of the present invention.

FIG. 5 is a top view showing an example of the arrangement inside the cell shown in FIG. 1;

FIG. 6 is a top view showing another example of arrangement inside the cell shown in FIG. 1;

FIG. 7 is a top view showing an example of the arrangement inside the cell shown in FIG. 2;

FIG. 8 is a top view showing an example of the arrangement inside the cell shown in FIG. 3;

FIG. 9 is a sectional view of a cell portion of a conventional solid-state imaging device.

FIG. 10 is a top view of a conventional cell corresponding to the structure of FIG.

[Explanation of symbols]

11 P well, 12 photodiode n region, 13 photodiode p ⁺⁺ region, 14 element isolation region, 15 gate electrode, 17 first conductivity type p ⁺ region, 18 photodiode p ⁺ region, 19, 21, 25, 27 ion implantation region, 20 insulating film, 22 drain region.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroshi Yamashita 1 Toshiba R & D Center, Komukai, Kawasaki-shi, Kanagawa Prefecture (72) Inventor Ikuko Inoue Tokuba Komukai, Koyuki-ku, Kawasaki-shi, Kanagawa (72) Inventor Hidetoshi Nozaki 1 Tokoba-Toshiba-cho, Komukai Toshiba-cho, Kawasaki-shi, Kanagawa

Claims (4)

[Claims] 1. A plurality of photodiode regions of a second conductivity type opposite to the first conductivity type for photoelectric conversion on a semiconductor substrate of a first conductivity type or inside a well, and one end in the photodiode region. A solid-state imaging device having a gate electrode portion formed adjacent to the second conductive type and a drain region of the second conductive type formed adjacent to the other end of the gate electrode. A first region having a first concentration of a first conductivity type and being formed at a predetermined distance from one end of the gate electrode on a surface portion of the region, and a photodiode region of the second conductivity type And one end thereof is formed close to one end of the gate electrode and the other end thereof is in contact with the first region. The first conductive type has a different concentration from the first region. A second region having a density of 2. The solid-state imaging device, characterized by. A second region formed below the second region;
The solid-state imaging device according to claim 1, further comprising a third region of a conductivity type. 3. The solid-state imaging device according to claim 1, wherein the second density of the second area is lower than the first density of the first area. 4. A plurality of photodiode regions of a second conductivity type opposite to the first conductivity type for performing photoelectric conversion on a semiconductor substrate of a first conductivity type or inside a well, and one end in the photodiode region. And a second conductive type drain region formed adjacent to the other end of the gate electrode, at least below the gate electrode portion. A solid-state imaging device comprising a second region of a second conductivity type formed in a part thereof.