JPH1074928A - Amplification type solid-state image pickup element and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the dark currents of picture elements by performing electric charge injection at the interface between the surface of a semiconductor and an insulating film within a required time in a horizontal cycle period at every plurality of horizontal cycle periods. SOLUTION: An occurrence of paired electron-Hall at the interface between the surface of a p-type sensor area 8 and a gate insulating film 9 of a pixel MOS transistor 11 is suppressed by injecting electronic charges (electrons) into the interface within a horizontal effective scanning period in an electric charge storing period, for example, the horizontal cycle period. Namely, the electrons are injected into a channel from a source area 2 or drain area 3, by making at least the source potential or drain potential lower than the channel potential. This electron injection is performed once per plurality of horizontal cycle periods. Therefore, the dark current caused by the interface can be suppressed and, at the same time, the occurrence of the dark current which is generated when a channel current flows can be suppressed by preventing the flow of the channel current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplification type solid-state imaging device and a driving method thereof.

[0002]

2. Description of the Related Art It is well known that in a CCD solid-state image pickup device having a buried channel, holes or electrons are injected into the surface to prevent generation of dark current from the surface, thereby burying interface states. ing.

[0003]

A technique for injecting charges into this surface to fill the interface state (hereinafter abbreviated as charge injection).
Can also be applied to a certain type of amplification type solid-state imaging device. For example, there is a solid-state imaging device in which a potential well region is formed in a substrate below a gate electrode of a MOS transistor, carriers that have been photoelectrically converted are accumulated in the potential well region, and thereby modulation of the substrate bias is extracted as a signal. is there.

FIG. 10 shows an amplification type solid-state imaging device of this type using an n-channel MOS transistor as a pixel. It should be noted that a solid-state imaging device can be similarly configured in the case of the p-channel.

FIG. 10B shows a light receiving element as a unit pixel.
That is, it is a cross-sectional view showing a semiconductor structure of the pixel MOS transistor 20. In the pixel MOS transistor 20, an n-type semiconductor region 25 and a p-type semiconductor region 26 serving as an overflow barrier region are sequentially formed on a semiconductor substrate 24 made of p-type silicon. A so-called sensor region 28 made of a p-type semiconductor region having a high concentration is formed. Further, the sensor area 2
A ring-shaped gate electrode 21 capable of transmitting light through a gate insulating film 29 made of, for example, SiO ₂ is formed on the gate electrode 8, and signals corresponding to the inside and outside of the ring-shaped gate electrode 21 are respectively n-type. Are formed in the p-type semiconductor region 26 immediately below the drain region 23, and n-type for preventing signal charges accumulated under the gate from leaking to adjacent pixels. The channel stop region 27 is formed. This pixel M
As shown in FIG. 10A, a plurality of OS transistors 20 are arranged in a matrix, and
Is configured.

In the pixel MOS transistor 20, as shown in FIG. 10B, the light L transmitted through the ring-shaped gate electrode 21 is photoelectrically converted in a silicon semiconductor to generate a pair of electrons and holes. One of the charges, in this example, the hole h is a potential well formed in the p-type sensor region 28 below the gate electrode 21 as a signal charge (FIG. 11).
(See the potential diagram of The modulation of the substrate bias by the charge (hole) h is taken out as a signal. That is, when a high-level potential (see the gate potential V _{g-read in} FIG. 11) is applied to the gate electrode 21 through the vertical selection line and the pixel MOS transistor 20 is turned on, a channel current (a so-called drain current) is applied to the surface of the sensor region 28. This channel current is modulated by the signal charge h, and this channel current is output through a vertical signal line connected to the source region 22, and the amount of change is used as a signal output.

FIG. 8 shows an amplifying type solid-state imaging device of the capacitive load operation type.
FIG. 2 is a circuit configuration diagram of an image element. This amplification type solid-state imaging device 3
0, a light receiving element constituting a plurality of unit pixels (cells);
That is, the pixel MOS transistors 20 are arranged on a matrix.
And the gate of each pixel MOS transistor 20 is shifted.
From the vertical scanning circuit 41 composed of
Vertical scanning signal (ie, vertical selection pulse) φV [φV₁, ...
..ΦV_i, ΦV_{i + 1}, ....] vertical selection line
42, the drain of which is connected to the power supply V_DDConnected to
The source for each column is connected to the vertical signal line 43. Hanging
The direct signal line 43 receives a signal via an operation MOS switch 44.
A load capacitance element 45 that holds a signal voltage (charge) is connected.
You. The load capacitance element 45 is connected between the vertical signal line 43 and the ground potential.
Connected between them. The gate of the operation MOS switch 44
Operation pulse φ _OPSIs applied.

A reset bias voltage V _RB is applied to a vertical signal line 43 between the source of the pixel MOS transistor 20 and the operation MOS switch 44 via a reset MOS switch 46 which also serves to reset the load capacitance element 45 and reset the vertical signal line 43. Is connected to a reset bias voltage supply terminal 47 for supplying the reset bias voltage. Reset MOS switch 46
_Are supplied with a reset pulse φ _RST . Reference numeral 48 denotes a horizontal scanning circuit composed of a shift register or the like. This horizontal scanning circuit 48 sequentially supplies horizontal scanning pulses φH [φH ₁ ,... ΦH to the gate of a horizontal MOS switch 50 connected to a horizontal signal line 49. _n , φ
H _{n + 1} ,...]. An output circuit (for example, a charge detection circuit) is connected to an output terminal of the horizontal signal line 49.

FIG. 9 is a circuit configuration diagram corresponding to one pixel in FIG. In the amplification type solid-state imaging device 30, first, during the horizontal blanking time, before the operation period of the pixel MOS transistor, the vertical signal line 43 and the load capacitance element 45 are reset to the reset bias voltage V _RB .
That is, the operation MOS switch 4 reset MOS switch 46 is given a reset pulse phi _RST and operation pulse phi _OPS
And 4 simultaneously. As a result, the initial voltage of the vertical signal line 43 and the load capacitance element 45 before the operation period of the pixel MOS transistor 20 is reset to the reset bias voltage V _RB .

[0010] After this, the vertical selection line to turn off the reset MOS switch 46 is supplied with a vertical selection pulse .phi.V _i to the vertical selection line 42 of the example i row, this time, the operation pulse phi _{OP S} are given subsequently, the operation The MOS switch 44 is on. At this point, the signal voltage for one column of the pixel MOS transistor 20 on the i-th row selected is held in each load capacitance element 45. That is, the pixel MOS
Signal charge amount (hole amount) accumulated in transistor 20
Is held in the load capacitance element 45. In the pixel reset period at the end of the horizontal blanking period, for example, the substrate pulse φ is applied to the substrate.
V _SUB (not shown) is applied, and the signal charges stored in the pixel MOS transistor 20 are discharged to the substrate side.

Next, the signal voltage held by these load capacitance elements 45 is applied to the horizontal scanning circuit 48 during the horizontal scanning period.
Horizontal scanning signal φH [φH ₁ ,... ΦH _n , φH
_{n + 1} ,...], the horizontal MOS switches 50 are sequentially turned on to flow as signal charges to the horizontal signal lines 49,
It is output as a signal voltage through the output circuit.

By the way, the amplification type solid-state imaging device 30 described above is used.
It is desired to reduce dark current as much as possible. There are two causes for dark current, one is the pixel M
The generation of hot carriers in the OS transistor, and the generation of electron-hole pairs at the gate interface of the pixel MOS transistor, ie, at the interface between the gate insulating film and the semiconductor surface, are the other. In the above-described amplification type solid-state imaging device 30, when the pixel MOS transistor 20 is off, the pixel M
No minute current flows through the OS transistor 20, and no hot carriers are generated. Therefore, no dark current is generated due to the generation of hot carriers. However, during the charge accumulation period (so-called light receiving period), the pixel MOS transistor 20 is in an off state. In this off state, charges (electrons) cannot be injected into the surface of the gate portion of the pixel MOS transistor 20, and thus the electrons are The dark current increases due to the generation of hole pairs and the accumulation of holes in the sensor region 28.

The present invention has been made in view of the above circumstances, and provides an amplifying solid-state imaging device capable of reducing dark current of a pixel and a driving method thereof.

[0014]

According to the present invention, a charge injection for suppressing a dark current at an interface between a semiconductor surface of a pixel and an insulating film is performed within a required period within a horizontal repetition period,
This charge injection is performed once every several times the horizontal repetition cycle.
To be performed twice.

As described above, the charge injection to the interface is performed once every multiple times of the horizontal repetition cycle.
The dark current caused by the interface can be suppressed, and the dark current caused by the operation of injecting charge into the interface can be suppressed.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An amplification type solid-state imaging device according to the present invention is an amplification type solid-state imaging device in which electric charge is injected into an interface between a semiconductor surface of a pixel and an insulating film to suppress a dark current. Means are provided for injecting charges into the interface during a required period in the horizontal repetition cycle, and the charge injection is performed once every multiple times the horizontal repetition cycle.

According to the present invention, in the amplification type solid-state imaging device, the sum of the amount of dark current caused by the operation of injecting charge into the interface and the amount of dark current caused by the interface is minimized. The configuration is set to the cycle.

According to the present invention, in the above-mentioned amplification type solid-state image pickup device, the multiple cycle is set to a cycle of 2 to 10 times.

In the driving method of the amplification type solid-state imaging device according to the present invention, charge injection for suppressing a dark current at an interface between a semiconductor surface of a pixel and an insulating film is performed during a required period in a horizontal repetition period, and The charge injection is performed once every multiple times the horizontal repetition cycle.

According to the present invention, in the method for driving an amplification type solid-state image pickup device, the sum of the dark current amount caused by the operation of injecting charges into the interface and the dark current amount caused by the interface may be set to the plural times period. Set to the minimum cycle.

According to the present invention, in the method of driving an amplification type solid-state image pickup device, the cycle of the multiple is set to a cycle of 2 to 10 times.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows an amplification type solid-state imaging device according to the present embodiment, and the pixel structure has the same configuration as that of FIG. That is, FIG. 1B is a cross-sectional view showing a light receiving element as a unit pixel according to the present embodiment, that is, a semiconductor structure of the pixel MOS transistor 11.

The pixel MOS transistor 11 has a first
A second conductivity type, for example, an n-type semiconductor region 5 and a p-type semiconductor region 6 serving as overflow barrier regions are sequentially formed on a semiconductor substrate 4 made of a conductivity type, for example, p-type silicon, and the surface of the p-type semiconductor region 6 is formed. Then, a so-called sensor region 8 made of a p-type semiconductor region having a higher concentration is formed. Further, a ring-shaped gate electrode 1 capable of transmitting light is formed on the sensor region 8 via a gate insulating film 9 made of, for example, SiO ₂ or the like, and at positions corresponding to the inside and outside of the ring-shaped gate electrode 1. An n-type source region 2 and a drain region 3 are formed respectively, and signal charges accumulated under the gate are prevented from leaking to adjacent pixels in the p-type semiconductor region 6 immediately below the drain region 3. An n-type channel stop region 7 is formed. As shown in FIG. 1A, a plurality of pixel MOS transistors 11 are arranged in a matrix to form an amplification type solid-state imaging device 10. This pixel MOS transistor 1
The operation of No. 1 is the same as that of the pixel MOS transistor 20 of FIG.

In this embodiment, the charge is applied to the pixel MOS transistor 11 at the interface between the surface of the p-type sensor region 8 and the gate insulating film 9 during the charge accumulation period, for example, the horizontal effective scanning period of the horizontal repetition period (H). In this example, electrons are injected to suppress the generation of electron-hole pairs at this interface. That is, a bias voltage is applied to the gate electrode 1 so that the channel on the surface of the p-type sensor region 8 is turned on (so-called electrons are injected). In other words, at least one of the source potential and the drain potential is set lower than the channel potential. Then, electrons are injected from the source region 2 or the drain region 3 into the channel, thereby suppressing dark current caused by the interface. At that time, the source potential and the drain potential are made the same, and the channel potential is reduced. By preventing the current from flowing, generation of dark current due to, for example, hot carriers or the like caused by the flow of the channel current is suppressed.

FIG. 2 shows a circuit configuration of the amplification type solid-state imaging device 10 according to the present embodiment. That is, this is an example of a circuit configuration that enables injection of charge to the interface and the same potential of the source and the drain during the charge injection period. However, FIG. 2 shows a circuit configuration corresponding to one pixel as in FIG. 9 described above.

The circuit configuration of FIG. 2 is similar to that of FIG. 9 described above, in which light receiving elements constituting a plurality of unit pixels (cells), that is, pixel MOS transistors 11, are arranged in a matrix. A vertical scanning signal (ie, a vertical selection pulse) φV [φV ₁ ,... ΦV _i , φ from a vertical scanning circuit 41 whose gate is constituted by a shift register or the like.
V _{i + 1} ,...], The drain is connected to the power supply _VDD, and the source for each column is connected to the vertical signal line 43. Vertical signal line 43
Is connected to a load capacitance element 45 that holds a signal voltage (charge) via an operation MOS switch 44 composed of, for example, an n-channel MOS transistor. Load capacitance element 4
5 is connected between the vertical signal line 43 and the ground potential. An operation pulse φ _OPS is applied to the gate of the operation MOS switch 44.

The vertical signal line 43 between the source of the pixel MOS transistor 20 and the operation MOS switch 44 is used to reset the load capacitance element 45 and reset the vertical signal line 43, that is, charge the source-side parasitic capacitance of the pixel MOS transistor 11. A reset bias voltage supply terminal 47 for supplying a reset bias voltage V _RB is connected via a reset MOS switch 46 also formed of, for example, an n-channel MOS transistor. Reset MOS switch 46
_Are supplied with a reset pulse φ _RST . Reference numeral 48 denotes a horizontal scanning circuit composed of a shift register or the like. The horizontal scanning circuit 48 sequentially supplies a horizontal scanning signal (that is, a horizontal scanning signal) to a gate of a horizontal MOS switch 50 composed of, for example, an n-channel MOS transistor connected to a horizontal signal line 49. (Scanning pulse) φH [φH ₁ , ··· φH
_{n, φH n + 1, ····} ] is supplied. An output circuit (for example, a charge detection circuit) is connected to an output terminal of the horizontal signal line 49.

In this embodiment, a first MOS switch 12 composed of, for example, a p-channel MOS transistor is connected between the drain of the pixel MOS transistor 11 and the power supply V _DD, and the drain of the pixel MOS transistor 11 A second MOS switch 13 composed of, for example, an n-channel type MOS transistor for charging a parasitic capacitance on the drain side of the pixel MOS transistor is connected between the second MOS switch 13 and the reset bias voltage supply terminal 47. The drive pulse φ _PDSP is applied to the gate of the first MOS switch 12, and the drive pulse φ _PDSN is applied to the gate of the second MOS switch 13.
Here, the relationship between the power supply V _DD and the reset bias voltage V _RB is V
_DD > V _RB .

Next, the operation of the circuit configuration of FIG. 2 will be described. First, as briefly described, as shown in the timing chart of FIG. 5, the pixel MOS transistor 11 is not in the horizontal blanking period when it is not selected, that is, the horizontal blanking period H _BLK and horizontal effective scanning period (so-called standby) when it is selected. During the period T _A , the vertical selection pulse φV is continuously applied to the gate, and the gate is in the ON state. The signal voltage in the pixel MOS transistor 11, that is, the signal voltage corresponding to the channel potential corresponding to the signal charge amount (hole amount) accumulated in the pixel MOS transistor 11, is read out to the load capacitance element 45 by horizontal blanking. Done during the period. That is, the reset pulse φ is applied to the reset period T ₁ before the readout period T ₂ of the pixel MOS transistor 11 during the horizontal blanking period H _BLK.
At the same time that the reset MOS switch 46 is turned on by the _{application of RST} , the operation pulse φ _OPS is applied and the operation MOS
When the switch 44 is also turned on, the load capacitance element 45 is reset to the reset bias voltage V _RB .

Next, the signal voltage of the pixel MOS transistor 11 is held in the load capacitance element 45 during the readout period T ₂ in which the reset MOS switch 48 is turned off and the operation MOS switch 44 is turned on. After the read is completed, the substrate pulse .phi.V _SUB pixel reset period T ₃ is applied to the substrate, the charge accumulated in the pixel MOS transistor 11 (hole) is discharged through the substrate. Thereafter, during the horizontal effective scanning period T _A , the horizontal scanning pulse φH [φH ₁ ,... ΦH _n , φH _{n + 1} ,.
..], the signal charges of one line are sequentially transferred to the horizontal signal line 49.
And output. The above is the outline of the operation.

Then, the amplification type solid-state imaging device 10 of this embodiment
Adopts the circuit configuration shown in FIG. 2 so that no current flows through the pixel MOS transistor 11 except during reading. FIG. 6 shows an example of this drive timing. As shown in FIG. 6, in the reset period T _1, and turns off the first MOS switch 12 and the drive pulse phi _PDSP and the drive pulse phi _PDSN to a high level, thereby turning on the second MOS switch 13, a reset pulse to turn on the reset MOS transistor 46 and the phi _RST to high level, also operate in the operation pulse phi _OPS to the high level MOS
The switch 44 is turned on.

As a result, the load capacitance element 45 is reset to the reset bias voltage V _RB , and at the same time, the parasitic capacitance of the vertical signal line 43 on the source side and the parasitic capacitance of the wiring on the drain side of the pixel MOS transistor 11 are charged. The potentials of the drains are reset to the same reset bias voltage V _RB .

Next, in the readout period T ₂ , the low level of the drive pulse φ _{PDSP and} the low level of the drive pulse φ _PDSN are applied to the gates of the first MOS switch 12 and the second MOS switch 13 respectively. Is turned on, the second MOS switch is turned off, and the low level of the reset pulse φ _RST is applied to the gate of the reset MOS switch 46, so that the reset MOS switch 46 is turned off. Thereby, the pixel MO
The signal voltage of S transistor 11 is held in load capacitance element 45.

Next, after the operation MOS switch 44 is turned off, the signal voltage held in the load capacitance element 45 is changed to a horizontal scanning pulse φH [φH ₁ ,.
_n, .phi.H _n + 1, by turning on successively the horizontal MOS switch 50 in ...], the horizontal signal line as the signal charges 49
And output as a signal voltage through an output circuit.
In the non-read period T _2, the first MOS switch 12 is turned off, the second MOS switch 13 turned on, the reset MOS switch 46 is turned on. According to this example, at the time of reset, the source and the drain of the pixel MOS transistor 11 have the same potential due to the reset bias voltage V _RB . No current flows. Therefore, there is no generation of hot carriers, and dark current due to generation of hot carriers can be suppressed. Moreover, by injecting electrons into the gate surface with the pixel MOS transistor 11 turned on, generation of electron-hole pairs at the interface can be suppressed, and dark current due to the interface can be suppressed.

In the example of FIG. 5 described above, the read operation is performed in the horizontal blanking period H _BLK , and the phase of charge injection is the horizontal effective scanning period. By turning on the non-selected pixels in the charge injection phase, it is expected that the time for the charges to fill the interface state becomes longer and the dark current is further suppressed.

By the way, in the case of the driving timing example of FIG. 5, the non-selected pixel is turned off every horizontal blanking period H _BLK during which the selected pixel is read out. As described above, when the non-selected pixels into which the charge injection has been performed to perform the read operation are turned off, the remaining charge injected into the channel region is discharged to the source / drain region. Acceleration is caused by an electric field between the drains, and hot carriers are generated, which may cause dark current.

FIG. 7 is a schematic diagram showing this state. Pixel MO
When the S transistor is on, the channel potential has a slightly higher potential than the source / drain region potential V _RB . When the pixel MOS transistor is turned off, the potential of the channel becomes low and the difference between the potential of the source / drain region and the potential of the source / drain region (corresponding to the electric field between the two) also increases.

Accordingly, when the electrons e injected into the interface are discharged, the electrons e are accelerated by the electric field and have a large energy, which are impact-ionized to generate holes h, which are a source of dark current.

On the other hand, if an attempt is made to increase the time during which the charge is injected, the charge is injected and discharged a plurality of times.
For example, as shown in FIG. 5, when charge injection is performed every horizontal repetition period H, the number of times is equal to the number of vertical lines, which results in an increase in dark current.

Therefore, in the present embodiment, the number of times of charge injection is further reduced to reduce the occurrence of dark current.

The present inventor has found that, by injecting charges into the interface between the sensor region 8 and the gate insulating film 9, the effect of suppressing the dark current caused by the interface can be several to several tens even if the charge is subsequently depleted. μsec, the horizontal repetition cycle H is 2H ~
It was confirmed to last for about 10H. Therefore, in the present embodiment, the charge injection to the interface is not performed at every horizontal repetition period H, but is performed once every 2H or every 3H, for example.
H is performed at regular intervals, such as once, so that the sum of the dark current caused by the hot carriers and the dark current caused by the interface is minimized.

FIG. 4 shows this conceptual diagram. In FIG.
The vertical axis represents the amount of generation of dark current as a relative value, and the horizontal axis represents the frequency of charge injection.
This is the case where charge injection is performed. That is, the right end has an infinite charge injection interval, and the left end has a charge injection interval of 1H.

Dark current caused by hot carriers (curve 1)
Since 5) is proportional to the frequency of charge injection, the charge is injected most often every H, and becomes 0 when there is no charge injection. The dark current (curve 16) due to the interface often occurs without charge injection, and hardly occurs every H charge injection. The increase during that time becomes exponential.

Therefore, the sum of the dark current caused by the hot carriers and the dark current caused by the interface is calculated (curve 17), and the charge injection frequency that minimizes this is adopted.

The effect of suppressing the dark current due to one charge injection lasts up to about 10 H. Therefore, depending on other conditions of the solid-state image pickup device, the charge injection frequency at which the sum of the dark currents is minimized is as follows. Approximately once every 2H to 1 every 10H
Times. Therefore, it is desirable to set the interval of the charge injection period to 2H or more and about 10H or less.

FIG. 3 shows one example of the drive timing according to the present invention.
This is an example, and charge injection is performed once every 2H, that is, horizontal repetition cycle.
This is a case where it is performed once every twice the period H.
Every 1H for one line of pixel MOS transistor
Horizontal effective scanning period T _AThe vertical selection pulse φV [φ
V₁, ... · φV_i, ΦV_{i + 1}, ΦV_{i + 2}, ... ・]
The bell potential is applied to the gate electrode 1 of the pixel MOS transistor 11.
To give to.

In this way, by minimizing the dark current, a solid-state image sensor having good characteristics can be constructed.

In the above example, the case where the reading operation is performed during the horizontal blanking period and the phase of the charge injection is set to the horizontal effective scanning period has been described. The present invention can be applied to the case where the phase is a horizontal blanking period. In addition, the present invention is not limited to the above-described amplification type solid-state imaging device, and can be applied to an amplification type solid-state imaging device such as a CMD.

The solid-state image pickup device of the present invention is not limited to the above-described example, and may take various other configurations without departing from the gist of the present invention.

[0050]

According to the present invention described above, the charge injection for suppressing the dark current at the interface between the pixels is performed during a required period within the horizontal repetition period, and the charge injection is performed at a period that is a multiple of the horizontal repetition period. By doing it once every time,
The amount of dark current can be reduced by suppressing both the dark current caused by hot carriers and the dark current caused by the interface due to the charge injection operation.

Further, by selecting the charge injection interval, that is, the cycle of a plurality of times as described above, the sum of the dark current caused by hot carriers and the dark current caused by the interface is minimized, and the amount of dark current is reduced. Can be minimized. Therefore, according to the present invention, an amplifying solid-state imaging device with small dark current and excellent characteristics can be configured. Further, it is possible to perform driving such that the dark current is reduced.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of an amplification type solid-state imaging device according to the present invention. A is a plan view. B is a cross-sectional view taken along line AA ′ of FIG. 1A.

FIG. 2 is a circuit configuration diagram corresponding to one pixel of the amplification type solid-state imaging device of FIG.

FIG. 3 is a drive timing chart of the amplification type solid-state imaging device of FIG. 1;

FIG. 4 is a schematic diagram showing the relationship between the frequency of charge injection and the amount of generation of dark current.

FIG. 5 is a comparative example of a drive timing chart of the amplification type solid-state imaging device.

FIG. 6 is a timing chart of capacitance load reading.

FIG. 7 is a schematic diagram showing a state of dark current generation accompanying a charge injection operation.

FIG. 8 is a circuit configuration diagram of an amplification type solid-state imaging device of a capacitive load operation system.

9 is a circuit configuration diagram corresponding to one pixel of the amplification type solid-state imaging device in FIG.

FIG. 10 is a schematic configuration diagram of an amplification type solid-state imaging device of a comparative example. A is a plan view. B It is sectional drawing in XX 'of FIG. 10A.

11 is a vertical potential diagram of the amplification type solid-state imaging device of FIG. 10;

[Explanation of symbols]

1,21 gate electrode, 2,22 source region, 3,2
3 drain region, 4,24 semiconductor substrate, 5,25
Overflow barrier region, 6,26 p-type semiconductor region, 7,27 channel stop region, 8,28 sensor region, 9,29 gate insulating film, 10,30 amplification solid-state imaging device, 11,20 pixel MOS transistor,
2 1st MOS switch, 13 2nd MOS switch, 41 vertical scanning circuit, 42 vertical selection line, 43 vertical signal line, 44 operation MOS switch, 45 load capacitance element, 46 reset MOS switch, 47 reset bias voltage supply terminal , 48 horizontal scanning circuits, 49 horizontal signal lines, 50 horizontal MOS switches, h holes, e
Electronic, H _BLK horizontal blanking period, H horizontal repetition period, T _A horizontal effective scanning period, T ₁ reset period, T ₂ readout period, T ₃ pixel reset period, V
_RB reset bias voltage, L light, V _g-read gate potential

Claims (6)

[Claims] 1. An amplifying solid-state imaging device in which a charge is injected into an interface between a semiconductor surface of a pixel and an insulating film to suppress dark current, wherein the interface is connected to the interface during a required period within a horizontal repetition period. An amplification type solid-state imaging device, comprising: means for injecting electric charge, wherein the electric charge is injected once every plural times the horizontal repetition period. 2. The method according to claim 1, wherein the multiple cycle is set to a cycle in which a sum of a dark current amount caused by an operation of injecting charges into the interface and a dark current amount caused by the interface is minimized. The amplification type solid-state imaging device according to claim 1. 3. The amplifying solid-state imaging device according to claim 1, wherein the multiple cycle is set to a cycle of 2 to 10 times. 4. A charge injection for suppressing a dark current at an interface between a semiconductor surface of a pixel and an insulating film is performed during a required period in a horizontal repetition cycle, and the charge injection is performed a plurality of times of the horizontal repetition cycle. A method for driving an amplification type solid-state imaging device, wherein the method is performed once every cycle. 5. The method according to claim 1, wherein the multiple cycle is set to a cycle in which a sum of a dark current amount caused by an operation of injecting charges into the interface and a dark current amount caused by the interface is minimized. The method for driving an amplification type solid-state imaging device according to claim 4. 6. The driving method of an amplification type solid-state imaging device according to claim 4, wherein the multiple cycle is set to a cycle of 2 to 10 times.