JP2004221339A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the fixed pattern noise due to dark current even at gain-up in a solid-state imaging device using a solid-state imaging element. <P>SOLUTION: The solid-state imaging device is provided with a solid-state imaging element 1, a signal processing circuit 2, a CPU 3, a timing generation circuit 4, and a driving circuit 5. The CPU 3 changes the driving timing of the timing generation means at gain-up. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a solid-state imaging device using a so-called two-dimensional imaging device in which charge-coupled devices such as CCDs are arranged in an array, in addition to a solid-state imaging device.
[0002]
[Prior art]
Conventionally, a CCD image sensor, a CCD linear sensor, a CCD delay line, and the like are known as those having a charge transfer unit using a CCD structure.
[0003]
Among them, a CCD image sensor, for example, a frame interline transfer (FIT) type image sensor described in Japanese Patent Application Laid-Open No. 8-279608 is known.
[0004]
FIG. 5 shows the structure of a conventional FIT type image sensor, in which a large number of light receiving sections 6 for photoelectrically converting into an amount of charge corresponding to the amount of incident light are arranged in a matrix. A large number of vertical transfer registers 7 common to the light receiving units 6 arranged in the horizontal direction, an image unit (imaging unit) 8 arranged in the row direction, and an image unit (imaging unit) 8 There is no light receiving section 6 formed in the section 8 and a storage section (accumulation section) 10 formed by extending only a large number of vertical transfer registers 7 in the imaging section 8. Further, one horizontal transfer register 11 is provided adjacent to the storage unit 10 and common to many vertical transfer registers 9.
[0005]
The output unit 12 is connected to the last stage of the horizontal transfer register 11. The output 12 is a charge-to-electrical signal conversion unit composed of, for example, a floating diffusion for converting signal charges transferred from the final stage of the horizontal transfer register 11 into an electric signal (for example, a voltage signal), and the like. It has an amplifier for amplifying the electric signal from the signal section.
[0006]
The supply of the vertical transfer pulses ΦVA1 to ΦVA4 and the accumulation units ΦVB1 to ΦVB4 in the imaging unit 8 sequentially changes the potential distribution under each vertical transfer electrode in the imaging unit 8 and the accumulation unit 10, thereby reducing the signal charge. The data is transferred in the vertical direction (horizontal transfer register side) along the vertical transfer register 7 in the imaging unit 8 and the vertical transfer register 9 in the storage unit 10, respectively.
[0007]
In particular, in the imaging section 8, the signal charges accumulated in the light receiving section 6 are firstly read out to the vertical transfer register 7 in the readout period P shown in FIG. 6, and then, during the period FS shown in FIG. The signal charges transferred to the register 7 are transferred to the vertical transfer register 9 of the storage unit 10 at high speed.
[0008]
The accumulation unit 10 transfers the signal charges transferred to the vertical transfer register 9 during the period FS to the first horizontal transfer register 11 side by row in the subsequent horizontal flyback period HBLK.
[0009]
Then, in the next horizontal transfer period HBLK, the signal charges are sequentially transferred to the corresponding output unit 12 side, and are taken out as the imaging signal S from the output terminal 13 of the output unit 12. That is, the signal charges are stored under the electrodes ΦVB3 and ΦVB4 during a period from one horizontal transfer period to the next horizontal transfer period.
[0010]
However, all solid-state imaging devices are affected by dark current, and the dark current is caused by the generation of electron-hole pairs due to thermal excitation. Hereinafter, the cause of the dark current will be described.
[0011]
In the sectional view of the vertical transfer register having the conventional structure shown in FIG. 7, 14 is an n-type silicon substrate, 15 is a P well, 16 is an N-type semiconductor layer, 17 is an insulating film (silicon oxide film) made of SiO ₂ , This vertical transfer register has an embedded n-channel structure in which a P-type well 15 is provided on an n-type silicon substrate 14 and an N-type semiconductor layer 16 is provided on the substrate surface.
[0012]
Also, polysilicon is used as a gate electrode material, 18 is a first-layer polysilicon, and 19 is a second-layer polysilicon. Each polysilicon 18, 19 as an electrode is connected to a drive terminal of a vertical transfer register.
[0013]
FIG. 8 shows a well-known basic structure of a vertical transfer register. In the figure, (a) shows a state when a high level pulse is applied to the polysilicon gate electrode level, and (b) shows a state when a low level pulse is applied to the polysilicon gate. Here, it is known that the dark current of the vertical transfer register is almost generated from the interface between the insulating film 17 and the silicon substrate 14 in the state (a). This is because levels serving as a source of dark current are concentrated at the interface.
[0014]
On the other hand, when a low-level pulse is applied to the polysilicon gate electrode shown in FIG. 4B, the potential on the surface of the silicon substrate 14 is sufficiently shallow. Holes supplied from a channel stop (not shown) adjacent to the vertical transfer register are accumulated on the surface. As a result, the interface states are filled with holes, and the generation of electrons (that is, dark current) from the interface states is suppressed. For this reason, the occurrence of dark current in the state (b) is sufficiently negligible as compared with the state (a).
[0015]
That is, the dark current becomes dominant during the period in which the electric charge is stored under ΦVB3 and ΦVB4 which are at the high level during most of the LS period shown in FIG.
[0016]
A general function of a solid-state imaging device using such a solid-state imaging device is a gain-up function. This function is used for photographing at night or the like, and makes it possible to capture an image even in a dark photographing environment by increasing the signal gain from the standard photographing state.
[0017]
[Patent Document 1]
JP-A-8-279608 [0002] to [0014]
[0018]
[Problems to be solved by the invention]
By the way, in recent years, the charge-electric signal conversion efficiency has been increased in order to increase the sensitivity of the solid-state imaging device, and as a result, the dark current has also been amplified. As a result, there is a problem that fixed pattern noise due to dark current increases as compared to before the conversion efficiency is increased. This fixed pattern noise has become a particularly serious problem when the above-described gain-up function is used.
[0019]
[Means for Solving the Problems]
In order to solve this problem, the present invention changes the driving condition of the solid-state imaging device according to the situation of gain increase. Specifically, the number of gates accumulated during the LS period is set to be smaller than that at the time of the normal gain.
[0020]
As a result, the amount of dark current generated when the gain is increased can be reduced.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
The invention according to claim 1 of the present invention is directed to a solid-state imaging device having a plurality of light receiving elements, a vertical transfer register that receives and transfers charges from the light receiving elements, a driving unit that drives the vertical register, Timing generating means for determining the drive timing of the driving means, signal processing means for performing signal processing on the output of the solid-state imaging device, control of the signal processing means, the driving means, and operation of the timing generating means Controlling means for changing the driving conditions of the timing generating means and the driving means in accordance with the state of the signal processing means.
[0022]
The invention according to claim 2 is a solid-state imaging device having a plurality of light receiving elements, a vertical transfer register that receives and transfers electric charges from the light receiving elements, a driving unit that drives the vertical register, and a driving unit that drives the vertical register. Timing generating means for determining drive timing, signal processing means for performing signal processing on the output of the solid-state imaging device, signal processing means, the driving means, and control means for controlling the operation of the timing generating means And an operation of changing the operation of the timing generating means in accordance with the state of the gain of the signal processing means.
[0023]
According to a third aspect of the present invention, there is provided a solid-state imaging device having a plurality of light receiving elements, a vertical transfer register that receives and transfers charges from the light receiving elements, a driving unit that drives the vertical register, and a driving unit that drives the vertical register. Timing generating means for determining drive timing, signal processing means for performing signal processing on the output of the solid-state imaging device, signal processing means, the driving means, and control means for controlling the operation of the timing generating means And has the effect of changing the substrate voltage of the driving means in accordance with the state of the gain of the signal processing means.
[0024]
Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 6 and FIG.
[0025]
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a solid-state imaging device according to a first embodiment of the present invention corresponding to claims 1 and 2, and FIG. 2 is a block diagram of a solid-state imaging device according to the first embodiment of the present invention. 6 is a timing chart illustrating an operation of the solid-state imaging device when a gain is increased.
[0026]
In FIG. 1, a solid-state imaging device 1 is a CCD having a general structure as shown in FIG. 5, for example, and its output is connected to a signal processing circuit 2. The signal processing circuit 2 performs signal processing such as normal gain and gain up by the CPU 3 and outputs the processed signal.
[0027]
Further, the timing generation circuit 4 is switched by the CPU 3 so that the operation of the conventional solid-state imaging device as shown in FIG. 6 is normally performed, and the operation as shown in FIG. The drive circuit 5 converts the timing signal input from the timing generation circuit 4 into a desired voltage, supplies some other DC voltage signals to the solid-state imaging device 1, and operates the solid-state imaging device 1.
[0028]
Next, the normal operation and the gain-up operation will be described in more detail with reference to FIGS.
[0029]
Normally, as shown in FIG. 6, the period other than the charge reading period P from the light receiving unit to the vertical transfer register, the FS period for transferring the signal charge from the imaging unit to the storage unit at high speed, and the horizontal transfer from the vertical transfer register of the storage unit ΦVB3 and ΦVB4 are fixed at a high-level potential in all periods other than the period for transferring charges to the transfer register. That is, the signal charge is stored under these two electrodes for the majority of the time. Therefore, a large amount of dark current is mixed under these two electrodes.
[0030]
On the other hand, when the gain is increased, other than the charge reading period P from the light receiving unit to the vertical transfer register and the FS period in which the signal charge is transferred from the imaging unit to the storage unit at high speed as shown in FIG. Only ΦVB4 is fixed at the high-level potential in all periods other than the period for transferring charges from the register to the horizontal transfer register. That is, the signal charge is stored under one electrode ΦVB4 for the majority of the period. That is, since a smaller amount of gate electrode signal charges are stored than in the normal state, the dark current is less mixed.
[0031]
However, since the number of gates to be stored is reduced, the amount of stored charges is reduced, and the so-called dynamic range is reduced. Not be.
[0032]
As described above, according to the first embodiment, the charge is accumulated with a smaller number of gates at the time of the gain increase than at the normal time, so that the dark current can be prevented from being mixed at the time of the gain increase, and the fixed pattern can be reduced. It is possible to provide a good image with less noise.
[0033]
In the first embodiment, the case of a solid-state imaging device using an FIT-CCD has been described. However, the present invention is not limited to this, and is widely applicable to a case where a different solid-state imaging device such as an IT-CCD is used. Applicable.
[0034]
(Embodiment 2)
FIG. 3 is a diagram illustrating a relationship between a substrate voltage which is a driving voltage applied to the solid-state imaging device and a saturation voltage which is a maximum voltage of a signal output from the solid-state imaging device. As shown in FIG. 3, the saturation voltage increases as the substrate voltage decreases. That is, the dynamic range of the solid-state imaging device using the solid-state imaging device increases.
[0035]
On the other hand, when a solid-state imaging device such as a CCD captures a high-luminance object such as a halogen lamp or the sun, a signal leaks to pixels in a region below the high-luminance object on a screen (hereinafter referred to as V sagging). Will occur). This is improved as the substrate voltage is increased, and is improved as the number of storage gates in the vertical transfer register is increased (FIG. 4).
[0036]
Therefore, in the present embodiment, in the solid-state imaging device as shown in FIG. 1, the number of storage gates of the solid-state imaging device is reduced when the gain is increased, and the substrate voltage applied to the solid-state imaging device is also changed. In other words, the gain is increased so that a higher voltage than normal is applied.
[0037]
As described above, according to the second embodiment, at the time of gain increase, charges are accumulated with a smaller number of gates than at the normal time, and different substrate voltages are applied. As a result, it is possible to provide a good image with little fixed pattern noise, and it is also possible to satisfactorily suppress V sagging when a high-luminance subject is imaged.
[0038]
In the second embodiment, as in the first embodiment, the case of the solid-state imaging device using the FIT-CCD has been described. However, the present invention is not limited to this, and a different solid-state imaging device such as an IT-CCD may be used. It can be widely applied even when using.
[0039]
【The invention's effect】
As described above, according to the present invention, the optimal driving conditions of the solid-state imaging device are separately set according to the state of the signal processing circuit. Therefore, an advantageous effect that a good video signal can be obtained for each state of the signal processing is obtained. is there.
[0040]
In addition, there is an advantageous effect that fixed pattern noise of dark current, which is particularly remarkable when the gain is increased, can be favorably reduced.
[0041]
Further, in both the normal state and the gain-up state, there is an advantageous effect that a good image with little V sag can be obtained even when a high-luminance subject is imaged.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a solid-state imaging device according to an embodiment of the present invention; FIG. 2 is a timing chart showing an operation when the gain of the solid-state imaging device according to an embodiment of the present invention is increased; FIG. 4 is a diagram showing a relationship between a substrate voltage and a saturation voltage. FIG. 4 is a diagram showing a relationship between a substrate voltage of a CCD and a V sag level. FIG. 5 is a structural diagram showing a conventional image sensor. FIG. 7 is a cross-sectional view showing the structure of a conventional vertical transfer register. FIG. 8 is a diagram showing the potential of a conventional image sensor.
DESCRIPTION OF SYMBOLS 1 Solid-state image sensor 2 Signal processing circuit 3 CPU
Reference Signs List 4 timing generation circuit 5 drive circuit 6 light receiving unit 7, 9 vertical transfer register 8 imaging unit 10 storage unit 11 horizontal transfer register 12 output unit 13 output terminal 14 n-type silicon substrate 15 p-type well 16 n-type semiconductor layer 17 insulating film ( Silicon oxide film)
18 First layer polysilicon gate 19 Second layer polysilicon gate

Claims (3)

A plurality of light receiving elements, a solid-state imaging device having a vertical transfer register that receives and transfers electric charges from the light receiving elements, a driving unit that drives the vertical register, and a timing generation unit that determines a driving timing of the driving unit. A signal processing unit that performs signal processing on an output of the solid-state imaging device; a signal processing unit; the driving unit; and a control unit that controls an operation of the timing generation unit. A solid-state imaging device, wherein driving conditions of the timing generation unit and the driving unit are changed according to a state. 2. The solid-state imaging device according to claim 1, wherein an operation of said timing generating means is changed according to a gain state of said signal processing means. A solid-state imaging device, wherein a substrate voltage of the driving unit is changed according to a gain state of the signal processing unit.

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