JP5067414B2 - Solid-state image sensor driving apparatus, image input apparatus, and solid-state image sensor driving method - Google Patents

Description

  The present invention relates to a solid-state image sensor driving apparatus, an image input device, and a solid-state image sensor driving method.

  Patent Document 1 discloses a driving method for transferring and driving a vertical transfer register using a four-phase transfer pulse having a binary voltage value of a high level and a low level for a CCD (Charge Coupled Device). Has been.

1A to 1D are waveform diagrams of the four-phase vertical transfer pulses Vφ1 to Vφ4 similar to those described in Patent Document 1. FIG. Here, the case where the high level voltage is 0 [V] and the low level voltage is the negative voltage value VL is shown.
As shown in FIGS. 1A to 1D, the four-phase vertical transfer pulses Vφ1 to Vφ4 for driving the vertical transfer register have a low level (for example, negative) during a high level (for example, 0 [V]) period. Normally high vertical transfer pulses Vφ1 and Vφ2 longer than the period of the voltage value VL), and normally low vertical transfer pulses Vφ3 and Vφ4 whose low level period is longer than the high level period. Is included.
Here, “normally high” means that the level is high during the standby period including the time of light reception, and “normally low” means that the level is low during the standby period.

As the potential of the vertical transfer electrode is set to the negative side, the potential of the silicon surface functioning as a charge transfer channel becomes shallower, and holes are more easily accumulated therein. For this reason, the influence of the surface level caused by defects on the silicon surface, that is, the generation of electrons from the surface level, which is the dominant cause of dark current, is significantly suppressed. As a result, an increase in dark current can be suppressed. This phenomenon is called pinning.
Pinning occurs strongly when a low-level potential is applied to the transfer electrode from a state in which a high-level potential is applied to the transfer electrode of the vertical transfer register. However, in the potential between them, pinning is weaker toward the high level side. The lower level is stronger.

  In Patent Document 2, as a technique for reducing noise caused by dark current, in the vertical transfer register, the number of vertical transfer electrodes (number of storage gates) driven by a normally high pulse with a long high level period in which pinning is weak is long. A technique for reducing the dark current and suppressing the generation of dark current is disclosed.

Japanese Patent Laid-Open No. 06-014269 (refer to FIG. 4 and the like and the corresponding specification part) JP 2004-221339 A

  However, in the example of FIG. 1, for example, in the transfer electrode to which the normally low vertical transfer pulses Vφ3 and Vφ4 are applied, the negative potential is applied for a long time, and a strong electric field is applied to the gate insulating film for this long time. There is a concern that the reliability of the device is lowered due to deterioration of the insulating film quality or the like. As a result, the electric field dominance of the transfer electrode on the transfer channel is weakened, and the transfer efficiency of the vertical transfer register is lowered. In order to prevent the reliability of the device from being lowered, it is sufficient to make the negative potential small (close to 0 [V]). However, since the pinning becomes weak, the dark current greatly increases.

On the other hand, in the transfer electrodes to which the normally high vertical transfer pulses Vφ1 and Vφ2 are applied, the time during which the high level potential 0 [V] is applied is long. Therefore, if this high level can be lowered as much as possible, pinning becomes stronger and dark current can be reduced.
However, when the high level potential is lowered, the amplitude of the vertical transfer pulse is reduced and the transfer efficiency of the vertical transfer register is lowered.

  In the example of Patent Document 2, since the number of normally low horizontal drive pulses is increased from 2 to 3, the dark current is reduced, but the reliability of device operation is reduced due to, for example, deterioration of the gate insulating film quality. The number of electrodes that may be reduced increases. For this reason, there is a drawback that the transfer efficiency further decreases.

In this way, there is a trade-off between the transfer efficiency (and signal readout) of the vertical transfer register and the pinning strength that prevents the occurrence of dark current, and the image sensor can be operated efficiently while suppressing the occurrence of dark current. It is difficult to make it.
Therefore, it is strongly desired to operate the image sensor with high transfer efficiency while suppressing the occurrence of dark current or reducing the influence of transfer efficiency reduction.

The solid-state imaging device driving device according to the present invention reads the signal charge generated in the light receiving unit in response to light reception to the charge transfer unit through the read gate unit, and transfers the read signal charge in the charge transfer unit, A solid-state imaging device driving device for driving a solid-state imaging device that converts and outputs an imaging signal, and has a positive potential during a standby period including light reception when the signal charge is generated, and is negative during charge transfer. The solid-state imaging using a first transfer pulse that is a pulse of a side potential and a second transfer pulse that is a negative potential during the standby period and a pulse of a positive potential during charge transfer as a drive pulse of the charge transfer unit supplied to the device, based on the imaging signals from the previous SL solid-state imaging device, when the captured image is determined to be dark to reduce the amount of charge that the charge transfer section is dealt, the captured image is determined to bright Place Has a feedback control circuit for controlling the standby level of at least one of the transfer pulse of the so as to maintain the amount of charge, the said first transfer pulses second transfer pulse.
In the present invention, preferably, the feedback control circuit amplifies the transfer pulse supply circuit that supplies the first transfer pulse and the second transfer pulse to the solid-state image sensor, and the image signal is input from the solid-state image sensor. And a control circuit that detects brightness of the imaging screen based on the imaging signal and supplies a gain corresponding to the detected brightness to the variable gain amplifier in a changeable manner. The supply circuit inputs the gain from the control circuit, and changes the standby level based on the input gain.

  According to this configuration, since the video signal from the solid-state imaging device includes the brightness information of the imaging screen, the brightness of the imaging screen is detected, and the gain is controlled based on the detected brightness. The transfer pulse supply circuit can change the standby level. In this case, by lowering the driving ability only when the influence is smaller, the influence of the lowering of the driving ability can be minimized while enhancing or maintaining the pinning.

An image input apparatus according to the present invention includes: a solid-state imaging device that reads a signal charge generated in a light receiving unit in response to light reception to a charge transfer unit through a read gate unit, and transfers the read signal charge in the charge transfer unit; The solid-state image sensor driving circuit, an optical system for guiding image light from a subject onto the imaging surface of the solid-state image sensor, and an image signal that changes in accordance with the amount of signal charge of the solid-state image sensor can be output. And a first transfer pulse that is a positive potential during a standby period including a time of light reception when the signal charge is generated and becomes a negative potential pulse during charge transfer, and the standby period. among is negative potential, and a second transfer pulse to be the positive potential pulse is supplied to the solid-state imaging device as a driving pulse of the charge transfer portion during charge transfer, the imaging signal from the previous SL solid-state imaging device on the basis of, If the image image is determined to be dark reduces the amount of charge that the charge transfer section is dealt, the case where the captured image is determined to bright so as to maintain the charge amount, the said first transfer pulse first A transfer pulse supply circuit that controls a standby level of at least one of the two transfer pulses is provided.

In the solid-state imaging device driving method according to the present invention, the signal charge generated in the light receiving unit in response to the received light is read out to the charge transfer unit through the readout gate unit, and the read signal charge is transferred in the charge transfer unit. A solid-state imaging device driving method for driving a solid-state imaging device that converts to a signal and outputs the signal, wherein the potential is positive during a standby period including light reception when the signal charge is generated, and is negative during charge transfer A first step of generating a first transfer pulse that becomes a potential pulse and a second transfer pulse that is a negative potential during the waiting period and becomes a positive potential pulse during charge transfer; and the generated first step During the second step of supplying and driving the transfer pulse and the second transfer pulse to the charge transfer unit of the solid-state imaging device, while generating and supplying the first transfer pulse and the second transfer pulse , before Symbol solid-state imaging Based on the imaging signals from the child, if the captured image is determined to be dark to reduce the amount of charge that the charge transfer section is dealt, the case where the captured image is determined to bright to maintain the charge amount And a third step of controlling a standby level of at least one of the first transfer pulse and the second transfer pulse .

  According to the present invention, it is possible to operate an image sensor with high transfer efficiency while suppressing generation of dark current or with reduced influence of transfer efficiency reduction.

FIG. 5 is a waveform diagram showing general four-phase vertical transfer pulses Vφ1 to Vφ4. It is a schematic block diagram of CCD which can be used in 1st-4th embodiment, and its drive circuit. It is sectional drawing of the principal part along the AA line of FIG. (A)-(D) is a wave form diagram which shows the 4-phase vertical transfer pulse in connection with 1st Embodiment. (A)-(D) is a wave form diagram which shows the vertical transfer pulse of 4 phases in connection with 2nd Embodiment. It is a figure which shows the block of the drive device containing the feedback control circuit of 3rd Embodiment with CCD. It is a block diagram which shows the structural example of a signal processing circuit. (A) and (B) are vertical transfer pulse waveform diagrams when the imaging screen is relatively bright and dark in the third embodiment. It is a graph for demonstrating the effect of positive side electric potential adjustment (3rd Embodiment). It is a block diagram which shows an example of a structure of the image input device which concerns on 4th Embodiment. (A)-(C) are circuit diagrams which show the structural example of a CCD output circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings, taking a case where the solid-state imaging device is a CCD as an example.

<< First Embodiment >>
FIG. 2 is a schematic configuration diagram of the CCD and its drive circuit according to the embodiment.

  The CCD 1 illustrated in FIG. 2 includes an imaging unit 1A and a peripheral unit 1B in which an output circuit, input / output terminals, a bus, and the like are arranged.

The imaging unit 1A is two-dimensionally arranged in a matrix on a semiconductor substrate, and a plurality of light receiving units (pixels) 12 that convert incident light into signal charges having a charge amount corresponding to the amount of light, and a matrix arrangement of the light receiving units 12 The signal charges that are photoelectrically converted by each of the light receiving sections 12 and read out from the light receiving sections 12 through the readout gate section 13 are arranged in the vertical direction (vertical direction in the figure) in units of columns. And a plurality of vertical transfer registers 14 as “vertical transfer units” for transfer.
A channel stop region 29 is disposed between the vertical transfer register 14 and each light receiving unit 12 in the adjacent pixel column. The channel stop region 29 prevents charges of different pixels from being mixed into the transfer signal. Although not particularly shown, it is also arranged in the vertical direction of each light receiving portion 12 to prevent mixing of pixel signals.

A horizontal transfer register 15 is provided as a “horizontal transfer unit” on one of the upper and lower sides of the imaging unit 1A.
The horizontal transfer register 15 sequentially transfers signal charges shifted in units of rows sequentially from the plurality of vertical transfer registers 14 in the horizontal direction (left and right direction in the figure).

An output unit 16 is provided at the end of the horizontal transfer register 15 on the transfer destination side.
The output unit 16 is constituted by, for example, a floating diffusion amplifier, converts the signal charges sequentially transferred by the horizontal transfer register 15 into a signal voltage, and outputs the signal voltage to the outside of the CCD 1 via the output terminal 17 as the output signal S1. .

Outside the CCD 1, a drive circuit 2 for the CCD 1 and a timing generation circuit (TG: Timing Generator) 3 are arranged.
The drive circuit 2 is a circuit that generates drive pulses for the vertical transfer register 14 and the horizontal transfer register 15 based on various signals from the timing generation circuit 3.
Specifically, the drive circuit 2 includes a vertical driver 2A that generates a drive pulse for the vertical transfer register 14 and a horizontal driver 2B that generates a drive pulse for the horizontal transfer register 15. Of these, the vertical driver 2A corresponds to an example of the “transfer pulse supply circuit” of the present invention.

The timing generation circuit 3 generates various timing signals for driving the vertical transfer register 14 and the horizontal transfer register 15 based on various signals, that is, the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, and the master clock MCK.
Accordingly, the vertical driver 2A generates, for example, four-phase vertical transfer pulses Vφ1, Vφ2, Vφ3, and Vφ4 as drive pulses for the vertical transfer register 14.
Further, the horizontal driver 2B generates, for example, two-phase horizontal transfer pulses Hφ1 and Hφ2 as drive pulses for the horizontal transfer register 15.

Four-phase vertical transfer pulses Vφ1 to Vφ4 are supplied from the vertical driver 2A via terminals 21-1 to 21-4 electrically connected to corresponding transfer electrodes (not shown) of the vertical transfer register 14. The
Note that the vertical transfer pulses Vφ1 to Vφ4 are both left and right of the imaging unit 1A with respect to each transfer electrode of the vertical transfer register 14 in order to prevent a propagation delay due to resistance and parasitic capacitance of a wiring for transferring the pulse. It is desirable to supply from.
On the other hand, the two-phase horizontal transfer pulses Hφ1 and Hφ2 are supplied from the horizontal driver 2B via terminals 22-1 and 22-2 that are electrically connected to the corresponding transfer electrodes of the horizontal transfer register 15.

  In the present embodiment, the potentials of the four-phase vertical transfer pulses Vφ1 to Vφ4 for driving the vertical transfer register 14 are characteristically set, and details will be described later.

FIG. 3 is a cross-sectional view of a main part taken along line AA of FIG.
In FIG. 3, for example, a P well region 22 that functions as an overflow barrier (OFB) impurity region is formed in an N type semiconductor substrate 21, a P type semiconductor layer 23 is formed in the P well region 22, and the P type semiconductor layer 23 is formed. In addition, various impurity regions constituting the light receiving portion 12, the read gate portion 13, and the vertical transfer register 14 are formed.

  Specifically, the light receiving unit 12 includes a photodiode that forms a PN junction by the P-type semiconductor layer 23 and the N-type impurity region 24 formed in the P-type semiconductor layer 23. In addition, the light receiving unit 12 has a hole accumulation region 25 made of a P-type impurity region on the surface side portion in the N-type impurity region 24.

  The vertical transfer register 14 includes a transfer channel 26 formed of an N-type impurity region formed in the surface layer portion of the P-type semiconductor layer 23 and polysilicon formed on the transfer channel 26 via a gate insulating film 27. And a transfer electrode 28. A channel stop region 29 made of a high concentration P-type impurity region is formed along the transfer channel 26.

The read gate unit 13 also uses a part of the transfer electrode 28 of the vertical transfer register 14 as a gate electrode, and is formed by the gate electrode, the gate insulating film 27 and the P-type semiconductor layer 23 thereunder. (metal-insulator-semiconductor) structure. The gate insulating film 27 is formed of a single layer insulating film or a multilayer film such as an ONO (oxide-nitride-oxide) structure.
A light shielding film 31 made of aluminum, tungsten, or the like is formed through an interlayer insulating film 30 so as to cover each of the vertical transfer registers 14 except for the light receiving portion 12.

Next, potential setting of the four-phase vertical transfer pulses Vφ1 to Vφ4, which is a feature of the present embodiment, will be described.
4A to 4D are waveform diagrams showing four-phase vertical transfer pulses Vφ1 to Vφ4 according to the present embodiment.
As shown in the figure, in the four-phase vertical transfer pulses Vφ1 to Vφ4, the period of the positive potential (0 [V] in this example) is longer than the period of the negative potential (negative voltage value VL in this example). Normally high transfer pulses (in this example, vertical transfer pulses Vφ1, Vφ2) and normally low transfer pulses in which the negative potential period is longer than the positive potential period (vertical transfer pulses Vφ3, Vφ4 in this example) Including.

The vertical transfer pulses Vφ1 and Vφ2 transfer signal charges from the vertical transfer register 14 to the horizontal transfer register 15 by repeating the waveform change shown in the period T1 during the vertical transfer for driving the vertical transfer register 14 of FIG. .
Although schematically shown in FIGS. 4A to 4D, a period in which the waveform does not change in the preceding period T0 and the subsequent period is referred to as “standby time”.

At the time of standby, it includes at least a light receiving period for accumulating signal charges generated by light reception by the light receiving unit 12 in FIG. 2 and a reading period for discharging the accumulated signal charges to the vertical transfer register 14 via the reading gate unit 13.
This is because, in the structure shown in FIG. 3, the transfer electrode 28 also serves as the gate electrode of the read gate section 13, and vertical transfer, light reception, and charge reading cannot be performed simultaneously.
Therefore, the vertical transfer pulses Vφ1 and Vφ2 shown in FIGS. 4 (A) and 4 (B) have a standby level of positive potential, and the vertical transfer pulses Vφ3 and Vφ4 shown in FIGS. 4 (C) and 4 (D) are Each of the standby levels is a negative potential and is constant.

  The vertical transfer pulses Vφ1 and Vφ2 correspond to the “first transfer pulse” of the present invention, and the vertical transfer pulses Vφ3 and Vφ4 correspond to the “second transfer pulse” of the present invention.

In the present embodiment, the negative side potential VL ′ of the normally low vertical transfer pulses Vφ3, Vφ4 (second transfer pulse) is set to be higher than the negative side potential VL of the normally high vertical transfer pulses Vφ1, Vφ2 (first transfer pulse). It is characterized by being set to a small absolute value (closer to 0 [V]).
As an example, the negative side potential VL ′ of the vertical transfer pulses Vφ3 and Vφ4 may be set smaller than the negative side potential VL of the vertical transfer pulses Vφ1 and Vφ2 by about 5% of the potential VL.

  The negative potential VL ′ of the vertical transfer pulses Vφ3 and Vφ4 is obtained by applying a vertical transfer pulse of “0 [V] −VL” amplitude supplied from the timing generation circuit 3 in the vertical driver 2A, for example, by a resistance voltage dividing circuit. It can be easily set by dividing the pressure. According to this, it is not necessary to provide a separate power source for the negative side potential VL ′.

  However, the transfer pulse supply circuit is not limited to the resistance voltage dividing circuit in the vertical driver 2A. For example, a resistance voltage dividing circuit is provided on the semiconductor substrate 21 (FIG. 3) and supplied from the vertical driver 2A. It is also possible to generate the vertical transfer pulses Vφ3 and Vφ4 having the amplitude of “0 [V] −VL ′” based on the vertical transfer pulse having the amplitude of 0 [V] −VL ”.

  In this way, the negative side potential VL ′ of the normally low vertical transfer pulses Vφ3, Vφ4 is set to be smaller in absolute value than the negative side potential VL of the normally high vertical transfer pulses Vφ1, Vφ2, and the vertical transfer pulses Vφ3, By driving the vertical transfer register 14 with the four-phase vertical transfer pulses Vφ1 to Vφ4 including Vφ4, the following operational effects can be obtained.

  The dark current in the vertical transfer register 14 is mainly generated in the lower part of the transfer electrode to which the normally high vertical transfer pulses Vφ1 and Vφ2 are applied. This is because the normally high vertical transfer pulses Vφ1 and Vφ2 have a short negative potential period and a short pinning time. Therefore, even if the negative side potential VL ′ of the normally low vertical transfer pulses Vφ3 and Vφ4 is reduced to some extent as an absolute value, the dark current is not generated much compared with the normally high vertical transfer pulses Vφ1 and Vφ2. There is almost no effect on the increase.

  On the other hand, the field applied to the gate oxide film 37 (see FIG. 3) is a transfer electrode to which normally-low vertical transfer pulses Vφ3 and Vφ4 are applied, and therefore, the negative side of normally-low vertical transfer pulses Vφ3 and Vφ4. Decreasing the absolute value of the potential VL ′ leads to relaxation of the electric field applied to the gate oxide film 37.

  As a result, the negative side potential VL ′ of the normally low vertical transfer pulses Vφ3 and Vφ4 is set to be smaller in absolute value than the negative side potential VL of the normally high vertical transfer pulses Vφ1 and Vφ2, thereby increasing the dark current. Since the electric field applied to the gate insulating film 37 can be relaxed while suppressing the influence, the reliability of the device can be improved and the transfer efficiency of the vertical transfer register 14 can be improved without increasing the dark current.

<< Second Embodiment >>
In this embodiment, the level of the transfer pulse is intermittently changed. 2 and 3 are common to this embodiment.

FIG. 5A to FIG. 5D are waveform diagrams showing four-phase vertical transfer pulses Vφ1 to Vφ4 according to the second embodiment.
As shown in the figure, the four-phase vertical transfer pulses Vφ1 to Vφ4 have a negative potential (negative voltage value) during the period of the positive potential (in this example, 0 [V]), as in the first embodiment. Normally high vertical transfer pulses Vφ1 and Vφ2 longer than the period of VL), and normally low vertical transfer pulses Vφ3 and Vφ4 of which the negative potential period is longer than the positive potential period.

However, in the present embodiment, the negative side potential VL ′ of the normally low vertical transfer pulses Vφ3, Vφ4 (second transfer pulse) is more than the negative side potential VL of the normally high vertical transfer pulses Vφ1, Vφ2 (first transfer pulse). Is also intermittently reduced in absolute value (closer to 0 [V]).
That is, as in the first embodiment, the negative side potential VL ′ of the normally low vertical transfer pulses Vφ3 and Vφ4 is always made smaller in absolute value than the negative side potential VL of the normally high vertical transfer pulses Vφ1 and Vφ2. Instead, the voltage is intermittently reduced to the negative potential VL for the remaining period.
As an example, the negative side potential VL ′ of the vertical transfer pulses Vφ3 and Vφ4 is intermittently reduced by about 5% of the potential VL of the negative side potential VL of the vertical transfer pulses Vφ1 and Vφ2.

Pinning becomes stronger with a change to the negative potential, and the effect remains for a while. Therefore, when the negative potential of the second transfer pulse is intermittently changed, the pinning effect is not changed as compared with the case where it is not, but the driving capability is increased.
For the above reasons, the pulse control method of the present embodiment can maintain the effect of making it difficult for electrons to be generated from the interface state by pinning when dark current is generated, as compared with the first embodiment.

  On the other hand, the negative side potential VL ′ of the normally low vertical transfer pulses Vφ3 and Vφ4 is intermittently made smaller in absolute value than the negative side potential VL of the normally high vertical transfer pulses Vφ1 and Vφ2, so that the gate insulating film 37 Is shorter than the conventional example in which the normally low vertical transfer pulses Vφ3 and Vφ4 are always at the negative potential VL, and the deterioration of the transfer efficiency of the vertical transfer register 14 is mitigated as compared with the conventional example. .

<< Third Embodiment >>
In the above two embodiments, the presence or absence of a level change is controlled by the difference in the standby level of the transfer pulse.
On the other hand, in this embodiment, the presence or absence of a change in the level of the transfer pulse is controlled by feedback based on the imaging signal S1 output from the CCD 1 in FIG.

FIG. 6 is a diagram showing a block of the driving device including the feedback control circuit together with the CCD 1.
The illustrated driving device includes a driving circuit 2, a timing generation circuit 3, a signal processing circuit 4, and a control circuit 5 in a feedback control circuit 20 surrounded by a broken line.
Among them, the drive circuit 2 and the timing generation circuit 3 have the same basic functions and operations as those in the first embodiment (FIG. 2 and the description thereof). The CCD 1 is the same as that in the first embodiment.

FIG. 7 is a block diagram illustrating a configuration example of the signal processing circuit 4.
The illustrated signal processing circuit 4 includes a correlated double sampling (CDS) circuit 41, an automatic gain control (AGC) circuit 42 including a variable gain amplifier, a gamma (γ) correction circuit 43, a synchronous output (Sync.) Circuit 44, and an automatic. An iris control (AIC) circuit 45 is included.

  The CDS circuit 41 is a circuit for inputting the imaging signal S1 from the CCD 1 and effectively removing induced noise superimposed on the imaging signal S1, particularly reset noise.

The AGC circuit 42 receives the gain control signal S5 from the control circuit 5 in FIG. 6 and adjusts the gain of the internal variable gain amplifier. As a result, the gain of the imaging signal S41 input from the CDS circuit 41 to the AGC circuit 42 is adjusted.
The control circuit 5 in FIG. 6 can receive the image pickup signal S41 from the CDS circuit 41, and detects the brightness of the screen (image pickup screen) indicated by the image pickup signal.
Although not particularly illustrated, the control circuit 5 can be configured to include a memory for storing an imaging signal in units of frames, a circuit for averaging (or integration), a CPU, and the like. Thereby, the control circuit 5 calculates the brightness of the imaging screen, calculates the gain of the AGC circuit 42 suitable for this brightness, and outputs the gain information to the AGC circuit 42 as the gain control signal S5. In the present embodiment, the gain control signal S5 and the control circuit 5 correspond to examples of “a signal that changes according to the amount of signal charge” and “means for outputting it”.

The γ correction circuit 43 is a circuit that performs luminance correction for adapting an input signal to a device or the like connected to the output.
The synchronization output circuit 44 is a circuit that receives a synchronization signal SYNC and sends the output signal S44 to a subsequent circuit or IC in synchronization with this signal. The synchronous output circuit 44 may have a signal amplification function.
The AIC circuit 45 is a circuit for automatically performing iris adjustment. For this reason, the AIC circuit 45 may have a function of detecting the brightness of the imaging screen. However, in this example, since the control circuit 5 of FIG. 6 has a brightness detection function, brightness information is acquired from the function, and an iris control signal S45 is generated and output based on the brightness information.
Note that the γ correction circuit 43, the synchronous output circuit 44, the AIC circuit 45, and the CDS circuit 41 described above are not essential components.

Next, level adjustment according to the brightness of the imaging screen will be described with reference to the waveform diagrams of FIGS. 8 (A) and 8 (B).
This adjustment is performed by the vertical driver 2A shown in FIG. This level adjustment is performed for normally high transfer pulses, that is, vertical transfer pulses Vφ1 and Vφ2 whose standby level is the positive potential.

FIG. 8 shows the vertical transfer pulse Vφ1 as a representative, and although not particularly shown, the vertical transfer pulse Vφ2 is similarly controlled.
FIG. 8A shows the waveform of the vertical transfer pulse Vφ1 when the imaging screen is relatively bright, and FIG. 8B shows the waveform of the vertical transfer pulse Vφ1 when the imaging screen is relatively dark.
When the imaging screen is relatively bright, the gain is set to be relatively small in the gain control signal S5 provided to the AGC circuit 42 in FIG. On the other hand, when the imaging screen is relatively dark, the gain is set to be large in the gain control signal S5. By performing automatic gain control in this way, the AGC circuit 42 can limit the amount of signal that can be handled by a circuit connected to the subsequent stage or the video display unit, or can make noise inconspicuous.

  When this gain is relatively small (when the imaging screen is bright), the amount of signal charge generated by the CCD 1 is relatively large, so that the signal-to-noise ratio (S / N) does not decrease even if there is some dark current. Therefore, as shown in FIG. 8A, the positive potential (0 [V] in this example) that is the standby level is maintained as it is. As a result, the amount of charge handled at the time of vertical transfer is not reduced, so that the transfer efficiency is not lowered when the amount of signal charge to be transferred is large. That is, it is possible to prevent the occurrence of uncharged charges during transfer.

On the other hand, when the gain is relatively large (when the imaging screen is dark), the amount of signal charge to be transferred is relatively small, so even if the peak value of the transfer pulse is reduced, there is no charge accumulation and efficient transfer is possible. It is. Therefore, as shown in FIG. 8B, control is performed to slightly lower the positive potential from 0 [V].
The amount of decrease has an optimum value according to the average signal charge amount (screen brightness) to be transferred and the extent to which the dark current increases. In this example, the negative potential is lowered from 0 [V] to −1 [V].
Note that this reduction width (level change amount) is arbitrary, and when changing the threshold value for detecting the brightness of the image and adjusting the gain according to the threshold value, for each gain or for each gain width The amount of level change can also be changed. As an example, the voltage can be adjusted from 0 [V] to -0.5 [V], -1 [V], -1.5 [V], or -2 [V].

In FIGS. 8A and 8B, the negative potential (the negative voltage value VL = −7.5 [V] in this example) is the same.
However, the first and second embodiments for changing the level of the negative potential can also be executed in combination.

Next, the effect of positive side potential adjustment will be described with reference to FIG.
FIG. 9 is a graph showing the positive potential (VH) dependence of the degree of white scratches (arbitrary unit: au) on the display screen.
The degree of white scratches is determined by ranking the voltage change in the direction that causes white scratches when a uniform video signal is input on the actual display screen, and the allowable number in each rank and the total number in all ranks. I manage.

In this graph, three broken lines corresponding to three CCDs are shown.
As can be seen from this graph, scratches are reduced by changing the positive potential (VH) from 0 [V] to -1 [V].

As described above, according to the present embodiment, when the signal amplification gain that does not affect the vertical transfer is large, the positive potential (VH) of the first transfer pulse (vertical transfer pulses Vφ1, Vφ2) is reduced. Change to be. For this reason, pinning can be strengthened and dark current can be reduced without lowering transfer efficiency.
For this reason, S / N when a dark screen is imaged can be improved. At this time, the peak value of the transfer charge can be lowered, so that the power consumption is reduced accordingly.

<< 4th Embodiment >>
The CCD driving device according to the above-described embodiment is suitable as an IC or the like for driving the imaging device in an image input device such as a digital still camera or a video camera.

  Here, the image input device includes a solid-state imaging device as an imaging device, an optical system that forms image light of a subject on an imaging surface (light-receiving surface) of the solid-state imaging device, and a signal processing circuit of the solid-state imaging device. A camera system including a camera module (for example, used in an electronic device such as a mobile phone) and a digital still camera or a video camera equipped with the camera module.

FIG. 10 is a block diagram showing an example of the configuration of the image input apparatus according to the present invention. In the following, the same components and signals as those in FIG. 6 and FIG.
An image input apparatus 50 shown in FIG. 10 includes an optical system including a lens 6, a diaphragm 7, and a diaphragm driving unit 8, an imaging device (for example, CCD 1), a driving circuit 2, a signal processing circuit 4, a control circuit 5, and the like. .

The optical system limits the area of the image light from the subject by the diaphragm 7, collects it with the lens 6, and forms an image on the imaging surface of the imaging device (for example, CCD 1). The imaging device (for example, CCD 1), for example, outputs an imaging signal S1 of one frame obtained by converting image light imaged on the imaging surface by the lens 6 into an electrical signal in units of pixels under the driving of the driving circuit 2. Output in field units.
At this time, the diaphragm driving means 8 is connected to the diaphragm 7. The diaphragm driving unit 8 is a mechanical driving unit that receives the iris control signal S45 from the AIC circuit 45 in the signal processing circuit 4 and controls the diaphragm amount of the diaphragm 7.

In the present embodiment, the iris control signal S45 is input to the drive circuit 2 via the control circuit 5, and thereby the iris control signal S45 is used as a “signal that changes according to the amount of signal charge and the brightness of the image”. Is input by the drive circuit 2. Then, in accordance with the iris control signal S45, the positive side potential of the fourth embodiment is adjusted.
Although not shown, the positive side potential can be adjusted based on the gain of the third embodiment.

  In such an image input device 50, the dark current is provided by mounting the optical system, the CCD 1 as the imaging device, the drive circuit drive circuit 2, and the signal processing circuit 4 and the control circuit 5 necessary for feedback control. Since the reliability or transfer efficiency of the device can be improved without increasing the image quality, a high-quality captured image can be obtained.

Finally, based on the gain of the third embodiment and the iris control of the present embodiment, a technique for further reducing the power consumption of the output circuit, thereby further reducing the noise, and the configuration for that purpose will be described.
Here, the “output circuit” is, for example, a circuit formed in the peripheral portion 1B of the CCD 1 in FIG. 2 (in this example, it may be a CMOS sensor).

  In addition to the dark current generated by the CCD 1 itself, noise that generates white flaws increases due to heat generation in a circuit portion (particularly, an output circuit) due to an increase in power consumption, that is, thermal noise. Therefore, it is important to suppress not only the dark current but also this thermal noise. In particular, when the exposure time is increased to several hundreds [msec] to several seconds, such as when shooting a night view, it is essential to reduce the noise of the output circuit.

Further, in order to optimize the output circuit according to a large data rate, it is necessary to extend the frequency characteristic of the output circuit to a higher range. However, an output circuit that is driven at a high frequency with a high-frequency signal input is likely to generate power noise due to increased power consumption. That is, the S / N of the circuit itself decreases. Further, since heat generated in the output circuit propagates to the entire imaging device and heats the imaging unit 1A, the dark current increases accordingly.
Therefore, here, by limiting the current consumption of the output circuit, the high-frequency noise component is suppressed together with the thermal noise generated by heat generation, and the dark current is hardly generated.

By the way, the CCD has two operation modes as a driving method: a moving image capturing mode with a high data rate and a still image capturing mode with a low data rate.
In particular, a CCD used in a digital still camera (DSC) has a mode for capturing a still image that is recorded and stored, and a monitoring that displays a moving image on a monitor screen for focusing and framing prior to capturing a still image. Mode is essential, and other cameras capable of shooting moving images have a moving image capturing mode.
The output circuit mounted on-chip in the CCD is optimally designed for a moving image mode with a high data rate that needs to exhibit its maximum capacity. Since the monitoring mode is also a kind of moving image mode, a higher data rate is required than in the still image capturing mode.

  However, when shooting still images, the data rate can be slower than with moving images, so the output circuit optimized for the moving image capture mode becomes overspec, resulting in unnecessary power consumption and heat generation. This leads to a decrease in S / N.

Hereinafter, a technique for eliminating this wasteful power consumption and unnecessary dynamic range expansion associated therewith, thereby suppressing heat generation and improving the S / N, and a configuration for the same will be described.
In this description, switching of the circuit configuration in the monitoring mode and the still image capturing mode based on DSC will be described. However, “monitoring mode” may be replaced with “moving image capturing mode” in the following description.
Further, the configuration of the CCD is the same as that in FIGS. 2 and 3, and FIGS. 6, 7 and 10 can be applied to portions other than the CCD.

For example, it is assumed that the mode switching is performed by the control circuit 5 in FIG. 6, and the mode switching signal S5m is applied from the control circuit 5 to the output circuit of the CCD 1 as indicated by a dotted line.
For example, the control circuit 5 sets the monitoring mode when power is turned on. Then, the focusing and the like are completed, and for example, when the subject is aimed, the mode immediately shifts to the still image capturing mode.

11A to 11C show configuration examples of the output circuit.
These output circuits are composed of a two-stage source follower circuit. Specifically, it has two NMOS transistors Q1 and Q2 connected by a source follower. An input signal Sin is input to the gate of the signal input transistor Q1, and its drain is connected to the supply line of the power supply voltage Vdd. The signal output transistor Q2 has a gate connected to the source of the signal input transistor Q1, a drain connected to the supply line of the power supply voltage Vdd, and an output signal Sout from the source.

11A and 11B, a load transistor Q3 made of an NMOS transistor is connected between the source of the input amplifier transistor Q1 and the ground voltage GND, and the source of the signal output transistor Q2 and the ground voltage GND are connected. A load transistor Q4 made of an NMOS transistor and a resistor R (which may be a variable resistor) are connected in cascade. A switch is connected in parallel with the resistor R. The load transistors Q3 and Q4 function as resistors determined by the bias voltage VGG. Therefore, changing the bias voltage VGG provides a variable resistor for optimizing the current value.
In FIG. 11B, this switch is formed by a bipolar transistor Q5. In FIG. 11A, the type of this switch is not limited by the general switch SW.

In any case, the switch SW and the bipolar transistor Q5 are controlled by a mode switching signal S5m supplied from the control circuit 5 of FIG. 6, for example.
Specifically, the switch SW or the bipolar transistor Q5 is turned on in the monitoring mode in which the gain is not increased, and is turned off in the still image capturing mode in which the gain is increased.
In the monitoring mode, the image quality may be reduced for viewing on a small monitor screen, so the gain is not increased. Therefore, the frequency response of the output circuit does not have to be high, and the current flowing through the resistor is bypassed to suppress heat generation. At this time, the currents flowing through the signal input transistor Q1 and the load transistor Q4 deviate from the optimum values, and the power consumption is also reduced.
On the other hand, in the still image capturing mode, the gain is increased because the image quality cannot be lowered for recording. Therefore, it is necessary to set the frequency response of the output circuit to the highest performance. For this reason, a resistor is inserted into the circuit, and a bias condition optimized by the bias voltage VGG is set. As a result, a current flows through the resistor R, heat is generated, and power consumption of the circuit increases.

  Such an operation can reduce wasteful heat generation and power consumption, particularly in the monitoring mode, thereby improving the S / N ratio.

On the other hand, in the output circuit shown in FIG. 11C, the resistor R is omitted, and instead, the capacitor C and the bipolar transistor Q6 are connected between the output node and the ground voltage GND. The bipolar transistor Q6 is controlled by the mode switching signal S5m, similarly to the bipolar transistor Q5 of FIG.
The bipolar transistor Q6 is turned on in the monitoring mode, and turned off in the still image capturing mode.
Therefore, in the monitoring mode, the frequency response of the output signal Sout with respect to the input signal Sin is low, and noise is reduced due to band limitation. However, since the capacitor C is charged / discharged, the power consumption and the heat generation amount are not changed much.
By adding the control as described above to the first to fourth embodiments, there is an advantage that the S / N can be further improved.

  In the first to fourth embodiments, the case of four-phase driving in which the vertical transfer register 14 is driven by four-phase vertical transfer pulses Vφ1 to Vφ4 has been described as an example. However, the present invention is not limited to four-phase driving. The present invention is not limited to application, and can be applied to general multi-phase driving such as three-phase driving and six-phase driving.

  In the above embodiment, the vertical transfer register 14 is exemplified as the charge transfer unit to be driven according to the present invention. However, a normally high transfer pulse in which the positive potential period is longer than the negative potential period; In the case of adopting a configuration in which the horizontal transfer register 15 is driven to transfer by a plurality of phase transfer pulses including a normally low transfer pulse in which the negative potential period is longer than the positive potential period, the present invention is also applied to the horizontal transfer register 15. Is possible.

  DESCRIPTION OF SYMBOLS 1 ... CCD, 2 ... Drive circuit, 2A ... Vertical driver, 2B ... Horizontal driver, 3 ... Timing generation circuit, 4 ... Signal processing circuit, 5 ... Control circuit, 6 ... Lens, 7 ... Diaphragm, 8 ... Diaphragm drive means, DESCRIPTION OF SYMBOLS 12 ... Light-receiving part, 13 ... Reading gate part, 14 ... Vertical transfer register, 15 ... Horizontal transfer register, 16 ... Output part, 42 ... AGC circuit, 45 ... AIC circuit, S1 ... Imaging signal, S5 ... Gain control signal, S45 ... Iris control signal.

Claims (9)

A solid-state imaging device that reads out signal charges generated in the light receiving unit in response to light reception to the charge transfer unit via the read gate unit, transfers the read signal charges in the charge transfer unit, converts them into imaging signals, and outputs them. A driving device for a solid-state imaging device for driving,
The first transfer pulse that is a positive potential during a standby period including the time of light reception when the signal charge is generated and becomes a negative potential pulse during charge transfer; and the negative transfer potential during the standby period; and a second transfer pulse to be the positive potential pulse is supplied to the solid-state imaging device as a driving pulse of the charge transfer section, based on the imaging signals from the previous SL solid-state imaging device, it is determined that the captured image is dark At least one of the first transfer pulse and the second transfer pulse so that the charge amount handled by the charge transfer unit is reduced and the charge amount is maintained when the captured image is determined to be bright. A solid-state image sensor driving device having a feedback control circuit for controlling a standby level of a transfer pulse of the solid-state imaging device. The solid-state imaging device driving device according to claim 1, wherein when the standby level of the second transfer pulse is changed, the feedback control circuit intermittently changes the absolute value of the negative potential during standby. The feedback control circuit includes:
A transfer pulse supply circuit for supplying the first transfer pulse and the second transfer pulse to the solid-state imaging device;
A variable gain amplifier for inputting and amplifying the imaging signal from the solid-state imaging device;
A control circuit that detects the brightness of the imaging screen based on the imaging signal and supplies a gain corresponding to the detected brightness to the variable gain amplifier in a changeable manner;
Have
The solid-state imaging device driving device according to claim 1, wherein the transfer pulse supply circuit receives the gain from the control circuit and changes the standby level based on the input gain. A solid-state imaging device that reads the signal charge generated in the light receiving unit in response to light reception to the charge transfer unit via the read gate unit, and transfers the read signal charge in the charge transfer unit;
A driving circuit for the solid-state imaging device;
An optical system for guiding image light from a subject onto the imaging surface of the solid-state imaging device;
Means capable of outputting an imaging signal that changes in accordance with the amount of signal charge of the solid-state imaging device;
With
The drive circuit is at a positive potential during a standby period including the time of light reception when the signal charge is generated, and at a negative potential during the standby period and a first transfer pulse that becomes a negative potential pulse during charge transfer. There, a second transfer pulse as a pulse of positive potential during the charge transfer is supplied to the solid-state imaging device as a driving pulse of the charge transfer section, based on the imaging signals from the previous SL solid-captured image The first transfer pulse and the second transfer so as to reduce the amount of charge handled by the charge transfer unit when it is determined to be dark, and to maintain the amount of charge when the captured image is determined to be bright. An image input apparatus having a transfer pulse supply circuit for controlling a standby level of at least one of the pulses . The image input device according to claim 4, wherein, when the standby level of the second transfer pulse is changed, the transfer pulse supply circuit intermittently changes the absolute value of the negative potential during standby. The drive circuit is
A variable gain amplifier for inputting and amplifying the imaging signal from the solid-state imaging device;
A control circuit that detects the brightness of the imaging screen based on the imaging signal and supplies a gain corresponding to the detected brightness to the variable gain amplifier in a changeable manner;
Have
The image input device according to claim 4, wherein the transfer pulse supply circuit changes the standby level based on the gain from the control circuit. A variable aperture in the optical system;
The drive circuit is
A circuit for detecting the brightness of the imaging screen based on the imaging signal;
An iris control circuit for controlling the aperture amount of the variable aperture based on the brightness of the imaging screen;
Including
The image input device according to claim 4, wherein the transfer pulse supply circuit controls the standby level based on the aperture amount from the iris control circuit. Drives the solid-state image sensor that reads the signal charge generated in the light receiving unit in response to light reception to the charge transfer unit through the readout gate unit, transfers the read signal charge in the charge transfer unit, converts it into an imaging signal, and outputs it. A method of driving a solid-state imaging device for performing
The first transfer pulse that is a positive potential during a standby period including the time of light reception when the signal charge is generated and becomes a negative potential pulse during charge transfer; and the negative transfer potential during the standby period; A first step of generating a second transfer pulse that is a positive potential pulse;
A second step of supplying and driving the generated first transfer pulse and the second transfer pulse to a charge transfer unit of the solid-state imaging device;
While being supplied to generate the second transfer pulse to the first transfer pulse, based on the imaging signals from the previous SL solid-state imaging device, the charge transfer when the captured image is determined to be dark The standby level of at least one of the first transfer pulse and the second transfer pulse so as to maintain the charge amount when it is determined that the captured image is bright when the charge amount handled by the unit is reduced A third step of controlling
A method for driving a solid-state imaging device including: The solid-state imaging device driving method according to claim 8, wherein in the third step, the absolute value of the negative potential, which is the standby level of the second transfer pulse, is intermittently changed during standby.

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