JP4243047B2 - CCD output circuit and CCD output method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an output circuit and an output method of a MOS type imaging device and other solid-state imaging devices, and more particularly, a digital camera, a line sensor, and other devices using a charge coupled device (CCD) as an imaging device. The present invention relates to a CCD output circuit and a CCD output method.
[0002]
[Prior art]
A floating diffusion amplifier (FDA) is well known as a circuit that samples and holds a signal charge output from a CCD in a minute capacity and detects it as a voltage signal. The voltage signal converted from the signal charge by the FDA is amplified by a source follower amplifier circuit having a plurality of stages (two or three stages are common). As described above, the CCD imaging device generally has an output circuit including the FDA and the source follower amplifier circuit.
[0003]
When attention is paid to the power supply voltage of the source follower amplifier circuit in each stage, these are uniformly set to a high value of about 16V. This is because, in a field effect transistor (FET) that constitutes a source follower amplifier circuit, when the voltage level drops from the drain to the source where the power supply voltage is set and falls below a certain voltage, the source follower This is because it does not function as a circuit. The bias current of the source follower amplifier circuit is also set to a constant value by the constant current source.
[0004]
[Problems to be solved by the invention]
However, with the high-speed readout of the CCD imaging device, high frequency characteristics are required also in the source follower amplifier circuit of the output circuit, and the bias current of each stage tends to increase. Therefore, the power consumption of the output circuit increases, but this may cause various problems. For example, when exposure is performed for a long time of about 20 seconds to 30 seconds, power consumption due to dark current increases in an output circuit including a source follower amplifier circuit. If the exposure time is long as described above, the thermal noise due to the dark current is relatively large compared to the incident light level to the CCD, so white flaws occur in the pixels located near the output circuit, and the image Cause disturbance. In addition, the adverse effect on the peripheral elements due to the heat generated in the output circuit is particularly undesirable for portable devices aiming at miniaturization.
[0005]
According to Japanese Patent Laid-Open No. 10-117306, a solid-state imaging device is proposed in which the power supply voltage is lowered as the bias current flowing through the source follower amplifier circuit is increased. According to Japanese Patent Laid-Open No. 9-252111, the power consumption is reduced by changing the structure of the final stage transistor of the source follower amplifier circuit. However, even in these prior arts, constant power consumption is constantly performed, and the above-described problems are not completely prevented.
[0006]
Japanese Patent Application No. 2001-69051 also relates to an output circuit of an image sensor, but does not mention that the power supply voltage is substantially zero.
[0007]
It is an object of the present invention to provide a CCD output circuit and a CCD output method that eliminate such drawbacks of the prior art and reduce power consumption without impairing the frequency characteristics of the output circuit.
[0008]
[Means for Solving the Problems]
In order to solve the above-described problem, the present invention provides a CCD output circuit including a plurality of source follower amplifier circuits that amplify and output a signal transferred from a CCD, and at least the power supply voltage of the last source follower amplifier circuit. Switching means for making the value substantially zero, and control means for switching the switching means to make the value of the power supply voltage substantially zero during a period when the CCD signal is not read, thereby reducing the power consumption. To reduce.
[0009]
In order to solve the above-described problem, the present invention provides a CCD output circuit including a plurality of source follower amplifier circuits that amplify and output a signal transferred from a CCD, and a value of a direct current flowing through the source follower amplifier circuit. Switching means for changing each stage individually and control means for switching the switching means to lower the DC current value in accordance with the signal readout frequency of the CCD, thereby reducing power consumption.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of a CCD output circuit and a CCD output method according to the present invention will be described in detail with reference to the accompanying drawings. In the figure, elements not related to the present invention are omitted, and signals are represented by reference numerals of signal lines on which they appear. Similar elements are denoted by the same reference numerals.
[0011]
FIG. 2 is a block diagram showing an example of a digital still camera to which the CCD output circuit according to the present invention is applied. The camera 10 is a device that uses a CCD (Charge Coupled Device) as an imaging device and records incident light taken from the object scene as a digital image signal. Camera 10 includes a lens 12 through which incident light 14 is captured. The image sensor 16 for the camera 10 photoelectrically converts the incident light 14 and transfers the obtained signal charges in the vertical and horizontal directions, and an output circuit 20A connected to the horizontal transfer path 32 of the pixel area 18. (20B). This output circuit 20A (20B) is an embodiment of the CCD output circuit according to the present invention. In the present embodiment, a CCD is used as the image pickup device. However, the present invention can also be applied to other solid-state image pickup devices such as a MOS type image pickup device that reads out signal charges obtained by photoelectric conversion.
[0012]
FIG. 3 is a schematic diagram of the pixel region 18. Photodiodes 24 corresponding to pixels are arranged in a lattice pattern in the pixel region 18, and the incident light 14 is photoelectrically converted and accumulated as signal charges on the substrate. The photodiode 24 shown in FIG. 3 is representatively limited in number for the sake of simplicity, and it goes without saying that there are actually several million pixels. The pixel region 18 receives the accumulated signal charges (field shift) and transfers them in the vertical direction 26, and further receives the vertical transferred signal charges (line shift) and transfers them in the horizontal direction 30. Includes horizontal transfer CCD 32. As described above, the pixel region 18 employs an interline CCD including the photodiode 24 that performs photoelectric conversion and the CCDs 28 and 32 that perform charge transfer. However, the use of the interline type is merely the most common type used in digital cameras, and a frame transfer type CCD or a frame interline transfer type CCD may be used.
[0013]
FIG. 1 is a circuit diagram showing a first embodiment 20A of a CCD output circuit according to the present invention. The output circuit 20A is a device that detects the horizontally transferred signal charge 34 as an electric signal having a voltage corresponding to the amount of charge. A capacitor 35 is connected to the signal line 34, and this is initially supplied with a reset voltage by a reset circuit (not shown), but the amount of charge is changed by applying the transferred signal charge 34, A voltage change corresponding to the signal charge 34 occurs. However, since the output impedance of the capacitor 35 is very high and this voltage change is small and cannot be put into practical use as it is, the output circuit 20A includes three-stage source follower amplifier circuits 36, 38, and 40.
[0014]
The source follower amplifying circuits 36, 38, and 40 include field effect transistors (FETs) 42, 44, and 46 for each stage, and gradually reduce the output impedance. The operation of each stage will be described by the first stage 36 as a representative. Due to the above-described voltage change applied to the gate 37 of the FET 42 in the first stage 36, a corresponding direct current flows between the drain 47 and the source 49. As a result, the source 49 has a potential dropped from the power supply voltage 60 (16V) of the drain 47, and this is applied to the gate 53 of the FET 44 in the second stage 38. In this way, the output impedance is gradually lowered (a direct current is amplified) with the change in the gate voltage as an input. The output signal 56 amplified in the final stage 40 is output to the amplifier 90. As in this embodiment, the number of stages of the output circuit 20A is usually 2 to 3, but is not limited to these stages.
[0015]
A constant current source 50, 52, 54 is connected to each stage 36, 38, 40, but in order for these to operate as a constant current source, a voltage of a certain value or more is required, and if it is less than that, Does not function as a source follower amplifier circuit. Therefore, the first stage 36 and the second stage 38 use a common high power supply voltage 60 (16 V). However, when such a high power supply voltage is set, power consumption tends to increase.
[0016]
FIG. 4 is a circuit diagram of a conventional source follower amplifier circuit having such a problem. 4, elements similar to those in FIG. 1 are denoted by the same reference numerals. As shown in FIG. 4, each stage 36, 38, 40 is conventionally connected to a high power supply voltage 60. The power consumption in each of the FETs 42, 44, 46 is the maximum in the FET 46 of the final stage 40 where the value of the current flowing between the drain and the source is the largest.
[0017]
Therefore, in this embodiment, as shown in FIG. 1, the power supply voltage of the final stage 40 is provided independently of the initial stage 36 and the second stage 38, and the voltage value can be freely switched by the switching element 64. did. According to the switching element 64, the final stage 40 can be connected to an independent power supply voltage 62 (5V) set to be low, or can be grounded 66 to make the voltage substantially zero (or off). The switching to the voltage value of zero can be performed during a period when the signal charge is not read. This is because it is not necessary for the output circuit 20A to detect the signal charge 34 if no reading is performed. Note that the switching element 64 may be formed of a transistor. The switching element 64 is controlled by the camera control unit 70, which will be described later.
[0018]
In the embodiment shown in FIG. 1, the power consumption is maximized when the power supply voltage of each stage is made common, and the power supply voltage of the final stage 40 is made independent. In this way, the power supply voltage is made independent. In addition, the voltage value can be freely switched by the switching element may be performed for the first stage 36 or the second stage 38.
[0019]
Please refer to FIG. 2 again. The camera control unit 70 is a device that switches the switching element 64 included in the output circuit 20A by giving a control signal 72 to the output circuit 20A. The camera control unit 70 also provides a control signal 82 to a timing generator 74 that provides synchronization signals 76, 78, and 80 to various devices in the camera 10, and provides the synchronization signals 76, 78, and 80 that the timing generator 74 oscillates. It can be freely changed to change the signal processing speed. On the other hand, the camera control unit 70 receives the synchronization signal 84 from the timing generator 74, and obtains the timing to give the control signal 72 to the output circuit 20A.
[0020]
In addition, although not so important in the present embodiment, the camera 10 includes the following elements. That is, a CCD drive circuit 88 that supplies a drive signal 86 for vertical and horizontal transfer to the image sensor 16 in synchronization with a synchronization signal from the timing generator 74, and an amplifier 90 that further amplifies the image signal 56 output from the output circuit 20. An A / D converter 94 that performs A / D conversion on the amplified image signal 92, a signal processing device 98 that performs various signal processing on the digital image signal 96, and a still image (hereinafter referred to as “main imaging”). A recording unit 102 that records the image signal 100 that has been subjected to signal processing, and a liquid crystal monitor 17 that displays the image signal 104 that has undergone rough signal processing as a moving image during a period other than during the main imaging. It is. These devices are driven by the synchronization signals 76, 78, 80 from the timing generator 74 as described above. On the other hand, the recording unit 102 records an image in accordance with a control signal 106 from the camera control unit 70.
[0021]
The operation of the first embodiment of the present invention configured as described above will be described below. FIGS. 5A, 5B and 5C are timing charts showing the operation of the first embodiment. The synchronization signal 84 that the timing generator 74 gives to the camera control unit 70 includes vertical and horizontal synchronization signals. FIG. 5A shows the vertical synchronization signal as a representative. Since the synchronization signals 76, 78, and 80 given to the other devices are also the same as the synchronization signal 84, the various devices 88, 90, 94, and 98 will be described below in a typical manner as shown in FIG. Consider being driven according to signal 84.
[0022]
The vertical synchronization signal 84 starts oscillating from when the power of the camera 10 is turned on, and is a period when the main imaging is not performed, that is, a period during which a moving image (through image) is simply drawn on the monitor 17 at high speed. As shown in FIG. 5A, a constant period 99 (1 V) is maintained. The blanking period 112 is during the stationary vertical synchronization signal during the low level 110, and the through mode 116 is during the high level 114.
[0023]
When the vertical synchronizing signal 84 falls to the low level 118, in principle, a field shift is performed in the pixel region 18. That is, the signal charge accumulated in the photodiode 24 is transferred to the vertical transfer CCD 28. In the blanking period 112 that starts simultaneously with the field shift, no signal charge is transferred. Therefore, the camera control unit 70 can turn off the power supply voltage of the final stage 40 by setting the switch 64 to the ground 66.
[0024]
Simultaneously with the end of the blanking period 112, the camera 10 enters the through mode 116. In the through mode 116, since a rough image may be used, a moving image must be drawn on the monitor 17, so that the field-shifted signal charges are transferred at high speed through the vertical transfer CCD 28 and the horizontal transfer CCD 32, and are electrically output by the output circuit 20A. Detected as a signal. At this time, since the output circuit 20A needs to function as a source follower amplifier circuit, the camera control unit 70 connects the switch 64 to the power supply voltage 62 (power on 121).
[0025]
Next, the operation when performing the main imaging will be described. The camera control unit 70 that has received an imaging command when the photographer presses a shutter release button (not shown) transmits a reset pulse 82 to the timing generator 74 to start preparation for the main imaging. This reset pulse 82 appears as an imaging command 122 in FIG. The vertical synchronizing signal 84 of the timing generator 74 is forced to fall 124 and a field shift is performed. Here, the field-shifted charges are swept out as unnecessary charges. In the unnecessary charge sweeping mode 126, the camera control unit 70 of the present embodiment connects the switch 64 to the power supply voltage 62 following the immediately preceding through mode 127 (power on 129). This is because, although unnecessary charges are swept out, unnecessary charges are swept out through the same path as in the signal reading operation, and therefore, the output circuit 20A needs to operate in the same manner as in the signal reading mode. However, when the vertical overflow drain (VOD) that discards unnecessary charges is not performed using the vertical / horizontal transfer paths 28 and 32 and is discarded in the direction of the substrate, the camera control unit 70 During mode 126, switch 64 may be grounded 66 to reduce power consumption.
[0026]
When the sweep mode 126 ends, the exposure mode 128 is entered. Since it is a still image shooting, the camera control unit 70 controls the timing generator 74 to delay the timing of the next falling edge 132 and to allow sufficient time for the exposure period 128. Since it is not necessary to read out the signal during the exposure period 128, the camera control unit 70 grounds 66 the switch 64 to make the power supply voltage of the final stage 40 substantially zero (power off 130).
[0027]
The accumulated signal charge is field-shifted by the falling edge 132 of the next synchronization signal, and the signal reading mode 134 is started. In this case, since the output circuit 20A must detect the read signal charge 34, the camera control unit 70 naturally connects the switch 64 to the power supply voltage 62 (power on 136).
[0028]
Thus, the power supply voltage of the source follower amplifier circuit 40 at the final stage is turned on only when the signal charge is read out through the output circuit 20A as in the signal readout mode 134, the through mode 116, 127, and the sweep mode 126. , 121, and 129, and in other blanking periods 112 and exposure modes 128, the power supply voltages are turned off 120 and 130, respectively. This is a feature of the first embodiment of the present invention that reduces power consumption.
[0029]
In this embodiment, as the blanking period, the voltage off 120 is set in the vertical blanking period 112, but the voltage may be turned off in the horizontal blanking period.
[0030]
FIG. 6 is a circuit diagram showing a second embodiment 20B of the CCD output circuit according to the present invention. Elements similar to those in FIG. 1 showing the first embodiment are denoted by the same reference numerals. In the second embodiment, the power source voltage 60 (16V) of the source follower amplifier circuits 36, 38, 40 of each stage of the output circuit 20B is common, while the switching elements connected to the second stage 38 and the final stage 40 are used. The configuration is such that the value of the direct current is switched by 140, 142, 144, and 146.
[0031]
The current value I _2H of the constant current source 148 on the second stage switch 140 side is higher than the current value I _2L of the constant current source 150 on the switch 142 side. This relationship is the same for the current values I _3H and I _3L of the constant current sources 152 and 154 in the final stage, and there is a relationship of I _2H > I _2L and I _3H > I _3L . Switches 140 and 144 are simultaneously switched to open / close by a common control signal 72A, and switches 142 and 146 are simultaneously switched to open / close by a common control signal 72B. Using such a configuration, the camera control unit 70 that controls each switch opens the switches 142 and 146 when the switches 140 and 144 are closed, and causes a high current to flow through the second stage 38 and the final stage 40, respectively. , 146 are closed, the switches 140, 144 are opened, and low currents are passed through the second stage 38 and the final stage 40, respectively.
[0032]
In such a three-stage source follower amplifier circuit, the value of the current flowing through the first stage, the second stage, and the last stage can be set to, for example, 1: 2: 7. In this embodiment, the current value can be changed by switching, but it is only possible to select a discontinuous current value set by each constant current source 148, 150, 152, 154. However, the idea of the present invention is to change the current value according to the signal charge readout frequency. Therefore, a variable current source may be provided for each of the stages 38 and 40 so that the current value is continuously changed. In this embodiment, the current can be changed for the second stage 38 and the final stage 40, but it is needless to say that the current value of the first stage 36 may be changed.
[0033]
The operation of the second embodiment of the CCD output circuit according to the present invention configured as described above will be described below with reference to FIGS. 5 (a) (b) (d). Note that FIG. 5C is a time chart of the first embodiment in which only the power supply voltage is turned on / off, and is not related to FIG. 5D showing the operation of the second embodiment. However, it is preferable to use the first embodiment and the second embodiment in combination because further reduction of power consumption can be realized.
[0034]
The operation of the second embodiment will be typically described using the second stage 38 of FIG. The current control in this embodiment is performed according to the following policy. That is, at the time of actual imaging (signal readout mode 134), either one of the switches 140 and 142 is closed, the other is opened, and either the current I _2H or I _{2L is} passed (period 156). In principle, a high current _I2H is supplied because a high frequency characteristic is required for signal readout in the main imaging.
[0035]
On the other hand, in the signal read mode 134, an exceptionally low current _I2L may flow (period 156). This is because the signal readout speed at the time of actual imaging is slower than that of the through mode 116, for example, and a high readout frequency may not be required. Thus, in the read mode 134, the current value is changed according to the read frequency of the signal charge. The reason why the current is not set to zero is to enable quick transition to the next mode.
[0036]
As described above, according to the rules for changing the current value according to the read frequency, the current value is set as follows in the other modes. In the through mode 116, only the switch 140 is closed and a high current _I2H is allowed to flow (period 158). This is because the reading frequency becomes high because high-speed reading is performed. In the unnecessary charge sweep-out period, that is, in the sweep-out mode 126, only the switch 142 is closed and a small current _{I2L is} passed (period 160). This is because a high read frequency is not required. In a period in which no signal is read, that is, in the blanking period 112, both the switches 140 and 142 are opened, and the current value is turned off (substantially zero) (period 162).
[0037]
In the exposure mode 128, the unnecessary charge sweeping operation (which is also a kind of signal readout) in the previous sweep mode 126 may continue, so only the switch 142 is closed and a small current _I2L is allowed to flow (period 164). . On the other hand, if exposure is performed for a long time as exposure mode 128 continues even after sweeping is completed, both switches 140 and 142 can be opened to turn the current value off (substantially zero) ( Period 164).
[0038]
Thus, the idea of the present invention is to reduce the power consumption by turning off the power supply voltage during the period when the CCD signal is not read. In addition, according to the signal reading frequency of the CCD, the value of the direct current is lowered or substantially zero to reduce power consumption.
[0039]
Although the present invention uses a digital still camera as an embodiment, it is obvious that the present invention can also be applied to many other devices using a CCD as an image sensor, such as a scanner (line sensor system).
[0040]
【The invention's effect】
As described above, according to the present invention, the power consumption of the CCD output circuit can be reduced without impairing the frequency characteristics of the CCD output circuit. Further, by reducing the power consumption of the output circuit, the heat generated in the output circuit can be reduced, and the dark current of the pixels located near the output circuit can be reduced. Therefore, the influence on the image due to heat generation can be reduced.
[0041]
In addition, since the current value is lowered or turned off during long exposure, heat generation due to dark current can be reduced.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of a CCD output circuit according to the present invention;
FIG. 2 is a block diagram showing an example of a digital still camera to which a CCD output circuit according to the present invention is applied.
3 is a schematic diagram of a pixel region shown in FIG. 2. FIG.
FIG. 4 is a circuit diagram of a source follower amplifier circuit in the prior art.
FIG. 5 is a timing chart showing the operation of the embodiment of the CCD output circuit according to the present invention.
FIG. 6 is a circuit diagram showing a second embodiment of a CCD output circuit according to the present invention.
[Explanation of symbols]
10 Digital still camera
16 Image sensor
18 pixel area
20 Output circuit
36, 38, 40 source follower amplifier
64, 140, 142, 144, 146 Switching element
70 Camera control unit

Claims (7)

In a CCD output circuit including a multi-stage source follower amplifier circuit that amplifies and outputs a signal transferred from a charge coupled device (CCD), the circuit includes:
Switching means for switching the value of the final stage power supply voltage of the source follower amplifier circuit to a voltage set lower than the power supply voltage of other source follower amplifier circuits excluding the final stage, or substantially zero voltage ;
And control means for controlling the switching of the timing generator and the switching means for generating a whole synchronization signal camera including the CCD,
Wherein, the period in which CCD signal readout is not performed, by switching the switching means in synchronism with the switching of the vertical synchronizing signal in the synchronous signal, substantially to zero the value of the final stage supply voltage CCD output circuit, wherein the Turkey.   2. The CCD output circuit according to claim 1, wherein the control means switches the switching means during exposure of the CCD to make the value of the power supply voltage substantially zero. In a CCD output method for amplifying a signal transferred from a charge coupled device ( CCD ) with a plurality of stages of source follower amplifier circuits and outputting the amplified signal, the method includes:
A switching step of switching the value of the power supply voltage of the final stage of the source follower amplifier circuit to a power supply voltage set lower than a power supply voltage of other source follower amplifier circuits other than the final stage, or a substantially zero voltage;
And a control step of controlling the switching of the timing generator and the switching means for generating a whole synchronization signal camera including the CCD,
The control step switches the switching step in synchronization with the switching of the vertical synchronizing signal in the synchronizing signal during a period in which the CCD signal is not read, so that the value of the final stage power supply voltage is substantially zero. A CCD output method characterized by that . Claim 3 CCD In the output method, the control step includes: CCD The switching step is switched during the exposure to make the value of the power supply voltage substantially zero. CCD output method. In a CCD output circuit including a multi-stage source follower amplifier circuit that amplifies and outputs a signal transferred from a CCD, the circuit includes:
A switching means for the value of the DC current flowing through the source follower amplifier circuit is change for each stage,
Control means for setting the DC current value lower than the CCD signal readout period by switching the switching means during the unnecessary charge sweeping period of the CCD,
As a result, the CCD output circuit is characterized by reducing power consumption.   In the CCD output method in which the signal transferred from the CCD is amplified and output by a multi-stage source follower amplifier circuit, the value of the direct current flowing through the source follower amplifier circuit of each stage during the CCD unnecessary charge sweeping period is A CCD output method characterized in that it is set lower than the readout period. 7. The CCD output method according to claim 6 , wherein when the exposure is continued for a predetermined time or longer, the value of the direct current is lowered or made substantially zero.

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