JP4001841B2 - Driving method of solid-state imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a driving method of a solid-state imaging equipment using an over over flow drain (OFD) structure CCD (Charge Coupled Device).
[0002]
[Prior art]
In recent years, electronic devices for recording images such as digital cameras, digital video cameras, and camera-equipped mobile phones have become widespread, and miniaturization of image sensors such as CCD image pickup devices has been progressing with higher resolution.
[0003]
FIG. 8 is a block diagram showing a configuration of a conventional CCD solid-state imaging device disclosed in Patent Document 1 and the like. In the figure, a solid-state imaging device 10 includes a plurality of photodiodes 11 arranged two-dimensionally, a plurality of readout gate units 12, a plurality of vertical CCDs 13, a horizontal CCD 15, an output amplifier 16, and a substrate bias generation circuit 20. And a transistor Q1. In the same figure, a transistor Q2 and resistors R1 to R3 are also shown as a circuit for modulating a bias voltage (hereinafter referred to as substrate bias) Vsub of the semiconductor substrate of the solid-state imaging device.
[0004]
Japanese Patent Application Laid-Open No. H10-228561 and the like disclose a technique for predicting a decrease in the saturation signal charge amount Qs at the time of frame reading by controlling the substrate bias Vsub and increasing the decrease in advance. Here, frame reading is a method in which the mechanical shutter (not shown) is closed after the exposure time has elapsed, and the signal charges of the odd lines and the signal charges of the even lines are read in field units, and one still image is acquired. Often used in cases.
[0005]
In FIG. 8, a plurality of photodiodes 11 are two-dimensionally arranged to form an imaging area 14. Each photodiode 11 converts incident light into a signal charge corresponding to the amount of light and accumulates it. Each photodiode 11 is composed of, for example, a PN junction photodiode. The signal charges accumulated in the photodiodes 11 forming a vertical column are read out to the vertical CCD 13 by applying a read pulse XSG to the read gate unit 12.
[0006]
The vertical CCD 13 is provided for each vertical column of the photodiodes 11, and vertically transfers the signal charges read from each photodiode 11 through the read gate unit 12 to the horizontal CCD 15. In the case of an interline transfer (IT) type solid-state imaging device, each vertical CCD 13 is repeatedly provided with vertical transfer gate electrodes for transfer driving by, for example, four-phase vertical transfer clocks φV1 to φV4. The read signal charges are sequentially transferred in the vertical direction. As a result, signal charges for one scanning line (one line) are output from the plurality of vertical registers 13 to the horizontal register 15 in the horizontal blanking period. Of the four-phase vertical transfer clocks ΦV1 to ΦV4, ΦV2 and ΦV4 of the second phase and the fourth phase can take two values of a low level and a middle level for vertical transfer. On the other hand, since the vertical transfer gate electrodes corresponding to the first phase and the third phase also serve as the read gate electrode of the read gate unit 12, the vertical transfer clocks φV1 and φV3 are low level and middle level. And three levels of high levels. This third high-level pulse becomes a read pulse XSG given to the read gate section 12.
[0007]
The horizontal CCD 15 sequentially transfers the charges for one line transferred from the plurality of vertical CCDs 13 in the horizontal blanking period in one horizontal scanning period, and outputs them through the output amplifier 16. The horizontal CCD 15 is driven to transfer by, for example, two-phase horizontal transfer clocks φH 1 and φH 2, and the signal charges for one line transferred from the plurality of vertical CCDs 13 are sequentially horizontal in the horizontal scanning period after the horizontal blanking period. Forward to.
[0008]
The output amplifier 16 sequentially converts the signal charges horizontally transferred by the horizontal CCD 15 into voltage signals and outputs them.
[0009]
The substrate bias voltage generation circuit 20 generates a substrate bias voltage Vsub and applies it to the substrate 17 via the transistor Q1. This substrate bias Vsub is set to a first bias voltage when the transistor Q2 is off and to a lower second bias voltage when the transistor Q2 is on under the control of the VsubCont signal.
[0010]
The solid-state image sensor 10 is formed on a semiconductor substrate (hereinafter referred to as a substrate) 17. Various timing signals such as a substrate shutter pulse φSUB for sweeping signal charges accumulated in the photodiode 11 to the substrate 17 are applied to the substrate 17. The function of sweeping out all signal charges accumulated in the photodiode 11 to the drain, including the substrate shutter by the substrate shutter pulse φSUB, is also called an electronic shutter. The drain may be a horizontal overflow drain.
[0011]
FIG. 9 is a diagram showing the potential distribution in the substrate depth direction of the photodiode 11. The amount of signal charge e accumulated in the photodiode 11 is determined by the height of the potential barrier of the overflow barrier OFB. That is, the overflow barrier OFB determines the saturation signal charge amount Qs accumulated in the photodiode 11. When the accumulated charge amount exceeds the saturation signal charge amount Qs, the excess charge is swept out toward the substrate 17 beyond the potential barrier. The potential of the overflow barrier OFB in such a vertical overflow drain structure can be controlled by the overflow drain bias, that is, the substrate bias Vsub. That is, the height of the barrier can be controlled by the substrate bias Vsub.
[0012]
FIG. 10 is a time chart showing the operation timing of the solid-state imaging device in frame reading with control of the substrate bias Vsub. In the figure, the open / close state of the mechanical shutter, the substrate bias Vsub (substrate voltage in the drawing), and the vertical transfer clocks ΦV1 and ΦV3 applied to the read gate electrode from the photodiode 11 to the vertical CCD 13 are shown. High-level pulses of the vertical transfer clocks ΦV1 and ΦV3 are read pulses XSG given to the read gate electrodes.
[0013]
In the monitor period, an image is read from the solid-state image sensor for display on a viewfinder or a liquid crystal monitor while the mechanical shutter is open, and is displayed as a moving image (referred to as a high-speed moving image capturing mode).
[0014]
In addition, when a user performs a shutter operation or the like, still image capturing (referred to as a still image capturing mode) by frame readout using a mechanical shutter is started. First, a plurality of substrate shutter pulses ΦSUB (substrate shutter voltage pulses in the figure) are applied to the substrate bias Vsub. The substrate shutter means that all signal charges of the photodiode 11 are swept out to the substrate 17 by eliminating the barrier of the overflow barrier (see FIG. 9) by increasing the substrate bias Vsub by ΦSUB. When the application of the substrate shutter pulse is completed, the signal charge accumulation amount of the photodiode 11 becomes zero. The period from the end of the application of the substrate shutter pulse to the closing of the mechanical shutter is the exposure period. Following this, a high-speed sweep period in which signal charges in the vertical CCD 13 are swept in advance, a first field output period, a high-speed sweep period, a second field output period, and an invalid data output period are sequentially provided. At the heads of the first and second field readout periods, signal charges in the first and second fields are read from the photodiode 11 to the vertical CCD by the readout pulse XSG superimposed on ΦV1 and ΦV3. Thereafter, the period returns to the monitor output period after an invalid data output period.
[0015]
As for the substrate bias Vsub, the first bias voltage is applied in the high-speed moving image capturing mode (during the monitoring period). In the still image capturing mode, the first bias voltage and the second bias voltage are switched as shown in the figure (referred to as substrate bias modulation). Since the second bias voltage is lower than the first bias voltage, the height of the overflow barrier OFB is higher in the second bias voltage and the saturation signal accumulation amount Qs is increased. The period of the second bias voltage is an invalid data output period from the exposure period in the drawing, but includes at least the second field output period. It is possible to reduce the difference (step) in the saturation signal charge amount Qs between the first field and the second field.
[0016]
Thereby, the saturation signal charge amount Qs that decreases with the passage of time when the mechanical shutter is shielded can be increased in anticipation of the decrease. As a result, deterioration of characteristics such as S / N and dynamic range due to the decrease of the saturation signal charge amount Qs with the passage of time is prevented.
[0017]
[Patent Document 1]
Japanese Patent Laid-Open No. 10-150183
[Problems to be solved by the invention]
However, according to the prior art, the characteristic deterioration due to the decrease of the saturation signal charge amount with the passage of time is only prevented. Along with the recent miniaturization of solid-state imaging devices, the area of the photodiode, the gate electrode, etc. are miniaturized, and in addition to increasing the capacity of the saturation signal charge amount, the quantum efficiency (photoelectric conversion efficiency) can be improved and the sensitivity can be improved. is needed.
[0019]
The present invention aims to provide a driving method of a solid-state imaging equipment with improved improved sensitivity photoelectric conversion efficiency in the exposure period.
[0020]
[Means for Solving the Problems]
In order to solve the above problems, a driving method of a solid-state imaging device according to the present invention employs an overflow drain structure that discharges excess charge generated in a photodiode to the drain, and a substrate that discharges the charge accumulated in the photodiode to the drain. A solid-state imaging device driving method comprising: a solid-state imaging device having a shutter; and a light-shielding unit that controls the incidence of light on the solid-state imaging device, wherein the light-shielding unit from the end of discharge of the charge by the substrate shutter The bias voltage that defines the height of the overflow barrier is changed from the first bias voltage to the second bias voltage that is lower than the first bias voltage from the beginning of the exposure period until the exposure period is closed. Chi coercive substantially the bias voltage over the entire constant, and at the end fall start to the second bias voltage There is a time difference, and at the start of the exposure period the fall start to the second bias voltage, further characterized in that the fall at the end of the second bias voltage be within the exposure period. Here, the change of the bias voltage may be performed in synchronization with the last falling edge of the substrate shutter pulse or triggered by the last falling edge of the substrate shutter pulse.
[0021]
Here, the field read out first is provided with a charge readout period composed of a plurality of fields after the exposure period, and the readout gate electrode of the field not read out first is set to a low level voltage during the horizontal effective period. The charge may be read out with a middle level voltage. The first bias voltage may be the bias voltage for discharging the excess charge to the drain when the light is continuously irradiated with the light shielding unit opened.
[0023]
According to this configuration, it is possible to increase the saturation charge signal charge amount accumulated in the photodiode 11 over almost the entire exposure period, improve the photoelectric conversion efficiency in the exposure period, and improve the sensitivity. In particular, the sensitivity can be improved as the wavelength of incident light is longer.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
<Configuration>
FIG. 1 is a block diagram showing a schematic configuration of a solid-state imaging device according to an embodiment of the present invention. The solid-state imaging device 1 includes a lens 2, a mechanical shutter 3, a driving unit 4, a signal processing unit 5, and a solid-state imaging device 10, and in the frame readout method that sequentially reads a plurality of fields with the mechanical shutter 3 closed. The substrate bias voltage applied to the solid-state imaging device 10 by the driving of is reduced from the first bias voltage to the second bias voltage immediately after the completion of the application of the substrate shutter pulse. Here, the first bias voltage is a bias voltage in the moving image capturing mode when the mechanical shutter 3 is open. The second bias voltage is lower than the first bias voltage, and is a voltage for increasing the overflow barrier and increasing the saturation signal accumulation amount Qs.
[0026]
In this way, by reducing the first bias voltage to the second bias voltage immediately after the application of the substrate shutter pulse, the saturation signal accumulation amount Qs is increased over almost the entire exposure period immediately after the application of the substrate shutter pulse, The photoelectric conversion efficiency is improved to improve sensitivity.
[0027]
In the figure, incident light from a subject (not shown) enters an imaging area of a CCD solid-state imaging device 10 through an optical system such as a lens 2 and a mechanical shutter 3.
[0028]
The mechanical shutter 3 controls incident light to the imaging area of the CCD solid-state imaging device 10. Note that a liquid crystal shutter or the like having a function of shielding light may be provided instead of the mechanical shutter 3.
[0029]
The solid-state image sensor 10 is the same as the solid-state image sensor shown in FIG. FIG. 2A is an example showing the arrangement of photodiodes in the solid-state imaging device 10 and the arrangement of vertical transfer electrodes of the vertical CCD 13. The arrangement of the photodiodes is a so-called Bayer arrangement. Four types of Φ1 to Φ4 corresponding to the four-phase clock pulses ΦV1 to ΦV4 are repeatedly arranged on the vertical transfer electrode of the vertical CCD 13. Of these, Φ1 and Φ3 also serve as readout gate electrodes for reading out signal charges from the photodiodes on the odd and even lines to the vertical CCD, respectively. In frame readout in the still image capturing mode, after the exposure period, readout of the first field composed of odd lines read from the readout gate electrode Φ1 as shown in FIG. 2B, and as shown in FIG. 2C. The second field consisting of even lines read from the read gate electrode Φ3 is sequentially read.
[0030]
The driving unit 4 includes four-phase clock pulses ΦV1 to ΦV4 that control the transfer of the vertical CCD of the solid-state imaging device 10, two-layer clock pulses ΦH1 and ΦH2 that control the transfer of the horizontal CCD, a substrate bias voltage control signal VsubCont, and a substrate shutter pulse. Φsub and the like are generated and supplied to the solid-state imaging device 10. Among the four-phase clock pulses, ΦV1 and ΦV3 are signals that can take three values of low level, middle level, and high level, and the high level pulse is a read pulse XSG applied to the read gate electrode. The drive unit 4 lowers the substrate bias voltage from the first bias voltage to the second bias voltage immediately after applying the substrate shutter pulse in the still image capturing mode (that is, at the start of the exposure period), and after the second field reading is completed, Substrate bias modulation is performed so as to return to 1 bias voltage. Immediately after the completion of the application of the substrate shutter pulse, for example, it is synchronized with the last falling edge of the substrate shutter pulse, or triggered by the last falling edge of the substrate shutter pulse, and lowered to the second bias voltage. It can be realized by.
[0031]
The signal processing unit 5 performs various signal processing such as automatic white balance adjustment on the output signal from the solid-state imaging device 10 and outputs the signal as an imaging signal to the outside.
[0032]
FIG. 3 is a cross-sectional view showing the structure in the substrate depth direction around the photodiode 11 and the vertical CCD 13. In the figure, for example, a P-type well region 31 is formed on the surface of an N-type substrate 17. An N-type signal charge storage region 32 is formed on the surface of the well region 31, and a P + -type hole storage region 33 is further formed thereon, thereby constituting the photodiode 11.
[0033]
The amount of signal charge e accumulated in the photodiode 11 is determined by the height of the potential barrier of the overflow barrier OFB formed of the P-type well region 31. The overflow barrier OFB determines the saturation signal charge amount Qs accumulated in the photodiode 11. When the accumulated charge amount exceeds the saturation signal charge amount Qs, the excess charge exceeds the potential barrier. Sweeped to the substrate 17 side.
[0034]
In this way, a photodiode 11 having a so-called vertical overflow drain structure is formed.
[0035]
In the lateral direction of the photodiode 11, an N-type signal charge transfer region 35 and a P + -type channel stopper region 36 are formed via a portion of the P-type region 31 that constitutes the readout gate portion 12. Under the signal charge transfer region 35, a P + -type impurity diffusion region 37 is formed for preventing a smear component from being mixed. Further, a transfer electrode 39 made of, for example, polycrystalline silicon is disposed above the signal charge transfer region 35, whereby the vertical CCD 13 is configured. In the transfer electrode 39, the portion located above the P-type region 31 also serves as the gate electrode of the read gate unit 12.
[0036]
A substrate bias Vsub that determines the amount of signal charge accumulated in the photodiode 11 (that is, determines the potential of the overflow barrier OFB) is applied to the substrate 17.
[0037]
<Operation>
FIG. 4 is a time chart showing the operation timing of the solid-state imaging device 10 in frame readout with substrate bias Vsub modulation. In the figure, the open / close state of the mechanical shutter, the substrate bias Vsub (substrate voltage in the drawing), and the vertical transfer clocks ΦV1 and ΦV3 applied to the read gate electrode from the photodiode 11 to the vertical CCD 13 are shown. The high level pulse superimposed on the vertical transfer clocks ΦV1 and ΦV3 is a read pulse XSG applied to the read gate electrode.
[0038]
In the monitor output period (high-speed moving image capturing mode), images are continuously read from the solid-state image sensor and displayed as moving images for display on a viewfinder or a liquid crystal monitor while the mechanical shutter is open.
[0039]
In addition, when a user performs a shutter operation or the like, still image capturing (still image capturing mode) is started by frame readout using a mechanical shutter together. In this still image capturing mode, first, a plurality of substrate shutter pulses ΦSUB are applied to the substrate bias Vsub.
[0040]
FIG. 5A shows the potential distribution when the substrate shutter pulse ΦSUB is applied. XY on the horizontal axis indicates the horizontal direction of the substrate from the vertical CCD 13 to the photodiode 11 shown in FIG. 2, and YZ indicates the substrate depth direction of the photodiode 11 shown in FIG. The vertical axis represents potential. As shown in FIG. 5A, when the substrate shutter pulse is applied, by raising the substrate bias Vsub, the overflow barrier is eliminated and all the signal charges of the photodiode 11 are swept out to the semiconductor substrate. Thus, at the end of application of the plurality of substrate shutter pulses ΦSUB, all signal charges of the photodiode 11 are swept out.
[0041]
Further, immediately after the application of the last substrate shutter pulse among the plurality of substrate shutter pulses is completed, the drive unit 4 performs bias modulation to lower the substrate bias voltage Vsub from the first bias voltage to the second bias voltage.
[0042]
FIG. 5B is a potential distribution diagram when the first bias voltage and the second bias voltage are applied. As shown in the figure, the overflow barrier OFB becomes higher when the second bias voltage is applied than the first bias voltage, and the saturation signal accumulation amount Qs increases. Furthermore, not only the saturation signal accumulation amount Qs is increased, but also the sensitivity is improved. The improvement in sensitivity is due to the fact that the overflow barrier of the photodiode is positioned deeper in the substrate depth direction, so that more signal charges generated by photoelectric conversion can be accumulated in the photodiode, that is, the photoelectric conversion efficiency is improved.
[0043]
FIG. 6 shows the characteristics of the wavelength of incident light and the spectral sensitivity when the first bias voltage and the second bias voltage are applied. A solid line and a broken line indicate characteristics when the first and second bias voltages are applied. The sensitivity is improved as the wavelength of incident light is longer. This is because light having a longer wavelength reaches deeper and the influence of the depth of the overflow barrier becomes larger.
[0044]
In FIG. 4, the operation timing after the exposure period is the same as that in FIG.
[0045]
The second bias voltage is applied immediately after the application of the substrate shutter pulse is completed until the second field readout period is completed. The reason why the first bias voltage is switched to the second bias voltage immediately after the application of the substrate shutter pulse is completed is as follows. (1) This is because the sensitivity is improved by applying the second bias voltage over almost the entire exposure period. (2) If the first bias voltage is lowered from the first bias voltage to the second bias voltage before or during the application of the substrate shutter pulse, the substrate shutter pulse is applied in a state where the overflow barrier OFB is higher. This is because a signal charge cannot be swept out unless a high substrate shutter is applied.
[0046]
In addition, the shorter the time from the end of charge discharge by the electronic shutter to the start of the fall to the second bias voltage, the better in this embodiment. This is because the shorter the time until the start of the fall, the longer the period of the second bias voltage level that occupies the exposure time, and the higher the exposure sensitivity.
[0047]
Generally, at the time of high-speed electronic shutter (for example, 1/2000 second), the mechanical shutter closing time varies due to mechanical factors, and the exposure time, that is, the exposure amount varies by about 10%, but is practically acceptable in a camera system. . Therefore, the time allowed for the exposure time error is about 10% of the exposure time. Therefore, it is desirable that the time from the end of the charge discharge by the electronic shutter to the start of the fall to the second bias voltage be within 10% of the exposure time.
[0048]
Specifically, if the exposure time of the high-speed electronic shutter realized by the substrate shutter is 500 μS, it is desirable that the time is 50 μS or less when the allowable error is within 10%.
[0049]
As described above, according to the solid-state imaging device of the present embodiment, since the substrate bias Vsub is set to the second bias voltage over almost the entire exposure period, the depth of the overflow barrier becomes deeper and more Is accumulated in the photodiode, the photoelectric conversion efficiency (quantum efficiency) is improved. As a result, the sensitivity can be improved. By improving the sensitivity, the S / N of the color is improved, and the image quality at the time of imaging is improved even at low illumination. Further, since the improvement in sensitivity is high in the longer wavelength, that is, from R (red) to infrared (IR) region, it is possible to improve the performance when the solid-state imaging device is used as a surveillance camera or a night vision camera. it can.
[0050]
Note that the substrate bias voltage generation circuit 20, the transistors Q1 and Q2, and the resistors R1 to R3 and C in FIG. 8 may be formed entirely or partially on the substrate of the solid-state imaging device 10 or outside the substrate. It may be provided. Further, the substrate bias voltage generation circuit 20 may be configured to generate the substrate bias voltage Vsub as a divided value by a resistor connected in series between the power source and the ground.
[0051]
Further, in the above embodiment, the case of frame reading by the interline transfer method in the 2-to-1 interlace scan has been described as an example. However, the solid state in which the exposure time is determined in combination with the substrate shutter and the mechanical shutter. Any image sensor may be used, and the present invention is not limited thereto. For example, it may be a reading of 3 to 1, such as a many-to-one interns race-scan method, it may be a reading of the progressive scan method.
[0052]
Further, the solid-state imaging device having the vertical overflow drain structure has been described as an example, but the present invention can be similarly applied to a horizontal overflow drain structure.
[0053]
<Modification>
FIG. 7 is a flowchart showing the operation timing in the modification of the solid-state imaging device in the above embodiment.
[0054]
The time chart of FIG. 7 differs from FIG. 4 in the voltage levels in the horizontal effective period of the read gate electrodes ΦV1 and ΦV3. Here, the horizontal effective period is a period in which the horizontal transfer operation is performed in the horizontal CCD 15 and the vertical transfer clock pulse is not changed in the vertical CCD 13.
[0055]
In FIG. 7, in the first field output period, the readout pulse XSG superimposed on the middle level voltage is applied to the readout gate electrode Φ 1, whereby the signal charges constituting the first field are read out to each vertical CCD 13. In the subsequent horizontal effective period, the voltage ΦV1 of the read gate electrode Φ1 in the first field is a middle level voltage (hereinafter referred to as a VM read case). On the contrary, as shown in FIG. 4, there may be a case where the voltage ΦV1 of the read gate electrode Φ1 in the first field is a low level voltage (hereinafter referred to as a VL read case) in the first field output period. Which case is used in the first field readout period is arbitrary. Similarly, in which case the second field is set in the second field readout period is arbitrary.
[0056]
In interlaced reading, it is desirable to use the VM reading case in the first field as shown in FIG. This is because the blooming is less likely to occur in the low level when the voltage of the readout gate electrode Φ3 in the second field where the signal charge is not read out from the photodiode 11 is the middle level and the low level. is there. When the first field is VM readout case, voltage V .phi.3 readout gate electrode .phi.3 of the second field in the horizontal effective period becomes a low level. This is because the vertical transfer clocks ΦV1 and ΦV3 are the first and third phases of the four-phase clock signal, and when one is at a low level during the horizontal scanning period, the other is usually at a middle level.
[0057]
Therefore, when a plurality of fields are sequentially read after the mechanical shutter is closed, as shown in FIG. 7, the read gate electrode Φ3 of the second field that is not read first is set to the low level during the horizontal effective period. Therefore, the first field that is read first is read in the VM case. In other words, the readout gate electrode Φ3 in the second field that stores the signal charge in the photodiode 11 without being read out in the first field period is not at the middle level where blooming is likely to occur, but at the low level where blooming is unlikely to occur. ing. For this reason, since the first field read out first does not generate blooming in the horizontal effective period after reading out, the VM gate in which the read gate electrode Φ1 of the first field becomes the middle level in the horizontal effective period is used. In the case of many-to-one interlace as well as two-to-one interlace, the same effect can be obtained by setting the read gate electrode of a field that is not read out to a low level.
[0058]
【The invention's effect】
According to the driving method of the solid-state imaging device of the present invention, the saturation charge signal charge amount accumulated in the photodiode 11 is increased almost throughout the exposure period, and the photoelectric conversion efficiency in the exposure period is improved and the sensitivity is improved. Can do. In particular, the sensitivity can be improved as the wavelength of incident light is longer. The sensitivity is improved because the depth of the overflow barrier of the photodiode becomes deeper, and more signal charges are accumulated in the photodiode, thereby improving the efficiency (quantum efficiency) of photoelectric conversion. As a result, the S / N of the color is improved, and the image quality at the time of imaging can be improved even at low illuminance.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a schematic configuration of a solid-state imaging device according to an embodiment.
FIG. 2A is an example showing the arrangement of photodiodes in a solid-state imaging device and the arrangement of transfer electrodes of a vertical CCD.
(B) It is explanatory drawing of the read-out of the 1st field which consists of odd lines.
(C) It is explanatory drawing of the reading of the 2nd field consisting of an even number line.
FIG. 3 is a cross-sectional view showing a structure in a substrate depth direction around a photodiode and a vertical CCD.
FIG. 4 is a time chart showing the operation timing of the solid-state imaging device in frame readout with substrate bias Vsub modulation.
FIG. 5A shows a potential distribution when a substrate shutter pulse is applied.
FIG. 6B is a potential distribution diagram when a first bias voltage and a second bias voltage are applied.
FIG. 6 shows the characteristics of the wavelength of incident light and the spectral sensitivity when a first bias voltage and a second bias voltage are applied.
FIG. 7 is a flowchart illustrating operation timing in a modification of the solid-state imaging device.
FIG. 8 is a block diagram showing a configuration of a CCD solid-state imaging device.
FIG. 9 is a diagram showing a potential distribution in the substrate depth direction of a photodiode.
FIG. 10 is a time chart showing the operation timing of the solid-state imaging device in frame readout with control of the substrate bias Vsub in the prior art.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Solid-state imaging device 2 Lens 3 Mechanical shutter 4 Drive part 5 Signal processing part 10 Solid-state image sensor 11 Photodiode 12 Read-out gate 13 Vertical CCD
14 Imaging area 15 Horizontal CCD
16 Output amplifier 17 Semiconductor substrate

Claims (5)

A solid-state imaging device having an overflow drain structure that discharges excess charge generated in the photodiode to the drain, and a substrate shutter that discharges the charge accumulated in the photodiode to the drain; and incidence of light on the solid-state imaging device A method of driving a solid-state imaging device comprising a light-shielding means for controlling
A bias voltage that defines the height of the overflow barrier from the start of the exposure period immediately after the end of application of the substrate shutter pulse is defined as an exposure period from the end of discharge of the electric charge by the substrate shutter to the closing of the light shielding means. change to the second bias voltage is a voltage lower than the first bias voltage from the first bias voltage, Chi coercive the bias voltage constant over substantially the entire area of the exposure period,
There is a time difference between the start and end of the fall to the second bias voltage, the start of the fall to the second bias voltage is set as the start of the exposure period, and the fall to the second bias voltage is further performed. A method for driving a solid-state imaging device, characterized in that the end time is within the exposure period . The changing of the bias voltage, the substrate shutter pulse for the last synchronization with the falling edge, or claim 1 wherein the solid and performing by the last falling edge of the previous SL substrate shutter pulse triggers Driving method of imaging apparatus. A charge readout period consisting of a plurality of fields is provided after the exposure period, and in order to set the readout gate electrode of the field that has not been read out first to a low level voltage during the horizontal effective period, the field read out first is set to the middle level The method of driving a solid-state imaging device according to claim 1, wherein the electric charge is read out with a voltage. The first bias voltage is the bias voltage for discharging the excess charge to the drain when the photodiode is continuously irradiated with light with the light shielding means opened. The method for driving a solid-state imaging device according to claim 1. Changing the bias voltage so that the time from the end of discharge of the charge by the substrate shutter to the start of the fall to the second bias voltage is within a time allowed as an error in the exposure time,
The method of driving a solid-state imaging device according to claim 1, wherein a time allowed as the error is within 10% of the exposure time.

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