JP4563848B2 - Solid-state imaging device and camera - Google Patents

Description

  The present invention relates to a substrate bias circuit, a solid-state imaging device, and a camera that apply a substrate bias voltage that defines the height of an overflow barrier in a CCD (Charge Coupled Device) having an overflow drain (OFD) structure to a semiconductor substrate on which the CCD is formed. About.

  In recent years, electronic devices for recording images such as digital cameras, digital video cameras, and camera-equipped mobile phones have become widespread, and miniaturization of image sensors such as CCD image pickup devices has been progressing with higher resolution.

  FIG. 11 is a block diagram showing a configuration of a conventional CCD solid-state imaging device disclosed in Patent Document 1 and the like. In the figure, a solid-state imaging device 1 includes a plurality of photodiodes 11 arranged two-dimensionally, a plurality of readout gate units 12, a plurality of vertical CCDs 13, a horizontal CCD 15, an output amplifier 16, and a substrate bias voltage generation circuit. 20 and a transistor Q1. In the same figure, a transistor Q2, resistors R1 to R3, and a capacitor C are also shown as a circuit for modulating the bias voltage (hereinafter referred to as substrate bias) Vsub of the semiconductor substrate of the solid-state imaging device.

  Japanese Patent Application Laid-Open No. H10-228561 and the like disclose a technique for predicting a decrease in the saturation signal charge amount Qs at the time of frame reading by controlling the substrate bias Vsub and increasing the decrease in advance. Here, frame reading is a method in which the mechanical shutter (not shown) is closed after the exposure time has elapsed, and the signal charges of the odd lines and the signal charges of the even lines are read in field units, and one still image is acquired. Often used in cases.

  In FIG. 11, a plurality of photodiodes 11 are two-dimensionally arranged to form an imaging area 14. Each photodiode 11 converts incident light into a signal charge corresponding to the amount of light and accumulates it. Each photodiode 11 is composed of, for example, a PN junction photodiode. The signal charges accumulated in the photodiodes 11 forming a vertical column are read out to the vertical CCD 13 by applying a read pulse XSG to the read gate unit 12.

  The vertical CCD 13 is provided for each vertical column of the photodiodes 11, and vertically transfers the signal charges read from each photodiode 11 through the read gate unit 12 to the horizontal CCD 15. In the case of an interline transfer (IT) type solid-state imaging device, each vertical CCD 13 is repeatedly provided with vertical transfer gate electrodes for transfer driving by, for example, four-phase vertical transfer clocks φV1 to φV4. The read signal charges are sequentially transferred in the vertical direction. As a result, signal charges for one scanning line (one line) are output from the plurality of vertical CCDs 13 to the horizontal CCD 15 in the horizontal blanking period. Of the four-phase vertical transfer clocks ΦV1 to ΦV4, ΦV2 and ΦV4 of the second phase and the fourth phase can take two values of a low level and a middle level for vertical transfer. On the other hand, since the vertical transfer gate electrodes corresponding to the first phase and the third phase also serve as the read gate electrode of the read gate unit 12, the vertical transfer clocks φV1 and φV3 are low level and middle level. And three levels of high levels. This third high-level pulse becomes a read pulse XSG given to the read gate section 12.

  The horizontal CCD 15 sequentially transfers the charges for one line transferred from the plurality of vertical CCDs 13 in the horizontal blanking period in one horizontal scanning period, and outputs them through the output amplifier 16. The horizontal CCD 15 is driven to transfer by, for example, two-phase horizontal transfer clocks φH 1 and φH 2, and the signal charges for one line transferred from the plurality of vertical CCDs 13 are sequentially shifted in the horizontal direction in the horizontal scanning period after the horizontal blanking period. Forward to.

  The output amplifier 16 sequentially converts the signal charges horizontally transferred by the horizontal CCD 15 into voltage signals and outputs them.

  The substrate bias voltage generation circuit 20 generates a substrate bias voltage Vsub and applies it to the substrate 17 via the transistor Q1. This substrate bias Vsub is set to a first bias voltage when the transistor Q2 is off and to a lower second bias voltage when the transistor Q2 is on under the control of the VsubCont signal.

  The solid-state imaging device 1 is formed on a semiconductor substrate (hereinafter referred to as a substrate) 9. Various timing signals such as a substrate shutter pulse φSUB for sweeping signal charges accumulated in the photodiode 11 to the substrate 17 are applied to the substrate 17. The substrate shutter function based on the substrate shutter pulse φSUB is also called an electronic shutter.

  FIG. 12 is a diagram showing a potential distribution in the substrate depth direction of the photodiode 11. The amount of signal charge e accumulated in the photodiode 11 is determined by the height of the potential barrier of the overflow barrier OFB. That is, the overflow barrier OFB determines the saturation signal charge amount Qs accumulated in the photodiode 11. When the accumulated charge amount exceeds the saturation signal charge amount Qs, the excess charge is swept out toward the substrate 17 beyond the potential barrier. The potential of the overflow barrier OFB in such a vertical overflow drain structure can be controlled by an overflow drain bias, that is, a substrate bias Vsub. That is, the height of the barrier can be controlled by the substrate bias Vsub.

  FIG. 13 is a time chart showing the operation timing of the solid-state imaging device in frame reading with control of the substrate bias Vsub. In the figure, the open / close state of the mechanical shutter, the substrate bias Vsub (substrate voltage in the drawing), and the vertical transfer clocks ΦV1 and ΦV3 applied to the read gate electrode from the photodiode 11 to the vertical CCD 13 are shown. High-level pulses of the vertical transfer clocks ΦV1 and ΦV3 are read pulses XSG given to the read gate electrodes.

  In the monitor period, an image is read from the solid-state image sensor for display on a viewfinder or a liquid crystal monitor while the mechanical shutter is open, and is displayed as a moving image (referred to as a high-speed moving image capturing mode).

  In addition, when a user performs a shutter operation or the like, still image capturing (referred to as a still image capturing mode) by frame readout using a mechanical shutter is started. First, a plurality of substrate shutter pulses ΦSUB (substrate shutter voltage pulses in the figure) are applied to the substrate bias Vsub. The substrate shutter means that all signal charges of the photodiode 11 are swept out to the substrate 17 by eliminating the barrier of the overflow barrier (see FIG. 12) by increasing the substrate bias Vsub by ΦSUB. When the application of the substrate shutter pulse is completed, the signal charge accumulation amount of the photodiode 11 becomes zero. The period from the end of the application of the substrate shutter pulse to the closing of the mechanical shutter is the exposure period. Following this, a high-speed sweep period in which signal charges in the vertical CCD 13 are swept in advance, a first field output period, a high-speed sweep period, a second field output period, and an invalid data output period are sequentially provided. At the heads of the first and second field readout periods, signal charges in the first and second fields are read from the photodiode 11 to the vertical CCD by the readout pulse XSG superimposed on ΦV1 and ΦV3. Thereafter, the period returns to the monitor output period after an invalid data output period.

  As for the substrate bias voltage Vsub, the first bias voltage is applied in the high-speed moving image capturing mode (during the monitoring period). In the still image capturing mode, the first bias voltage and the second bias voltage are switched as shown in the figure (referred to as substrate bias modulation). Since the second bias voltage is lower than the first bias voltage, the height of the overflow barrier OFB is higher in the second bias voltage and the saturation signal charge amount Qs is increased. The period of the second bias voltage is an invalid data output period even during the exposure period in the figure, but includes at least a second field output period.

Non-Patent Document 1 specifically discloses the modulation of the substrate bias and its timing.
Japanese Patent Laid-Open No. 10-150183 Sony Corporation "ICQ232BQ specification (diagonal 5mm (1 / 3.6 type) square pixel type frame readout type solid-state image sensor for color)", [online], [Search April 23, 2003], Internet <URL: http: // www. sony. co. jp / ~ semicon / japan / img / sonyj01 / e68001383. pdf>

  However, according to the above prior art, in the substrate bias modulation for switching from the first bias voltage to the second bias voltage, the voltage is applied only with a time constant of about 10 ms determined by the load resistor R1, the φSUB coupling capacitor C and the SUB capacitor of the substrate bias circuit. Therefore, it is necessary to start the substrate bias control 20 ms before the actual exposure start time. Therefore, the electronic shutter pulse ΦSUB to be finally applied is superimposed on the second bias voltage, and the charge is extracted to the substrate. In order to reduce the substrate bias circuit time constant, the required peak substrate voltage is reduced by the amount of substrate bias modulation, and an element design that can extract charges to the substrate at a lower voltage is required. If the φSUB coupling capacitance C is reduced, the capacitance between the substrate capacitance and this C Since the electronic shutter pulse ΦSUB decreases due to the division, it is necessary to apply a high-amplitude φSUB pulse in advance, or to design an element that can extract charges to the substrate with a lower voltage as in the previous problem countermeasures. In these cases, these measures are more difficult.

  On the other hand, if the first bias voltage is switched from the first bias voltage to the second bias voltage immediately after the final application of the electronic shutter pulse ΦSUB, it is possible to avoid the problems of the element design and the increase in the φSUB pulse amplitude, but especially if the voltage fall time is not shortened as much as possible. Spectral characteristics at the time of high-speed shutter operation fluctuate, and a new problem arises that the image quality of the image by the high-speed shutter operation is deteriorated (color reproducibility is different) than the image by the normal shutter operation.

  Next, these problems will be specifically described. FIG. 14 shows a time chart in which the falling section of the substrate bias voltage is enlarged from the first bias voltage to the second bias voltage. As shown in the figure, the fall time Tf from the first bias voltage to the second bias voltage takes about 1000 μS (about 1 mS). On the other hand, the exposure period in the high-speed shutter operation may be shorter (eg, 100 μS) than the fall time Tf in the figure, and the exposure period is completed in the transition period of the fall.

  FIG. 15A is a diagram illustrating the spectral characteristics of the photodiode when the substrate bias voltage is the first bias voltage. FIG. 15B is a diagram showing the spectral characteristics of the photodiode when the substrate bias voltage is the second bias voltage. In the figure, the horizontal axis indicates the wavelength, and the vertical axis indicates the spectral sensitivity. As shown in the figure, the spectral sensitivity at the second bias voltage is superior to the spectral sensitivity at the first bias voltage as the wavelength is longer (especially red R and green G).

  FIG. 16 is a diagram illustrating a change in the overflow barrier in the falling section of the substrate bias voltage. As shown in the drawing, the peak of the overflow barrier at the time of the second bias voltage exists at a deeper position than the first bias voltage. Light having a longer wavelength (especially red R and green G) reaches a deeper position from the substrate surface and undergoes photoelectric conversion, so that a difference in spectral sensitivity as shown in FIGS. 15A and 15B appears. The spectral characteristics during the high-speed shutter operation are deteriorated because the peak of the overflow barrier is in a transition period in which the peak changes in the substrate depth direction.

  The fall period is determined by the load resistance R1 of the substrate bias circuit, the φSUB coupling capacitance C, and the SUB capacitance as described in the conventional example. When the φSUB coupling capacitance C is reduced, the substrate capacitance and the C are reduced. Since the electronic shutter pulse ΦSUB decreases due to the capacitive division, it is conceivable to reduce the resistance value of the resistor R1, which is the ground resistance of the transistor Q1, in order to shorten the fall time without causing them. Since the normal substrate current is supposed to sweep out excess charges, the resistor R1 has a large resistance value of, for example, about 100 kΩ to 1000 kΩ. If the resistance value of the resistor R1 is reduced, an unnecessary large current always flows through the resistor R1, resulting in a problem that the power supply circuit becomes larger, consumes more power, and generates heat.

The present invention aims to facilitate the device design, the power supply circuit and power consumption to provide a conventional equivalent and fast solid-state image sensor and a camera spectral characteristics improves by that to prevent deterioration of image quality by the shutter operation And

Upper Symbol solid-state imaging device of the object of the present invention to achieve has an electronic shutter function for discharging the charge accumulated in the photodiode take an overflow drain structure for discharging excess charges generated in the photodiode to the drain to the drain A solid-state imaging device, a light shielding means for controlling the incidence of light on the photodiode, and a substrate bias voltage that defines the height of the overflow barrier in the overflow drain structure are applied to the semiconductor substrate on which the solid-state imaging device is formed. A solid-state imaging device including a substrate bias circuit and a drive unit that modulates a substrate bias voltage, the substrate bias circuit including a voltage follower transistor that applies a substrate bias voltage to a semiconductor substrate, and an output terminal of the voltage follower transistor Connected through a diode to Comprising a ground resistor value variable.

  According to this configuration, since the resistance value of the ground resistor is variable, the fall time can be easily shortened by reducing the resistance value at the fall of the substrate bias voltage. By shortening the fall time, the same spectral characteristic as that of the normal shutter operation can be realized even during the high-speed shutter operation. As a result, image quality deterioration can be prevented even in a high-speed shutter operation compared to a normal shutter operation.

  Here, the ground resistor includes a first ground resistor and a resistor circuit connected in parallel to the first ground resistor, and the resistor circuit has a smaller resistance than the first ground resistor. A second resistor having a value and a switch connected in series to the second resistor may be provided.

According to this configuration, the ground resistor can be realized with a simple circuit configuration.
Here, the drive unit performs the first bias modulation in the mode in which the exposure period is from the end of the discharge of the charge to the drain by the electronic shutter until the light shielding unit is closed, and at the same time, the resistance of the ground resistor The first bias value is changed from a first resistance value to a second resistance value smaller than the first resistance value, and the first bias modulation changes the substrate bias voltage from the first bias voltage to the first bias voltage immediately after the end of the electronic shutter. Alternatively, the second bias voltage may be changed to a lower voltage.

  According to this configuration, the fall time can be shortened when the first bias voltage is changed to the second bias voltage under the control of the drive unit.

  Here, the drive unit uses the control signal to instruct the first bias modulation in an imaging mode in which imaging is performed with an exposure period from the end of discharge of charge to the drain by the electronic shutter until the light shielding unit is closed. Turn on.

  The first bias modulation may be to change the substrate bias voltage from the first bias voltage to a second bias voltage lower than the first bias voltage immediately after the electronic shutter is finished.

  According to this configuration, since the control signal instructing the first bias modulation is also used for the switch control, an increase in the circuit scale can be suppressed to a minimum only by increasing the second resistor and the switch.

  Here, the drive unit may further change the substrate bias voltage from the second bias voltage to the first bias voltage at the end of the imaging mode, and simultaneously turn off the switch.

  According to this configuration, since the switch is turned off at the end of the imaging mode, the period during which the current flowing through the ground resistor increases can be limited to the period until the end of the imaging mode.

  Here, the first bias voltage is a voltage for setting the height of the overflow barrier to be lower than the barrier in the read gate, and the second bias voltage is the height of the overflow barrier in the barrier at the read gate. The voltage may be set higher than that.

  According to this configuration, since the height of the overflow barrier is set higher than the barrier at the read gate at the second bias voltage, signal charges can be accumulated up to the barrier height of the read gate, and as a result, the photodiode The linear range can be expanded and the sensitivity can be improved.

  Here, the driving unit further performs second bias modulation after the end of the exposure period and before sweeping out the charge of the vertical CCD, and the second bias modulation is configured such that the substrate bias voltage is higher than the second bias voltage. It may be changed to 3 bias voltage.

  Here, the drive unit further performs second bias modulation after the end of the exposure period and before sweeping out the charge of the vertical CCD, and the second bias modulation superimposes a saturation signal control pulse on the second bias voltage. It is also possible to temporarily lower the overflow barrier.

  According to this configuration, signal charges are accumulated up to the barrier height of the read gate by the first bias modulation, and further, excessive signal charges that are almost full of the barrier height of the read gate are discharged to the substrate by the second bias modulation. And the occurrence of blooming can be suppressed.

  In order to achieve the above object, a camera of the present invention includes the above solid-state imaging device.

  As described above, in the substrate bias circuit, the solid-state imaging device, and the camera according to the present invention, the substrate bias voltage fall time can be easily shortened, and the fall time can be shortened so that the low-speed shutter operation can be performed even during the high-speed shutter operation. As in the case of time, fluctuations in spectral characteristics within the accumulation time can be prevented. As a result, it is possible to perform imaging without deterioration in image quality due to a change in color reproducibility even in a high-speed shutter operation.

  It can also be realized with a simple circuit configuration.

  FIG. 1 is a block diagram showing a schematic configuration of a solid-state imaging device according to an embodiment of the present invention. The solid-state imaging device 1 includes a lens 2, a mechanical shutter 3, a driving unit 4, a signal processing unit 5, and a solid-state imaging element 10. In the figure, incident light from a subject (not shown) enters an imaging area of a CCD solid-state imaging device 10 through an optical system such as a lens 2 and a mechanical shutter 3. The mechanical shutter 3 controls incident light to the imaging area of the CCD solid-state imaging device 10. Note that a liquid crystal shutter or the like having a function of shielding light may be provided instead of the mechanical shutter 3.

  FIG. 2 is a circuit diagram showing a schematic configuration of the substrate bias circuit in the solid-state imaging device. The solid-state imaging device 10 shown here has a Vsub terminal that applies a substrate bias voltage to be applied to the semiconductor substrate on which the solid-state imaging device 10 is formed. This substrate bias circuit is connected to an emitter follower transistor Q1 constituting a voltage follower that applies a substrate bias voltage from a Vsub terminal to a semiconductor substrate, and an emitter, which is an output terminal of the emitter follower transistor Q1, via a diode D1. And a variable grounding resistor. The ground resistor includes a first ground resistor R1 and a resistor circuit connected in parallel to the first ground resistor. This resistance circuit includes a second resistor R2 having a resistance value smaller than that of the first ground resistor R1, and a switch SW connected in series to the second resistor R2.

  Here, the above-described switch Sw enables only the first ground resistor of the emitter follower circuit at the time of the first bias voltage, and the first ground resistor and the first ground of the emitter follower circuit at the time of the second bias voltage. The second ground resistor having a resistance value smaller than the resistance value of the ground resistor is made effective, and the first ground resistor and the second ground resistor are configured as a parallel circuit. That is, in the first bias voltage period, which is longer than the second bias voltage period, a large resistance value is used to prevent problems such as a large current flowing through the first ground resistor and an increase in power consumption or heat generation. In order to shorten the fall time when the second bias voltage period is decreased from the first bias voltage to the second bias voltage (during the first bias modulation), the first ground resistor and the second ground resistor are set. The combined resistance value of the body is set to be small.

  The above CCD camera circuit configuration suppresses increase in power consumption and heat generation during the first bias voltage period, and shortens the fall time when the first bias voltage is lowered to the second bias voltage (during the first bias modulation). It is possible.

  The first and second resistors may be R or a semiconductor element ON or OFF resistor as long as current can be suppressed, and the resistance value can be switched by simply switching a single resistor. Alternatively, the resistance value may be switched by a combination of resistors. In FIG. 1, the substrate bias circuit is outside the solid-state imaging device 10, but all or part of it may be inside the solid-state imaging device 10. The transistor circuit element may be a bipolar type, a MOS type, or a junction field effect type.

  FIG. 3 is a circuit diagram showing a more specific example of the substrate bias circuit. In the figure, the switch SW of FIG. 2 is constituted by a switch transistor Q3. The gate of the switch transistor Q3 is controlled by a control signal VsubCont that controls the substrate bias voltage. The control signal VsubCont for controlling the substrate bias voltage is the first bias voltage when the transistor Q2 is turned off, and the lower second bias voltage when the transistor Q2 is turned on. Set to.

  The first grounding resistor R1 may be, for example, 100 k ohms, and the second grounding resistor R2 may be several k ohms (such as 5 k ohms). In this case, the combined resistance of the first grounding resistor R1 and the second grounding resistor R2 is about 5 k ohms.

  FIG. 4 is a time chart showing the relationship between SubCont and the substrate bias voltage. This figure is an enlarged view of a part of the time chart showing the operation timing of the solid-state imaging device shown in FIG. In FIG. 4, SubCont is a control signal for instructing substrate bias modulation, and at the same time, controls on and off of the switch transistor Q3. Specifically, the SubCont signal is the first bias voltage immediately after the end of the electronic shutter in the imaging mode in which the exposure period is from the end of the discharge of the charge to the drain by the electronic shutter until the light shielding means is closed. Is a control signal for instructing to change to a second bias voltage lower than the first bias voltage. Since the switch transistor Q3 is turned on by this signal, the switch transistor Q3 is turned on at the same time when the substrate bias voltage changes from the first bias voltage to the second bias voltage. Conversely, the substrate bias voltage is turned off simultaneously with the change from the second bias voltage to the first bias voltage.

  FIG. 5 is a diagram showing a time chart in the falling section of the substrate bias voltage. The fall time of the substrate bias voltage in the figure depends on the first and second ground resistors R1, R2, the capacitance of the semiconductor substrate itself, etc., but compared with the time chart shown in FIG. It falls in a time sufficiently shorter than the exposure time.

  FIG. 6A is an example showing the arrangement of the photodiodes in the solid-state imaging device 10 and the arrangement of the vertical transfer electrodes of the vertical CCD 13. The arrangement of the photodiodes is a so-called Bayer arrangement. Four types of Φ1 to Φ4 corresponding to the four-phase clock pulses ΦV1 to ΦV4 are repeatedly arranged on the vertical transfer electrode of the vertical CCD 13. Of these, Φ1 and Φ3 also serve as readout gate electrodes for reading out signal charges from the photodiodes on the odd and even lines to the vertical CCD, respectively. In frame readout in the still image capturing mode, after the exposure period, readout of the first field composed of odd lines read from the readout gate electrode Φ1 as shown in FIG. 6B and readout gate electrode Φ3 as shown in FIG. 6C. The second field consisting of the even lines read from is read out sequentially.

  The driving unit 4 includes four-phase clock pulses ΦV1 to ΦV4 that control the transfer of the vertical CCD of the solid-state imaging device 10, two-layer clock pulses ΦH1 and ΦH2 that control the transfer of the horizontal CCD, a substrate bias voltage control signal VsubCont, and a substrate shutter pulse. Φsub and the like are generated and supplied to the solid-state imaging device 10. Among the four-phase clock pulses, ΦV1 and ΦV3 are signals that can take three values of low level, middle level, and high level, and the high level pulse is a read pulse XSG applied to the read gate electrode. The drive unit 4 lowers the substrate bias voltage from the first bias voltage to the second bias voltage at the start of the exposure period in the still image capturing mode, and returns the substrate bias to the first bias voltage after the completion of the second field reading. Modulate.

  Here, the first bias voltage is a substrate bias voltage in the moving image capturing mode with the mechanical shutter 26 open. The second bias voltage is a substrate bias voltage that is lower than the first bias voltage, increases the overflow barrier, and increases the saturation signal charge amount Qs. The barrier height of the overflow barrier OFB by the second bias voltage is set to be higher than the barrier of the read gate.

  FIG. 7 shows a potential distribution diagram of the overflow barrier by the first bias voltage and the second bias voltage. XY on the horizontal axis represents the substrate horizontal direction from the vertical CCD 13 to the photodiode 11 shown in FIG. 8, and YZ represents the substrate depth direction of the photodiode 11 shown in FIG. The vertical axis represents potential. As shown in the figure, the first bias voltage is a voltage that sets the height of the overflow barrier to be lower than the barrier at the read gate. The second bias voltage is a voltage that sets the height of the overflow barrier higher than the barrier at the read gate.

  FIG. 8 is a cross-sectional view showing the structure in the substrate depth direction around the photodiode 11 and the vertical CCD 13. In the figure, for example, a P-type well region 32 is formed on the surface of an N-type substrate 31. An N-type signal charge accumulation region 33 is formed on the surface of the well region 32, and a P + -type hole accumulation region 34 is further formed thereon, so that the photodiode 11 is configured.

  The amount of signal charge e accumulated in the photodiode 11 is determined by the height of the potential barrier of the overflow barrier OFB formed of the P-type well region 32. The overflow barrier OFB determines the saturation signal charge amount Qs accumulated in the photodiode 11. When the accumulated charge amount exceeds the saturation signal charge amount Qs, the excess charge exceeds the potential barrier. Sweeped to the substrate 31 side.

  In this way, a photodiode 11 having a so-called vertical overflow drain structure is formed.

  In the lateral direction of the photodiode 11, an N-type signal charge transfer region 35 and a P + -type channel stopper region 36 are formed via a portion of the P-type region 32 that constitutes the readout gate portion 12. Under the signal charge transfer region 35, a P + type impurity diffusion region 37 is formed for preventing the smear component from being mixed. Further, a transfer electrode 39 made of, for example, polycrystalline silicon is disposed above the signal charge transfer region 35, whereby the vertical CCD 13 is configured. In the transfer electrode 39, the portion located above the P-type region 32 also serves as the gate electrode of the read gate unit 12.

  A substrate bias Vsub that determines the amount of signal charge accumulated in the photodiode 11 (that is, determines the potential of the overflow barrier OFB) is applied to the substrate 17.

(Embodiment 2)
The configuration of the solid-state imaging device according to the present embodiment is almost the same as that of the first embodiment, except that the drive unit 4 performs the second bias modulation as the substrate bias modulation. Explanation of the same points is omitted, and different points will be mainly described below.

  FIG. 9 is a time chart showing the operation timing of the solid-state imaging device according to the second embodiment. As shown in the figure, the drive unit 4 performs the second bias modulation after the exposure period ends and before the charge discharge of the vertical CCD. Here, the second bias modulation is to temporarily lower the overflow barrier by superimposing a saturation signal control pulse on the second bias voltage. As a result, the signal charge can be accumulated up to the barrier height of the read gate by the first bias modulation, and further, the excessive signal charge that is almost full of the barrier height of the read gate can be discharged to the substrate by the second bias modulation. . In addition, the occurrence of blooming can be suppressed.

(Embodiment 3)
The configuration of the solid-state imaging device according to the present embodiment is substantially the same as that of the second embodiment, except that the drive unit 4 performs another second bias modulation as the substrate bias modulation. Explanation of the same points is omitted, and different points will be mainly described below. The second bias modulation in the present embodiment is to change the substrate bias voltage to a third bias voltage higher than the second bias voltage.

  FIG. 10 is a time chart showing the operation timing of the solid-state imaging device according to the second embodiment. As shown in the figure, the drive unit 4 performs the second bias modulation after the exposure period ends and before the charge discharge of the vertical CCD. Here, the second bias modulation is to change the substrate bias voltage to a third bias voltage higher than the second bias voltage. Accordingly, the signal charge can be accumulated up to the barrier height of the read gate by the first bias modulation, and further, the excessive signal charge can be discharged to the substrate by the second bias modulation. The occurrence of blooming can be suppressed.

  The present invention is suitable for a CCD image sensor formed on a semiconductor substrate, a digital still camera, a camera-equipped mobile phone, a camera built in a notebook computer, a camera unit connected to an information processing device, and the like.

1 is a block diagram illustrating a schematic configuration of a solid-state imaging device according to Embodiment 1. FIG. It is a circuit diagram which shows schematic structure of a substrate bias circuit. It is a circuit diagram which shows the specific example of a substrate bias circuit. 5 is a time chart showing the relationship between Sub Cont and substrate bias voltage. It is a figure which shows the time chart in the fall area of a substrate bias voltage. It is an example which shows the arrangement | sequence of the photodiode in a solid-state image sensor, and the arrangement | sequence of the transfer electrode of a vertical CCD. It is explanatory drawing of the read-out of the 1st field which consists of an odd number line. It is explanatory drawing of the reading of the 2nd field which consists of an even number line. FIG. 7 is a potential distribution diagram when a first bias voltage and a second bias voltage are applied. It is sectional drawing which shows the structure of the substrate depth direction around a photodiode and vertical CCD. 6 is a time chart illustrating the operation timing of the solid-state imaging device according to Embodiment 2. 12 is a time chart illustrating operation timings of the solid-state imaging device according to Embodiment 3. It is a block diagram which shows the structure of the solid-state image sensor (CCD) in a prior art. It is a figure which shows the potential distribution of the substrate depth direction of a photodiode. It is a time chart which shows the operation timing of the solid-state imaging device in an embodiment. It is a figure which shows the time chart in the fall area of a substrate bias voltage. It is a figure which shows the spectral characteristics in a 1st bias voltage. It is a figure which shows the spectral characteristics in a 2nd bias voltage. It is a figure which shows the mode of the change of the overflow barrier in the fall area of a substrate bias voltage.

Explanation of symbols

1 Solid-state imaging device 1
2 Lens 3 Mechanical shutter 3
4 Drive unit 4
5 Signal processor 5
10 Solid-state image sensor 10
20 Substrate bias generation circuit 20
Q1 Emitter-follower transistor Q1
Q2 Switch transistor Q2
Q3 Switch transistor Q3
D1 Diode D1
C Capacitor C
R1 first grounding resistor R1
R2 Second ground resistance R2
SW switch SW
R3 resistance R3
R4 resistance R4

Claims (3)

A solid-state image sensor having an electronic shutter function that discharges the charge accumulated in the photodiode to the drain by adopting an overflow drain structure that discharges excess charge generated in the photodiode to the drain, and a light shielding for controlling the incidence of light on the photodiode Means, a substrate bias circuit for applying a substrate bias voltage defining the height of the overflow barrier in the overflow drain structure to the semiconductor substrate on which the solid-state imaging device is formed, and a drive unit for modulating the substrate bias voltage. A solid-state imaging device,
The substrate bias circuit includes:
A voltage follower transistor for applying the substrate bias voltage to the semiconductor substrate;
A variable resistance ground resistor connected to the output terminal of the voltage follower transistor via a diode ;
The drive unit performs the first bias modulation and simultaneously sets the resistance value of the ground resistor in the mode in which the exposure period is from the end of the discharge of the charge to the drain by the electronic shutter until the light shielding unit is closed. The resistance value of 1 is changed to a second resistance value smaller than the first resistance value,
Wherein the first bias modulation state, and it is changing the substrate bias voltage from the first bias voltage immediately after the electronic shutter ended second bias voltage lower voltage than the first bias voltage,
The first bias voltage is a voltage that sets the height of the overflow barrier lower than the barrier in the read gate,
The second bias voltage is a voltage for setting the height of the overflow barrier higher than the barrier in the read gate,
The driving unit further performs second bias modulation after the end of the exposure period and before the charge discharge of the vertical CCD,
The second bias modulation is to change the substrate bias voltage to a third bias voltage that is higher than the second bias voltage, and to discharge the excessive signal charge to the semiconductor substrate just as high as the read gate barrier height. A solid-state imaging device. A solid-state image sensor having an electronic shutter function that discharges the charge accumulated in the photodiode to the drain by adopting an overflow drain structure that discharges excess charge generated in the photodiode to the drain, and a light shielding for controlling the incidence of light on the photodiode Means, a substrate bias circuit for applying a substrate bias voltage defining the height of the overflow barrier in the overflow drain structure to the semiconductor substrate on which the solid-state imaging device is formed, and a drive unit for modulating the substrate bias voltage. A solid-state imaging device,
The substrate bias circuit includes:
A voltage follower transistor for applying the substrate bias voltage to the semiconductor substrate;
A variable resistance ground resistor connected to the output terminal of the voltage follower transistor via a diode;
The drive unit performs the first bias modulation and simultaneously sets the resistance value of the ground resistor in the mode in which the exposure period is from the end of the discharge of the charge to the drain by the electronic shutter until the light shielding unit is closed. The resistance value of 1 is changed to a second resistance value smaller than the first resistance value,
Wherein the first bias modulation state, and it is changing the substrate bias voltage from the first bias voltage immediately after the electronic shutter ended second bias voltage lower voltage than the first bias voltage,
The first bias voltage is a voltage that sets the height of the overflow barrier lower than the barrier in the read gate,
The second bias voltage is a voltage for setting the height of the overflow barrier higher than the barrier in the read gate,
The driving unit further performs second bias modulation after the end of the exposure period and before the charge discharge of the vertical CCD,
The second bias modulation is to temporarily lower the overflow barrier by superimposing a saturation signal control pulse on the second bias voltage, and an excessive signal charge just below the height of the read gate barrier is applied to the substrate. Drain
A solid-state imaging device. A camera comprising the solid-state imaging device according to claim 1 .

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