JP2012120106A - Solid-state imaging device and imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that image quality deterioration due to noise, such as white lines in darkness, in a first driving mode is caused when the amount of charge handled in a second driving mode is secured.SOLUTION: By a mechanism which selectively adjusts conversion efficiency and an output circuit gain in the first driving mode and the second driving mode by using a substrate bias adjustment unit for adjusting the amount of saturation signals of pixel parts, the conversion efficiency and the output circuit gain are set lower in the first driving mode, and the conversion efficiency and the output circuit gain are set higher in the second driving mode.

Description

  The present invention relates to a solid-state imaging device and an imaging apparatus.

  2. Description of the Related Art In recent years, imaging apparatuses that can capture and store an image using an imaging element, such as a digital still camera and a digital video camera, have been widely used. As an image pickup element used in such an image pickup apparatus, a CCD type solid-state image pickup element or a CMOS type solid-state image pickup element made of a semiconductor is used.

  A CCD type solid-state imaging device includes a plurality of pixel units (photoelectric conversion units) arranged in a two-dimensional array on a semiconductor substrate, and a plurality of pixel units adjacent to each other via a readout gate region. And a vertical transfer unit. A horizontal transfer unit adjacent to one end of the vertical transfer unit is provided, and the signal charge photoelectrically converted in each pixel unit by light reception is transferred by the vertical transfer unit and the horizontal transfer unit.

  An output portion having a floating diffusion portion (hereinafter referred to as “FD portion”) is provided at the end portion of the horizontal transfer portion. The FD unit is configured to be able to output a voltage corresponding to the signal charge transferred from the horizontal transfer unit, and outputs the signal charge accumulated in each pixel unit as an image signal from the output unit.

  In an imaging device such as a video camera having a CCD type solid-state imaging device having the above-described configuration, a multi-pixel addition that adds and transfers signal charges of a plurality of pixel units adjacent in the column direction in a vertical transfer unit Some have drive modes.

  In such a solid-state imaging device, miniaturization of the pixel size of the pixel portion is required for the purpose of miniaturization of the device and increase in the number of pixels in the pixel portion, and the area of the vertical transfer portion is reduced with the miniaturization of the pixel size. It has become. Therefore, in the multiple pixel addition drive mode, a sufficient amount of signal charge to be transferred may not be ensured, resulting in a transfer failure. Thereby, the output of the image signal output from the output unit may be reduced.

  In view of this, a technique has been proposed in which the reduction in the output of the image signal is suppressed by increasing the charge-voltage conversion efficiency in the FD section and the output circuit gain in the output circuit and amplifying the output of the image signal. However, when the charge-voltage conversion efficiency and the output circuit gain are increased, noise is amplified together with the output of the image signal. For this reason, at the time of low illuminance, noise such as a white line in the dark is excessively amplified, and there is a problem that the image quality deteriorates.

  As a technique for solving such a problem, Patent Document 1 discloses a technique for switching charge-voltage conversion efficiency by system control from a drive system independent of a solid-state imaging device.

Japanese Patent Laid-Open No. 11-331706

  However, in the technique described in Patent Document 1 described above, conversion efficiency is switched by system control from a drive system that is independent of the solid-state imaging device, which increases the number of components and increases costs.

  The present invention has been made in view of the above problems, and an object of the present invention is to use a substrate bias adjustment unit that adjusts a saturation signal amount of a pixel unit, and converts conversion efficiency for each drive mode of a vertical transfer unit. It is another object of the present invention to provide a solid-state imaging device and an imaging apparatus that can easily switch output circuit gain without increasing the number of components.

  Therefore, according to the present invention, a plurality of pixel portions arranged in a matrix and performing photoelectric conversion on a semiconductor substrate, and a vertical transfer for vertically transferring signal charges read from the plurality of pixel portions. A transfer unit; a horizontal transfer unit that horizontally transfers the signal charge transferred from the vertical transfer unit; a charge-voltage conversion unit that converts the signal charge transferred from the horizontal transfer unit into a charge voltage; and the charge-voltage conversion unit An output unit having an output circuit that amplifies the signal voltage converted by step (b), and a substrate bias generation circuit that controls a substrate bias voltage applied to the semiconductor substrate in order to adjust a saturation signal amount of the pixel unit. Then, the substrate bias voltage controlled by the substrate bias generation circuit is applied to a region under the charge voltage conversion unit, and conversion efficiency by the charge voltage unit or by the output circuit To a solid state imaging device for adjusting the amplification factor of the serial signal voltage.

  According to a second aspect of the present invention, in the solid-state imaging device according to the first aspect, the vertical transfer unit first vertically transfers signal charges read from the plurality of pixel units. Select a driving mode and a second driving mode in which signal charges of only pixels of a predetermined repeating unit are read from the pixel unit, and then the signal charges for a plurality of pixels are added and transferred in the vertical transfer unit. The substrate bias generation circuit adjusts the conversion efficiency or the amplification factor for each of the drive modes.

  According to a third aspect of the present invention, in the solid-state imaging device according to the second aspect, the substrate bias generation circuit is configured to change the conversion efficiency or the amplification factor in the second drive mode to the first The adjustment was made to be higher than the conversion efficiency or the amplification factor in the drive mode.

  According to a fourth aspect of the present invention, in the solid-state imaging device according to the second aspect, the substrate bias generation circuit is configured to set the conversion efficiency or the amplification factor in the first drive mode as the second efficiency. The adjustment was made to be higher than the conversion efficiency or the amplification factor in the drive mode.

  According to a fifth aspect of the present invention, in the solid-state imaging device according to the first aspect, the substrate bias generation circuit adjusts the conversion efficiency by changing a capacitance of the charge-voltage conversion unit. It was decided.

  According to a sixth aspect of the present invention, in the solid-state imaging device according to the first aspect, the output unit is formed so that the substrate bias voltage is applied. The amplification factor is adjusted by changing the substrate bias voltage in the output circuit.

  According to a seventh aspect of the present invention, in the solid-state imaging device according to the first aspect, the output circuit includes a plurality of stages of source follower circuits, and the substrate bias control means includes the plurality of stages of sources. The amplification factor was adjusted by switching the number of stages of the follower circuit.

  The present invention according to claim 8 is a solid-state imaging device, an optical system that forms a subject image on the solid-state imaging device, a driving unit that generates a driving pulse for driving the solid-state imaging device, and the solid-state imaging device. A signal processing circuit that processes an output image signal of the image sensor, wherein the solid-state image sensor is arranged in a matrix on a semiconductor substrate and performs photoelectric conversion, and the plurality of pixel units. A vertical transfer unit that vertically transfers the read signal charges, a horizontal transfer unit that horizontally transfers the signal charges transferred from the vertical transfer unit, and a charge-voltage conversion of the signal charges transferred from the horizontal transfer unit And an output unit having an output circuit for amplifying the signal voltage converted by the charge voltage conversion unit, and a substrate via applied to the semiconductor substrate in order to adjust a saturation signal amount of the pixel unit A substrate bias generation circuit for controlling a voltage, and the substrate bias generation circuit controlled by the substrate bias generation circuit is applied to a region under the charge voltage conversion unit so that the conversion efficiency by the charge voltage unit or the output is applied. The imaging device adjusts the amplification factor of the signal voltage by the circuit.

  According to the present invention, the substrate bias generation circuit applies the controlled substrate bias voltage to the region under the charge voltage conversion unit so as to adjust the conversion efficiency by the charge voltage unit or the amplification factor of the signal voltage by the output circuit. Therefore, for example, the conversion efficiency and the amplification factor of the signal voltage can be adjusted for each drive mode of the solid-state imaging device.

  Accordingly, for example, in the first drive mode in which the signal charges read from the plurality of pixel units are independently vertically transferred, the conversion efficiency and the amplification factor of the signal voltage are adjusted to be reduced from the pixel unit. In the second driving mode in which the signal charges of only the repetitive unit pixels are read and then the signal charges for a plurality of pixels are added and transferred in the vertical transfer unit, the conversion efficiency and the amplification factor of the signal voltage are increased. Can be adjusted. Accordingly, since the second drive mode in which the conversion efficiency and the output circuit gain are set high and the first drive mode in which the conversion efficiency and the output circuit gain are set low can be compatible, the second drive mode has high sensitivity characteristics. While the output can be realized, in the first drive mode, it is possible to prevent image quality deterioration particularly in the dark without excessively amplifying the signal output.

It is a figure showing the plane composition of the solid-state image sensing device concerning a 1st embodiment. It is a figure which shows the structure of the FD part and output circuit of the solid-state image sensor which concerns on 1st Embodiment. It is a figure which shows the structure of the substrate bias generation circuit of the solid-state image sensor which concerns on 1st Embodiment. It is a figure which shows the structure of a general substrate bias generation circuit. It is a figure which shows the structure of the horizontal transfer part and output part of a general solid-state image sensor. It is a figure which shows the block configuration of the imaging device which concerns on 1st Embodiment. It is a figure which shows the structure of FD part of the solid-state image sensor which concerns on the modification 1, and an output circuit. It is a figure which shows the structure of FD part and output circuit of the solid-state image sensor which concerns on 2nd Embodiment. It is a figure which shows the structure of the substrate bias generation circuit of the solid-state image sensor which concerns on 2nd Embodiment. It is a figure which shows the structure of FD part of the solid-state image sensor which concerns on the modification 1, and an output circuit. It is a figure which shows the structure of the FD part and output circuit of the solid-state image sensor which concerns on 3rd Embodiment. It is a figure which shows the structure of FD part of the solid-state image sensor which concerns on the modification 3, and an output circuit. It is a figure which shows the structure of FD part and output circuit of the solid-state image sensor which concerns on 4th Embodiment. It is a figure which shows the structure of FD part of the solid-state image sensor which concerns on the modification 4, and an output circuit.

The best mode for carrying out the invention (hereinafter referred to as an embodiment) will be described below. The description will be given in the following order.
1. 1. Configuration of solid-state imaging device and imaging apparatus according to first embodiment 2. Configuration of solid-state imaging device in the second embodiment 3. Configuration of solid-state image sensor in the third embodiment Configuration of Solid-State Image Sensor in Fourth Embodiment

[1. First Embodiment]
[1.1. Overall configuration of solid-state image sensor]
First, the configuration of the solid-state imaging device of the first embodiment will be described with reference to the drawings. FIG. 1 is a diagram illustrating a planar configuration of the solid-state imaging device according to the first embodiment.

  As shown in FIG. 1, the solid-state imaging device 1 includes an imaging region 20, a horizontal transfer unit 30, an output unit 40, and a substrate bias generation circuit 50, which are formed on the semiconductor substrate 10. The Hereinafter, each part will be sequentially described.

  In the imaging region 20, a plurality of pixel portions 21, readout gate portions 22, vertical transfer portions 23, and element isolation regions 24 are formed.

  A plurality of pixel units 21 are provided in the imaging region 20 and are two-dimensionally arranged in a matrix in the horizontal direction X and the vertical direction Y. In the present embodiment, the pixel unit 21 includes, for example, a photodiode, receives light from the subject image, photoelectrically converts it into signal charges, and accumulates the signal charges.

  The read gate unit 22 is arranged between the pixel unit 21 and the vertical transfer unit 23, and reads the signal charges accumulated in the pixel unit 21 to the vertical transfer unit 23.

  The vertical transfer unit 23 is provided corresponding to each column of the plurality of pixel units 21 arranged in a matrix, and sequentially transfers signal charges read from the plurality of pixel units 21 arranged in the same column in the vertical direction Y. To do. In the present embodiment, the vertical transfer unit 23 is driven by receiving, for example, four-phase drive pulses φV1, φV2, φV3, and φV4 from the outside. The vertical transfer unit 23 is a first drive mode in which signal charges read from the plurality of pixel units 21 are independently vertically transferred in accordance with a drive pulse applied from the outside (for example, a timing generator described later). Alternatively, the signal charges can be transferred in the second drive mode in which the signal charges of only pixels of a predetermined repeating unit are read from the pixel unit 21 and then added and transferred in the vertical transfer unit 23. It is formed as follows. Note that the drive pulse is not limited to the case of four phases.

  The element isolation region 24 is provided adjacent to each pixel portion 21 and prevents signal charges from moving from each pixel portion 21 to adjacent elements. This element isolation region 24 is connected to GND outside the imaging region 20.

  The horizontal transfer unit 30 is arranged at the end of the imaging region 20 in the vertical direction Y, that is, at the end of each vertical transfer unit 23. The horizontal transfer unit 30 is driven by, for example, two-phase drive pulses φH1 and φH2 being input from the outside. As a result, the horizontal transfer unit 30 transfers the signal charges transferred in the vertical direction Y in each of the vertical transfer units 23 in the horizontal direction X.

  The output unit 40 is disposed at the end of the horizontal transfer unit 30 in the horizontal direction X. The output unit 40 includes, for example, a charge-voltage conversion unit configured by the FD unit 41, converts the signal charge horizontally transferred by the horizontal transfer unit 30 into an electric signal, and outputs the signal as an analog image signal. The FD unit 41 corresponds to a specific example of the “charge voltage conversion unit” of the present invention.

  More specifically, the horizontal transfer unit 30 and the output unit 40 have a configuration as shown in FIG. That is, the P-type well region 12 is formed on the N-type subregion 11 in the semiconductor substrate 10. The P-type well region 12 constitutes an overflow barrier (OFB) that determines the saturation signal amount Qs accumulated in the pixel unit 21.

In the horizontal transfer portion 30 on the surface of the semiconductor substrate 10, an N-type channel region 13 is formed, and an N ⁻ -type transfer (TR) region 14 is formed on the surface portion of the N-type channel region 13 in the horizontal direction of the drawing. A channel region between the TR regions 14 is a storage (ST) region 15 formed at a constant pitch. Further, a horizontal transfer electrode H1 made of polysilicon is formed above the ST region 15 and a horizontal transfer electrode H2 made of polysilicon is formed above the TR region 14 via an insulating film (not shown). . In the horizontal transfer unit 30 having such a configuration, adjacent horizontal transfer electrodes H1 and H2 form a pair, and two-phase drive pulses φH1 and φH2 are alternately applied to the electrode pair (H1, H2) in the arrangement direction. Thus, horizontal transfer of two-phase driving is realized.

  Further, a horizontal transfer output gate 31 made of polysilicon is formed at the final stage of the horizontal transfer unit 30, and the HOG 31 is connected to the ground potential GND. The HOG 31 constitutes a horizontal transfer output gate (hereinafter referred to as “HOG”) 31 together with the underlying N-type channel region 13.

HOG31 FD portion 41 of the ^{N +} type is formed adjacent to, next to sandwich the channel region 46 ^{N +} -type reset drain portion of the FD portion 41 (hereinafter, referred to as "RD unit") 43 is formed Yes. Further, a reset gate portion (hereinafter referred to as “RG portion”) 42 is formed above the channel region 46 via an insulating film (not shown).

  The FD unit 41 is connected to an output circuit 44 formed of a source follower circuit, and the RD unit 43 is applied with a constant drain voltage φVrd. If the amount of change in the signal charge of the FD unit 41 is ΔQ and the capacitance of the FD unit 41 is C, the voltage change ΔV output from the output circuit 44 can be expressed as ΔV = ΔQ / C.

  In the output unit 40 having such a configuration, by applying a drive pulse to the transfer electrodes (H1, H2, LH) on the horizontal transfer unit 30, the signal charges transferred to the horizontal transfer unit 30 are transferred to the FD unit 41, The signal charge transferred to the FD unit 41 is converted into a signal voltage corresponding to the amount of charge. The signal voltage is amplified by the output circuit 44. Is output.

  After the signal voltage is converted by the FD unit 41, a reset gate pulse φRG is applied to the reset gate terminal 45, and the signal charge accumulated in the FD unit 41 is swept away by the RD unit 43.

  Further, in the output unit 40 in the solid-state imaging device 1, the first P-type well region 17 and the first N-type well region 16 are formed between the FD unit 41 and the P-type well region 12. The first P-type well region 17 and the first N-type well region 16 are formed independently of the P-type well region 12 or the N-type subregion 11, respectively. That is, the first N-type well region 16 is formed such that a voltage φN1 different from the substrate bias voltage φVsub is applied via the contact region 16a. The first P-type well region 17 is formed to be grounded to GND through the contact region 12a. The application of the voltage φN1 is generated by the substrate bias generation circuit 50 of the solid-state imaging device.

  As shown in FIG. 3, the substrate bias generating circuit 50 mainly includes an emitter follower circuit 51, a substrate bias adjusting unit 52, and a resistance dividing circuit 53, and includes an overflow barrier (P type well region 12). OFB) generates a substrate bias voltage φVsub that determines the height of the potential barrier. The substrate bias generation circuit 50 also generates a voltage φN1 applied to the first N-type well region 16.

  The emitter follower circuit 51 includes resistors R1 and R2, a transistor Tr1, and a capacitor C1. The resistor R1 has one end connected to the power supply voltage Vdd and the other end connected to the collector of the transistor Tr1. The transistor Tr1 has an emitter connected to the substrate bias output terminal Vsub and a base connected to an input terminal to which a reference voltage is applied. Further, one end of the resistor R2 and one end of the capacitor C1 are connected in parallel to the substrate bias output terminal Vsub, and the other end of the resistor R2 and the other end of the capacitor C1 are grounded to GND.

  The substrate bias adjustment unit 52 is a circuit that adjusts the value of the substrate bias voltage φVsub generated by the emitter follower circuit 51. The substrate bias adjusting unit 52 includes a first switch element including resistors R3 and R4 and a transistor Tr2, and a second switch element including resistors R5 and R6 and a transistor Tr3. Any one of the switch elements is operated.

  In the first switch element, one end of the resistor R3 is connected to the collector of the transistor Tr2, and the emitter of the transistor Tr2 is grounded to GND. The base of the transistor Tr2 is connected to the external terminal via the resistor R4. In the first switch element having such a configuration, the transistor Tr2 is turned on by applying a predetermined voltage to the external terminal. As a result, since a current flows through the resistor R3 and the transistor Tr2, the first switch element functions as a resistor element having a predetermined resistance value.

  In the second switch element, one end of the resistor R5 is connected to the collector of the transistor Tr3, and the emitter of the transistor Tr3 is grounded to GND. The base of the transistor Tr3 is connected to the external terminal via the resistor R6. In the second switch element having such a configuration, the transistor Tr3 is turned on by applying a predetermined voltage to the external terminal. Thereby, current flows through the resistor R4 and the transistor Tr3, so that the first switch element functions as a resistor element having a predetermined resistance value.

  The resistance dividing circuit 53 is configured by resistors R7, R8, and R9 connected in series between the power supply voltage Vdd and GND. An output terminal of the substrate bias adjusting unit 52 is connected between the resistors R8 and R9, and an output terminal is connected between the resistors R7 and R8. In the resistance dividing circuit 53 having such a configuration, a voltage φN1 corresponding to the input voltage generated by the substrate bias adjusting unit 52 is generated.

  In the resistance dividing circuit 53, the resistance value of the resistor R3 is made smaller than the resistance value of the resistor R5. Accordingly, the saturation amount of the signal charge stored in the pixel unit 21 is increased by operating the first switch element, and the saturation amount of the signal charge stored in the pixel unit 21 is decreased by operating the second switch element. ing.

  The substrate bias generation circuit 50 generates the substrate bias voltage φVsub and the voltage φN1 applied to the first N-type well region 16 as described above. This voltage φN1 is formed such that the voltage value can be changed, like the substrate bias voltage φVsub described above. That is, the voltage φN1 can be increased by operating the first switch element of the substrate bias adjusting unit 52, and the voltage φN1 can be decreased by operating the second switch element.

  In the solid-state imaging device 1 having the above-described configuration, the first N-type well region 16 and the first P-type well region 17 are formed in the semiconductor substrate 10 in the output unit 40, and a resistance for applying a voltage to the first N-type well region 16 is formed. Since the dividing circuit 53 is formed in the substrate bias generating circuit 50, the conversion efficiency η of the FD unit 41 can be changed.

Here, the principle of the conversion efficiency η will be described.
Total capacitance C _FD and charge-voltage conversion efficiency (hereinafter simply referred to as “conversion efficiency”) η relating to the FD portion are expressed by the following equations (1) and (2).
C _FD = C _j + C _H + C _R + C _D + (1-g) C _S (1)
η = q / C _FD * G [μV / e] (2)
However,
C _j : Junction capacitance between the FD portion and the first N-type well region (or N-type subregion) C _H : Capacitance between the FD portion and HOG C _R : between the FD portion and RG Capacitance between C _D : Capacitance between the drain region and the gate electrode of the output element C _S : Capacitance between the source region of the output element and the gate electrode g: Gain of the source follower circuit at the first stage of the output circuit q: Charge amount of one electron G: Gain of the entire output circuit

By controlling the reverse bias voltage between the FD portion 41 and the first N-type well region 16, the width of the depletion layer can be controlled. Thereby, the conversion efficiency η of the FD unit 41 can be controlled. That is, by controlling the junction capacitance C _j between the FD portion 41 and the first N-type well region 16 (or N-type subregion 11), the total capacitance C _FD related to the FD portion 41 is controlled. As a result, the conversion efficiency η is controlled.

  Thus, in the solid-state imaging device of the present embodiment, by providing the output unit 40a and the substrate bias generation circuit 50a, the potential of the first N-type well region 16 can be adjusted independently. Thereby, the conversion efficiency η of the FD portion 41 can be controlled in accordance with the potential of the first N-type well region 16.

For example, in the second drive mode in which the signal charges of only pixels of a predetermined repeating unit are read from the pixel unit 21 and then transferred by adding the signal charges for a plurality of pixels in the vertical transfer unit 23, the second switch element By turning on, the value of the voltage φN1 can be increased compared to the first drive mode in which the signal charges read from the plurality of pixel portions are independently vertically transferred, and the FD portion 41 and the first N-type well The reverse bias voltage between the region 16 can be increased. Accordingly, the width of the depletion layer becomes wider, the capacitance C _j between the FD portion 41 and the first N-type well region 16 can be reduced, and the conversion efficiency η can be increased with respect to the first drive mode. .

On the other hand, in the first drive mode, by turning on the first switch element, the value of the voltage φN1 can be made lower than in the second drive mode, and the depletion layer width can be narrowed. Therefore, the capacitance C _j between the FD portion 41 and the first N-type well region 16 can be increased, and the conversion efficiency η can be lowered compared to the second drive mode.

  As described above, in the solid-state imaging device 1 of the present embodiment, by using the existing substrate bias generation circuit 50, switching of the conversion efficiency η for each drive mode can be easily realized without increasing the number of components. Become.

  In contrast to the solid-state imaging device 1 according to the present embodiment, the output unit 40 does not include the first N-type well region 16 and the first P-type well region 17, and the substrate bias generation circuit 50 includes the resistance dividing circuit 53. In a solid-state imaging device that is not provided (see FIGS. 4 and 5), the potential of the region under the FD unit 41 cannot be controlled independently. Therefore, the conversion efficiency η cannot be switched for each drive mode.

  In the solid-state imaging device according to the present embodiment, the value of the voltage φN1 is adjusted by the substrate bias adjustment unit 52 provided in the substrate bias generation circuit 50, but the adjustment of the value of the voltage φN1 is not limited to this method. For example, as shown in FIG. 6, the value of the voltage φN1 may be adjusted by a reference voltage generation circuit 60 provided in the solid-state imaging device and a voltage value switching unit provided outside the solid-state imaging device.

[1.4. Configuration of Imaging Device in First Embodiment]
(Overall configuration of imaging device)
Hereinafter, an imaging apparatus including the solid-state imaging device 1 configured as described above will be described. FIG. 7 is a diagram illustrating a configuration of an image pickup apparatus including the solid-state image pickup device 1.

  As shown in FIG. 7, the imaging device 90 includes an optical block 91, a solid-state imaging device 1, an A / D (analog / digital) conversion circuit 92, a signal processing circuit 93, a system controller 94 that is a control unit, and an input unit 95. It has. Further, the imaging device 90 is provided with a driver 96 for driving a mechanism in the optical block 91, a timing generator (hereinafter referred to as “TG”) 97 for generating a driving pulse for driving the solid-state imaging device 1, and the like. .

  The optical block 91 includes a lens for condensing light from the subject onto the solid-state imaging device 1, a driving mechanism for moving the lens to perform focusing and zooming, a mechanical shutter, a diaphragm, and the like. The driver 96 controls driving of the mechanism in the optical block 91 in accordance with a control signal from the system controller 94.

  The solid-state imaging device 1 is driven based on drive pulses (φV1, φV2, φV3, φV4, φH1, φH2, etc.) generated by the TG 97, and converts incident light from a subject into an electrical signal. The TG 97 generates drive pulses under the control of the system controller 94.

  The A / D conversion circuit 92 A / D converts the image signal output from the solid-state imaging device 1 and outputs a digital image signal.

The signal processing circuit 93 performs AF (Auto) on the digital image signal from the A / D conversion circuit 92.
Various camera signal processes such as Focus), AE (Auto Exposure), and defective pixel interpolation are executed.

  The system controller 94 includes, for example, a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and the like. The CPU executes a program stored in a ROM or the like, thereby controlling each part of the image pickup apparatus in an integrated manner and executing various calculations for the control. The input unit 95 includes operation keys, dials, levers, and the like that accept user operation inputs, and outputs a control signal corresponding to the operation inputs to the system controller 94.

  In this imaging apparatus 90, image signals corresponding to the signal charges received by the solid-state imaging device 1 and subjected to photoelectric conversion are sequentially supplied to the A / D conversion circuit 92 and converted into digital signals, and the image processing circuit 93 performs image quality. The correction processing is performed, and finally the luminance signal and the color difference signal are converted and output. The image data output from the signal processing circuit 93 is supplied to a graphic interface circuit (not shown) and converted into a display image signal, whereby a camera-through image is displayed on a monitor (not shown).

[2. Second Embodiment]
Next, a solid-state imaging device according to the second embodiment will be described with reference to FIGS. Note that components other than the output unit 40b and the substrate bias generation circuit 50b, which are characteristic configurations of the present embodiment, are denoted by the same reference numerals for configurations common to the above-described general solid-state imaging device. Omitted.

  As shown in FIG. 8, in the output unit 40b of the solid-state imaging device according to the present embodiment, the second P-type well region independent of the P-type well region 12 is located at a position in the depth direction of the semiconductor substrate with respect to the FD unit 41. 18 is formed. The second P-type well region 18 is formed so that the voltage φP2 is applied via the contact region 18a. The application of the voltage φN1 is generated by the substrate bias generation circuit 50b of the solid-state imaging device according to the present embodiment.

  That is, as shown in FIG. 9, the substrate bias generation circuit 50 b of the solid-state imaging device according to the present embodiment includes a resistance dividing circuit 54 connected in series with the substrate bias adjustment unit 52. The resistance dividing circuit 54 includes a resistor R10 and a transistor Tr4 connected in series between GND and the voltage VL.

  One end of the resistor R10 is connected to GND, and the other end of the resistor R10 is connected to the drain of the transistor Tr4. The source of the transistor Tr4 is connected to the voltage VL, and the output terminal is connected between the resistors R7 and R8. In the resistance dividing circuit 53 having such a configuration, a voltage φP2 corresponding to the input voltage generated by the substrate bias adjustment unit 52 is generated.

  In the substrate bias generation circuit 50b according to the present embodiment, the substrate bias voltage φVsub and the voltage φP2 are generated. Further, the voltage φP2 generated by the substrate bias generating circuit 50b is formed such that the voltage value can be changed, similarly to the substrate bias voltage φVsub described above. That is, the voltage φP2 can be increased by turning on the first switch element of the substrate bias adjusting unit 52, and the voltage φP2 can be lowered by turning on the second switch element.

As described above, in the solid-state imaging device of the present embodiment, the second P-type well region is formed at a position in the substrate depth direction with respect to the FD portion 41, and the potential control of the second P-type well region is performed. Therefore, by making the second P-type well region neutral, capacitance is added and the conversion efficiency η can be reduced. That is, by controlling the junction capacitance C _j between the FD portion 41 and the N-type well region or the N-type sub-region 11, the total capacitance C _FD related to the FD portion 41 is controlled and converted as a result. The efficiency η can be controlled.

  For example, in the second drive mode, by operating the second switch element, the transistor Tr4 is turned off, the voltage φP2 applied to the second P-type well region 18 is set to a negative value, and the second P-type well region 18 is set to the neutral state. Then, the amplification factor of the output circuit (hereinafter referred to as “output circuit gain”) decreases due to the substrate bias effect. As a result, the capacitance of the FD unit 41 decreases and the conversion efficiency η increases.

  On the other hand, in the first drive mode, by operating the first switch element, the transistor is turned on to apply a negative bias to the FD portion 41 in order to make the second P-type well region neutral. As a result, the capacitance of the FD unit 41 increases and the conversion efficiency η decreases.

  As described above, in the solid-state imaging device of the present embodiment, by using the existing substrate bias generation circuit 50, switching of the conversion efficiency η for each drive mode can be easily realized without increasing the number of components. .

  In the solid-state imaging device according to the present embodiment, the value of the voltage φP2 is adjusted by the substrate bias adjusting unit 52 included in the substrate bias generating circuit 50, but the adjustment of the value of the voltage φP2 is not limited to this method. For example, as shown in FIG. 10, the value of the voltage φP2 may be adjusted by a reference voltage generation circuit 60 provided in the solid-state imaging device and a voltage value switching unit provided outside the solid-state imaging device.

[3. Third Embodiment]
Next, a solid-state imaging device according to a third embodiment will be described with reference to FIG. Note that components other than the output unit 40c and the substrate bias generation circuit 50c, which are characteristic configurations of the present embodiment, are given the same reference numerals for configurations common to the above-described general solid-state imaging device. Omitted.

  As shown in FIG. 11, the substrate bias generating circuit 50 c of the solid-state imaging device according to the present embodiment includes a resistance dividing circuit 55 connected in series with the substrate bias adjusting unit 52. The resistance dividing circuit 55 includes a resistor R11 and a transistor Tr5 connected in series between the power supply voltage Vdd and the reference voltage Vss.

  One end of the resistor R11 is connected to the power supply voltage Vdd, and the other end of the resistor R11 is connected to the drain of the transistor Tr5. The source of the transistor Tr5 is connected to the voltage VL. In the resistance dividing circuit 55 having such a configuration, a voltage corresponding to the input voltage generated by the substrate bias adjusting unit 52 is generated.

  In the substrate bias generating circuit 50c according to this embodiment, the voltage φP2 can be increased by turning on the first switch element of the substrate bias adjusting unit 52, and the voltage φP2 can be increased by turning on the second switch element. The voltage can be lowered. The voltage φP2 is applied to the base of the transistor Tr6 that functions as a switch that increases or decreases the number of stages of the output circuit 44.

  Thus, in the solid-state imaging device of this embodiment, the gain g of the output circuit 44 (source follower circuit) is smaller than 1, and the gain of the entire output circuit can be reduced by increasing the number of output circuit stages.

  For example, when switching from the second drive mode to the first drive mode, the transistor Tr6 functioning as a switch is turned on, and the number of stages of the source follower circuit is switched from two to three, thereby reducing the gain g of the output circuit. It will be. At this time, the voltage output from Vout2 is handled as a signal output.

  On the other hand, when switching from the first drive mode to the second drive mode, the transistor Tr6 is turned off, and the number of stages of the source follower circuit is switched from three to two, thereby increasing the gain g of the output circuit. At this time, the voltage output from Vout1 is handled as a signal output.

  As described above, in the solid-state imaging device of the present embodiment, by using the existing substrate bias generation circuit 50, switching of the gain g of the output circuit for each drive mode can be easily realized without increasing the number of components. It becomes.

  In the solid-state imaging device according to the present embodiment, the value of the voltage φP2 is adjusted by the substrate bias adjusting unit 52 included in the substrate bias generating circuit 50, but the adjustment of the value of the voltage φP2 is not limited to this method. For example, as shown in FIG. 12, the value of the voltage φP2 may be adjusted by a reference voltage generation circuit 60 provided in the solid-state imaging device and a voltage value switching unit provided outside the solid-state imaging device.

[4. Fourth Embodiment]
Next, a solid-state imaging device according to the fourth embodiment will be described with reference to FIG. Note that components other than the output unit 40d and the substrate bias generation circuit 50d, which are characteristic configurations of the present embodiment, are denoted by the same reference numerals for configurations common to the above-described general solid-state imaging device. Omitted.

  As illustrated in FIG. 13, the third P-type well region 19 of the output circuit 44 a is formed separately from the P-type well region 12 such as the imaging region 20 and the output unit 40. The substrate bias generating circuit 50d includes a substrate bias adjusting unit 52 and the resistance dividing circuit 54 described above.

  The substrate bias generation circuit 50 d includes an emitter follower circuit 51, a substrate bias adjustment unit 52, a resistance dividing circuit 54, and a reference voltage generation circuit 60. In the substrate bias generating circuit 50d having such a configuration, the gate of the transistor Tr4 constituting the resistance dividing circuit 54 is connected to the substrate bias adjusting unit 52. The input terminal of the reference voltage generation circuit 60 is connected between the resistor R10 and the drain of the transistor Tr4, and an output voltage corresponding to the input voltage adjusted by the substrate bias adjustment unit 52 is supplied to the reference voltage generation circuit 60. It is designed to be entered.

  For example, when switching from the second driving mode to the first driving mode, the transistor Tr6 functioning as a switch is turned on, and the number of stages of the source follower circuit is switched from two to three, thereby reducing the gain g of the output circuit. It will be. At this time, the voltage output from Vout2 is handled as a signal output.

  On the other hand, when switching from the first drive mode to the second drive mode, the transistor Tr6 is turned off, and the number of stages of the source follower circuit is switched from three to two, thereby increasing the gain g of the output circuit. At this time, the voltage output from Vout1 is handled as a signal output.

  As described above, in the solid-state imaging device of the present embodiment, by using the existing substrate bias generation circuit 50, switching of the gain g of the output circuit for each drive mode can be easily realized without increasing the number of components. It becomes.

  In the solid-state imaging device according to the present embodiment, the value of the voltage φP2 is adjusted by the substrate bias adjusting unit 52 included in the substrate bias generating circuit 50, but the adjustment of the value of the voltage φP2 is not limited to this method. For example, as shown in FIG. 14, the value of the voltage φP <b> 2 may be adjusted by a reference voltage generation circuit 60 provided in the solid-state image sensor and voltage value switching means provided outside the solid-state image sensor.

  As described above, according to the present invention, the conversion efficiency η and the output circuit gain can be changed in the solid-state imaging device for each drive mode by the selective output voltage using the substrate bias adjustment unit. Accordingly, since the second drive mode in which the conversion efficiency η and the output circuit gain are set high and the first drive mode in which the conversion efficiency η and the output circuit gain are set low can be compatible, in the second drive mode, the sensitivity While an output with high characteristics can be realized, in the first drive mode, it is possible to prevent image quality deterioration particularly in the dark without excessively amplifying the signal output.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

DESCRIPTION OF SYMBOLS 1 Solid-state image sensor 10 Semiconductor substrate 11 N-type sub-region 12 P-type well region 12a Contact region 13 N-type channel region 14 Transfer region 15 Storage region 16 First N-type well region 16a, 18a Contact region 17 First P-type well region 18 2P type well region 20 Imaging region 21 Pixel portion 22 Read gate portion 23 Vertical transfer portion 24 Element isolation region 30 Horizontal transfer portion 31 Horizontal transfer output gates 40, 40a, 40b, 40c, 40d Output portion 41 Floating diffusion portion 42 Reset gate portion 43 Reset drain section 44, 44a Output circuit 45 Reset gate terminal 46 Channel region 50, 50a, 50b, 50c, 50d Substrate bias generation circuit 51 Emitter follower circuit 52 Substrate bias adjustment section 53, 54, 55 Resistance division Road 60 reference voltage generating circuit

Claims (8)

A plurality of pixel units arranged in a matrix and performing photoelectric conversion on a semiconductor substrate,
A vertical transfer unit that vertically transfers signal charges read from the plurality of pixel units;
A horizontal transfer unit that horizontally transfers the signal charges transferred from the vertical transfer unit;
An output unit having a charge-voltage conversion unit that converts the signal charge transferred from the horizontal transfer unit into a charge-voltage, and an output circuit that amplifies the signal voltage converted by the charge-voltage conversion unit;
A substrate bias generating circuit for controlling a substrate bias voltage applied to the semiconductor substrate in order to adjust a saturation signal amount of the pixel unit;
With
Solid imaging that applies the substrate bias voltage controlled by the substrate bias generation circuit to a region under the charge voltage conversion unit to adjust the conversion efficiency by the charge voltage unit or the amplification factor of the signal voltage by the output circuit element. The vertical transfer unit reads the signal charge of only a predetermined repeating unit pixel from the first drive mode for independently vertically transferring the signal charge read from the plurality of pixel units, and A second drive mode in which signal charges for a plurality of pixels are added and transferred in the vertical transfer section can be selectively set in the first drive mode;
The solid-state imaging device according to claim 1, wherein the substrate bias generation circuit adjusts the conversion efficiency or the amplification factor for each of the driving modes.   The substrate bias generation circuit adjusts the conversion efficiency or the amplification factor in the second drive mode to be higher than the conversion efficiency or the amplification factor in the first drive mode. Solid-state image sensor.   The substrate bias generation circuit adjusts the conversion efficiency or the amplification factor in the first drive mode to be higher than the conversion efficiency or the amplification factor in the second drive mode. Solid-state image sensor.   The solid-state imaging device according to claim 1, wherein the substrate bias generation circuit adjusts the conversion efficiency by changing a capacitance of the charge-voltage conversion unit. The output unit is formed so that the substrate bias voltage is applied;
The solid-state imaging device according to claim 1, wherein the substrate bias generation circuit adjusts the amplification factor by changing the substrate bias voltage in the output circuit. The output circuit includes a plurality of source follower circuits,
The solid-state imaging element according to claim 1, wherein the substrate bias control unit adjusts the amplification factor by switching the number of stages of the plurality of source follower circuits. A solid-state image sensor;
An optical system for forming a subject image on the solid-state image sensor;
A drive unit that generates a drive pulse for driving the solid-state imaging device;
A signal processing circuit for processing an output image signal of the solid-state imaging device,
The solid-state imaging device is
A plurality of pixel units arranged in a matrix and performing photoelectric conversion on a semiconductor substrate,
A vertical transfer unit that vertically transfers signal charges read from the plurality of pixel units;
A horizontal transfer unit that horizontally transfers the signal charges transferred from the vertical transfer unit;
An output unit having a charge-voltage conversion unit that converts the signal charge transferred from the horizontal transfer unit into a charge-voltage, and an output circuit that amplifies the signal voltage converted by the charge-voltage conversion unit;
A substrate bias generating circuit for controlling a substrate bias voltage applied to the semiconductor substrate in order to adjust a saturation signal amount of the pixel unit;
With
An imaging apparatus that adjusts the conversion efficiency by the charge voltage unit or the amplification factor of the signal voltage by the output circuit by applying the substrate bias voltage controlled by the substrate bias generation circuit to a region under the charge voltage conversion unit .

Images