JP4013700B2 - Imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is a solid that can be switched between a first state that outputs an electric signal that linearly changes with respect to the amount of incident light and a second state that outputs an electric signal that naturally changes logarithm with respect to the amount of incident light. The present invention relates to an imaging apparatus having an imaging element.
[0002]
[Prior art]
Conventionally, in a solid-state imaging device that performs a linear conversion operation that linearly converts the amount of incident light, its dynamic range is as narrow as two orders of magnitude, so when imaging a subject that constitutes a luminance distribution in a wide luminance range, other than the dynamic range The luminance information in the range is not output. Further, as a conventional solid-state imaging device, there is one that performs a logarithmic conversion operation for logarithmically converting the amount of incident light (see Patent Document 1).
[0003]
In this solid-state imaging device, the dynamic range is as wide as 5 to 6 digits. Therefore, even if an image of a subject constituting a luminance distribution in a slightly wide luminance range is captured, all luminance information in the luminance distribution is converted into an electrical signal. Can be output. However, since the imageable area becomes wider with respect to the luminance distribution of the subject, an area without luminance data is formed in the low luminance area or the high luminance area in the imageable area. On the other hand, there is a conventional solid-state imaging device capable of switching between the above-described linear conversion operation and logarithmic conversion operation (Patent Document 2).
[0004]
[Patent Document 1]
JP-A-11-313257 [Patent Document 2]
Japanese Patent Laid-Open No. 2002-77733
[Problems to be solved by the invention]
According to the solid-state imaging device described in Patent Document 2, the logarithmic conversion operation and the linear conversion operation are switched by binarizing and changing the source voltage of the MOS transistor connected to the photodiode. In this way, since the switching between the logarithmic conversion operation and the linear conversion operation is switched by the source voltage, it is necessary to switch from judging the luminance range of the subject every time the subject is photographed. Depending on the subject, there may be a mixture of a low-luminance part and a high-luminance part. In this case, it is better to perform a linear conversion operation to increase the contrast of the low-luminance part. It is better to perform a logarithmic conversion operation with a wide dynamic range so that the portion is not crushed white.
[0006]
Further, in order to improve the contrast when the luminance of the subject is low, there is a method of increasing the sensitivity by increasing the integration time in each pixel of the solid-state imaging device. However, in order to increase the sensitivity of each pixel only by this integration time, there is a limit to increasing the time required to capture one frame, such as when shooting a movie, and there is a limit. Sensitivity may not be obtained.
[0007]
In view of such a problem, an object of the present invention is to provide an imaging apparatus that can capture an image with good contrast and can adapt the dynamic range of a subject to the dynamic range of a solid-state imaging device. And
[0008]
[Means for Solving the Problems]
In order to achieve the above object, an image pickup apparatus according to the present invention includes a photosensitive element that outputs an electrical signal corresponding to the amount of incident light, a transistor that is supplied with the electrical signal from the photosensitive element, and an integration that integrates the electrical signal from the transistor. A first state in which an electrical signal corresponding to the amount of incident light is linearly converted and output when the subject is on a relatively low luminance side and a logarithmic conversion of the electrical signal corresponding to the amount of incident light on the relatively high luminance side In the imaging apparatus having a solid-state imaging device composed of a plurality of pixels that can be automatically switched to and from the second state to be output, the value of the bias voltage applied to the transistor at the time of reset is imaged by the solid-state imaging device. The potential state of the transistor immediately after resetting can be changed by switching to multiple stages according to the state of the luminance distribution of the subject. Be one that is of, the luminance range of the subject is narrowed, that the operation state of the pixel has a bias adjustment unit for shifting a value that is a turning point of switching from the first state to the second state to the high luminance side Features. The bias adjustment unit and the integration time adjustment unit are configured by a main control unit and a vertical scanning circuit in the following embodiments.
[0009]
In such a configuration , when the luminance range of the subject is narrowed , the voltage difference between the bias voltage value at the time of imaging and the bias voltage value at the time of reset is increased. When the luminance range of the subject is narrowed, the integration time is extended by the integration time adjustment unit. Furthermore, an integration time adjustment unit that switches the integration time in each pixel in a plurality of stages according to the state of the luminance distribution of the subject imaged by the solid-state imaging device may be provided .
[0010]
In such an imaging apparatus , the image processing unit includes an image processing unit that performs image processing on an electrical signal output from the solid-state imaging device. In the image processing unit, the solid state is formed by the bias adjustment unit and the integration time adjustment unit. The image processing method applied to the electrical signal output from the solid-state image sensor is switched according to the setting state of the image sensor.
[0011]
For example, when the bias voltage applied to the transistor at the time of reset is changed by the bias adjustment unit, the inflection point at which the transition from the first state to the second state changes, so the image processing unit changes the image according to the transition of the inflection point. Also for the processing operation, a range for performing processing according to the linearly converted electrical signal and a range for performing processing according to the logarithmically converted electrical signal are set. In addition, when the integration time is switched by the integration time adjustment unit, the dynamic range of the electrical signal output from the solid-state imaging device changes, so that the image processing unit outputs the electrical signal output during A / D conversion or the like. The dynamic range of is changed according to the length of the integration time.
[0012]
In the above-described imaging device, the pixel serves as the photosensitive element, and a first electrode and a gate electrode are connected to a photodiode in which a DC voltage is applied to the first electrode, and a second electrode of the photodiode. And a MOS transistor that outputs an electric signal from the gate electrode, and when the luminance range of the luminance distribution of the subject is narrow by the bias adjustment unit, the MOS transistor is provided between the gate electrode and the second electrode. The potential state of the MOS transistor immediately after reset is adjusted so that the potential difference between the gate electrode and the second electrode of the MOS transistor is large when the luminance range of the luminance distribution of the subject is wide. The potential of the MOS transistor immediately after resetting is reduced so that the potential difference between Le state is adjusted.
[0013]
At this time, if the MOS transistor is a P-channel MOS transistor, when the luminance range of the subject is wide, the voltage value applied to the second electrode of the MOS transistor at the time of resetting is set low, and when the luminance range of the subject is narrow, at the time of resetting A voltage value applied to the second electrode of the MOS transistor is set high. If the MOS transistor is an N-channel MOS transistor, the voltage value applied to the second electrode of the MOS transistor at the time of resetting is set high when the luminance range of the subject is wide. The voltage value applied to the second electrode of the MOS transistor is set low.
[0014]
In addition, the pixel includes a capacitor that integrates the electrical signal output from the transistor as one of the integration circuits, and changes the sensitivity of the pixel by switching the length of the integration period of the capacitor. Let
[0015]
Further, in the above-described imaging device, an electrical signal obtained by integrating the electrical signal generated from the transistor during the imaging operation by the integration circuit is used as a video signal, and the electrical signal generated from the transistor during the reset is generated by the integration circuit. When the electric signal obtained by integration is a noise signal, the potential of the reference voltage applied to the integration circuit is changed when the video signal and the noise signal are derived to the output circuit. When the noise of the video signal is removed by the output noise signal, the offset of the video signal from which the noise has been removed can be reduced.
[0016]
In such a configuration, when the integration circuit is a capacitor, an output signal line from which an electrical signal obtained by integration with the capacitor is output, and an electrical connection between the capacitor and the output signal line. A first switch that performs the separation, and changes the potential of the reference voltage in synchronization with the ON / OFF operation of the first switch.
[0017]
In addition, a second switch for electrically connecting / disconnecting the photodiode and the MOS transistor is provided, and when a reset operation is performed, an electric signal output from the MOS transistor with the second switch turned off is provided. When the electric signal obtained by accumulating in the capacitor is derived as a noise signal to the output signal line, the potential of the reference voltage applied to the capacitor may be changed.
[0018]
In addition, a second switch for electrically connecting and separating the photodiode and the MOS transistor is provided, and when performing an imaging operation, an electric signal output from the MOS transistor with the second switch turned on is provided. When an electrical signal obtained by accumulating in the capacitor is derived as a video signal to the output signal line, the potential of the reference voltage applied to the capacitor may be changed.
[0019]
In addition, a second switch for electrically connecting and separating the photodiode and the MOS transistor is provided, and when performing an imaging operation, an electric signal output from the MOS transistor with the second switch turned on is provided. When the electric signal obtained by accumulating in the capacitor is derived as a video signal to the output signal line, the potential of the reference voltage applied to the capacitor is changed, and when performing a reset operation, the second switch is The potential of the reference voltage applied to the capacitor when the electrical signal obtained by accumulating the electrical signal output from the MOS transistor in the OFF state in the capacitor is derived as a noise signal to the output signal line. You may make it change.
[0020]
At this time, the reference voltage is ternary, and the change width of the reference voltage potential at the time of deriving the video signal is larger than the change width of the reference voltage potential at the time of deriving the noise signal. By taking the difference between the video signal and the noise signal, the offset generated in the video signal from which noise has been removed can be reduced.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0022]
1. Configuration of Solid-State Image Sensor First, the solid-state image sensor of this embodiment will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the solid-state imaging device of the present embodiment.
[0023]
In FIG. 1, G11 to Gmn indicate pixels arranged in a matrix (matrix arrangement). Reference numeral 1 denotes a vertical scanning circuit, which sequentially scans rows (lines) 3-1, 3-2,..., 3-n that apply a signal φV to each pixel, and lines 4-1, 4-2. ,..., 4-n, a signal φVD is applied to each pixel, and a signal φVPS is applied to each pixel via lines 5-1, 5-2,. A horizontal scanning circuit 2 sequentially reads out photoelectric conversion signals derived from the pixels to the output signal lines 6-1, 6-2, ..., 6-m in the horizontal direction for each pixel. Reference numeral 10 denotes a power supply line. For each pixel, not only the lines 3-1 to 3-n, 4-1 to 4-n, 5-1 to 5-n, the output signal lines 6-1 to 6-m, and the power supply line 10, but also These lines (for example, a clock line and a bias supply line) are also connected, but these are omitted in FIG.
[0024]
Also, constant current sources 7-1 to 7-m are connected to the output signal lines 6-1 to 6-m, and pixels are provided via the signal lines 6-1 to 6-m, respectively. Selection circuits 8-1 to 8-m are provided for sample-holding video signals and noise signals supplied from G11 to Gmn. Then, when the video signal and the noise signal are sequentially transmitted from the selection circuits 8-1 to 8-m to the correction circuit 9, the correction circuit 9 performs correction processing and outputs the video signal from which noise is removed to the outside. Is done. The DC voltage VPS is applied to one end of the constant current sources 7-1 to 7-m.
[0025]
In such a solid-state imaging device, the video signal and the noise signal output from the pixel Gab (a: 1 ≦ a ≦ m natural number, b: 1 ≦ b ≦ n natural number) are respectively output signal lines 6- The signal is output via a and amplified by a constant current source 7-a connected to the output signal line 6-a. The video signal and noise signal output from the pixel Gab are sequentially sent to the selection circuit 8-a, and the sent video signal and noise signal are sampled and held in the selection circuit 8-a.
[0026]
Thereafter, after the sampled and held video signal is sent to the correction circuit 9 from the selection circuit 8-a, the same sampled and held noise signal is sent to the correction circuit 9. In the correction circuit 9, the video signal given from the selection circuit 8-a is corrected based on the noise signal also given from the selection circuit 8-a, and the noise-removed video signal is output to the outside. An example of the configuration of each of the selection circuits 8-1 to 8-n and the correction circuit 9 is a configuration presented by the present applicant in Japanese Patent Laid-Open No. 2001-223948. Further, a correction circuit may be provided at the configuration position of the selection circuits 8-1 to 8-n.
[0027]
2. Pixel Configuration Example An example of the configuration of the pixels G11 to Gmn provided in the solid-state imaging device of FIG. 1 will be described below with reference to FIG. In the pixel of FIG. 2, the drain of the MOS transistor T1 is connected to the anode of the photodiode PD to which the DC voltage VPD is applied to the cathode, the gate and drain of the MOS transistor T2 and the gate of the MOS transistor T3 are connected to the source of the MOS transistor T1. Connected.
[0028]
The gate of the MOS transistor T4 and the drain of the MOS transistor T5 are connected to the source of the MOS transistor T3, and the drain of the MOS transistor T6 is connected to the source of the MOS transistor T4. The drain of the MOS transistor T6 is connected to the output signal line 6 (corresponding to the output signal lines 6-1 to 6-m in FIG. 1). The MOS transistors T1 to T6 are P-channel MOS transistors.
[0029]
The signal φVPS is input to the source of the MOS transistor T2 via the line 5 (corresponding to the lines 5-1 to 5-n in FIG. 1), and the DC voltage VPD is applied to the drains of the MOS transistors T3 and T4. Further, the other end of the capacitor C to which the signal φVD is supplied via the line 4 (corresponding to the lines 4-1 to 4-n in FIG. 1) is connected to the source of the MOS transistor T3. The DC voltage VRG is input to the source of the MOS transistor T5, and the signal φRS is input to the gate thereof. Further, signals φS and φV are input to the gates of the MOS transistors T1 and T6, respectively.
[0030]
In the pixel thus configured, the constant current source 7 (corresponding to the constant current sources 7-1 to 7-m in FIG. 1) having the DC voltage VPS applied to one end via the MOS transistor T6 and the output signal line 6 is used. Is connected to the source of the MOS transistor T4. Therefore, when the MOS transistor T6 is ON, the MOS transistor T4 operates as a source follower MOS transistor, and outputs the voltage signal amplified by the constant current source 7 to the output signal line 6.
[0031]
By configuring the source follower circuit in this way, an amplifier circuit that outputs a large signal is configured. Therefore, since the signal is amplified to a sufficiently large signal by the present amplifier circuit, the subsequent signal processing circuit can be easily processed. In addition, the constant current sources 7-1 to 7-m constituting the load resistance portion of the amplifier circuit are not provided in the pixels, but the output signal lines 6-1 to 6 to which a plurality of pixels arranged in the column direction are connected. By providing each −m, the number of load resistors or constant current sources can be reduced, and the area occupied by the amplifier circuit on the semiconductor chip can be reduced.
[0032]
The imaging operation and sensitivity variation detection operation by the pixel having such a configuration will be described below. The signal φVPS is a binary voltage signal. When the amount of incident light exceeds a predetermined value, the voltage for operating the MOS transistor T2 in the subthreshold region is VL, and the voltage higher than this voltage is used for the MOS transistor T2. The voltage for making the conductive state is VH. The signal φVD is a ternary voltage signal, the voltage value when integrating the capacitor C is set to the highest Vh, the voltage value when reading the video signal is set to Vm lower than Vh, and the noise signal is read The voltage value is set to Vl lower than Vm.
[0033]
(1) Basic operation at reset (when noise signal is output)
First, the operation at the time of resetting each pixel will be described with reference to the timing chart of FIG. First, when a pulse signal φVD having a voltage value Vm and a pulse signal φV are supplied and a video signal is output, the signal φVD is set to Vh, then the signal φS is set high, the MOS transistor T1 is turned off, and the reset operation is performed. Begins. At this time, positive charges flow in from the source side of the MOS transistor T2, and the negative charges accumulated in the gate and drain of the MOS transistor T2 and the gate of the MOS transistor T3 are recombined. And the potential of the drain increases.
[0034]
However, when the potential of the gate and drain of the MOS transistor T2 rises to a certain value, the reset speed becomes slow. This tendency is particularly noticeable when a bright subject suddenly becomes dark. Therefore, next, the signal φVPS applied to the source of the MOS transistor T2 is set to VH. Thus, by increasing the source voltage of the MOS transistor T2, the amount of positive charge flowing from the source side of the MOS transistor T2 increases and accumulates at the gate and drain of the MOS transistor T2 and at the gate of the MOS transistor T3. The negative charge generated is quickly recombined. At this time, the signal φRS is set to low, the MOS transistor T5 is turned on, and the voltage at the connection node between the capacitor C and the gate of the MOS transistor T4 is initialized.
[0035]
When the potential of the gate and drain of the MOS transistor T2 is further increased by setting the signal φVPS to VH, the signal φVPS applied to the source of the MOS transistor T2 is set to VL, and the potential state of the MOS transistor T2 is based on the state. Return to. As described above, when the potential state of the MOS transistor T2 is reset to the original state, the signal φRS is set high and the MOS transistor T5 is turned off.
[0036]
Then, the capacitor C performs an integration operation, and the voltage at the connection node between the capacitor C and the gate of the MOS transistor T4 becomes in accordance with the reset gate voltage of the MOS transistor T2. Then, by applying the pulse signal φV to the gate of the MOS transistor T6 to turn on the MOS transistor T6 and setting the voltage value of the signal φVD to V1, the sensitivity of each pixel due to the variation in the characteristics of the MOS transistors T2 and T3. An output current representing the variation of the current flows from the output signal line 6.
[0037]
At this time, since the MOS transistor T4 operates as a source follower type MOS transistor, a noise signal appears on the output signal line 6 as a voltage signal. Thereafter, the pulse signal φRS is again applied to the MOS transistor T5 to reset the voltage at the connection node between the capacitor C and the gate of the MOS transistor T4, and then the signal φS is set low to turn on the MOS transistor T1 to perform the imaging operation. Make it ready.
[0038]
(2) Basic operation during imaging (when outputting video signals)
Next, the operation at the time of imaging each pixel will be described. First, the signal φS is always low during the imaging operation, and the MOS transistor T1 is turned on. At this time, the signal φRS is set high and the MOS transistor T5 is turned off. Further, the signal φVPS applied to the source of the MOS transistor T2 is set to VL, and the voltage value of the signal φVD applied to the capacitor C is set to Vh to perform the integration operation.
[0039]
At this time, photocharge corresponding to the amount of incident light flows from the photodiode PD into the MOS transistor T2. Now, since the MOS transistor T2 is in the cut-off state, photocharge is accumulated at the gate of the MOS transistor T2. Therefore, when the brightness of the subject to be imaged is low and the amount of incident light entering the photodiode PD is small, a voltage corresponding to the amount of photocharge accumulated at the gate of the MOS transistor T2 appears at the gate of the MOS transistor T2, A voltage linearly proportional to the integrated value of the light quantity appears at the gate of the MOS transistor T3.
[0040]
Also, when the luminance of the subject to be imaged is high and the amount of incident light entering the photodiode PD is large, and the voltage according to the amount of photocharge accumulated at the gate of the MOS transistor T2 increases, the MOS transistor T2 operates in the subthreshold region. Therefore, a voltage that is naturally logarithmically proportional to the amount of incident light appears at the gate of the MOS transistor T3.
[0041]
A drain current obtained by amplifying a voltage linearly or naturally logarithmically proportional to the amount of incident light by the MOS transistor T3 flows from the capacitor C, and the capacitor C is discharged. Therefore, the gate voltage of the MOS transistor T4 becomes a voltage linearly or naturally logarithmically proportional to the integrated value of the incident light quantity. In order to read a video signal that appears when the capacitor C performs an integration operation, the voltage value of the signal φVD is set to Vm, and a pulse signal φV is given to the MOS transistor T6. Therefore, a source current corresponding to the gate voltage of the MOS transistor T4 flows to the output signal line 6 via the MOS transistor T6.
[0042]
Thus, since the MOS transistor T4 operates as a source follower type MOS transistor, the video signal appears on the output signal line 6 as a voltage signal. Thereafter, the signal φV is set high to turn off the MOS transistor T6, and the voltage value of the signal φVD is set to Vh. Thus, since the video signal output through the MOS transistors T4 and T6 has a value proportional to the gate voltage of the MOS transistor T4, the integral value of the amount of light incident on the photodiode PD is linear or natural logarithm. Converted signal.
[0043]
At this time, the amount of photoelectric charge flowing into the MOS transistor T2 until reaching the gate voltage of the MOS transistor T2 when changing to the logarithmic conversion operation at the time of imaging becomes equal in all the pixels. In this way, since the amount of photocharge generated from the photodiode PD when the conversion operation in each pixel is switched to the logarithmic conversion operation is the same, it is incident on the photodiode PD when the conversion operation in each pixel is switched to the logarithmic conversion operation. The amount of incident light is also equal. That is, in all the pixels, the luminance of the subject becomes the same when the conversion operation is switched from the linear conversion operation to the logarithmic conversion operation, and the difference in threshold voltage of the MOS transistor T2 affects the switching of the conversion operation of each pixel. Can be reduced.
[0044]
Further, as described above, the voltage value applied to the capacitor C when reading the noise signal is set to Vl, and the offset value is proportional to (Vl−Vm) by making it lower than the voltage value Vm when integrating the video signal. Therefore, the proportion of the offset value can be reduced as compared with the conventional case.
[0045]
(3) Switching of shooting conditions When the reset operation and the shooting operation are performed as described above, the voltage value VH of the signal φVPS at the time of reset increases, and the difference between the voltage value VL of the signal φVPS at the time of imaging increases. The potential difference between the gate and the source of the MOS transistor T2 becomes large, and the ratio of the subject luminance at which the MOS transistor T2 operates in the cutoff state increases. Therefore, as shown in FIG. 4, the higher the voltage value VH, the larger the ratio of subject luminance to be linearly converted. That is, the voltage value VH is increased when the luminance range of the subject is narrow, and the voltage value VH is decreased when the luminance range of the subject is wide.
[0046]
As described above, when the inflection point for switching between the linear conversion operation and the logarithmic conversion operation is changed by changing the voltage value VH of the signal φVPS at the time of resetting, the operation of each signal is as shown in FIGS. By changing the length of time, the length of integration time in the photodiode PD and the capacitor C can be changed, and the sensitivity of each pixel can be changed. That is, when the luminance range of the subject is narrow, the operation time of each signal is lengthened as shown in FIG. 5, and when the luminance range of the subject is wide, the operation time of each signal is shortened as shown in FIG. Therefore, in the case of FIG. 5, since the integration time is doubled compared with FIG. 3, the frame rate at each pixel is ½ times.
[0047]
That is, when the luminance value of the entire subject is low and the luminance range becomes narrow, in order to capture a good contrast, the voltage value VH is maximized and the range for linear conversion as shown by the dotted line in FIG. 4 is widened. At the same time, as shown in FIG. 5, the operating time of each signal is lengthened to increase the sensitivity. When the luminance value becomes slightly high, the operation time of each signal is shortened as shown in FIG. Further, when the luminance range becomes wider, the range for linear conversion as shown by the one-dot chain line in FIG. 4 is slightly narrowed with the voltage value VH being an intermediate value. Further, when the luminance value of the entire subject is high and the luminance range becomes wide, the voltage value VH is minimized to further narrow the range for linear conversion as shown by the solid line in FIG. 4, and as shown in FIG. The operating time of each signal is shortened. That is, in this embodiment, when the voltage value VH of the signal φVPS at the time of reset is changed in three stages and the operation time of each signal is changed in two stages, according to the luminance value of the entire subject and its luminance range, It can be changed in 6 steps.
[0048]
3. Configuration of Imaging Device As described above, an imaging device including a solid-state imaging device in which each pixel operates will be described with reference to FIG. FIG. 6 is a block diagram illustrating an internal configuration of the imaging apparatus according to the present embodiment.
[0049]
The imaging apparatus in FIG. 6 includes a solid-state imaging device 100 configured as shown in FIG. 1 and an A / D conversion unit that converts a noise-removed video signal output from the correction circuit 9 in the solid-state imaging device 100 into a digital signal. 101, an image processing unit 102 that performs image processing on the video signal converted by the A / D conversion unit 101, a value of the voltage VH of the signal φVPS applied to each pixel in the solid-state imaging device 100, and the operation of each signal A main control unit 103 that controls the solid-state imaging device 100 by setting time. Each of the A / D conversion unit 101 and the image processing unit 102 is supplied with the value of the voltage VH of the signal φVPS given to each pixel from the solid-state imaging device 100 and the operation time of each signal as pixel control information.
[0050]
In this way, when pixel control information is given to the A / D conversion unit 101 and the image processing unit 102 from the solid-state image sensor 100, first, the A / D conversion unit 101 first outputs an image output from the solid-state image sensor 100. The upper and lower limits of the signal dynamic range are set. That is, when the operation time of each signal applied to each pixel is set to be long, the dynamic range is widened and the lower limit of the dynamic range is increased. At this time, the value serving as the inflection point of the video signal output from the A / D conversion unit 101 is set to be equal regardless of the length of the operation time of each signal. .
[0051]
Further, the image processing unit 102 recognizes the value that becomes the inflection point of the video signal output from the A / D conversion unit 101 from the value of the voltage VH of the signal φVPS, and the video signal lower than the value that becomes the inflection point. Is subjected to image processing as a linearly converted video signal, and a video signal higher than a value serving as an inflection point is subjected to image processing as a logarithmically converted video signal.
[0052]
In the present embodiment, in the A / D conversion unit 101, the inflection point of the video signal is set to be the same value regardless of the length of the operation time of each signal, but it is not set in this way. It does n’t matter. At this time, the image processing unit 102 also recognizes the operation time of each signal, confirms the value as the inflection point in each case, compares the value of the given video signal with the value as the inflection point, and linearly Switching between image processing for the converted video signal and image processing for the logarithmically converted video signal is performed.
[0053]
In the present embodiment, each pixel is configured using a P-channel MOS transistor, but may be configured using an N-channel MOS transistor. At this time, since the polarities of the respective elements are reversed, the constant current sources 7-1 to 7-m provided in the solid-state imaging device also have the opposite polarities as those in FIG. The relationship between the lines and blocks is the same as that of the solid-state imaging device of FIG. 1 except that the polarities of the elements in each block are reversed.
[0054]
Further, the MOS transistors constituting each pixel at this time are N-channel and are represented as shown in FIG. The connection relationship between the MOS transistors T1 to T6 and the capacitor C and the role of each element are the same as in FIG. 2, and each element performs an operation corresponding to the polarity opposite to that in FIG. That is, the voltage value of the signal φVD is set to the lowest Va when integrating the video signal and the noise signal, Vb being an intermediate value when reading the video signal, and the highest Vc when reading the noise signal.
[0055]
As described above, the timing of changing the signals φVPS, φVD, φS, φRS, and φV given to each pixel when the MOS transistors constituting each pixel are N-channel is expressed as shown in FIG. That is, the operation timings of the MOS transistors T1, T2, T5, and T6 can be set to the same timing by reversing the relation between high and low in the signals φVPS, φS, φRS, and φV as in FIG.
[0056]
Also, by making the timings for applying the voltage values Vh, Vm, Vl of the signal φVD in FIG. 3 and the timings for applying the voltage values Va, Vb, Vc of the signal φVD in FIG. The operating state of the capacitor C can be the same as in the present embodiment at each timing. Further, by lowering the value VL of the signal φVPS at the time of reset, the value of the inflection point can be lowered and the range in which the linear conversion operation is performed can be widened.
[0057]
【The invention's effect】
According to the present invention, the potential state and integration time of the transistors in each pixel provided in the solid-state imaging device can be adjusted according to the luminance of the subject, so that the degree of freedom in selecting the photographing condition of the subject is greatly expanded. Is done. Therefore, it is possible to select an imaging condition that can capture an image with good contrast and gradation. In particular, by increasing the integration time and setting the value that becomes the inflection point to switch from the first state to the second state on the high luminance side, the sensitivity in the dark portion can be increased and the contrast is good. can do.
[Brief description of the drawings]
FIG. 1 is a block circuit diagram showing a configuration of a solid-state image sensor.
FIG. 2 is a circuit diagram illustrating a configuration of a pixel in the solid-state imaging device of FIG.
FIG. 3 is a timing chart showing the operation of the pixel in FIG. 2;
FIG. 4 is a graph showing the relationship between the brightness of a subject and the output of a solid-state image sensor.
FIG. 5 is a timing chart showing an operation when the frame rate of the pixel in FIG. 2 is changed;
6 is a block diagram showing an internal configuration of an image pickup apparatus including the solid-state image pickup device shown in FIG.
FIG. 7 is a block circuit diagram showing a configuration of a solid-state imaging device.
8 is a circuit diagram showing a configuration of a pixel in the solid-state imaging device of FIG.
9 is a timing chart showing the operation of the pixel in FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Vertical scanning circuit 2 Horizontal scanning circuit 3-1 to 3-n Line 4-1 to 4-n Line 5-1 to 5-n Line 6-1 to 6-m Output signal line 7-1 to 7-m Fixed Current source 8-1 to 8-m selection circuit 9 correction circuit 10 power supply line G11 to Gmn pixel PD photodiode T1 to T6 MOS transistor C capacitor

Claims (6)

It has a photosensitive element that outputs an electrical signal corresponding to the amount of incident light, a transistor to which the electrical signal from the photosensitive element is applied, and an integration circuit that integrates the electrical signal from the transistor, and the subject is incident on the relatively low brightness side. Automatic switching between a first state in which an electric signal corresponding to the amount of light is linearly converted and output, and a second state in which the subject outputs a logarithmically converted electric signal corresponding to the amount of incident light on a relatively high brightness side. In an imaging apparatus having a solid-state imaging device composed of a plurality of possible pixels,
By switching a plurality of steps in accordance with the state of the luminance distribution of the subject imaged by the solid-value of the bias voltage applied to the transistor at the time of resetting, it is one that changes the potential state of the transistor immediately after reset In addition, the imaging apparatus further includes a bias adjustment unit that shifts a value that becomes an inflection point at which the operation state of the pixel switches from the first state to the second state to the high luminance side when the luminance range of the subject is narrowed. . The imaging apparatus according to claim 1, wherein the bias adjustment unit increases a voltage difference between a bias voltage value at the time of imaging and a bias voltage value at the time of reset when the luminance range of the subject is narrowed . The imaging apparatus according to claim 1, further comprising an integration time adjustment unit that switches an integration time in each pixel in a plurality of stages according to a state of a luminance distribution of a subject imaged by the solid-state imaging device. The imaging apparatus according to claim 3 , wherein when the luminance range of the subject is narrowed, the integration time is extended by the integration time adjustment unit. An image processing unit that performs image processing on an electrical signal output from the solid-state imaging device;
The image processing unit is configured to switch an image processing method applied to an electrical signal output from the solid-state imaging device in accordance with a setting state of the solid-state imaging device by the bias adjustment unit. 5. The imaging device according to any one of 4. An image processing unit that performs image processing on an electrical signal output from the solid-state imaging device, and in the image processing unit, according to a setting state of the solid-state imaging device by the bias adjustment unit and the integration time adjustment unit The imaging apparatus according to claim 3, wherein an image processing method applied to an electrical signal output from the solid-state imaging device is switched.

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