JP2001250933A - Solid-state image sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image sensor which outputs a logarithmicconverted signal according to an incident light quantity and has an image sensible brightness range narrowed according to the brightness distribution of an object. SOLUTION: The drain and the gate of a MOS transistor T1 are connected to the anode of a photo diode PD with a d-c voltage VPD applied to its cathode, and the drain and the gate of a MOS transistor T3 are connected to the source of the MOS transistor T1. Thus, connected MOS transistors T1, T3 are operated in their respective sub-threshold ranges to narrow the dynamic range of pixels.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device having a plurality of pixels.

[0002]

2. Description of the Related Art Conventionally, a solid-state imaging device having a photoelectric conversion element such as a photodiode converts the luminance of light incident on the photosensitive element linearly as shown in FIG. Output a signal. Using a solid-state imaging device that performs this linear conversion (hereinafter, referred to as a “linear sensor”),
When an object having a luminance distribution as shown in FIG. 40B is imaged, a luminance range (dynamic range) of approximately two digits (approximately 40 [dB]) serving as an imageable area of this linear sensor.
The luminance information in the range other than the range is not output. The minimum value of the luminance range in the luminance distribution of the subject is Lmin [c
d / m ² ], and when its maximum value is Lmax [cd / m ² ], it means Lmax / Lmin. The range of the output of the solid-state imaging device corresponding to the luminance range that is the imageable area is referred to as “dynamic range”.

Therefore, when a signal from such a linear sensor is reproduced as an image on a display or the like, black spots occur in a low luminance area outside the imageable area, and white highlights occur in a high luminance area. It is possible to move the imageable area shown in FIG. 40 (b) to the left to suppress such black spots, or to move the imageable area to the right to suppress the white highlight. Since it is necessary to change the aperture and shutter speed of the camera, or the integration time for entering the light, the usability is deteriorated.

On the other hand, the present applicant has proposed a photosensitive means capable of generating a photocurrent corresponding to the amount of incident light, a MOS transistor for inputting the photocurrent, and biasing the MOS transistor so that a subthreshold current can flow. A solid-state image pickup device (hereinafter, referred to as a “LOG sensor”) that includes a bias means for performing a logarithmic conversion of a photocurrent has been proposed (see Japanese Patent Application Laid-Open No. 3-192664). Since the output level of such a LOG sensor is proportional to the natural logarithm of the luminance as shown in FIG.
The dynamic range is 5-6 digits (100-120
[DB]). Therefore, even if the luminance distribution moves, in most cases, the luminance distribution of the subject falls within the imageable area as shown in FIG.

[0005]

However, in general, the brightness range of a subject is two to three digits (40 to 60 [d
B]), the dynamic range is 5
In the case of a LOG sensor having up to six digits (100 to 120 [dB]), the imageable area is wider than the luminance distribution of the subject. There will be a region without any gaps.
That is, as shown in FIG.
In the LOG sensor of Ra, the range of the output corresponding to the luminance distribution is narrowed to DRb.

Therefore, when the level of the output signal of the LOG sensor is converted into, for example, an 8-bit digital signal as shown in FIG. 42 to reproduce an image on an output device such as a display, the dynamic range DR of the output device is used.
Let c correspond to the dynamic range DRa of the LOG sensor, the maximum output value of the LOG sensor corresponds to the maximum output level of the output device (level 255), and the minimum output value of the LOG sensor corresponds to the minimum output level of the output device (level 0). When the conversion is performed, only the signal of the level within the range width DRd which is a partial range of the 8-bit digital signal is input to the output device. Therefore, when the image of the subject having the luminance distribution is reproduced by using such a signal, black having the minimum luminance is reproduced as dark gray, and white having the maximum luminance is reproduced as light gray, and the contrast is insufficient as a whole. Is reproduced.

In view of such a problem, the present invention provides a solid-state imaging device that outputs a signal obtained by logarithmically converting the amount of incident light to reduce the imageable luminance range to a luminance range corresponding to the luminance distribution of a subject. It is an object of the present invention to provide a solid-state imaging device. Another object of the present invention is to provide a solid-state imaging device capable of changing a luminance range in which imaging can be performed.

[0008]

According to a first aspect of the present invention, there is provided a solid-state imaging device, comprising: a photoelectric conversion unit having a photoelectric conversion element for generating an electric signal corresponding to an amount of incident light; A deriving path for deriving an output signal of the photoelectric conversion unit to an output signal line, wherein the photoelectric conversion unit converts the electrical signal into a natural logarithm in a solid-state imaging device. Where Ma is the highest luminance in the image, and Mi is the lowest luminance in the luminance region where the solid-state imaging device can image the image, 20 × log (Ma / Mi)
Can be imaged at 60 [dB] or less.

Further, as described in claim 2, 20 ×
It is assumed that an image can be captured when log (Ma / Mi) is 40 [dB] or more and 60 [dB] or less. As described above, since the luminance range in which the image can be captured is determined, most of the luminance distribution of the object to be imaged adapts to the luminance range. Therefore, an image is formed based on the output signal logarithmically converted by such a solid-state imaging device. Can be reproduced as an image with rich gradation.

According to a third aspect of the present invention, there is provided a solid-state imaging device, comprising: a photoelectric conversion unit having a photoelectric conversion element for generating an electric signal according to the amount of incident light; and a derivation for leading an output signal of the photoelectric conversion unit to an output signal line. A solid-state imaging device in which pixels that include a path and that convert the electrical signal into a natural logarithm are arranged in a matrix. Assuming that the minimum luminance in the luminance region where the apparatus can image is Mi, imaging is possible at 20 × Log (Ma / Mi) of 60 [dB] or less.

Furthermore, as described in claim 4, 20 ×
It is assumed that an image can be captured when log (Ma / Mi) is 40 [dB] or more and 60 [dB] or less. As described above, since the luminance range in which the image can be captured is determined, most of the luminance distribution of the object to be imaged adapts to this luminance range. Can be reproduced as an image with rich gradation.

[0012] An amplifying transistor for amplifying an output signal of the photoelectric conversion means may be provided in each of the pixels, and an output signal of the amplifying transistor may be output to the output signal line via the output path. . In this way, signals from each pixel are read out in a large and stable state.

The solid-state imaging device may have a load resistance or a constant current source whose total number connected to the output signal lines is smaller than the total number of pixels. By providing the load resistance or the constant current source, a current signal output from each pixel can be read as a voltage signal. In such a solid-state imaging device, the load resistance or the constant current source is:
It may be a resistance transistor having a first electrode connected to the output signal line, a second electrode connected to a DC voltage, and a control electrode connected to the DC voltage.

Further, in the solid-state imaging device according to claim 3 or 4, a predetermined one is sequentially selected from all the pixels in the lead-out path, and a signal amplified from the selected pixel is output as an output signal. By providing a switch that leads to a line, a signal output from each pixel to the output signal line can be sequentially read and output as serial data.

According to a fifth aspect of the present invention, in the solid-state imaging device according to any one of the first to fourth aspects, a plurality of transistors operating in a sub-threshold region are provided in the photoelectric conversion means. It is characterized in that it is connected in series with the conversion element.

In such a solid-state imaging device, when n transistors operating in the sub-threshold region and the photoelectric conversion element are connected in series, one transistor operating in the sub-threshold region and the photoelectric conversion element are connected in series. 20 × log (Ma / Mi) compared to when connected to
Can be reduced to 1 / n times. Therefore, the dynamic range when one transistor operating in the subthreshold region and the photoelectric conversion element are connected in series is 12
When it becomes 0 [dB], the dynamic range can be made 120 / n [dB] by using n transistors operating in the sub-threshold region as described above.

According to a sixth aspect of the present invention, in the solid-state imaging device according to the fifth aspect, the photoelectric conversion means includes: a photoelectric conversion element having a first electrode to which a DC voltage is applied;
A first transistor including a first electrode, a second electrode, and a control electrode, wherein the first electrode and the control electrode are connected to a second electrode of the photoelectric conversion element, and an output current from the photoelectric conversion element flows into the first transistor; A second transistor that includes a first electrode, a second electrode, and a control electrode, a DC voltage is applied to the first electrode, the control electrode is connected to a control electrode of the first transistor, and an electric signal is output from the second electrode. And a third transistor to which a first electrode and a control electrode are connected. The first transistor and the third transistor are connected in series, and the first transistor and the third transistor are connected. Operate in the sub-threshold region, respectively.

In such a solid-state imaging device, a constant current source and one end are connected to the first electrode of the first transistor and the other end is connected to the constant current source. A first switch connected to the constant current source, and a constant current flowing through the first transistor. The voltage applied to the control electrode of the second transistor may be initialized to improve its response.

Further, by changing the voltage applied to the control electrode of the first transistor, the voltage applied to the control electrode of the second transistor may be initialized to improve the response.

According to an eighth aspect of the present invention, in the solid-state imaging device according to the fifth aspect, the photoelectric conversion unit includes: a photoelectric conversion element having a second electrode to which a DC voltage is applied;
A first transistor having a first electrode, a second electrode, and a control electrode, wherein the first electrode is connected to the control electrode, and the second electrode is connected to the first electrode of the photoelectric conversion element; A second electrode that includes an electrode, a second electrode, and a control electrode; a DC voltage is applied to the first electrode; the control electrode is connected to a second electrode of the first transistor; and an electric signal is output from the second electrode. , And a third transistor to which a DC voltage is applied to each of the first electrode and the control electrode, wherein the first transistor and the third transistor are connected in series, and the first transistor and the third transistor are connected in series. Each of the third transistors operates in a sub-threshold region.

As described in claim 9, a constant current source;
A switch having one end connected to the second electrode of the first transistor and the other end connected to the constant current source, and turning the switch on to provide a second electrode of the first transistor. May be connected to the constant current source to supply a constant current to the first transistor, thereby initializing the voltage applied to the control electrode of the second transistor to improve the responsiveness.

By changing the voltage applied to the second electrode of the first transistor, the voltage applied to the control electrode of the second transistor may be initialized to improve the response.

The solid-state imaging device according to any one of claims 6 to 9, wherein the photoelectric conversion means integrates an electric signal output from a second electrode of the second transistor and outputs the integrated signal to the output signal line. An integrating circuit may be provided. With such a configuration, the signal output from the photoelectric conversion unit becomes a signal once integrated by the integration circuit, so that the fluctuation component of the light source and high-frequency noise are absorbed and removed by the capacitor.

According to a tenth aspect of the present invention, the photoelectric conversion means is provided with the first transistor by the plurality of transistors.
By providing selection means for selecting a transistor connected in series with the first transistor, and changing the number of transistors connected in series with the first transistor,
The brightness range may be changed.

Further, as set forth in claim 11, a switch is provided in the photoelectric conversion means between the first transistor and the photoelectric conversion element, and the switch is turned off when performing a reset operation. Thus, a configuration in which the photocurrent from the photoelectric conversion element is cut off may be adopted.

According to a twelfth aspect of the present invention, in the solid-state imaging device having a plurality of pixels, each pixel includes a photoelectric conversion element, and a first electrode and a gate electrode formed on one of the electrodes of the photoelectric conversion element. A connected first MOS transistor;
A second MOS transistor having a gate electrode connected to a first electrode and a gate electrode of the first MOS transistor; and a third MOS transistor having a first electrode and a gate electrode connected to a second electrode of the first MOS transistor. And operating the first and third MOS transistors in a sub-threshold region below a threshold.

According to a thirteenth aspect of the present invention, in the solid-state imaging device having a plurality of pixels, each of the pixels includes a photoelectric conversion element and a second electrode connected to one electrode of the photoelectric conversion element. 1 MOS transistor and a second MOS transistor having a gate electrode connected to a second electrode of the first MOS transistor.
An OS transistor; and a third transistor having a second electrode connected to a first electrode and a gate electrode of the first MOS transistor.
And an S transistor, wherein the first and third MOS transistors are operated in a sub-threshold region below a threshold.

[0028] The solid-state imaging device according to claim 14 is the solid-state imaging device according to claim 12 or 13,
A first electrode is connected to a first electrode of the third MOS transistor, and a second electrode of the third MOS transistor is connected to a first electrode.
A fourth MOS transistor having a second electrode connected to the electrode, and when the fourth MOS transistor is turned on,
The luminance range of each pixel is widened, and when the fourth MOS transistor is turned off, the luminance range of each pixel is narrowed.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment of Pixel Configuration Each embodiment of the solid-state imaging device of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows a partial configuration of a two-dimensional MOS solid-state imaging device according to an embodiment of the present invention. In the figure, G11 to Gmn are arranged in a matrix (matrix arrangement).
FIG. Reference numeral 2 denotes a vertical scanning circuit, which sequentially scans rows (lines) 4-1, 4-2,..., 4-n. Reference numeral 3 denotes a horizontal scanning circuit, which sequentially reads out the photoelectric conversion signals derived from the pixels to the output signal lines 6-1, 6-2,..., 6-m for each pixel in the horizontal direction. 5 is a power supply line. For each pixel, the lines 4-1 and 4-
, 4-n and output signal lines 6-1, 6-2,.
6-m, not only the power supply line 5 but also other lines (for example, a clock line and a bias supply line) are connected, but these are omitted in FIG. 1 and shown in the first embodiment shown in FIG. ing.

The output signal lines 6-1, 6-2,.
As shown, one N-channel MOS transistor Q2 is provided for each m. MOS transistor Q2
Is connected to the output signal line 6-1, the source is connected to the final signal line 9, and the gate is connected to the horizontal scanning circuit 3. As described later, an N-channel fifth MOS transistor T5 for switching is provided in each pixel. Here, the MOS transistor T5 is for selecting a row, and the transistor Q2 is for selecting a column.

<First Embodiment> A first embodiment applied to each pixel of the first example of the pixel configuration shown in FIG. 1 will be described with reference to the drawings. FIG. 2 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment.

In FIG. 2, a pn photodiode PD
Form a photosensitive portion (photoelectric conversion portion). The anode of the photodiode PD is connected to a first MOS transistor T1.
Drain and gate of the second MOS transistor T2
Connected to the gate. The source of the MOS transistor T1 is connected to the drain and the gate of the third MOS transistor T3. The source of the MOS transistor T2 is connected to the drain of the fifth MOS transistor T5 for row selection. The source of the MOS transistor T5 is an output signal line 6 (this output signal line 6 is connected to 6-1 and 6 in FIG. 1).
,..., 6-m).
The MOS transistors T1, T2, T3 and T5 are N
The back gate is grounded by the MOS transistor of the channel.

The DC voltage VPD is applied to the cathode of the photodiode PD. On the other hand, M
The DC voltage VPS is applied to the source of the OS transistor T3, and one end of the capacitor C to which the DC voltage VPS is applied is connected to the other end of the MOS transistor T2. Signal φD is input to the drain of MOS transistor T2. The signal φV is input to the gate of the MOS transistor T5.

Now, as shown in FIG. 3, the DC voltage V
A photodiode PD to which PD has been applied, and an M diode having a drain and a gate connected to the anode of the photodiode PD and a DC voltage VPS applied to the source thereof.
In the circuit composed of the OS transistor Tx and M
It is known that when the OS transistor Tx operates in the sub-threshold region, the following equation is satisfied. still,
The MOS transistors T2 and T5 and the capacitor C have the same configuration as the pixel in FIG. Vg = VPS + Vt + (nkT / q) · ln (Ip / Id) (1) where Vg: gate voltage of MOS transistor Tx, Vt:
Threshold voltage of MOS transistor Tx, n: constant determined by gate insulating film capacitance and depletion layer capacitance, k: Boltzmann constant,
q: electron charge, Ip: photocurrent flowing from the photodiode PD, Id: drain current of the MOS transistor Tx.

Therefore, in the solid-state imaging device having the configuration shown in FIG. 2, when the source voltages of the MOS transistors T1 and T3 are VPS1 and VPS2, respectively, the gate voltages Vg1 and Vg2 of the MOS transistors T1 and T3 are respectively Expressions (2) and (3) are given. Vg1 = VPS1 + Vt + (nkT / q) · ln (Ip / Id) (2) Vg2 = VPS2 + Vt + (nkT / q) · ln (Ip / Id) (3)

In FIG. 2, since the source voltage of the MOS transistor T3 is VPS and the source voltage of the MOS transistor T1 is equal to the gate voltage Vg2 of the MOS transistor T3, the MOS transistors T1, T3
Of the gate voltages Vg1 and Vg2 are given by the following equations (4),
It is expressed by equation (5). Vg1 = Vg2 + Vt + (nkT / q) · ln (Ip / Id) (4) Vg2 = VPS + Vt + (nkT / q) · ln (Ip / Id) (5)

Therefore, from the equations (4) and (5), M
The gate voltage Vg1 of the OS transistor T1 becomes lower (6)
It is expressed like a formula. Vg1 = VPS + 2Vt + 2 (nkT / q) .ln (Ip / Id) (6)

As described above, the relationship between the gate voltage Vg1 of the MOS transistor T1 and the logarithm conversion value ln (Ip) of the photocurrent Ip is determined by the MOS transistor Tx of the pixel having the configuration shown in FIG.
Is similar to the relationship between the gate voltage Vg and the logarithmic conversion value ln (Ip) of the photocurrent Ip. Therefore, when the expressions (1) and (6) are compared, the slope of Vg1 and ln (Ip) becomes
It can be seen that the slope is twice the slope between g and ln (Ip).
Also, the MOS transistor T1 and the MOS transistor Tx
Are MOS transistors having the same characteristics,
The gate voltages Vg1, Vg of the transistors T1, Tx, respectively
The area where g changes is the same.

Therefore, the MOS transistors T1, T
x The region where each gate voltage Vg1, Vg changes is
Let Vmin to Vmax. At this time, in the pixel of FIG. 3, the gate voltage Vg of the MOS transistor Tx is Vmin
The photocurrent I flowing from the photodiode PD when
pmin and the gate voltage Vg of the MOS transistor Tx
Is Vmin, the photocurrent Ipmax flowing from the photodiode PD is expressed by the following equations (7) and (8), respectively. Ipmin = Id · exp {q · (Vmin−VPS−Vt) / (nkT)} (7) Ipmax = Id · exp {q · (Vmax−VPS−Vt) / (nkT)} (8)

In the pixel shown in FIG. 2, the photocurrent Ipmin flowing from the photodiode PD when the gate voltage Vg1 of the MOS transistor T1 is Vmin, and the MOS
The photocurrent Ipmax flowing from the photodiode PD when the gate voltage Vg1 of the transistor T1 is Vmin is expressed by the following equations (9) and (10), respectively. Ipmin = Id · exp {q · (Vmin−VPS−2Vt) / (2nkT)} (9) Ipmax = Id · exp {q · (Vmax−VPS−2Vt) / (2nkT)} (10)

Accordingly, the luminance range D1 of the light incident on the photodiode PD corresponding to the change region of the gate voltage Vg of the MOS transistor Tx in the pixel of FIG. 3 is expressed in dB by 20 × log (Ipmax / Ipmin). Therefore, the following equation (11) is obtained. Also, the MO in the pixel of FIG.
Since the luminance range D2 of the light incident on the photodiode PD corresponding to the change region of the gate voltage Vg1 of the S transistor T1 is expressed in dB by 20 × log (Ipmax / Ipmin), the following equation (12) is used. Become like Here, e is the base of the natural logarithm. The luminance ranges D1 and D2 are respectively
This corresponds to the dynamic range of the pixel in FIG. 3 and the pixel in FIG. D1 = 20q · (Vmax−Vmin) / (nkT) · log (11) D2 = 20q · (Vmax−Vmin) / (2nkT) · log (12)

When the above equations (11) and (12) are compared, it is found that the luminance range D2 is １ ／ of the luminance range D1. That is, as shown in the pixel of FIG.
When two MOS transistors operating in the sub-threshold region connected in series to D are provided, one MOS transistor operates in the sub-threshold region connected in series to the photodiode PD as in the pixel of FIG. The dynamic range is halved as compared with the case where it is. Therefore, the dynamic range of the pixel in FIG.
In contrast to 0 [dB], the dynamic range of the pixel in FIG. 2 is 60 [dB], which is advantageous for capturing an image with contrast while keeping the dynamic range relatively large.

In the pixel as shown in FIG. 2, when light enters the photodiode PD, a photocurrent is generated, and the MOS
Due to the subthreshold characteristic of the transistor, a voltage having a value obtained by natural logarithmically converting the photocurrent is generated at the gates of the MOS transistors T1 and T2. With this voltage,
A current flows through the MOS transistor T2, and a charge equivalent to a value obtained by natural logarithmically converting the integrated value of the photocurrent is accumulated in the capacitor C. That is, a voltage proportional to a value obtained by natural logarithmically converting the integrated value of the photocurrent is generated at the connection node a between the capacitor C and the source of the MOS transistor T2. However, at this time, the MOS transistor T5 is kept OFF.

When the pulse signal φV is applied to the gate of the MOS transistor T5 to turn on the MOS transistor T5, the electric charge accumulated in the capacitor C is led out to the output signal line 6 as an output current. The current led out to the output signal line 6 is a value obtained by natural logarithmically converting the integrated value of the photocurrent. In this manner, a signal (output current) proportional to the logarithmic value of the incident light amount can be read.
After reading the signal, the transistor T5 is turned off.
Thereafter, the transistor T5 is turned off, the signal φD is set to low level, and the electric charge accumulated in the capacitor C is discharged to the signal line of the signal φD through the transistor T3, whereby the potentials of the capacitor C and the connection node a are initialized. Is done. By repeating such an operation at predetermined time intervals, it is possible to continuously capture a subject image that changes every moment.

<Second Example of Pixel Configuration> FIG. 4 schematically shows a partial configuration of a two-dimensional MOS solid-state imaging device according to another embodiment of the present invention. In the figure, G11 to Gm
n indicates pixels arranged in a matrix (matrix arrangement). Reference numeral 2 denotes a vertical scanning circuit, and rows (lines) 4-1 and 4
.., 4-n are sequentially scanned. Reference numeral 3 denotes a horizontal scanning circuit which outputs output signal lines 6-1 to 6-2,.
.. The photoelectric conversion signals derived in 6-m are sequentially read in the horizontal direction for each pixel. 5 is a power supply line. .., 4-n, output signal lines 6-1, 6-2,.
Not only that, but other lines (for example, a clock line and a bias supply line) are also connected, but these are omitted in FIG. 4 and are shown in each embodiment after FIG.

The output signal lines 6-1, 6-2,..., 6
As shown in the figure, a set of N-channel MOS transistors Q1 and Q2 is provided for each m. MOS transistor Q1 has a gate connected to DC voltage line 7, a drain connected to output signal line 6-1, and a source connected to DC voltage VPS '.
Is connected to the line 8. On the other hand, the drain of the MOS transistor Q2 is connected to the output signal line 6-1, the source is connected to the final signal line 9, and the gate is connected to the horizontal scanning circuit 3.

As described later, the pixels G11 to Gmn have
An N-channel MOS transistor Ta for outputting a signal based on photocharges generated in those pixels is provided. FIG. 5A shows a connection relationship between the MOS transistor Ta and the MOS transistor Q1. This MO
The S transistor Ta includes second, third, ninth, and tenth
In the embodiment, the fourth MOS transistor T4 includes the fourth MOS transistor T4.
In the eighth to eleventh and fourteenth embodiments, the second MOS
It corresponds to the transistor T2. Here, DC voltage VPS 'connected to the source of MOS transistor Q1 and MO
DC voltage V connected to the drain of S transistor Ta
The relationship with PD 'is VPD'> VPS ', and the DC voltage VPS'
Is, for example, a ground voltage (ground). In this circuit configuration, a signal is input to the gate of the upper MOS transistor Ta, and a DC voltage DC is constantly applied to the gate of the lower MOS transistor Q1. Therefore, the lower-stage MOS transistor Q1 is equivalent to a resistor or a constant current source.
The circuit (a) is a source follower-type amplifier circuit. In this case, what is amplified and output from the MOS transistor Ta may be a current.

The MOS transistor Q2 is connected to the horizontal scanning circuit 3
And is operated as a switch element. still,
As described later, an N-channel fifth MOS transistor T5 for switching is also provided in the pixel of each of the embodiments after FIG. If the fifth MOS transistor T5 is also included, the circuit of FIG. 5A is exactly as shown in FIG. 5B. That is, the MOS transistor T5 is inserted between the MOS transistor Q1 and the MOS transistor Ta. Here, the MOS transistor T5 is for selecting a row, and the transistor Q2 is for selecting a column. The configuration shown in FIGS. 4 and 5 is a configuration common to the second to fourteenth embodiments described below.

With the configuration as shown in FIG. 5, a large signal gain can be output. Therefore, since the pixel converts the photocurrent generated from the photosensitive element into a natural logarithm, the output signal is small as it is, but is amplified to a sufficiently large signal by the present amplifier circuit. (Not shown)). Further, the output signal lines 6-1, 6-2,..., 6 to which a plurality of pixels arranged in the column direction are connected without providing the transistor Q1 constituting the load resistance part of the amplifier circuit in the pixel. By providing every −m, the number of load resistances or constant current sources can be reduced, and the area occupied by the amplifier circuit on the semiconductor chip can be reduced.

<Second Embodiment> A second embodiment applied to each pixel of the second example of the pixel configuration shown in FIG. 4 will be described with reference to the drawings. FIG. 6 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 6, in this embodiment, FIG.
A fourth MOS transistor having a gate connected to the connection node a and performing current amplification according to the voltage applied to the connection node a
A transistor T4, a fifth MOS transistor T5 for row selection having a drain connected to the source of the MOS transistor T4, and a sixth MOS transistor T5 having a drain connected to the connection node a for initializing the potentials of the capacitor C and the connection node a.
MOS transistor T6 is added. M
The source of the OS transistor T5 is connected to an output signal line 6 (the output signal line 6 corresponds to 6-1 to 6-m in FIG. 4). Note that, similarly to the MOS transistors T1 to T3, the MOS transistors T4 to T6 are N-channel MOS transistors and have a back gate grounded.

The DC voltage VPD is applied to the drains of the MOS transistors T2 and T4, and the signal φV is input to the gate of the MOS transistor T5. The DC voltage V RB is applied to the source of the MOS transistor T6, and the signal φVRS is input to its gate.
In this embodiment, the MOS transistors T1, T
3 operates in the sub-threshold region as in the first embodiment (FIG. 2), so that compared with the case where one MOS transistor operates in this sub-threshold region,
The dynamic range can be narrowed. Also, M
The OS transistors T1 to T3, T5 and the capacitor C perform the same operation as in the first embodiment. Less than,
The operation of the pixel having such a configuration will be described.

When light enters the photodiode PD, a photocurrent is generated. Due to the subthreshold characteristics of the MOS transistors T1 and T3, a voltage having a value obtained by natural logarithmic conversion of the photocurrent is applied to the gates of the MOS transistors T1 and T2. appear. With this voltage, the MOS transistor T
2, a charge equivalent to a value obtained by natural logarithmically converting the integrated value of the photocurrent is accumulated in the capacitor C.
That is, a voltage proportional to a value obtained by natural logarithmically converting the integrated value of the photocurrent is generated at the connection node a between the capacitor C and the source of the MOS transistor T2. However, at this time, the MOS transistors T5 and T6 are turned off.
It is in the F state.

When a pulse signal φV is applied to the gate of the MOS transistor T5 to turn on the MOS transistor T5, a current proportional to the voltage applied to the gate of the MOS transistor T4 is generated.
Through the output signal line 6. Since the voltage applied to the gate of the MOS transistor T4 is a voltage applied to the connection node a, the current led out to the output signal line 6 is a value obtained by natural logarithmically converting the integrated value of the photocurrent.

In this manner, a signal (output current) proportional to the logarithmic value of the amount of incident light can be read. After reading the signal, the MOS transistor T5 is turned off, and the MOS transistor T6 is turned on by applying a high-level signal φVRS to the gate of the MOS transistor T6.
As a result, the potentials of the capacitor C and the connection node a can be initialized.

<Third Embodiment> A third embodiment will be described with reference to the drawings. FIG. 7 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 7, in this embodiment, the MO
By applying the signal φD to the drain of the S transistor T2, the potentials of the capacitor C and the connection node a are initialized, thereby eliminating the MOS transistor T6. Other configurations are the same as those of the second embodiment (FIG. 6). Note that during the high level period of the signal φD, integration is performed by the capacitor C.
2, the voltage of the capacitor C and the gate of the MOS transistor T4 become substantially the low level voltage of the clock φD (reset). In the present embodiment, the configuration is simplified because the MOS transistor T6 can be omitted.

In this embodiment, the signal φD is set to a high level (for example, a voltage substantially equal to the DC voltage VPD),
A charge equivalent to a value obtained by natural logarithmically converting the integrated value of the photocurrent is stored in the capacitor C. Then, the MOS transistor T5 is turned on at a predetermined timing, and the current proportional to the voltage applied to the gate of the MOS transistor T4 is set to MO.
It is led to the output signal line 6 through the S transistors T4 and T5. Thereafter, when the MOS transistor T5 is turned off and the signal φD is set to a low level (a voltage lower than the DC voltage VPS), the electric charge of the capacitor C is discharged to the signal line of the signal φD through the MOS transistor T2. The voltage of the connection node a is initialized.

<Fourth Embodiment> A fourth embodiment will be described with reference to the drawings. FIG. 8 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 7 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 8, in this embodiment, the MO
DC voltage VPD is applied to the drain of S transistor T2, and capacitor C and MOS transistor T
4 is deleted. Other configurations are the same as those of the third embodiment (FIG. 7).

In the circuit having such a configuration, by changing the gate voltage of the MOS transistor T2 in a natural logarithmic manner with respect to the photocurrent generated in the photodiode PD, the gate voltage is proportional to the natural logarithm with respect to the photocurrent. The drain current having the value flows through the MOS transistor T2. When the signal φV is applied to the gate of the MOS transistor T5 to turn it on, a drain current having a value proportional to the logarithm of the photocurrent is led out to the output signal line 6 through the MOS transistor T5. At this time, the drain voltage of the MOS transistor Q1, which is determined by the on-state resistance of the MOS transistor T2 and the MOS transistor Q1 (FIG. 4) and the current flowing through them, appears on the output signal line 6 as a signal. After the signal is read in this way,
The MOS transistor T5 turns off.

In this embodiment, the integration of the optical signal with the capacitor C is not performed as in the third embodiment, so that the integration time is not required, and the reset of the capacitor C is not required. As a result, the signal processing can be speeded up accordingly. Further, in the present embodiment, as compared with the third embodiment, since the capacitor C and the MOS transistor T4 can be omitted, the configuration is further simplified and the pixel size can be reduced.

<Fifth Embodiment> A fifth embodiment will be described with reference to the drawings. FIG. 9 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 8 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 9, a seventh MOS transistor T connected between a photodiode PD and a MOS transistor T1 is connected to a pixel of the fourth embodiment (FIG. 8).
7 and a capacitor C1 having one end connected to the gate and drain of the MOS transistor T1. That is, the drain of the MOS transistor T7 is connected to the anode of the photodiode PD, and the source is connected to the gate and the drain of the MOS transistor T1. The signal φS is input to the gate of the MOS transistor T7, and the signal φS is input to the other end of the capacitor C1.
VRS is input. Note that the MOS transistor T7 also
Similar to the OS transistors T1 to T3 and T5, an N-channel MOS transistor has a back gate grounded.

In the pixel having such a circuit configuration, the signal φVRS applied to the capacitor C1 is set to the low level and the MOS transistor T7 is turned on to operate the MOS transistors T1 and T3 in the sub-threshold region. Therefore, similar to the fourth embodiment,
A voltage obtained by logarithmically converting the photocurrent flowing from the photodiode PD appears at the connection node a. Then, by turning on the MOS transistor T5, the logarithmically converted output signal is output to the output signal line 6 through the MOS transistors T2 and T5.

Also, when resetting each pixel, FIG.
The operation is performed as shown in the timing chart of FIG. First, after the pulse signal φV is applied, the signal φS is set to low level to turn off the MOS transistor T7, and the reset operation starts. Next, the signal φVRS is set to a high level, and M
By increasing the gate voltage of the OS transistor T1, the amount of charge flowing from the source of the MOS transistor T3 is increased.

Thus, the MOS transistor T
1, T3 gate and drain, MOS transistor T
The positive charge stored in the gate of C2 and the capacitor C1 is quickly recombined. Then, the signal φVRS is changed to low level to reset the potentials of the MOS transistors T1 and T3 to the initial state. At this time, the pulse signal φV is applied to the gate of the MOS transistor T5,
The output voltage at the time of this reset is led out to the output signal line 6 for each pixel, and can be detected as correction data for correcting the output from each pixel. After detecting the correction data and turning off the MOS transistor T5,
When the signal φS is set to the high level, the MOS transistor T7
Is turned on to prepare for the next imaging operation.

<Sixth Embodiment> A sixth embodiment will be described with reference to the drawings. FIG. 11 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 11, the circuit configuration is such that the capacitor C1 is removed from the pixel of the fifth embodiment (FIG. 9). The signal φVPS is input to the source of the MOS transistor T3. The signal .phi.VPS is a binary voltage signal. The voltage for operating the MOS transistors T1 and T3 in the subthreshold region is set to a high level at a voltage substantially equal to the DC voltage VPS, and the voltage applied to the MOS transistor T3 is lower than this voltage. A voltage at which a larger current can flow than when a high-level voltage is applied is set to a low level.

In the pixel having such a circuit configuration, the MO
By turning the signal φVPS given to the source of the S transistor T3 to high level and turning on the MOS transistor T7, the MOS transistors T1 and T3 operate in the subthreshold region. Therefore, as in the fifth embodiment, a voltage obtained by logarithmically converting the photocurrent flowing from the photodiode PD appears at the connection node a. And
By turning on the MOS transistor T5, the logarithmically converted output signal is output to the MOS transistors T2 and T5.
To the output signal line 6 through

Also, when resetting each pixel, FIG.
The operation is performed as shown in the timing chart of FIG. First, after the pulse signal φV is applied, the signal φS is set to low level to turn off the MOS transistor T7, and the reset operation starts. Next, the signal φVPS is set to low level, and M
By reducing the source voltage of the OS transistor T3, the amount of charge flowing from the source of the MOS transistor T3 is increased.

Thus, the MOS transistor T
The positive charges stored in the gate and drain of T1, and the gate of the MOS transistor T2 are quickly recombined. Then, the signal φVPS is set to a high level to
The potentials of the S transistors T1 and T3 are reset to the initial state. At this time, the pulse signal φV is
The output voltage at the time of resetting is applied to the gate of the transistor T5 and output to the output signal line 6 for each pixel, and can be detected as correction data for correcting the output from each pixel. In this way, the correction data is detected and the MO
After turning off the S transistor T5, the signal φS is set to the high level, and the MOS transistor T7 is turned on to prepare for the next imaging operation.

<Seventh Embodiment> A seventh embodiment will be described with reference to the drawings. FIG. 13 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 11 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 13, the pixel of the sixth embodiment (FIG. 11) has a constant current source 10, an eighth MOS transistor T8 having a drain connected to the constant current source 10, and a MOS transistor T3 having a drain. And the ninth and tenth MOS transistors T9 and T10 to which the source of the above is connected. The source and the gate of the MOS transistor T1 are connected to the source of the MOS transistor T8, and the signal φSW is applied to the gate. MOS transistor T9 has a source to which DC voltage VPSH is applied and a gate having a signal φ.
SW1 is provided, and the MOS transistor T10 is
DC voltage VPSL is applied to its source, and signal φSW2 is applied to its gate. Note that the MOS transistors T8 to T10 are also the MOS transistors T1 to T10.
Similar to 3, T5 and T7, an N-channel MOS transistor has a back gate grounded.

The operation of the pixel having such a configuration will be described below. The DC voltage VPSH is a voltage for operating the MOS transistors T1 and T3 in the sub-threshold region, and the DC voltage VPSL is a constant current source 1
This is a voltage for operating the MOS transistors T1 and T3 to flow a current from 0 to the MOS transistors T1 and T3.

In the pixel having such a circuit configuration, the MO
Turn on the S transistor T9 and turn on the MOS transistor T
By applying the DC voltage VPSH to the source of No. 3 and turning on the MOS transistor T7, the MOS transistors T1 and T3 are operated in the sub-threshold region. At this time, the signal φSW and the signal φSW2 are set to low level, and the MOS transistors T8 and T10 are turned off.
Set to FF. Therefore, similarly to the sixth embodiment, a voltage obtained by logarithmically converting the photocurrent flowing from the photodiode PD appears at the connection node a. Then, the MOS transistor T5
Is turned on, the logarithmically converted output signal is output to the output signal line 6 through the MOS transistors T2 and T5.

Further, when resetting each pixel, FIG.
The operation is performed as shown in the timing chart of FIG. First, after the pulse signal φV is supplied, first, the signal φSW1 is set to the low level to turn off the MOS transistor T9, and the signal φSW2 is set to the high level to turn on the MOS transistor T10. Apply the voltage VPSL. Then, the signal φSW is set to high level to turn on the MOS transistor T8, and the signal φS is set to low level to turn off the MOS transistor T7.

As described above, the constant current source 10
A current flows through the transistors T1 and T3, and the MOS transistor T
1, so that no photocurrent flows through T3. At this time, a constant current flows from the constant current source 10 to the MOS transistors T1 and T3 via the MOS transistor T8. Therefore,
Since the source-gate voltages of the MOS transistors T1 and T3 are determined by the drain currents of the MOS transistors T1 and T3, the gate voltages of the MOS transistors T1 and T3 are reset to the initial values.

As described above, the MOS transistors T1, T
3 is reset to the initial value, a pulse signal φV is applied to the gate of the MOS transistor T5,
A signal when the OS transistors T1 and T3 are reset is output to the output signal line 6. Then, first, the signal φS
Set W to low level to turn off MOS transistor T8
To Next, the signal φSW1 is set to the high level to set the MOS
The transistor T9 is turned on, the signal φSW2 is set to low level to turn off the MOS transistor T10, and the DC voltage VPSH is applied to the source of the MOS transistor T1.
give. Then, the signal φS is set to the high level to set the MOS
The transistor T7 is turned on, so that the next imaging can be performed.

In the fifth to seventh embodiments, the output signal read at the time of resetting is serially output for each pixel from the signal line 9 in FIG. 4, and is stored in a memory in a subsequent circuit as correction data for each pixel. Remember. And
If the output current at the time of actual imaging is corrected for each pixel using the stored correction data, a component due to pixel variation can be removed from the output signal. This correction method is
This can also be realized by providing a memory such as a line memory in a pixel.

In the fifth to seventh embodiments, the second
As in the embodiment (FIG. 6), the MOS transistor T2
Of the capacitor C to which the DC voltage VPS is applied to the other end, the gate of the MOS transistor T4, and the MOS transistor T for resetting the capacitor C.
6 and the source of the MOS transistor T4 may be connected to the drain of the MOS transistor T5. Also, as in the third embodiment (FIG. 7), the signal φD is applied to the drain of the MOS transistor T2, and the MOS transistor T6 is deleted from the configuration of the above-described second embodiment (FIG. 6). A configuration may be adopted.

Further, in the fifth to seventh embodiments, M
OS transistor T7 is a depletion type MOS
It may be a transistor or a P-channel MOS transistor. By making MOS transistor T7 a depletion type MOS transistor, the high level voltage of signal φS applied to its gate can be reduced, and the same voltage as the high level signal applied to other MOS transistors can be achieved. become. Also MO
Since the ON / OFF operation of the S transistor T7 is not affected by the MOS transistors T1 and T3, it is not necessary to provide another power supply for supplying the signal φS.

<Eighth Embodiment> An eighth embodiment will be described with reference to the drawings. FIG. 15 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 8 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 15, to the pixel of the fourth embodiment (FIG. 8), the drain of the MOS transistor T3 is added to the drain, and the eleventh MOS transistor T11 applied with the DC voltage VPS to the source is added. It has a circuit configuration. Signal φSW3 is applied to the gate of MOS transistor T11. By connecting the MOS transistor T11 in this manner, the MOS transistor T11 functions as a bypass MOS transistor between the source of the MOS transistor T1 and the signal line of the DC voltage VPS. The operation of the pixel having such a circuit configuration will be described below. Incidentally, the MOS transistor T
Similarly to the MOS transistors T1 to T3 and T5, an N-channel MOS transistor 11 has a back gate grounded.

When the signal φSW3 is at a high level, M
Since the OS transistor T11 is turned on, the DC voltage VPS is applied to the source of the MOS transistor T1. Therefore, since only the MOS transistor T1 operates in the sub-threshold region, the dynamic range of the pixel becomes 1
It becomes as wide as 20 [dB]. When the signal φSW3 is set to low level, the MOS transistor T11 is turned off.
Is applied. Therefore, the MOS transistors T1, T3
Operate in the sub-threshold region, so that the dynamic range of the pixel is narrowed to 60 [dB]. Thus, according to the pixel of the present embodiment, the MOS transistor T
By turning ON / OFF 11, the dynamic range of each pixel can be adjusted.

The circuit configuration of each pixel is different from the source of the first MOS transistor T1 used in this embodiment and the DC voltage V
The eleventh MOS transistor T11 serving as a bypass MOS transistor between the PS signal line and the PS signal line may have a circuit configuration applied to the first to third and fifth to seventh embodiments.

<Ninth Embodiment> A ninth embodiment will be described with reference to the drawings. FIG. 16 is a circuit diagram illustrating a configuration of a pixel provided in a solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 16, in this embodiment, the MOS transistors T2, T4 to
T6 and the capacitor C have the same configuration as the pixel in FIG. In such a pixel of FIG. 16, a DC voltage VPS is applied to the anode of the photodiode PD,
DC voltage VPD is applied to the drain of S transistor T3, and its source is connected to the gate and drain of MOS transistor T1. In addition, the gate of the second MOS transistor T2 and the cathode of the photodiode PD are connected to the source of the MOS transistor T1. Also, M
The DC voltage VPG is applied to the gate of the OS transistor T3. The operation of the pixel having such a configuration will be described below.

When light enters the photodiode PD, a photocurrent is generated. Due to the subthreshold characteristics of the MOS transistors T1 and T3, a voltage obtained by natural logarithmically converting the photocurrent is applied to the source and the MO of the MOS transistor T1.
It occurs at the gate of the S transistor T2. At this time, the negative photocharge generated in the photodiode PD is MO
Since the current flows into the source of the S transistor T1, the source voltage of the MOS transistor T1 becomes lower as more intense light enters.

When a voltage which changes in a natural logarithm with respect to the photocurrent appears at the gate of the MOS transistor T2, a high-level signal φVRS is applied to the gate of the MOS transistor T6 to turn on the MOS transistor T6. Then, the voltages of the capacitor C and the connection node a are reset. At this time, the voltage of the connection node a is reset to a voltage lower than the surface potential determined by the gate voltage of the MOS transistor T2 so that the MOS transistor T2 can operate. Next, the signal φV
Set RS to low level to turn off MOS transistor T6
After that, the signal φV is set to the high level to turn on the MOS transistor T5.

At this time, the voltage of the connection node a is reset by the MOS transistor T6, so that the MOS
The transistor T2 operates, and the MOS transistor T
A voltage obtained by sampling the surface potential determined by the gate voltage of No. 2 is applied to the gate of the MOS transistor T4. Therefore, since the gate voltage of the MOS transistor T4 becomes a value proportional to the value obtained by logarithmically converting the incident light amount, when the MOS transistor T5 is turned on, the current or voltage at which the photocurrent becomes a value obtained by natural logarithmically converting the photocurrent is obtained. ,
The signal is output to the output signal line 6 via the MOS transistors T4 and T5. When the signal (output current) proportional to the logarithmic value of the incident light amount is read in this way, the MOS transistor T5 is turned off.

Note that, as in the third embodiment (FIG. 7), M
The structure is such that a pulse signal (for example, φVPD ′) is applied to the drain of the OS transistor T2.
By allowing the voltage of the connection node a to be reset by the MOS transistor T2 using VPD ′, the configuration may be such that the MOS transistor T6 is omitted from the pixel having the configuration of FIG.

<Tenth Embodiment> A tenth embodiment will be described with reference to the drawings. FIG. 17 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 16 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 17, in the present embodiment, the MOS transistors T2 and T6 in the pixel of FIG.
A DC voltage VPS is applied to the drain of the MOS transistor T2, and a DC voltage VPD is applied to the other end of the capacitor C having one end connected to the source of the MOS transistor T2. The DC voltage V RB is applied to the drain of the MOS transistor T6, and the source of the MOS transistor T4
Are connected. For other configurations, see FIG.
This is the same as the configuration of the six pixels. The DC voltage V RB applied to the source of the MOS transistor T6 is higher than V PS. The operation of the pixel having such a configuration will be described below.

When light is incident on the photodiode PD, a photocurrent is generated. Due to the subthreshold characteristics of the MOS transistors T1 and T3, the voltage obtained by natural logarithmically converting the photocurrent is applied to the source and the MO of the MOS transistor T1.
It occurs at the gate of the S transistor T2. At this time, the negative photocharge generated in the photodiode PD is MO
Since the current flows into the source of the S transistor T1, the source voltage of the MOS transistor T1 becomes lower as more intense light enters.

When a voltage which changes in a natural logarithm with respect to the photocurrent appears at the gate of the MOS transistor T2, a positive charge flows from the capacitor C via the MOS transistor T2. At this time, the amount of positive charge flowing from the capacitor C is determined by the gate voltage of the MOS transistor T2. In other words, when strong light is
As the source voltage of the S transistor T1 becomes lower,
The amount of positive charges flowing from the capacitor C is large.

In this manner, positive charges flow from the capacitor C, and the voltage at the connection node a becomes a value proportional to the value obtained by logarithmically converting the integrated value of the incident light amount. And the pulse signal φ
When V is applied to turn on the MOS transistor T5,
A current having a value obtained by converting the integral value of the photocurrent into a natural logarithm is led out to the output signal line 6 via the MOS transistors T4 and T5. When the signal (output current) proportional to the logarithmic value of the incident light amount is read in this way, the MOS transistor T5 is turned off. Then, a low-level pulse signal φVRS is applied to the gate of the MOS transistor T6 to reset the connection node “a”.
2 is reset to a voltage higher than the surface potential determined by the gate voltage.

Note that, as in the third embodiment (FIG. 7), M
The structure is such that a pulse signal (for example, φVPS) is applied to the drain of the OS transistor T2.
By allowing the voltage of the connection node a to be reset by the MOS transistor T2 by the PS, FIG.
The configuration may be such that the MOS transistor T6 is omitted from the pixel having the configuration described above. In this case, the pulse signal φVPS applied to the drain of the MOS transistor T2 is supplied from a power supply line different from the DC voltage VPS applied to the anode of the photodiode PD.

<Eleventh Embodiment> An eleventh embodiment will be described with reference to the drawings. FIG. 18 is a circuit diagram illustrating a configuration of a pixel provided in a solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 16 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 18, in this embodiment, M
The MOS transistor T is connected to the source of the OS transistor T2.
5 is connected to the capacitor C and MO.
The configuration is such that the S transistors T4 and T6 are omitted. Other configurations are the same as those of the ninth embodiment (FIG. 16). The operation of the pixel having such a configuration will be described below.

When light enters the photodiode PD, a photocurrent is generated. Due to the subthreshold characteristics of the MOS transistors T1 and T3, the voltage obtained by natural logarithmically converting the photocurrent is applied to the source and the MO of the MOS transistor T1.
It occurs at the gate of the S transistor T2. At this time, the negative photocharge generated in the photodiode PD is MO
Since the current flows into the source of the S transistor T1, the source voltage of the MOS transistor T1 becomes lower as more intense light enters.

When a voltage which has changed in a natural logarithmic manner with respect to the photocurrent appears at the gate of the MOS transistor T2, a pulse signal φV is supplied to turn on the MOS transistor T5, and the photocurrent is converted into a natural logarithm. Is output to the output signal line 6 via the MOS transistors T2 and T5. When a signal (output current) proportional to the logarithmic value of the incident light amount is read out in this manner,
Turn off the MOS transistor T5.

<Twelfth Embodiment> A twelfth embodiment will be described with reference to the drawings. FIG. 19 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 18 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 19, in the present embodiment, the pixels of the eleventh embodiment (FIG. 18) are provided with a constant current source 10 and
The circuit configuration is such that an eighth MOS transistor T8 whose source is connected to the constant current source 10 is added. The MOS transistor T8 has a drain connected to the MOS transistor T8.
1 is connected, and the signal φ
SW is provided. Hereinafter, the operation of the pixel having such a configuration will be described.

First, the signal φSW is set to low level to
The S transistor T8 is turned off. At this time, the eleventh
Similarly to the first embodiment, when light is incident on the photodiode PD, a photocurrent is generated. Due to the sub-threshold characteristics of the MOS transistors T1 and T3, the voltage obtained by natural logarithmically converting the photocurrent is applied to the source and the MOS transistor T1. It occurs at the gate of the MOS transistor T2. In this manner, the voltage that has changed in a natural logarithmic manner with respect to the photocurrent is M
When appearing at the gate of the OS transistor T2, a pulse signal φV is supplied to turn on the MOS transistor T5, and a current having a value obtained by natural logarithmic conversion of the photocurrent is output via the MOS transistor T2 and T5 to the output signal line. 6 is derived. When the signal (output current) proportional to the logarithmic value of the incident light amount is read in this way, the MOS transistor T5 is turned off.

When resetting each pixel, FIG.
The operation is performed as shown in the timing chart of FIG. First, when the pulse signal φV is applied to the gate of the MOS transistor T5 and the output signal is read, first, the signal φSW is set to the high level to turn on the MOS transistor T8, thereby setting the source of the MOS transistor T1. The current source 10 is connected.

At this time, a current substantially equal to the current flowing through constant current source 10 flows through MOS transistors T1 and T3. Therefore, at this time, the voltage appearing at the source of the MOS transistor T1 is determined by the current flowing through the constant current source 10 and becomes a voltage corresponding to the variation in the threshold value of the MOS transistor T1 of each pixel. Thus, MO
When a current flows through the S transistors T1 and T3, a pulse signal φV is supplied to the gate of the MOS transistor T5 to read an output signal. At this time, the read output signal is
Since the value becomes a value corresponding to the threshold voltage of the MOS transistor T1, it is possible to detect a variation in sensitivity of each pixel. Then, finally, the signal φSW is set to low level to turn off the MOS transistor T8 so that the next imaging operation can be performed.

In this embodiment, the output signal read at the time of this reset is serially output for each pixel from the signal line 9 in FIG. 4, and is stored in a memory as correction data for each pixel in a subsequent circuit. Then, if the output current at the time of actual imaging is corrected for each pixel using the stored correction data, it is possible to remove components due to pixel variations from the output signal. This correction method can also be realized by providing a memory such as a line memory in a pixel.

The circuit configuration of each pixel may be such that the reset constant current source 10 and the eighth MOS transistor T8 used in this embodiment are applied to the ninth and tenth embodiments. .

<Thirteenth Embodiment> A thirteenth embodiment will be described with reference to the drawings. FIG. 21 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 18 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 21, a DC voltage VPD is applied to the drain of the pixel of the eleventh embodiment (FIG. 18), and a MOS transistor T is applied to the source.
Eleventh MOS transistor T1 to which the third source is connected
1 is added to the circuit configuration. Signal φSW3 is applied to the gate of MOS transistor T11.
By connecting the MOS transistor T11 in this manner, the MOS transistor T11 functions as a bypass MOS transistor between the drain of the MOS transistor T1 and the signal line of the DC voltage VPD. The operation of the pixel having such a circuit configuration will be described below.

When the signal φSW3 is at a high level, M
Since the OS transistor T11 is turned on, the DC voltage VPD is applied to the drain and the gate of the MOS transistor T1. Therefore, since only the MOS transistor T1 operates in the sub-threshold region, the dynamic range of the pixel is widened to 120 [dB]. Also, the signal φSW
3 is low, the MOS transistor T11
Is turned off, the DC voltage VPD is applied to the drain of the MOS transistor T3. Therefore, since the MOS transistors T1 and T3 operate in the sub-threshold region, the dynamic range of the pixel is narrowed to 60 [dB]. Thus, according to the pixel of the present embodiment, the MOS
By turning on / off the transistor T11,
The dynamic range of each pixel can be adjusted.

The circuit configuration of each pixel is the same as that of the ninth MOS transistor T11 used as a bypass MOS transistor between the drain of the first MOS transistor T1 and the signal line of the DC voltage VPD used in the present embodiment. , First
The circuit configuration may be applied to the 0th and twelfth embodiments.

<Fourteenth Embodiment> A fourteenth embodiment will be described with reference to the drawings. FIG. 22 is a circuit diagram illustrating a configuration of a pixel provided in a solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG.
Detailed description is omitted.

As shown in FIG. 22, the pixel of the fourth embodiment (FIG. 8) is provided with the source of the MOS transistor T3 at the drain and the gate, and the twelfth MOS transistor T12 applied with the DC voltage VPS at the source. The circuit configuration is added. Therefore, the MOS transistor operating in the sub-threshold region is the MOS transistor T
Since the number of pixels is 1, T3, and T12, the dynamic range of the pixel having such a circuit configuration can be narrowed to 1/3 as compared with the pixel having the circuit configuration of FIG. Note that M
The OS transistor T12 also has the MOS transistors T1 to T1.
Similarly to T3 and T5, an N-channel MOS transistor has a back gate grounded.

The twelfth MOS transistor T12 operating in such a sub-threshold region may be a pixel having a circuit configuration similar to that of each pixel of the first to third and fifth to seventh embodiments. . In the pixels having the ninth to thirteenth circuit configurations, the source is connected to the drain and the gate of the MOS transistor T3, the DC voltage VPG is applied to the gate, and the DC voltage VPG is applied to the drain.
By adding the twelfth MOS transistor T12 to which PD is applied, a pixel having a circuit configuration in which the dynamic range is narrowed may be used.

In each of the embodiments described above, the reading of signals from each pixel may be performed using a charge-coupled device (CCD). In this case, the charge can be read out to the CCD by providing a potential barrier having a variable potential level corresponding to the MOS transistor T5.

The MOS transistor T which is an active element in the pixel in the first to fourteenth embodiments described above.
1 to T12 may be replaced with MOS transistors of opposite polarity. FIGS. 24 and 27 to 39 show a first example in which the MOS transistors of the pixels according to the first to fourteenth embodiments are constituted by MOS transistors having opposite polarities.
The fifth to twenty-eighth embodiments are shown. Therefore, the polarity of the connection and the polarity of the applied voltage are reversed in FIGS. 24 and 27 to 39. For example, in FIG. 24 (fifteenth embodiment), the photodiode PD has a DC voltage V
PD is applied and the cathode is the first MOS transistor T1
Are connected to the drain and gate of the third MOS transistor. The DC voltage VPS is applied to the source of the second MOS transistor T2 whose drain and gate are connected to the source of the first MOS transistor T1.

When a pixel as shown in FIG. 24 performs logarithmic conversion, the voltage of the DC voltage VPS and the DC voltage VPD are
PS> VPD, which is the opposite of FIG. 2 (first embodiment). The output voltage of the capacitor C is a voltage having a high initial value and drops by integration. In addition, the fifth to twelfth M
When turning on the OS transistors T5 to T12,
Apply a low voltage to the gate. Further, in the embodiment of FIG. 35 (the twenty-fourth embodiment), when turning on the sixth MOS transistor T6, a high voltage is applied to the gate. As described above, when MOS transistors having opposite polarities are used, although the voltage relationship and the connection relationship are partially different, the configuration is substantially the same, and the basic operation is the same. 39 to 39 are only shown in the drawings, and the description of the configuration and operation is omitted.

FIG. 23 is a block diagram showing the overall configuration of a solid-state imaging device including pixels according to the fifteenth embodiment. FIG. 23 is a block diagram showing the overall configuration of a solid-state imaging device including pixels according to the sixteenth to twenty-eighth embodiments. FIG. 25 is a block diagram showing the configuration of the circuit. 23 and 25,
1 and 4 (the same role portions) are denoted by the same reference numerals, and description thereof is omitted. Hereinafter, the configuration of FIG. 25 will be briefly described. Output signal lines 6 arranged in the column direction
, 6-m, P-channel MO
The S transistor Q1 and the P-channel MOS transistor Q2 are connected. MOS transistor Q1 has a gate connected to DC voltage line 7, and a drain connected to output signal line 6.
-1 and the source is connected to line 8 of the DC voltage VPS '. On the other hand, the drain of the MOS transistor Q2 is connected to the output signal line 6-1, the source is connected to the final signal line 9, and the gate is connected to the horizontal scanning circuit 3. Here, the MOS transistor Q1 is connected together with the P-channel MOS transistor Ta in the pixel as shown in FIG.
An amplifier circuit as shown in FIG. In addition, MO
The S transistor Ta corresponds to the fourth MOS transistor T4 in the sixteenth, seventeenth, twenty-third and twenty-fourth embodiments, and the second MOS transistor T2 in the eighteenth to twenty-second and twenty-fifth to twenty-eighth embodiments. Is equivalent to

In this case, MOS transistor Q1 is connected to MO
It serves as a load resistance or a constant current source for the S transistor Ta. Therefore, the relationship between DC voltage VPS 'connected to the source of transistor Q1 and DC voltage VPD' connected to the drain of MOS transistor Ta is VPD '<V
PS ′, and the DC voltage VPD ′ is, for example, a ground voltage (ground). The drain of the transistor Q1 is connected to the transistor Ta, and a DC voltage is applied to the gate. The P-channel MOS transistor Q2 is controlled by the horizontal scanning circuit 3, and leads the output of the amplifier circuit to the final signal line 9. As in the sixteenth to twenty-eighth embodiments,
Considering the fifth MOS transistor T5 provided in the pixel, the circuit of FIG. 26A is represented as shown in FIG.

[0122]

As described above, according to the present invention, when the photoelectric conversion means for logarithmically converting the electric signal generated by the photoelectric conversion element is used, for example, the imaging is performed by using a plurality of transistors operating in a subthreshold region. The possible luminance range can be narrowed, and the imageable luminance range can be made closer to the luminance range of the subject to be actually imaged. As described above, since the luminance range of each pixel corresponds to the luminance range of the subject, when an image is reproduced using the photoelectrically converted output signal, a good image with high contrast can be obtained.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram for explaining the overall configuration of a two-dimensional solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of one pixel according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating a configuration of a pixel.

FIG. 4 is a block circuit diagram for explaining the overall configuration of a two-dimensional solid-state imaging device according to an embodiment of the present invention.

FIG. 5 is a partial circuit diagram of FIG. 4;

FIG. 6 is a circuit diagram showing a configuration of one pixel according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of one pixel according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of one pixel according to a fourth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a configuration of one pixel according to a fifth embodiment of the present invention.

FIG. 10 is a timing chart of a signal applied to each element of a pixel used in the fifth embodiment.

FIG. 11 is a circuit diagram showing a configuration of one pixel according to a sixth embodiment of the present invention.

FIG. 12 is a timing chart of a signal applied to each element of a pixel used in the sixth embodiment.

FIG. 13 is a circuit diagram showing a configuration of one pixel according to a seventh embodiment of the present invention.

FIG. 14 is a timing chart of signals applied to each element of a pixel used in the seventh embodiment.

FIG. 15 is a circuit diagram showing a configuration of one pixel according to an eighth embodiment of the present invention.

FIG. 16 is a circuit diagram showing a configuration of one pixel according to a ninth embodiment of the present invention.

FIG. 17 is a circuit diagram showing a configuration of one pixel according to a tenth embodiment of the present invention.

FIG. 18 is a circuit diagram showing a configuration of one pixel according to an eleventh embodiment of the present invention.

FIG. 19 is a circuit diagram showing a configuration of one pixel according to a twelfth embodiment of the present invention.

FIG. 20 is a timing chart of a signal applied to each element of a pixel used in the twelfth embodiment.

FIG. 21 is a circuit diagram showing a configuration of one pixel according to a thirteenth embodiment of the present invention.

FIG. 22 is a circuit diagram showing a configuration of one pixel according to a fourteenth embodiment of the present invention.

FIG. 23 is a block circuit diagram for explaining the overall configuration of a two-dimensional solid-state imaging device according to the present invention in the case where an active element in a pixel is configured by a P-channel MOS transistor.

FIG. 24 is a circuit diagram showing a configuration of one pixel according to a fifteenth embodiment of the present invention.

FIG. 25 is a block circuit diagram for explaining the overall configuration of a two-dimensional solid-state imaging device according to the present invention in the case of an embodiment in which active elements in pixels are configured by P-channel MOS transistors.

FIG. 26 is a circuit diagram of part of FIG. 25;

FIG. 27 is a circuit diagram showing a configuration of one pixel according to a sixteenth embodiment of the present invention.

FIG. 28 is a circuit diagram showing a configuration of one pixel according to a seventeenth embodiment of the present invention.

FIG. 29 is a circuit diagram showing a configuration of one pixel according to an eighteenth embodiment of the present invention.

FIG. 30 is a circuit diagram showing a configuration of one pixel according to a nineteenth embodiment of the present invention.

FIG. 31 is a circuit diagram showing a configuration of one pixel according to a twentieth embodiment of the present invention.

FIG. 32 is a circuit diagram showing a configuration of one pixel according to a twenty-first embodiment of the present invention.

FIG. 33 is a circuit diagram showing a configuration of one pixel according to a twenty-second embodiment of the present invention.

FIG. 34 is a circuit diagram showing a configuration of one pixel according to a twenty-third embodiment of the present invention.

FIG. 35 is a circuit diagram showing a configuration of one pixel according to a twenty-fourth embodiment of the present invention.

FIG. 36 is a circuit diagram showing a configuration of one pixel according to a twenty-fifth embodiment of the present invention.

FIG. 37 is a circuit diagram showing a configuration of one pixel according to a twenty-sixth embodiment of the present invention.

FIG. 38 is a circuit diagram showing a configuration of one pixel according to a twenty-seventh embodiment of the present invention.

FIG. 39 is a circuit diagram showing a configuration of one pixel according to a twenty-eighth embodiment of the present invention.

FIG. 40 is a graph showing a luminance distribution of a subject and a relationship between an input signal to an output device and a signal level of an output of an area sensor.

FIG. 41 is a graph showing a luminance distribution of a subject and a relationship between an input signal to an output device and a signal level of an output of an area sensor.

FIG. 42 is a view showing the relationship between the dynamic range of a LOG sensor and the level of a signal sent to an output device.

[Explanation of symbols]

 G11 to Gmn pixel 2 vertical scanning circuit 3 horizontal scanning circuit 4-1 to 4-n row selection line 6-1 to 6-m output signal line PD photodiode T1 to T12 first to twelfth MOS transistor C, C1 capacitor

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M118 AA02 AB01 BA06 BA14 CA02 FA06 5C024 BX00 CX43 GX03 GY31 GY35 GY39

Claims (14)

[Claims] A photoelectric conversion unit having a photoelectric conversion element for generating an electric signal according to an amount of incident light; and a lead-out path for leading an output signal of the photoelectric conversion unit to an output signal line.
In the solid-state imaging device in which the photoelectric conversion unit converts the electric signal into a natural logarithm, a maximum luminance in a luminance region where the solid-state imaging device can image is defined as Ma, and a minimum luminance in a luminance region where the solid-state imaging device can image. Is Mi, and 20 × log (Ma / M
A solid-state imaging device capable of imaging at i) of 60 [dB] or less. 2. 20 × log (Ma / Mi) is 40 [dB].
The solid-state imaging device according to claim 1, wherein imaging is possible at a level of 60 dB or less. 3. A photoelectric conversion device having a photoelectric conversion element for generating an electric signal according to the amount of incident light, and a lead-out path for leading an output signal of the photoelectric conversion device to an output signal line. Pixels to be converted logarithmically are
In a solid-state imaging device arranged in a matrix, when the highest luminance in the imageable luminance region of the solid-state imaging device is Ma and the minimum luminance in the imageable luminance region of the solid-state imaging device is Mi, 20 × Log (Ma /
A solid-state imaging device capable of imaging at Mi) of 60 [dB] or less. 4. 20 × log (Ma / Mi) is 40 [dB]
The solid-state imaging device according to claim 3, wherein an image can be captured in a range of 60 dB or less. 5. The photoelectric conversion unit according to claim 1, wherein a plurality of transistors operating in a sub-threshold region are connected in series with the photoelectric conversion element. Solid-state imaging device. 6. The photoelectric conversion means includes: a photoelectric conversion element having a first electrode to which a DC voltage is applied; a first electrode, a second electrode, and a control electrode, wherein the first electrode and the control electrode are photoelectric conversion elements. A first transistor that is connected to the second electrode of the first transistor and into which an output current from the photoelectric conversion element flows, a first electrode, a second electrode, and a control electrode, and a DC voltage is applied to the first electrode and the control electrode Has a second transistor connected to a control electrode of the first transistor, and outputs an electric signal from a second electrode; and a third transistor connected to the first electrode and the control electrode. The first transistor and the third transistor are connected in series, and the first transistor and the third transistor are connected in series.
6. The solid-state imaging device according to claim 5, wherein each of the transistors operates in a sub-threshold region. 7. The photoelectric conversion unit includes: a constant current source; and a switch having one end connected to a first electrode of the first transistor and the other end connected to the constant current source. When the switch is turned on, the first electrode of the first transistor is connected to the constant current source, and a constant current is applied to the first transistor, so that the first electrode is applied to the control electrode of the second transistor. The solid-state imaging device according to claim 6, wherein the voltage is initialized. 8. The photoelectric conversion means includes: a photoelectric conversion element having a DC voltage applied to a second electrode; a first electrode, a second electrode, and a control electrode; and the first electrode and the control electrode are connected. And a first transistor having a second electrode connected to the first electrode of the photoelectric conversion element; a first electrode, a second electrode, and a control electrode, wherein a DC voltage is applied to the first electrode and control is performed. An electrode is connected to a second electrode of the first transistor, a second transistor that outputs an electric signal from the second electrode, and a third transistor that has a DC voltage applied to each of the first electrode and the control electrode. The first transistor and the third transistor are connected in series, and the first transistor and the third transistor
6. The solid-state imaging device according to claim 5, wherein each of the transistors operates in a sub-threshold region. 9. The photoelectric conversion unit includes: a constant current source; and a switch having one end connected to the second electrode of the first transistor and the other end connected to the constant current source. When the switch is turned on, the second electrode of the first transistor is connected to the constant current source, and a constant current is applied to the first transistor, so that the second electrode is applied to the control electrode of the second transistor. The solid-state imaging device according to claim 8, wherein the voltage is initialized. 10. The luminance range is changed by changing the number of transistors operating in a sub-threshold region from the plurality of transistors by the photoelectric conversion unit. The solid-state imaging device according to any one of the above. 11. The photoelectric conversion unit has a switch between the first transistor and the photoelectric conversion element,
The solid-state imaging device according to claim 7, wherein the switch is turned on when performing an imaging operation, and is turned off when performing a reset operation. 12. In a solid-state imaging device having a plurality of pixels, each pixel includes: a photoelectric conversion element; a first MOS transistor having a first electrode and a gate electrode connected to one electrode of the photoelectric conversion element; A second MOS transistor having a gate electrode connected to a first electrode and a gate electrode of the first MOS transistor; and a third MOS transistor having a first electrode and a gate electrode connected to a second electrode of the first MOS transistor. A solid-state imaging device, wherein the first and third MOS transistors are operated in a sub-threshold region below a threshold. 13. A solid-state imaging device having a plurality of pixels, wherein each pixel includes: a photoelectric conversion element; a first MOS transistor having a second electrode connected to one electrode of the photoelectric conversion element; A second MOS transistor having a gate electrode connected to a second electrode; and a third MOS transistor having a second electrode connected to a first electrode and a gate electrode of the first MOS transistor. A solid-state imaging device in which a transistor is operated in a subthreshold region equal to or less than a threshold. 14. A fourth MOS transistor having a first electrode connected to a first electrode of the third MOS transistor and a second electrode connected to a second electrode of the third MOS transistor.
It has an S transistor, and when the fourth MOS transistor is turned on, the brightness range of each pixel is widened, and when the fourth MOS transistor is turned off, the brightness range of each pixel is narrowed. The solid-state imaging device according to claim 12.