JP2001094877A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device capable of highly accurately picking up the image of a subject in a wide luminance range from a high luminance area up to a low luminance area and having high responsiveness capable of quickly resetting each pixel to an original state even in the low luminance area. SOLUTION: In the case of allowing each pixel to execute image pickup operation, a signal ϕVPS to be applied to the source of a MOS transistor(TR) T1 is set up as 1st voltage, a MOS TR T3 is turned off and the MOS TR T1 is driven in a subthreshold area. In the case of allowing each pixel to execute reset operation, the signal ϕVPS to be applied to the MOS TR T1 is set up as 2nd voltage, the MOS TR T3 is turned on and a constant current is allowed to flow from a constant current source 9 into the MOS TR T1. Since the drain current of the MOS TR T3 is determined by a current flowing from the constant current source 9, the gate voltage of the MOS TR T1 is reset so as to be a value corresponding to the drain current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device having a plurality of pixels.

[0002]

2. Description of the Related Art Solid-state imaging devices are not only compact, lightweight and low power consumption, are free from image distortion and image sticking, and are resistant to environmental conditions such as vibration and magnetic fields. LSI (Large Scale)
Since it can be manufactured by a process common to or similar to that of an integrated circuit, it has high reliability and is suitable for mass production. For this reason, solid-state imaging devices having pixels arranged in a line are widely used in facsimile and flatbed scanners, and solid-state imaging devices having pixels arranged in a matrix are widely used in video cameras, digital cameras, and the like. By the way, such a solid-state imaging device is roughly classified into a CCD type and a MOS type by means for reading out (extracting) photocharges generated by a photoelectric conversion element. The CCD type has a drawback that the dynamic range is narrow because the photoelectric charge is transferred while being accumulated in the potential well. On the other hand, the MOS type uses the charge accumulated in the pn junction capacitance of the photodiode as M
Reading is performed through an OS transistor.

Here, one of the conventional MOS-type solid-state imaging devices is described.
The configuration per pixel will be described with reference to FIG. In the figure, PD is a photodiode whose cathode is M
The gate of the OS transistor T1 and the MOS transistor T
2 drain. MOS transistor T
1 is connected to the drain of the MOS transistor T3, and the source of the MOS transistor T3 is connected to the output signal line V3.
connected to out. The DC voltage VPD is applied to the drain of the MOS transistor T1 and the source of the MOS transistor T2, and the DC voltage VPS is applied to the anode of the photodiode.

When light enters the photodiode PD,
Photocharge is generated, and the charge is stored in the gate of the MOS transistor T1. Here, the MOS transistor T3
Pulse φV to the gate of the MOS transistor T3
Is turned on, a current proportional to the electric charge of the gate of the MOS transistor T1 is led to the output signal line Vout through the MOS transistors T1 and T3. In this way, an output current proportional to the amount of incident light can be read. After reading the signal, the MOS transistor T3 is turned off and the signal φRS is applied to the gate of the MOS transistor T2.
And turning on the MOS transistor T2,
The gate voltage of the S transistor T1 can be initialized.

[0005]

As described above, the conventional M
The OS-type solid-state imaging device reads out the photocharge generated by the photodiode in each pixel and stored in the gate of the MOS transistor as it is, so the dynamic range is narrow, and therefore, the exposure amount must be precisely controlled. In addition, even if the exposure amount is precisely controlled, dark portions are blackened and bright portions are saturated. On the other hand, the present applicant has disclosed a photosensitive means capable of generating a photocurrent corresponding to the amount of incident light, a MOS transistor for inputting the photocurrent, and a bias means for biasing the MOS transistor to a state in which a subthreshold current can flow. Prepared,
A solid-state imaging device that converts the photocurrent into a logarithm has been proposed (see Japanese Patent Application Laid-Open No. 3-192664). Although such a solid-state imaging device has a wide dynamic range, the threshold characteristics of MOS transistors provided for each pixel may be different, and the sensitivity may be different for each pixel. Therefore, it is necessary to take measures such as holding the output obtained by previously irradiating bright light (uniform light) having a uniform luminance as correction data for correcting the output of each pixel when the subject is imaged. .

However, there are problems that it is complicated for the operator to irradiate each pixel using an external light source, and that the exposure cannot be uniformly performed well. Further, when the uniform light irradiation mechanism is provided in the imaging device, there is a problem that the configuration of the imaging device becomes complicated or large. In order to solve such a problem, the inventors of the present invention have made various studies on a circuit configuration that can eliminate the variation in sensitivity of each pixel without previously irradiating uniform light. The present invention has been made in view of such a point, and a solid-state imaging device capable of accurately obtaining correction data for correcting an output of each pixel at the time of imaging a subject without previously irradiating uniform light. The purpose is to provide. It is another object of the present invention to provide a solid-state imaging device in which the variation in sensitivity of each pixel is suppressed by setting the gate portion surface potential of each pixel to be substantially the same.

[0007]

According to a first aspect of the present invention, there is provided a solid-state imaging device, comprising: a photosensitive element for generating an electric signal corresponding to an amount of incident light; and a first electrode connected to the photosensitive element. A photoelectric conversion unit having a transistor that is operated and operating the transistor in a sub-threshold region to convert the electrical signal into a natural logarithm, and a derivation path that leads an output signal of the photoelectric conversion unit to an output signal line. In the solid-state imaging device, a first electrode and a control electrode of the transistor are connected to the photosensitive element, a constant current source is provided, a current flows from the constant current source to the transistor, and a voltage of a control electrode of the transistor is controlled. Is set to a predetermined voltage value corresponding to the transistor to perform a reset operation.

In such a solid-state imaging device, when an imaging operation is performed by providing first switching means between the first electrode of the transistor and the constant current source, The first switch means
When the transistor is operated in the sub-threshold region while the FF is set, and the reset operation is performed,
The first switch means is turned on, and a current flows from the constant current source to the transistor to make it conductive.

Further, as set forth in claim 3, a second switch means is provided between the photosensitive element and the first electrode of the transistor, and the second switch means is turned on when performing an imaging operation. In addition, the solid-state imaging device may be configured such that the transistor is operated in a sub-threshold region, and when performing a reset operation, the second switch is turned off and the transistor is turned on.

In the solid-state image pickup device according to the third aspect, for example, when a moving image is picked up, light is incident on a photosensitive element by repeatedly performing an image pickup operation and a reset operation like an image pickup device for a video-movie or the like. In this state, the photoelectric conversion means can be reset by turning off the second switch means.

According to a fourth aspect of the present invention, there is provided a solid-state imaging device which generates an output signal obtained by natural logarithmically converting an incident light amount, and derives an output signal of the photoelectric conversion unit to an output signal line. In a solid-state imaging device having a plurality of pixels including a lead-out path, the photoelectric conversion unit includes: a photoelectric conversion element in which a DC voltage is applied to a first electrode;
An electrode and a control electrode; a first transistor in which the first electrode and the control electrode are connected to a second electrode of the photoelectric conversion element; and a first electrode, a second electrode, and a control electrode. A second transistor to which a DC voltage is applied and a control electrode is connected to the first electrode and the control electrode of the first transistor to output an electric signal from a second electrode; and a constant current for flowing a constant current to the first transistor And a first switch connected between the constant current source and a connection node between the first electrode and the control electrode of the first transistor. When each pixel performs an imaging operation, the first switch is connected to the first switch. 1 When the switch is turned off and the pixels are reset, the first
The switch is turned on.

In such a solid-state imaging device, the solid-state imaging device is connected between a connection node between the control electrode and the first electrode of the first transistor and a second electrode of the photoelectric conversion element. A configuration in which a second switch is provided to turn on the second switch when each pixel performs an imaging operation, and to turn off the second switch when each pixel performs a reset operation. You may do it.
According to a sixth aspect of the present invention, there is provided a second switch having one end connected to the first electrode of the photoelectric conversion element and a DC voltage applied to the other end, and each of the pixels performs an imaging operation. At this time, the configuration may be such that the second switch is turned on, and when each pixel performs a reset operation, the second switch is turned off.

In such a solid-state imaging device, the second switch may be a transistor. Further, the first switch may be a transistor.

According to a ninth aspect of the present invention, in the solid-state imaging device according to any one of the fourth to eighth aspects, the pixels are arranged in a matrix.

According to a tenth aspect of the present invention, in the two-dimensional solid-state imaging device having pixels arranged in a matrix, each pixel includes a photodiode and a first electrode provided on one electrode of the photodiode. A first MOS transistor having a gate electrode connected to the first MOS transistor; a second MOS transistor having a gate electrode connected to the first electrode and the gate electrode of the first MOS transistor; a constant current source;
A second electrode connected to the first electrode and the gate electrode of the OS transistor, and a third MOS transistor having the first electrode connected to the constant current source. The third MOS transistor is turned off to convert the electric signal output from the photodiode into a natural logarithm, and the first MOS transistor is turned off.
When the transistor is operated in a sub-threshold region equal to or less than the threshold value and the pixel is reset, the third M
An OS transistor is turned on, a constant current flows through the first MOS transistor, and a gate electrode of the first MOS transistor is reset to a predetermined voltage value corresponding to the first MOS transistor.

According to a eleventh aspect of the present invention, in the solid-state imaging device according to the tenth aspect, the solid-state imaging device is provided between the photodiode and the first MOS transistor, and a first electrode is provided on a second electrode of the photodiode. An electrode is connected, and a fourth MOS transistor having a second electrode connected to a connection node between the first electrode and the gate electrode of the first MOS transistor is provided. The third MOS transistor converts the output electric signal into a natural logarithm.
When the transistor is turned off and the fourth MOS transistor is turned on, the first MOS transistor is operated in a sub-threshold region equal to or less than a threshold, and when the pixel is reset, the fourth MOS transistor is turned off and the second MOS transistor is turned off. The method is characterized in that a 3MOS transistor is turned on, a constant current flows through the first MOS transistor, and a gate electrode of the first MOS transistor is reset to a predetermined voltage value corresponding to the first MOS transistor.

According to a twelfth aspect of the present invention, in the solid-state imaging device according to the tenth aspect, a DC voltage is applied to the first electrode and a second electrode is connected to the first electrode of the photodiode. When the pixel performs an imaging operation, the third MOS transistor is turned off and the fourth MOS transistor is turned off so as to convert the electrical signal output from the photodiode into a natural logarithm. When the transistor is turned on, the first MOS transistor is operated in a sub-threshold region equal to or less than a threshold value, and when the pixel is reset, the fourth MOS transistor is turned off and the third MOS transistor is turned on. A constant current is applied to one MOS transistor to
The gate electrode of the OS transistor is reset to a predetermined voltage value corresponding to the first MOS transistor.

In the solid-state imaging device according to any one of claims 10 to 12, as described in claim 13, a first electrode is connected to the pixel and a second electrode of the second MOS transistor, A sixth MOS transistor having a second electrode connected to the output signal line and a gate electrode connected to the row selection line may be provided. Further, as in the solid-state imaging device according to claim 14, the pixel has a first electrode connected to a DC voltage, a gate electrode connected to a second electrode of the second MOS transistor, and the second MOS transistor. A fifth MOS transistor may be provided to amplify the output signal output from the second electrode.

According to a fifteenth aspect of the present invention, in the solid-state imaging device according to the fourteenth aspect, the pixel has a first electrode connected to a second electrode of the fifth MOS transistor, and a second electrode connected to an output terminal. A sixth MOS transistor is connected to the signal line and has a gate electrode connected to the row selection line.

The solid-state imaging device according to claim 16 is the solid-state imaging device according to claim 14 or 15,
The pixel has one end connected to a second electrode of the second MOS transistor, and a capacitor that is reset via the second MOS transistor when a reset voltage is applied to a first electrode of the second MOS transistor. It is characterized by the following.

The solid-state imaging device according to claim 17 is the solid-state imaging device according to claim 14 or 15,
The first electrode of the second MOS transistor is connected to a DC voltage, and the pixel includes a seventh MOS transistor having a first electrode connected to a second electrode of the second MOS transistor and a DC voltage connected to a second electrode. , The second
A capacitor having one end connected to the second electrode of the MOS transistor and being reset via the seventh MOS transistor when a reset voltage is applied to the gate electrode of the seventh MOS transistor. .

The solid-state imaging device according to claim 18 is the solid-state imaging device according to any one of claims 10 to 17, wherein the first MO of the pixels arranged in one line in the first direction is arranged.
A first DC voltage line commonly connected to the second electrode of the S transistor; and a first M voltage line of the pixels arranged in one column in the second direction.
A second DC voltage line commonly connected to a second electrode of the OS transistor; and when each pixel performs an imaging operation, the second electrode of the first MOS transistor is connected to the first electrode of the first MOS transistor.
When the pixel is connected to a DC voltage line and each pixel performs a reset operation, a second electrode of the first MOS transistor is connected to the second DC voltage line.

According to a nineteenth aspect of the present invention, in the solid-state imaging device according to any one of the tenth to eighteenth aspects, a load resistor or a constant resistor connected to the pixel via the output signal line is provided. It is characterized by having a MOS transistor as a current source.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment of Pixel Configuration Each embodiment of the solid-state imaging device of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows a partial configuration of a two-dimensional MOS solid-state imaging device according to an embodiment of the present invention. In the figure, G11 to Gmn are arranged in a matrix (matrix arrangement).
FIG. Reference numeral 2 denotes a vertical scanning circuit, which sequentially scans rows (lines) 4-1, 4-2,..., 4-n. Reference numeral 3 denotes a horizontal scanning circuit, which sequentially reads out the photoelectric conversion signals derived from the pixels to the output signal lines 6-1, 6-2,..., 6-m for each pixel in the horizontal direction. 5 is a power supply line. Also, constant current sources 9-1, 9-2,.
9-m are current supply lines 8-1, 8-2,
.., The pixels G11 to G1n and G21 to G2 via 8-m
.., Gm1 to Gmn. Signal φVPS
, 7-2,..., 7-n are supplied to the pixels G11 to Gm1, G12 to Gm2,.
., G1n to Gmn. .., 4-n and lines 7-1, 7
, 7-n and output signal lines 6-1, 6-2,.
, 6-m, current supply lines 8-1, 8-2, ..., 8-
m and other lines (for example, a clock line and a bias supply line) as well as the power supply line 5 are connected, but these are omitted in FIG.

Output signal lines 6-1, 6-2,..., 6
As shown, one N-channel MOS transistor Q2 is provided for each m. Taking the output signal line 6-1 as an example, the drain of the MOS transistor Q2 is connected to the output signal line 6-1, the source is connected to the final signal line 10, and the gate is connected to the horizontal scanning circuit 3. I have. As described later, an N-channel fourth MOS transistor T4 for switching is also provided in each pixel. Here, the MOS transistor T4 selects a row, and the MOS transistor Q2 selects a column.

<First Embodiment> A first embodiment (FIG. 2) applied to each pixel of the first example of the pixel configuration shown in FIG.
Will be described with reference to the drawings.

In FIG. 2, a pn photodiode PD
Form a photosensitive portion (photoelectric conversion portion). The anode of the photodiode PD is connected to a first MOS transistor T1.
, The gate of the second MOS transistor T2, and the source of the third MOS transistor T3. The source of the MOS transistor T2 is connected to the drain of the fourth MOS transistor T4 for row selection. The source of the MOS transistor T4 is an output signal line 6 (this output signal line 6 is connected to 6-1 and 6-2 in FIG.
.., 6-m). Note that M
Each of the OS transistors T1 to T4 is an N-channel MOS transistor, and has a back gate grounded.

The DC voltage VPD is applied to the cathode of the photodiode PD. On the other hand, M
A signal φVPS is input to the source of the OS transistor T1 from a line 7 (this line 7 corresponds to 7-1, 7-2,..., 7-n in FIG. 1).
The other end of the capacitor C to which the DC voltage VPS is applied is connected to the other source. The constant current source 9 is connected to the drain of the MOS transistor T3.
1, 9-2,..., 9-m) are current supply lines 8 (the current supply lines 8 are 8-1, 8-2,.
, 8-m), and the signal φS is input to its gate.

The signal φD is input to the drain of the MOS transistor T2. Further, the MOS transistor T
The signal φV is input to the gate of No. 4. In the present embodiment, the signal φVPS is a voltage whose value for operating the MOS transistor T1 in the sub-threshold region is close to the DC voltage VPS (this voltage is referred to as “first voltage”).
And a voltage for flowing a current from the constant current source 9 to the MOS transistor T1 (this voltage is referred to as a “second voltage”).

(1) Operation for converting incident light to each pixel into an electric signal First, the signal φS is set to low level to turn off the MOS transistor T3 so that no current flows from the constant current source 9 to the MOS transistor T1. At the same time, the signal φVPS is set to the first voltage so that the MOS transistor T1 operates in the subthreshold region. At this time, when light enters the photodiode PD, a photocurrent is generated, and the MOS
Due to the subthreshold characteristic of the transistor, a voltage having a value obtained by natural logarithmically converting the photocurrent is generated at the gates of the MOS transistors T1 and T2. With this voltage,
A current flows through the MOS transistor T2, and a charge equivalent to a value obtained by natural logarithmically converting the integrated value of the photocurrent is accumulated in the capacitor C. That is, a voltage proportional to a value obtained by natural logarithmically converting the integrated value of the photocurrent is generated at the connection node a between the capacitor C and the source of the MOS transistor T2. However, at this time, it is assumed that the MOS transistor T4 is in the OFF state.

Next, a pulse signal φV is applied to the gate of the MOS transistor T4 to turn on the MOS transistor T4.
When N is set, the electric charge accumulated in the capacitor C is led out to the output signal line 6 as an output current. This output signal line 6
Is a value obtained by natural logarithmically converting the integrated value of the photocurrent. In this manner, a signal (output current) proportional to the logarithmic value of the incident light amount can be read.
After reading the signal, the MOS transistor T4 is turned off.
I do.

(2) Reset Operation of Each Pixel The reset operation of the pixel having the circuit configuration shown in FIG. 2 will be described below with reference to the drawings. FIG. 3 is a timing chart of signals applied to each signal line connected to each element in a pixel when performing a reset operation.

As described in (1), the pulse signal φV
Is applied to the gate of the MOS transistor T4 to output an output signal. First, the signal φS is set to high level to turn on the MOS transistor T3, and the signal φ
VPS is set to the second voltage. In this manner, a current flows from the constant current source 9 to the MOS transistor T1.
Since the current flowing from the constant current source 9 is sufficiently larger than the photocurrent supplied from the photodiode PD, the drain current flowing through the MOS transistor T1 is substantially equal to the current supplied from the constant current source 9. Can be equal. At this time, the voltage of the signal φD is at a high level (a potential equal to or close to the DC voltage VPD). Then, once the signal φD is set to low level, the electric charge accumulated in the capacitor C is released to the signal line of the signal φD through the MOS transistor T2, and the potential of the capacitor C and the connection node a is initialized.
The signal φD is returned to the high level.

As described above, while the signal φS is at the high level and the signal φVPS is at the second voltage, the constant current source 9
More constant current flows through the MOS transistor T3 and the MOS
It flows to the transistor T1. Therefore, the source-gate voltage of the MOS transistor T1 is
It is determined by one drain current and is initialized. As described above, when the gate voltage of the MOS transistor T1 is reset to the initial value, the pulse signal φV is applied to the gate of the MOS transistor T4, and a signal (output current) at the time of the reset is output to the output signal line 6. I do.

As described above, when the signal at the time of resetting is read, the signal φS is set to the low level, the MOS transistor T3 is turned off, and the signal φVPS is set to the first voltage. Thereafter, the signal φD is set to low level, and the electric charge accumulated in the capacitor C is released to the signal line of the signal φD through the MOS transistor T2, whereby the potentials of the capacitor C and the connection node a are initialized. Then, φD is returned to the original high level so that the next imaging can be performed.

Furthermore, as described above, by operating each MOS transistor for each pixel, the MOS
When a signal at the time of resetting the gate voltage of the transistor T1 is output to the output signal line 6, the signal at the time of resetting is output serially and stored in a subsequent circuit in a memory as correction data for each pixel. Then, if the signal at the time of actual imaging is corrected for each pixel using the stored correction data, it is possible to remove variations for each pixel from the output signal. A specific example of this correction method is shown in FIG. 32 described later. This correction method can also be realized by providing a memory such as a line memory in the element.

In the present embodiment, the signal reading from each pixel may be performed using a charge-coupled device (CCD). In this case, the charge can be read out to the CCD by providing a potential barrier corresponding to the MOS transistor T4 in FIG. 2 and having a variable potential level. In the present embodiment, the potential of the signal (φVPS) applied to the source of the first MOS transistor T1 is changed between the reset period and the logarithmic output operation period so as not to hinder signal reading in the subsequent stage.
The value of the signal φVPS may be a fixed value if the design of the subsequent stage is optimized so that the potential of the connection node a falls within a predetermined voltage range between the reset period and the logarithmic output operation period. This is the same for the second to fifth embodiments described later.

<Second Example of Pixel Configuration> FIG. 4 schematically shows a partial configuration of a two-dimensional MOS solid-state imaging device according to another embodiment of the present invention. In the figure, G11 to Gm
n indicates pixels arranged in a matrix (matrix arrangement). Reference numeral 2 denotes a vertical scanning circuit, and rows (lines) 4-1 and 4
.., 4-n are sequentially scanned. Reference numeral 3 denotes a horizontal scanning circuit which outputs output signal lines 6-1 to 6-2,.
.. The photoelectric conversion signals derived in 6-m are sequentially read in the horizontal direction for each pixel. 5 is a power supply line. Also, the constant current sources 9-1, 9-2,..., 9-m are connected to the pixel G11 via the current supply lines 8-1, 8-2,. ~ G1n, G21 ~ G2n, ..., Gm1 ~ Gmn
To supply current. Line 7 to which the signal φVPS is supplied
1, 7-2,..., 7-n are pixels G
11 to Gm1, G12 to Gm2,..., G1n to Gmn. For each pixel, the lines 4-1 4-2,.
4-n, lines 7-1, 7-2,..., 7-n, output signal lines 6-1, 6-2,.
, 8-2,..., 8-m, the power supply line 5, and other lines (for example, a clock line and a bias supply line) are also connected, but these are omitted in FIG.

The output signal lines 6-1, 6-2,.
As shown in the figure, a set of N-channel MOS transistors Q1 and Q2 is provided for each m. Output signal line 6-1
The gate of the MOS transistor Q1 is connected to the DC voltage line 11, the drain is connected to the output signal line 6-1, and the source is connected to the line 12 of the DC voltage VPS '. On the other hand, MOS transistor Q2
Is connected to the output signal line 6-1, the source is connected to the final signal line 10, and the gate is connected to the horizontal scanning circuit 3.
It is connected to the.

As described later, the pixels G11 to Gmn have
An N-channel MOS transistor Ta for outputting a signal based on photocharges generated in those pixels is provided. FIG. 5A shows a connection relationship between the MOS transistor Ta and the MOS transistor Q1. This MO
The S transistor Ta corresponds to the fifth MOS transistor T5 in the second and third embodiments, and corresponds to the second MOS transistor T2 in the fourth and fifth embodiments. here,
The relationship between the DC voltage VPS 'connected to the source of the MOS transistor Q1 and the DC voltage VPD' connected to the drain of the MOS transistor Ta is VPD '>VPS',
The DC voltage VPS 'is, for example, a ground voltage (ground).
In this circuit configuration, a signal is input to the gate of the upper MOS transistor Ta, and a DC voltage DC is constantly applied to the gate of the lower MOS transistor Q1. Therefore, the lower-stage MOS transistor Q1 is equivalent to a resistor or a constant current source, and the circuit in FIG. 5A is a source follower-type amplifier circuit. In this case, what is amplified and output from the MOS transistor Ta may be a current.

The MOS transistor Q2 is connected to the horizontal scanning circuit 3
And is operated as a switch element. still,
As described later, an N-channel fourth MOS transistor T4 for switching is also provided in the pixel of each of the embodiments after FIG. When this MOS transistor T4 is also included, the circuit of FIG. 5A is exactly as shown in FIG. 5B. That is, the MOS transistor T4 is inserted between the MOS transistor Q1 and the MOS transistor Ta. Here, the MOS transistor T4 selects a row, and the MOS transistor Q2 selects a column. The configuration shown in FIGS. 4 and 5 is a configuration common to the second to fifth embodiments described below.

With the configuration shown in FIG. 5, a large signal gain can be output. Therefore, when the pixel converts the photocurrent generated from the photosensitive element in a natural logarithmic manner to expand the dynamic range, the output signal is small as it is, but is amplified to a sufficiently large signal by the present amplifier circuit. Therefore, processing in a subsequent signal processing circuit (not shown) is facilitated. Further, the output signal lines 6-1, 6-2,... To which a plurality of pixels arranged in the column direction are connected without providing the MOS transistor Q1 constituting the load resistance portion of the amplifier circuit in the pixel. The provision of each 6-m can reduce the number of load resistances or constant current sources, and reduce the area occupied by the amplifier circuit on the semiconductor chip.

<Second Embodiment> A second embodiment applied to each pixel of the second example of the pixel configuration shown in FIG. 4 will be described with reference to the drawings. FIG. 6 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 6, in this embodiment, FIG.
And a fifth MOS transistor T5 whose gate is connected to the connection node a and performs current amplification according to the voltage of the connection node a, and whose drain is connected to the connection node a and the potential of the capacitor C and the connection node a are initialized. 6M that performs
The configuration is such that an OS transistor T6 is added. MO
A fourth MOS for row selection is connected to the source of the S transistor T5.
The drain of the transistor T4 is connected. MOS
The source of the transistor T4 is connected to the output signal line 6 (the output signal line 6 corresponds to 6-1 to 6-m in FIG. 4). Incidentally, the MOS transistor T
5, T6, like the MOS transistors T1 to T4,
The back gate is grounded by an N-channel MOS transistor.

The DC voltage VPD is applied to the drain of the MOS transistor T5, and the signal φV is input to the gate of the MOS transistor T4. The DC voltage V RB is applied to the source of the MOS transistor T6, and the signal φVRS is input to its gate. Further, M
The DC voltage VPD is applied to the drain of the OS transistor T2. In this embodiment, the MOS transistors T1 to T4 and the capacitor C perform the same operation as in the first embodiment (FIG. 2), and can perform the reset operation and the imaging operation of each pixel. The operation will be described below.

(1) Operation for converting incident light to each pixel into an electric signal First, the signal φS is set to low level to turn off the MOS transistor T3, the signal φVPS is set to the first voltage, and the MOS transistors T1 and T2 are turned on. The operation when biased to operate in the sub-threshold region will be described. At this time, the MOS transistor T
Since 3 is OFF, no current flows from the constant current source 9 to the MOS transistor T1, as in the first embodiment.

When light enters the photodiode PD, a photocurrent is generated, and a voltage having a value obtained by natural logarithmic conversion of the photocurrent is generated at the gates of the MOS transistors T1 and T2 due to the subthreshold characteristic of the MOS transistor. With this voltage, a current flows through the MOS transistor T2, and a charge equivalent to a value obtained by natural logarithmically converting the integrated value of the photocurrent is accumulated in the capacitor C. That is, a voltage proportional to a value obtained by natural logarithmically converting the integrated value of the photocurrent is generated at the connection node a between the capacitor C and the source of the MOS transistor T2. However, at this time, the MOS transistors T4 and T6 are in the OFF state.

Next, when a pulse signal is applied to the gate of the MOS transistor T4 to turn on the MOS transistor T4, a current proportional to the voltage applied to the gate of the MOS transistor T5 passes through the MOS transistors T4 and T5 to output signal lines. 6 is derived. Since the voltage applied to the gate of the MOS transistor T5 is the voltage applied to the connection node a, the current led out to the output signal line 6 is a value obtained by natural logarithmically converting the integrated value of the photocurrent. Thus, a signal (output current) proportional to the logarithmic value of the incident light amount
Can be read.

(2) Reset Operation of Each Pixel The reset operation of the pixel having the circuit configuration as shown in FIG. 6 will be described below with reference to the drawings. FIG. 7 is a timing chart of signals applied to each signal line connected to each element in a pixel when performing a reset operation.

As described in (1), the pulse signal φV
Is applied to the gate of the MOS transistor T4 to output an output signal. First, the signal φS is set to high level to turn on the MOS transistor T3, and the signal φ
VPS is set to the second voltage. In this manner, a current flows from the constant current source 9 to the MOS transistor T1.
At this time, a constant current flows from the constant current source 9 to the MOS transistor T1 via the MOS transistor T3. Therefore, since the source-gate voltage of the MOS transistor T1 is determined by the drain current of the MOS transistor T1, the gate voltage of the MOS transistor T1 is reset to an initial value.

As described above, while the gate voltage of the MOS transistor T1 is reset to the initial value, the MOS
By turning on the MOS transistor T6 by applying the pulse signal φVRS to the gate of the transistor T6, the electric charge accumulated in the capacitor C is released through the MOS transistor T6, and the capacitor C and the connection node a are reset. Thereafter, the pulse signal φV is supplied to the gate of the MOS transistor T4, and a signal when the MOS transistor T1 is reset is output to the output signal line 6.
Then, the signal φS is set to low level to turn off the MOS transistor T3, and the signal φVPS is set to the first voltage. Thereafter, by applying the pulse signal φVRS, the potentials of the capacitor C and the connection node a are initialized. Then, φVRS is returned to the original low level so that the next imaging can be performed.

Further, as described above, the MOS transistor T
The signal output to the output signal line 6 when 1 is reset is stored as correction data for each pixel as in the first embodiment. Then, if the signal at the time of actual imaging is corrected for each pixel using the stored correction data, it is possible to remove variations for each pixel from the output signal. A specific example of this correction method is shown in FIG. 32 described later. This correction method can also be realized by providing a memory such as a line memory in the element.

<Third Embodiment> A third embodiment will be described with reference to the drawings. FIG. 8 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 8, in this embodiment, the MO
By applying the signal φD to the drain of the S transistor T2, the potentials of the capacitor C and the connection node a are initialized, thereby eliminating the MOS transistor T6. Other configurations are the same as those of the second embodiment (FIG. 6). During the high level period of the signal φD, integration is performed by the capacitor C as in the first embodiment (FIG. 2). During the low level period, the charge of the capacitor C is discharged through the MOS transistor T2.
The voltage of the capacitor C and the gate of the MOS transistor T5 substantially become the low level voltage of the signal φD (reset).
In the present embodiment, the configuration is simplified because the MOS transistor T6 can be omitted.

In this embodiment, when the imaging operation is performed, as in the second embodiment, the MOS transistor T3 is turned off so that no current flows from the constant current source 9 to the MOS transistor T1, and the signal is output. φVPS
At the first voltage so that the MOS transistor T1 operates in the sub-threshold state. Further, the signal φD is set to the high level, and the electric charge equivalent to the value obtained by natural logarithmically converting the integrated value of the photocurrent is stored in the capacitor C. And
At a predetermined timing, the MOS transistor T4 is turned on, and a current proportional to the voltage applied to the gate of the MOS transistor T5 is led out to the output signal line 6 through the MOS transistors T4 and T5.

When resetting each pixel, the signal is controlled at the timing shown in FIG. 3 as in the first embodiment.
That is, first, after the pulse signal φV is applied, the signal φS
And the signal φVPS is set to the second voltage, and the reset operation starts. By turning on the MOS transistor T3 in this manner, the constant current source 9
A constant current flows through the OS transistor T1 so that MO
The gate voltage of the S transistor T1 is reset to a constant initial value.

During this time, the signal φD is changed to low level, and the electric charge stored in the capacitor C is transferred to the MOS transistor T2.
To the signal line of the signal φD through the capacitor C
After the potential of the connection node a is initialized, the signal φD is returned to the high level. Thereafter, the pulse signal φV is supplied to the gate of the MOS transistor T4, and a signal when the MOS transistor T1 is reset is output to the output signal line 6. Then, after the signal φS is set to the low level and the signal φVPS is set to the first voltage, the signal φD is set to the low level, and the charges accumulated in the capacitor C are discharged to the signal line of the signal φD through the MOS transistor T2. The potentials of the capacitor C and the connection node a are initialized. Then, φD is returned to the original high level so that the next imaging can be performed.

Further, as described above, the MOS transistor T
The signal output to the output signal line 6 when 1 is reset is stored as correction data for each pixel as in the first embodiment. Then, if the signal at the time of actual imaging is corrected for each pixel using the stored correction data, it is possible to remove variations for each pixel from the output signal. A specific example of this correction method is shown in FIG. 32 described later. This correction method can also be realized by providing a memory such as a line memory in the element.

<Fourth Embodiment> A fourth embodiment will be described with reference to the drawings. FIG. 9 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 8 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 9, in this embodiment, the MO
DC voltage VPD is applied to the drain of S transistor T2, and capacitor C and MOS transistor T
5 is deleted. That is, the drain of the MOS transistor T4 is connected to the source of the MOS transistor T2. The other configuration is the third embodiment (FIG. 8)
Is the same as

In this embodiment, when the imaging operation is performed, as in the third embodiment, the MOS transistor T3 is turned off so that no current flows from the constant current source 9 to the MOS transistor T1, and the signal is output. φVPS
At the first voltage so that the MOS transistor T1 operates in the sub-threshold state. Thus MOS
By operating the transistor T1, a drain current having a value which is logarithmically proportional to the photocurrent is M
It flows through the OS transistor T2.

When a pulse signal φV is applied to the gate of the MOS transistor T4 to turn on the MOS transistor T4, the drain current having a value proportional to the logarithm of the photocurrent in natural logarithm is obtained.
It is led to the output signal line 6 through the S transistor T4. At this time, the drain voltage of the MOS transistor Q1 determined by the on-state resistance of the MOS transistor T2 and the MOS transistor Q1 (FIG. 5) and the current flowing therethrough appears on the output signal line 6 as a signal. After the signal is read out in this manner, the MOS transistor T4 is set to O
Set to FF.

Also, when resetting each pixel, FIG.
The operation is performed as shown in the timing chart of FIG. First, after the pulse signal φV is applied, the signal φS is set to the high level and the signal φVPS is set to the second voltage, and the reset operation starts. By turning on the MOS transistor T3 in this manner, a constant current flows from the constant current source 9 to the MOS transistor T1, and the gate voltage of the MOS transistor DC voltage T1 is reset to a constant initial value. Thereafter, the pulse signal φV is applied to the MOS transistor T
4 to output a signal to the output signal line 6 when the MOS transistor T1 is reset. Then, the signal φS is set to the low level, the MOS transistor T3 is turned off, and the signal φVPS is set to the first voltage, so that the next imaging can be performed.

Further, as described above, the MOS transistor T
The signal output to the output signal line 6 when 1 is reset is stored as correction data for each pixel as in the first embodiment. Then, if the signal at the time of actual imaging is corrected for each pixel using the stored correction data, it is possible to remove variations for each pixel from the output signal. A specific example of this correction method is shown in FIG. 32 described later. This correction method can also be realized by providing a memory such as a line memory in the element.

In this embodiment, since the integration of the optical signal with the capacitor C is not performed as in the third embodiment, the integration time is not required, and the reset of the capacitor C is not required. As a result, the signal processing can be speeded up accordingly. Further, in the present embodiment, as compared with the third embodiment, since the capacitor C and the MOS transistor T5 can be omitted, the configuration is further simplified and the pixel size can be reduced.

<Fifth Embodiment> A fifth embodiment will be described with reference to the drawings. FIG. 11 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 11, in the present embodiment, in the pixel shown in the fourth embodiment (FIG. 9), a seventh MOS transistor connected between the anode of the photodiode PD and the drain of the MOS transistor T1 is provided. The configuration is such that T7 is added. That is, the drain of the MOS transistor T7 is connected to the anode of the photodiode PD, and the source is connected to the connection node between the drain and gate of the MOS transistor T1 and the source of the MOS transistor T3. Signal φSW is applied to the gate of MOS transistor T7. Hereinafter, the operation of the pixel having such a configuration will be described.

(1) Operation for converting incident light to each pixel into an electric signal First, as in the fourth embodiment, the signal φS is set to the low level, and the signal φVPS is set to the first voltage. At this time, the signal φSW is set to the high level to turn on the MOS transistor T7, so that the photocurrent is supplied from the photodiode PD to the MOS transistor T1. or,
Since the MOS transistor T3 is OFF, the MOS transistor T1 is supplied from the constant current source 9 as in the fourth embodiment.
No current flows through In this way, the MOS transistor T1 operates in the sub-threshold state, and a drain current having a value which is logarithmically proportional to the photocurrent flows through the MOS transistor T2.

When the pulse signal φV is applied to the gate of the MOS transistor T4 to turn on the MOS transistor T4, the drain current having a value which is logarithmically proportional to the photocurrent becomes MO
It is led to the output signal line 6 through the S transistor T4. At this time, the drain voltage of the MOS transistor Q1 determined by the on-state resistance of the MOS transistor T2 and the MOS transistor Q1 (FIG. 5) and the current flowing therethrough appears on the output signal line 6 as a signal. After the signal is read out in this manner, the MOS transistor T4 is set to O
Set to FF.

(2) Reset Operation of Each Pixel The reset operation of the pixel having the circuit configuration shown in FIG. 11 will be described below with reference to the drawings. FIG. 12 is a timing chart of signals applied to each signal line connected to each element in a pixel when performing a reset operation.

As described in (1), the pulse signal φV
Is applied to the gate of the MOS transistor T4 to output an output signal.
The transistor T3 is turned on, and the signal φSW is set to low level to turn off the MOS transistor T7. At this time, similarly to the fourth embodiment, the signal φVPS is set to the second voltage. In this way, the constant current source 9
A current is allowed to flow through the transistor T1,
Photocurrent is prevented from flowing from the photodiode PD to the MOS transistor T1. At this time, a constant current flows from the constant current source 9 to the MOS transistor T1 via the MOS transistor T3. Therefore, the MOS transistor T
Since the source-gate voltage of the MOS transistor T1 is determined by the drain current of the MOS transistor T1, the gate voltage of the MOS transistor T1 is reset to an initial value.

When the gate voltage of MOS transistor T1 is reset to the initial value, pulse signal φV
To the gate of the MOS transistor T4 to output a signal when the MOS transistor T1 is reset to the output signal line 6. Then, the signal φS is set to low level to turn off the MOS transistor T3. At this time, the signal φVPS is set to the first voltage. Further, the signal φSW is set to the high level to turn on the MOS transistor T7, so that the next imaging can be performed.

As described above, when the reset operation is performed, the photocurrent does not flow from the photodiode PD to the first MOS transistor T1, so that the MOS transistor T1
Becomes a constant current flowing from the constant current source 9. Also, a MOS transistor T7 is provided and turned off.
By doing so, the drain current flowing through the MOS transistor T1 at the time of resetting
It is not affected by the photocurrent from Therefore, the fourth
The current value of the constant current supplied from the constant current source 9 can be smaller than that of the embodiment.

Further, as described above, the MOS transistor T
The signal output to the output signal line 6 when 1 is reset is stored as correction data for each pixel as in the first embodiment. Then, if the signal at the time of actual imaging is corrected for each pixel using the stored correction data, it is possible to remove variations for each pixel from the output signal. A specific example of this correction method is shown in FIG. 32 described later. This correction method can also be realized by providing a memory such as a line memory in the element.

In this embodiment, as in the second embodiment (FIG. 6), the capacitor C or the MOS transistor having the other end to which the DC voltage VPS is applied is connected to the source of the MOS transistor T2.
The configuration may be such that the gate of the transistor T5 and the drain of the MOS transistor T6 for resetting the capacitor C are connected, and the source of the MOS transistor T5 is connected to the drain of the MOS transistor T4. Further, as in the third embodiment (FIG. 8), the signal φD is applied to the drain of the MOS transistor T2, and the MOS transistor T6 is omitted from the configuration of the second embodiment (FIG. 6). A configuration may be adopted.

In this embodiment, the seventh MOS transistor T7 is replaced with a depletion type N-channel MO.
It may be an S transistor. The configuration of this pixel is
As shown in FIG. As shown in FIG. 13, the MOS transistors T1 to T4 other than the MOS transistor T7 are enhancement-type N-channel MOS transistors.

When all the MOS transistors provided in the pixel are constituted by enhancement type MOS transistors as in the pixel having the configuration of FIG. 11, the MOS transistors T7 and T1 are connected in series. Is higher than the voltage supplied to this pixel. Therefore, it is necessary to provide another power supply for supplying signal φSW to MOS transistor T7.

On the other hand, as described above, this MO
By making the S transistor T7 a depletion type MOS transistor, the high level voltage of the signal φSW applied to its gate can be reduced, and the same or close to the high level signal applied to the other MOS transistors. It becomes possible to do. This is because the threshold value of the depletion type MOS transistor is a negative value, and therefore, the transistor can be turned on with a lower gate voltage than that of the enhancement type MOS transistor.

In this embodiment, the seventh MOS transistor T7 may be a P-channel MOS transistor. FIG. 14 shows the configuration of this pixel. FIG.
As shown in FIG. 7, the MOS transistors T1 to T4 other than the MOS transistor T7 are N-channel MOS transistors. Further, the source of the MOS transistor T7 is connected to the anode of the photodiode PD,
The drain is connected to the drain of the MOS transistor T1.

In such a configuration, the MOS transistor T7 turns on when the voltage difference between the gate and the drain is larger than the threshold, and turns off when the voltage difference between the gate and the drain is smaller than the threshold. Therefore, MOS
The signal φSW applied to the gate of the transistor T7 is
2 signal φSW and its timing are reversed,
ON without being affected by the MOS transistor T1 connected in series to the drain of the MOS transistor T7.
/ OFF operation can be performed.

Also, ON / OF of the MOS transistor T7
Since the F operation is not affected by the MOS transistor T1, there is no need to provide another power supply for supplying the signal φSW. Further, by doing so, the MOS transistor T7 can be an enhancement type MOS transistor like the other MOS transistors, so that the MOS transistor T7 can be generated in the same process as the other MOS transistors. It is possible. Therefore, as described above, the production process is simplified as compared with the case where only the seventh MOS transistor T7 is a depletion type MOS transistor.

As shown in FIG. 15, the seventh MOS transistor T7 is connected to the DC voltage line VPD and the photodiode PD.
It may be configured to be connected between the cathode and the cathode. That is, the DC voltage VPD is applied to the drain of the MOS transistor T7, and the cathode of the photodiode PD is connected to its source. Further, in the pixel having such a configuration, as described above, the seventh MOS transistor T7 may be a depletion-type MOS transistor or a P-channel MOS transistor.

<Third Example of Pixel Configuration> FIG. 16 schematically shows the configuration of a part of a two-dimensional MOS solid-state imaging device according to another embodiment of the present invention. In the figure, G11 to G
mn indicates pixels arranged in a matrix (matrix arrangement). Reference numeral 2 denotes a vertical scanning circuit, which is a row (line) 4-1;
,..., 4-n are sequentially scanned. Reference numeral 3 denotes a horizontal scanning circuit which outputs output signal lines 6-1 and 6-2,
..., the photoelectric conversion signals derived in 6-m are sequentially read out in the horizontal direction for each pixel. 5 is a power supply line. or,
, 9-m are connected to the pixels G11 to G1n via the current supply lines 8-1, 8-2, ..., 8-m, respectively, for each column. , G21-G2n, ..., Gm1-G
Supply current to mn. The lines 7-1, 7-2,..., 7-n to which the DC voltage VPSH is supplied are respectively
Pixels G11 to Gm1, G12 to Gm2,..., G1n to Gmn. Further, the line 1 to which the DC voltage VPSL is supplied.
, 13-2,..., 13-m are pixels G11 to G1n, G21 to G2n,.
Connected to. For each pixel, the lines 4-1 and 4-
, 4-n, lines 7-1, 7-2, ..., 7
-N and lines 13-1, 13-2, ..., 13-m
, 6-m, the current supply lines 8-1, 8-2,..., 8-m, the power supply line 5, and other lines (for example, , Clock lines and bias supply lines) are also connected, but these are omitted in FIG.

Output signal lines 6-1, 6-2,..., 6
As shown in the figure, a set of N-channel MOS transistors Q1 and Q2 is provided for each m. Output signal line 6-1
The gate of the MOS transistor Q1 is connected to the DC voltage line 11, the drain is connected to the output signal line 6-1, and the source is connected to the line 12 of the DC voltage VPS '. On the other hand, MOS transistor Q2
Is connected to the output signal line 6-1, the source is connected to the final signal line 10, and the gate is connected to the horizontal scanning circuit 3.
It is connected to the. These MOS transistors Q1, Q2
Is the MOS transistor Q in the second example of the pixel configuration.
1 and Q2.

<Sixth Embodiment> A sixth embodiment applied to each pixel of the third example of the pixel configuration shown in FIG. 16 will be described with reference to the drawings. FIG. 17 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 11 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 17, in the present embodiment, in the pixel shown in the fifth embodiment (FIG. 11), an eighth MOS transistor T8 and a ninth MOS transistor T9 each having a drain connected to the source of the MOS transistor T1 are provided. Is added. MOS transistor T8 has a source to which DC voltage VPSH is applied, a gate supplied with signal φSW1, and a gate connected to MOS transistor T9.
Has a source supplied with a DC voltage VPSL and a gate supplied with a signal φSW2. Hereinafter, the operation of the pixel having such a configuration will be described. Note that the DC voltage VPSH is a voltage for operating the MOS transistor T1 in the sub-threshold region, and the DC voltage VPSL is a voltage for operating the MOS transistor T1 to flow a current from the constant current source 9 to the MOS transistor T1. It is.

(1) Operation for converting incident light to each pixel into an electric signal First, as in the fifth embodiment, the signal φS is set to low level and the signal φSW is set to high level. At this time, the DC voltage VPSH is applied to the source of the MOS transistor T1 by turning on the MOS transistor T8 by setting the signal φSW1 to the high level. In this manner, the MOS transistor T1 operates in the sub-threshold state, and the drain current having a value proportional to the logarithm of the photocurrent flows through the MOS transistor T2. At this time, the signal SW2 is set to low level,
The MOS transistor T9 is turned off.

When a pulse signal φV is applied to the gate of the MOS transistor T4 to turn on the MOS transistor T4, the drain current having a value proportional to the logarithm of the photocurrent in natural logarithm is obtained.
It is led to the output signal line 6 through the S transistor T4. At this time, the drain voltage of the MOS transistor Q1 determined by the on-state resistance of the MOS transistor T2 and the MOS transistor Q1 (FIG. 16) and the current flowing therethrough appears on the output signal line 6 as a signal. After the signal is read out in this manner, the MOS transistor T4 is turned off.

(2) Reset Operation of Each Pixel Hereinafter, the reset operation of the pixel having the circuit configuration as shown in FIG. 17 will be described with reference to the drawings. FIG. 18 is a timing chart of signals applied to each signal line connected to each element in a pixel when performing a reset operation.

As described in (1), the pulse signal φV
Is applied to the gate of the MOS transistor T4 to output an output signal. First, the signal φSW1 is set to low level to turn off the MOS transistor T8, and the signal φSW2 is set to high level to set the MOS transistor T9.
Is turned on to apply the DC voltage VPSL to the source of the MOS transistor T1. Then, the signal φS is set to the high level to turn on the MOS transistor T3, and the signal φ
SW is set to low level and the MOS transistor T7 is turned off.
Change to F.

Thus, the current is made to flow from the constant current source 9 to the MOS transistor T1, and the photocurrent is made not to flow from the photodiode PD to the MOS transistor T1. At this time, a constant current flows from the constant current source 9 to the MOS transistor T1 via the MOS transistor T3. Therefore, the MOS transistor T1
Is determined by the drain current of the MOS transistor T1, the gate voltage of the MOS transistor T1 is reset to an initial value.

When the gate voltage of MOS transistor T1 is reset to the initial value, pulse signal φV
To the gate of the MOS transistor T4 to output a signal when the MOS transistor T1 is reset to the output signal line 6. Then, first, the signal φS is set to low level to turn off the MOS transistor T3. next,
When the signal φSW1 is set to the high level, the MOS transistor T
8, the signal φSW2 is set to low level to turn off the MOS transistor T9, and the DC voltage VPSH is applied to the source of the MOS transistor T1. Then, the signal φSW is set to the high level to turn on the MOS transistor T7, so that the next imaging can be performed.

Further, as described above, the MOS transistor T
The signal output to the output signal line 6 when 1 is reset is stored as correction data for each pixel as in the first embodiment. Then, if the signal at the time of actual imaging is corrected for each pixel using the stored correction data, it is possible to remove variations for each pixel from the output signal. A specific example of this correction method is shown in FIG. 32 described later. This correction method can also be realized by providing a memory such as a line memory in the element.

In this embodiment, as in the second embodiment (FIG. 6), the capacitor C or the MOS transistor having the other end to which the DC voltage VPS is applied is connected to the source of the MOS transistor T2.
The configuration may be such that the gate of the transistor T5 and the drain of the MOS transistor T6 for resetting the capacitor C are connected, and the source of the MOS transistor T5 is connected to the drain of the MOS transistor T4. Further, as in the third embodiment (FIG. 8), the signal φD is applied to the drain of the MOS transistor T2, and the MOS transistor T6 is omitted from the configuration of the second embodiment (FIG. 6). A configuration may be adopted.

Further, the structure may be such that the MOS transistor T7 is omitted, or as described in the fifth embodiment, the MOS transistor T7 may be provided between the DC voltage line VPD and the photodiode PD. I do not care. Further, only the MOS transistor T7 has a depletion type MO.
An S transistor may be used, and a MOS transistor may be used.
Only the transistor T7 may be a P-channel MOS transistor.

For example, when the pixels G11 to Gm1 connected to the line 4-1 are reset, in the case of the solid-state imaging device as shown in FIG. 1 or FIG. 4, the current flows from the constant current sources 9-1 to 9-m. Since all the current flows to the line 7-1, the pixel G11
The second voltage of the signal .phi.VPS applied to the source of the first MOS transistor T1 in each pixel of .about.Gm1 tends to become unstable due to the voltage drop on the line 7-1. Therefore, FIG.
FIG. 16 in which pixels G11 to Gmn having a circuit configuration as shown in FIG.
According to the solid-state imaging device as described above, the pixels G11 to Gm1
Are reset, the constant current sources 9-1, 9-2,.
., The currents flowing from 9-m respectively
, 13-2,..., 13-m.
The voltage applied to the source of the first MOS transistor T1 in each of the pixels 11 to Gm1 is not affected by the current flowing through the constant current sources 9-1 to 9-m, and becomes constant at the DC voltage VPSL. Therefore, according to the pixel having the circuit configuration as in the present embodiment, the first pixel in each pixel is different from the first to fifth embodiments.
The difference in the initialized gate voltage of the MOS transistor T1 can be reduced.

In the first to sixth embodiments described above, the MOS transistors T1 to T9, which are the active elements in the pixel, are all constituted by N-channel MOS transistors except for the form shown in FIG. MOS transistor T
All of 1 to T9 may be configured by P-channel MOS transistors. FIGS. 20, 23 to 26, 29, and 31 show the first to sixth embodiments using the P-channel M
The seventh to twelfth embodiments, which are examples constituted by OS transistors, are shown. FIG. 27 shows the eleventh embodiment in which the seventh MOS transistor T7 is a depletion-type P-channel MOS transistor. FIG. 28 shows an eleventh embodiment in which the seventh MOS transistor T7 is an N-channel MOS transistor. Therefore, the polarity of the connection and the polarity of the applied voltage are reversed in FIGS. For example, in FIG. 20 (seventh embodiment), the photodiode PD has an anode connected to the DC voltage VPD, and a cathode connected to the drain of the first MOS transistor T1 and the second transistor M1.
It is connected to the gate of the OS transistor T2. MO
Signal φVPS is applied to the source of S transistor T1.

By the way, when the pixel as shown in FIG. 20 performs logarithmic conversion, the DC voltage VPS and the DC voltage VPD satisfy VPS> V.
PD, which is the reverse of FIG. 2 (first embodiment). The output voltage of the capacitor C is a voltage having a high initial value and drops by integration. When turning on the third MOS transistor T3 and the fourth MOS transistor T4, a low voltage is applied to the gate. Further, in the embodiment after FIG. 23 (eighth to twelfth embodiments), the sixth MOS transistor T6 and the seventh MOS transistor T
When turning on the seventh, eighth and ninth MOS transistors T8 and T9, a low voltage is applied to the gate. In the pixel having the configuration shown in FIG. 28, when turning on the seventh MOS transistor T7 serving as an N-channel MOS transistor, a high voltage is applied to the gate. As described above, when MOS transistors having opposite polarities are used, although the voltage relationship and the connection relationship are partially different, the configuration is substantially the same, and the basic operation is the same. 29 to 31 are only shown in the drawings, and the description of the configuration and operation is omitted.

FIG. 1 is a block diagram showing the overall configuration of a solid-state imaging device including pixels according to a seventh embodiment.
FIG. 9 is a block circuit configuration diagram for explaining an overall configuration of a solid-state imaging device including pixels according to the eighth to eleventh embodiments. FIG. 21 is an overall configuration of a solid-state imaging device including pixels according to the twelfth embodiment. FIG. 30 is a block circuit configuration diagram for explaining
Shown in 19, 21, and 30, the same portions (same role portions) as those in FIGS. 1, 4, and 16 are denoted by the same reference numerals, and description thereof is omitted. Hereinafter, the configuration of FIG. 21 will be briefly described. A P-channel MOS transistor Q1 and a P-channel MOS transistor Q2 are connected to output signal lines 6-1, 6-2,..., 6-m arranged in the column direction. MOS transistor Q
The gate of 1 is connected to the DC voltage line 11, the drain is connected to the output signal line 6-1, and the source is connected to the line 12 of the DC voltage VPS '.

On the other hand, the drain of the MOS transistor Q2 is connected to the output signal line 6-1, the source is connected to the final signal line 10, and the gate is connected to the horizontal scanning circuit 3. Here, the MOS transistor Q1 is connected to the P
FIG. 22A together with the channel MOS transistor Ta
The amplifier circuit shown in FIG. The MOS transistor Ta is a fifth MOS transistor in the eighth and ninth embodiments.
It corresponds to the transistor T5, and in the tenth and eleventh embodiments, corresponds to the second MOS transistor T2.

In this case, MOS transistor Q1 is connected to MO
It serves as a load resistance or a constant current source for the S transistor Ta. Accordingly, the relationship between the DC voltage VPS 'connected to the source of the MOS transistor Q1 and the DC voltage VPD' connected to the drain of the MOS transistor Ta is VP
D ′ <VPS ′, and the DC voltage VPD ′ is, for example, a ground voltage (ground). The drain of the MOS transistor Q1 is connected to the MOS transistor Ta, and a DC voltage is applied to the gate. The P-channel MOS transistor Q2 is controlled by the horizontal scanning circuit 3, and leads the output of the amplifier circuit to the final signal line 10. Eighth to eleventh
Considering the fourth MOS transistor T4 provided in the pixel as in the embodiment, the circuit of FIG. 22A is represented as shown in FIG. 22B.

<Image Data Correction Method>
An example in which a solid-state imaging device provided with a pixel having a circuit configuration as in the twelfth embodiment is used in an image input device such as a digital camera will be described with reference to the drawings.

The image input device shown in FIG. 32 includes an objective lens 51, a solid-state imaging device 52 that outputs an electric signal in accordance with the amount of light incident through the objective lens 51, and a solid-state imaging device 52 during imaging. A memory 53 to which an electric signal (hereinafter, referred to as “image data”) is input and temporarily stored.
And the electric signal of the solid-state imaging device 52 at the time of reset (hereinafter, referred to as
It is called “correction data”. ) Is inputted and temporarily stored, a correction operation circuit 55 for correcting the correction data stored from the memory 54 from the image data sent from the memory 53, and a correction operation circuit 55 A processing unit 56 for performing arithmetic processing on the corrected image data and outputting the processed data to the outside. Note that the solid-state imaging device 52 has the first to twelfth embodiments (FIGS. 2, 6, 8, 9, 11, 13 to 15, 17, 20, 23 to
This is a solid-state imaging device provided with pixels having a circuit configuration as shown in FIGS.

The image input device having such a configuration firstly
The imaging operation is performed, and the image data is output from the solid-state imaging device 52 to the memory 53 for each pixel. Then, when each pixel has completed the imaging operation and performed the reset operation, as described above, the variation in the sensitivity of each pixel is examined,
The correction data is output to the memory 54. And the memory 5
The image data of each pixel in 3 and the correction data of each pixel in the memory 54 are sent to the correction arithmetic circuit 55 for each pixel.

In the correction operation circuit 55, from the image data transmitted from the memory 53, the correction data transmitted from the memory 54 of the same pixel which has output this image data is corrected and calculated for each pixel. Image data on which the correction data has been corrected and calculated is sent to the processing unit 56, subjected to a calculation process, and then output to the outside. In such an image input device, a line memory for recording data transmitted from the solid-state imaging device 52 line by line is used as the memories 53 and 54, respectively. Therefore, the memories 53 and 54
Can be easily incorporated into a solid-state imaging device.

[0106]

As described above, according to the solid-state imaging device of the present invention, in order to obtain correction data for correcting the output of each pixel at the time of imaging a subject, it is necessary to obtain uniform light as in the prior art. Need not be irradiated. Further, the active element is M
The use of OS transistors facilitates high integration, and can be formed on one chip together with peripheral processing circuits (A / D converter, digital system processor, memory) and the like.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram for explaining the overall configuration of a two-dimensional solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of one pixel according to the first embodiment of the present invention.

FIG. 3 is a timing chart of a signal applied to each element of a pixel used in the first embodiment.

FIG. 4 is a block circuit diagram for explaining the overall configuration of a two-dimensional solid-state imaging device according to an embodiment of the present invention.

FIG. 5 is a partial circuit diagram of FIG. 4;

FIG. 6 is a circuit diagram showing a configuration of one pixel according to a second embodiment of the present invention.

FIG. 7 is a timing chart of a signal applied to each element of a pixel used in the second embodiment.

FIG. 8 is a circuit diagram showing a configuration of one pixel according to a third embodiment of the present invention.

FIG. 9 is a circuit diagram showing a configuration of one pixel according to a fourth embodiment of the present invention.

FIG. 10 is a timing chart of signals applied to each element of a pixel used in the fourth embodiment.

FIG. 11 is a circuit diagram showing a configuration of one pixel according to a fifth embodiment of the present invention.

FIG. 12 is a timing chart of a signal applied to each element of a pixel used in the fifth embodiment.

FIG. 13 is a circuit diagram showing a configuration of one pixel according to a fifth embodiment of the present invention.

FIG. 14 is a circuit diagram showing a configuration of one pixel according to a fifth embodiment of the present invention.

FIG. 15 is a circuit diagram showing a configuration of one pixel according to a fifth embodiment of the present invention.

FIG. 16 is a block circuit diagram for explaining the overall configuration of a two-dimensional solid-state imaging device according to an embodiment of the present invention.

FIG. 17 is a circuit diagram showing a configuration of one pixel according to a sixth embodiment of the present invention.

FIG. 18 is a timing chart of a signal applied to each element of a pixel used in the sixth embodiment.

FIG. 19 is a block circuit diagram for explaining an overall configuration of a two-dimensional solid-state imaging device according to the present invention in the case of an embodiment in which an active element in a pixel is configured by a P-channel MOS transistor.

FIG. 20 is a circuit diagram showing a configuration of one pixel according to a seventh embodiment of the present invention.

FIG. 21 is a block circuit diagram for explaining the overall configuration of a two-dimensional solid-state imaging device according to the present invention in the case where an active element in a pixel is configured by a P-channel MOS transistor.

FIG. 22 is a partial circuit diagram of FIG. 21;

FIG. 23 is a circuit diagram showing a configuration of one pixel according to an eighth embodiment of the present invention.

FIG. 24 is a circuit diagram showing a configuration of one pixel according to a ninth embodiment of the present invention.

FIG. 25 is a circuit diagram showing a configuration of one pixel according to a tenth embodiment of the present invention.

FIG. 26 is a circuit diagram showing a configuration of one pixel according to an eleventh embodiment of the present invention.

FIG. 27 is a circuit diagram showing a configuration of one pixel according to an eleventh embodiment of the present invention.

FIG. 28 is a circuit diagram showing a configuration of one pixel according to an eleventh embodiment of the present invention.

FIG. 29 is a circuit diagram showing a configuration of one pixel according to an eleventh embodiment of the present invention.

FIG. 30 is a block circuit diagram for explaining the overall configuration of a two-dimensional solid-state imaging device according to the present invention in the case of an embodiment in which active elements in pixels are configured by P-channel MOS transistors.

FIG. 31 is a circuit diagram showing a configuration of one pixel according to a twelfth embodiment of the present invention.

FIG. 32 is a block diagram illustrating a configuration of an image input device.

FIG. 33 is a circuit diagram showing a configuration of one pixel in a conventional example.

[Explanation of symbols]

 G11 to Gmn pixel 2 vertical scanning circuit 3 horizontal scanning circuit 4-1 to 4-n row selection line 6-1 to 6-m output signal line 7-1 to 7-n line 8-1 to 8-m current supply line 9-1 to 9-m Constant current source 10 Signal line 11 DC voltage line 12 line 13-1 to 13-m line 51 Objective lens 52 Solid-state imaging device 53, 54 Memory 55 Correction operation circuit 56 Processing unit PD Photodiode T1 T9 1st to 9th MOS transistors C capacitor

Claims (19)

[Claims] A photosensitive element for generating an electrical signal corresponding to the amount of incident light; a transistor having a first electrode connected to the photosensitive element; and operating the transistor in a sub-threshold region to generate a natural logarithm of the electrical signal. A solid-state imaging device, comprising: a photoelectric conversion unit for performing an optical conversion; and a lead-out path for leading an output signal of the photoelectric conversion unit to an output signal line, wherein a first electrode and a control electrode of the transistor are connected to the photosensitive element. And providing a constant current source, performing a reset operation by flowing a current from the constant current source to the transistor and setting a voltage of a control electrode of the transistor to a predetermined voltage value corresponding to the transistor. Solid-state imaging device. 2. A first switch means is provided between a first electrode of the transistor and the constant current source, and when performing an imaging operation, the first switch means is turned off.
And operating the transistor in a sub-threshold region, and performing a reset operation by turning on the first switch means and passing a current from the constant current source to the transistor to make it conductive. Claim 1
3. The solid-state imaging device according to item 1. 3. The method according to claim 1, wherein the photosensitive element and the first transistor are connected to each other.
A second switch means provided between the first electrode and the electrode; when performing an imaging operation, turning on the second switch means and operating the transistor in a sub-threshold region; 3. The solid-state imaging device according to claim 1, wherein the switch is turned off and the transistor is turned on. 4. A plurality of pixels comprising: photoelectric conversion means for generating an output signal obtained by natural logarithmically converting the amount of incident light; and a derivation path for deriving an output signal of the photoelectric conversion means to an output signal line. Wherein the photoelectric conversion means comprises: a photoelectric conversion element having a DC voltage applied to a first electrode; a first electrode, a second electrode, and a control electrode, wherein the first electrode and the control electrode are A first transistor connected to a second electrode of the photoelectric conversion element; a first electrode, a second electrode, and a control electrode, wherein a DC voltage is applied to the first electrode and the control electrode is connected to a first electrode of the first transistor. A second transistor connected to the one electrode and the control electrode and outputting an electric signal from the second electrode; a constant current source for supplying a constant current to the first transistor; a first electrode of the constant current source and the first transistor And control electronics A first switch connected between a pole connection node and the first switch, wherein the first switch is turned off when each pixel performs an imaging operation, and the first switch is reset when each pixel is reset. O
N. A solid-state imaging device. 5. A second switch connected between a control electrode of the first transistor and a connection node between the first electrode and a second electrode of the photoelectric conversion element, wherein each pixel performs an imaging operation. 5. The solid-state imaging device according to claim 4, wherein the second switch is turned on when the pixel performs a reset operation, and the second switch is turned off when the pixel performs a reset operation. 6. A second switch having one end connected to a first electrode of the photoelectric conversion element and a DC voltage applied to the other end, wherein when each pixel performs an imaging operation, the second switch is connected to the second switch. 5. The solid-state imaging device according to claim 4, wherein a switch is turned on, and when each of the pixels performs a reset operation, the second switch is turned off. 7. The solid-state imaging device according to claim 5, wherein the second switch is a transistor. 8. The solid-state imaging device according to claim 4, wherein said first switch is a transistor. 9. The solid-state imaging device according to claim 4, wherein said pixels are arranged in a matrix. 10. In a solid-state imaging device having a plurality of pixels, each pixel includes a photodiode, a first MOS transistor having a first electrode and a gate electrode connected to one electrode of the photodiode, and a first MOS transistor. A second MOS transistor having a gate electrode connected to the first electrode and the gate electrode of the first MOS transistor; a constant current source; a second electrode connected to the first electrode and the gate electrode of the first MOS transistor; And a third MOS transistor connected to a constant current source. When the pixel performs an imaging operation, the third MOS transistor is turned off so as to convert an electric signal output from the photodiode into a natural logarithm. Operating the first MOS transistor in a sub-threshold region equal to or less than a threshold value, When resetting the element, the third MOS transistor is turned on, a constant current flows through the first MOS transistor, and the gate electrode of the first MOS transistor is reset to a predetermined voltage value corresponding to the first MOS transistor. A solid-state imaging device characterized by the above-mentioned. 11. The photodiode and the first MO
A fourth MOS transistor provided between the first transistor and the S transistor, wherein a first electrode is connected to a second electrode of the photodiode, and a second electrode is connected to a connection node between the first electrode and the gate electrode of the first MOS transistor; When the pixel performs an imaging operation, the third MOS transistor is turned off and the fourth MOS transistor is turned on so that an electric signal output from the photodiode is converted into a natural logarithm. Operating the first MOS transistor in a sub-threshold region equal to or less than a threshold value, and when resetting the pixel, turning off the fourth MOS transistor and turning on the third MOS transistor to set the first MOS transistor as the first MOS transistor. Supplying a current to the first MOS transistor The solid-state imaging device according to the gate electrode to claim 10, characterized in that the resetting to a predetermined voltage value corresponding to the first 1MOS transistor. 12. When a DC voltage is applied to a first electrode and a fourth MOS transistor having a second electrode connected to a first electrode of the photodiode, the fourth MOS transistor is connected to the first electrode of the photodiode. The third MOS transistor is turned off and the fourth MOS transistor is turned on so that the first MOS transistor is operated in a sub-threshold region equal to or less than a threshold so as to convert an electric signal output from the photodiode into a natural logarithm. When resetting the pixel, the fourth MOS transistor is turned off and the third MOS transistor is turned on, a constant current flows through the first MOS transistor, and the gate electrode of the first MOS transistor is connected to the first MOS transistor. Reset to a predetermined voltage value corresponding to the transistor The solid-state imaging device according to claim 10, characterized in Rukoto. 13. The pixel according to claim 1, wherein the first electrode is the second MO.
13. The semiconductor device according to claim 10, further comprising a sixth MOS transistor connected to a second electrode of the S transistor, the second electrode connected to an output signal line, and a gate electrode connected to a row selection line. A solid-state imaging device according to any one of claims 1 to 3. 14. The pixel according to claim 1, wherein a first electrode is connected to a DC voltage, a gate electrode is connected to a second electrode of the second MOS transistor, and an output signal output from the second electrode of the second MOS transistor. Fifth to amplify
2. The semiconductor device according to claim 1, further comprising a MOS transistor.
The solid-state imaging device according to claim 1. 15. The pixel according to claim 15, wherein the first electrode is the fifth MO.
The solid-state imaging device according to claim 14, further comprising a sixth MOS transistor connected to a second electrode of the S transistor, the second electrode connected to an output signal line, and a gate electrode connected to a row selection line. . 16. The pixel according to claim 16, wherein one end of the pixel is connected to a second electrode of the second MOS transistor, and
2. A capacitor which is reset via the second MOS transistor when a reset voltage is applied to a first electrode of the MOS transistor.
The solid-state imaging device according to claim 4 or claim 15. 17. The pixel, wherein a first electrode of the second MOS transistor is connected to a DC voltage, and the pixel has a first electrode connected to a second electrode of the second MOS transistor, and a DC voltage connected to a second electrode. A seventh MOS transistor, a capacitor having one end connected to a second electrode of the second MOS transistor and being reset via the seventh MOS transistor when a reset voltage is applied to a gate electrode of the seventh MOS transistor; The solid-state imaging device according to claim 14, comprising: 18. A first DC voltage line commonly connected to a second electrode of a first MOS transistor of the pixel arranged in one column in a first direction, and the pixel arranged in one column in a second direction. A second DC voltage line commonly connected to a second electrode of the first MOS transistor, and when each pixel performs an imaging operation, the second electrode of the first MOS transistor is connected to the first DC voltage line. And when each pixel performs a reset operation, the first MO
18. The solid-state imaging device according to claim 10, wherein a second electrode of the S transistor is connected to the second DC voltage line. 19. The apparatus according to claim 10, further comprising a MOS transistor forming a load resistor or a constant current source connected to said pixel via said output signal line. Solid-state imaging device.