JP4345145B2 - Solid-state imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device including a plurality of pixels.
[0002]
[Prior art]
The solid-state imaging device is not only small, lightweight, and has low power consumption, but also has no image distortion or image sticking, and is resistant to environmental conditions such as vibration and magnetic field. In addition, since it can be manufactured through a process common to LSI (Large Scale Integrated circuit) or a similar process, it is highly reliable and suitable for mass production. For this reason, solid-state imaging devices in which pixels are arranged in a line are widely used for facsimiles and flatbed scanners, and solid-state imaging devices in which pixels are arranged in a matrix are widely used for video cameras and digital cameras. By the way, such a solid-state imaging device is roughly classified into a CCD type and a MOS type by means for reading (extracting) the photocharge generated in the photoelectric conversion element. The CCD type is designed to transfer photocharges while accumulating them in a potential well, and has a drawback that the dynamic range is narrow. On the other hand, in the MOS type, the charge accumulated in the pn junction capacitance of the photodiode is read out through the MOS transistor.
[0003]
Here, the configuration per pixel of the conventional MOS type solid-state imaging device will be described with reference to FIG. In the figure, PD is a photodiode, and its cathode is connected to the gate of the MOS transistor T1 and the drain of the MOS transistor T2. The source of the MOS transistor T1 is connected to the drain of the MOS transistor T3, and the source of the MOS transistor T3 is connected to the output signal line Vout. A DC voltage VPD is applied to the drain of the MOS transistor T1, and a DC voltage VPS is applied to the source of the MOS transistor T2 and the anode of the photodiode.
[0004]
When light enters the photodiode PD, photocharge is generated, and the charge is accumulated in the gate of the MOS transistor T1. Here, when a pulse φV is applied to the gate of the MOS transistor T3 to turn on the MOS transistor T3, a current proportional to the charge of the gate of the MOS transistor T1 is led to the output signal line Vout through the MOS transistors T1 and T3. In this way, an output current proportional to the amount of incident light can be read. After the signal is read, the MOS transistor T3 is turned off, and the gate voltage of the MOS transistor T1 can be initialized by applying the signal φRS to the gate of the MOS transistor T2 to turn on the MOS transistor T2.
[0005]
[Problems to be solved by the invention]
As described above, the conventional MOS type solid-state imaging device reads out the photocharge generated by the photodiode in each pixel and accumulated in the gate of the MOS transistor as it is, so that the dynamic range is narrow, and therefore the exposure amount is precisely controlled. Moreover, even if the exposure amount was controlled precisely, the dark part was crushed black or the bright part was saturated. On the other hand, the applicant of the present invention has a photosensitive means that can generate a photocurrent according to the amount of incident light, a MOS transistor that inputs the photocurrent, and a bias means that biases the MOS transistor to a state in which a subthreshold current can flow. And a solid-state image pickup device in which the photocurrent is logarithmically converted has been proposed (see Japanese Patent Application Laid-Open No. 3-192964).
[0006]
When the solid-state imaging device performs an imaging operation and then resets to the original state, each pixel has a MOS current (referred to as a “reset current”) having a reverse polarity to the photocurrent up to the low luminance state. Since it easily flows into the transistor, the photocharges charged in the MOS transistor are recombined and reset at high speed. However, when each pixel is in a low luminance region, the reset current hardly flows due to the influence of the threshold voltage of the MOS transistor. Therefore, the photocharges charged in the MOS transistor are difficult to be recombined, so that resetting takes time. As described above, since the responsiveness of each pixel is deteriorated in the low luminance region, there is a problem that afterimages are easily generated when the imaging operation is performed again.
[0007]
The present invention has been made in view of the above points, and can capture a subject in a wide luminance range from a high luminance region to a low luminance region with high definition, and each pixel can be rapidly operated even in the low luminance region. An object of the present invention is to provide a solid-state imaging device with good responsiveness that is reset to a basic state.
[0009]
[Means for Solving the Problems]
  To achieve the above objectiveClaim1The solid-state imaging storage includes a photoelectric conversion unit that generates an output signal that is a natural number converted with respect to an incident light amount, and a lead-out path that derives the output signal of the photoelectric conversion unit to an output signal line. In the solid-state imaging device having a plurality of pixels, the photoelectric conversion means includes a photoelectric conversion element in which a DC voltage is applied to the first electrode, a first electrode, a second electrode, and a control electrode. The electrode is connected to the second electrode of the photoelectric conversion element, and includes a first transistor into which an output current from the photoelectric conversion element flows, a first electrode, a second electrode, and a control electrode, and a DC voltage is applied to the first electrode. And a control electrode is connected to the first electrode and the control electrode of the first transistor, and the second transistor outputs an electrical signal from the second electrode, and the second transistor of the first transistor electrode A first voltage is applied, the first transistor is operated in a subthreshold region below a threshold value to perform imaging, a second voltage is applied to the second electrode of the first transistor, and the first transistor is applied to the first transistor. The reset is performed such that a larger current can flow than before the second voltage is applied.
[0010]
  Claim2The solid-state imaging device according to claim1In the solid-state imaging device according to item 1, the pixels are arranged in a matrix.
[0011]
  Claim3The solid-state imaging device according to claim 1.OrClaim2The solid-state imaging device according to claim 1, further comprising: an integrating circuit that integrates an electric signal output from the photoelectric conversion unit, and deriving the signal integrated by the integrating circuit to the output signal line through the deriving path. Features.
[0012]
  According to such a configuration, since the output signal from each pixel is integrated by the integration circuit, the fluctuation component of the light source and high-frequency noise included in the output signal are absorbed and removed by the integration circuit. Claims4As described in (1), after the integrated signal is output to the output signal line, by providing a reset unit that discharges the charge of the integration circuit, initialization can be performed after each pixel performs output. . The reset means is claimed in claim5To change the level of the voltage applied to the control electrode of the transistor by providing a transistor having a first electrode, a second electrode, and a control electrode, the first electrode being connected to the integrating circuit. Then, the transistor can be made conductive to discharge the charge accumulated in the integrating circuit.
[0013]
  Claim6The solid-state imaging device according to claim1Or claim2In the solid-state imaging device according to claim 1, each of the pixels includes an amplifying transistor that amplifies an output signal of the photoelectric conversion unit, and the output signal line of the amplifying transistor is output to the output signal line via the derivation path. It is characterized by being output to.
[0014]
  According to such a solid-state imaging device, the output signal is amplified by the amplifying transistor and output with a sufficient magnitude, so that the imaging signal has a high sensitivity. In such a solid-state imaging device, the claim7As described above, a load resistor or a constant current source in which the total number connected to the output signal line is smaller than the total number of pixels may be provided.
[0015]
  Claimed as load resistance or constant current source8As described above, the transistor may be a resistance transistor having a first electrode connected to the output signal line, a second electrode connected to a DC voltage, and a control electrode connected to the DC voltage. Further, when the amplifying transistor is an N-channel MOS transistor,9As described above, the DC voltage applied to the first electrode of the amplifying transistor may be higher than the DC voltage connected to the second electrode of the resistance transistor. If the amplifying transistor is a P-channel MOS transistor,10As described above, the DC voltage applied to the first electrode of the amplifying transistor may be lower than the DC voltage connected to the second electrode of the resistance transistor. Further, as the lead-out path, the claim11As described above, a switch including a switch that sequentially selects a predetermined one from all the pixels and derives a signal amplified from the selected pixel to an output signal line may be used.
[0016]
  Claim12The solid-state imaging device described in the above is a solid-state imaging device having a plurality of pixels, each pixel including a photodiode, a first MOS transistor in which a first electrode and a gate electrode are connected to one electrode of the photodiode, A first MOS transistor having a first MOS transistor and a second MOS transistor having a gate electrode connected to the gate electrode. When the pixel is caused to perform an imaging operation, the electrical signal output from the photodiode is converted to a natural logarithm. As described above, when resetting the pixel by applying a first voltage to the second electrode of the first MOS transistor to operate the first MOS transistor in a subthreshold region equal to or lower than a threshold, The second voltage is applied to the two electrodes, and is larger than before the second voltage is applied to the first transistor. Characterized by such a current can flow.
[0017]
  Claims13In the fourth MOS transistor, the first electrode is connected to the second electrode of the second MOS transistor, the second electrode is connected to the output signal line, and the gate electrode is connected to the row selection line. May be provided. Claims14The DC voltage is applied to the first electrode of the pixel, the gate electrode is connected to the second electrode of the second MOS transistor, and the second electrode of the second MOS transistor is connected to the pixel. A third MOS transistor for amplifying the output signal to be output may be provided.
[0018]
  Claim15The solid-state imaging device according to claim 15, wherein in the solid-state imaging device according to claim 15, the pixel has a first electrode connected to a second electrode of the third MOS transistor, a second electrode connected to an output signal line, and a gate. It has a fourth MOS transistor whose electrode is connected to a row selection line.
[0019]
  Claim16The solid-state imaging device according to claim14Or claim15In the solid-state imaging device according to claim 1, when the pixel has one end connected to the second electrode of the second MOS transistor and the second MOS transistor is turned on when a reset voltage is applied to the first electrode of the second MOS transistor. It has the capacitor reset via this.
[0020]
  Claim17The solid-state imaging device according to claim14Or claim15In the solid-state imaging device according to claim 1, a direct current voltage is applied to the first electrode of the third MOS transistor, the first electrode is connected to the second electrode of the second MOS transistor, and the direct current voltage is applied to the second electrode. Is applied to the second MOS transistor and the second electrode of the second MOS transistor, and is reset via the fifth MOS transistor when a reset voltage is applied to the gate electrode of the fifth MOS transistor. And a capacitor.
[0021]
  Claim18The solid-state imaging device according to claim12~ Claim17The solid-state imaging device according to any one of the above, further includes a load resistor connected to the pixel via the output signal line or a MOS transistor forming a constant current source.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
<First Example of Pixel Configuration>
Hereinafter, embodiments of the solid-state imaging device of the present invention will be described with reference to the drawings. FIG. 1 schematically shows a partial configuration of a two-dimensional MOS solid-state imaging device according to an embodiment of the present invention. In the drawing, G11 to Gmn indicate pixels arranged in a matrix (matrix arrangement). Reference numeral 2 denotes a vertical scanning circuit, which sequentially scans rows (lines) 4-1, 4-2, ..., 4-n. A horizontal scanning circuit 3 sequentially reads out photoelectric conversion signals derived from the pixels to the output signal lines 6-1, 6-2, ..., 6-m in the horizontal direction for each pixel. Reference numeral 5 denotes a power supply line. For each pixel, not only the lines 4-1, 4-2,..., 4-n, output signal lines 6-1, 6-2,. (For example, a clock line and a bias supply line) are also connected. However, these are omitted in FIG. 1 and are shown in the first embodiment shown in FIG.
[0023]
As shown in the figure, one N-channel MOS transistor Q2 is provided for each of the output signal lines 6-1, 6-2,. The drain of the MOS transistor Q2 is connected to the output signal line 6-1, the source is connected to the final signal line 9, and the gate is connected to the horizontal scanning circuit 3. As will be described later, an N-channel third MOS transistor T3 for switching is also provided in each pixel. Here, the MOS transistor T3 is for selecting a row, and the MOS transistor Q2 is for selecting a column.
[0024]
<First Embodiment>
A first embodiment (FIG. 2) applied to each pixel of the first example of the pixel configuration shown in FIG. 1 will be described with reference to the drawings.
[0025]
In FIG. 2, a pn photodiode PD forms a photosensitive portion (photoelectric conversion portion). The anode of the photodiode PD is connected to the gate and drain of the first MOS transistor T1 and the gate of the second MOS transistor T2. The source of the MOS transistor T2 is connected to the drain of the third MOS transistor T3 for row selection. The source of the MOS transistor T3 is connected to the output signal line 6 (the output signal line 6 corresponds to 6-1, 6-2,..., 6-m in FIG. 1). Each of the MOS transistors T1 to T3 is an N-channel MOS transistor and the back gate is grounded.
[0026]
A DC voltage VPD is applied to the cathode of the photodiode PD. On the other hand, the signal φVPS is input to the source of the MOS transistor T1, and one end of a capacitor C to which the DC voltage VPS is applied is connected to the other end of the MOS transistor T2. A signal φD is input to the drain of the MOS transistor T2, and a signal φV is input to the gate of the MOS transistor T3. The signal φVPS is a binary voltage signal. The voltage for operating the MOS transistor T1 in the subthreshold region at a voltage substantially equal to the DC voltage VPS is set to a high level, and the MOS transistor T1 is made conductive lower than this voltage. The voltage to make the state low level.
[0027]
(1) About the operation | movement which converts the incident light to each pixel into an electrical signal
In the pixel having the circuit configuration as shown in FIG. 2, the signal φVPS applied to the source of the MOS transistor T1 is set to the high level so that the MOS transistor T1 operates in the subthreshold region. At this time, when light enters the photodiode PD, a photocurrent is generated. Due to the subthreshold characteristic of the MOS transistor, a voltage having a value obtained by natural logarithm conversion of the photocurrent is generated at the gates of the MOS transistors T1 and T2. This voltage causes a current to flow through the MOS transistor T2, and the capacitor C stores a charge equivalent to a value obtained by natural logarithmically converting the integrated value of the photocurrent. That is, a voltage proportional to a value obtained by natural logarithmically converting the integrated value of the photocurrent is generated at the connection node a between the capacitor C and the source of the MOS transistor T2. However, at this time, the MOS transistor T3 is in an OFF state.
[0028]
Next, when the pulse signal φV is applied to the gate of the MOS transistor T3 and the MOS transistor T3 is turned on, the charge accumulated in the capacitor C is led to the output signal line 6 as an output current. The current derived to the output signal line 6 is a value obtained by natural logarithmically converting the integrated value of the photocurrent. In this way, a signal (output current) proportional to the logarithmic value of the incident light quantity can be read. Further, after the signal is read, the MOS transistor T3 is turned off.
[0029]
(2) Reset operation of each pixel
Hereinafter, the reset operation of the pixel having the circuit configuration as shown in FIG. 2 will be described with reference to the drawings. FIG. 3 is a timing chart of signals given to the signal lines connected to the elements in the pixel when the reset operation is performed. FIG. 4 is a diagram showing a potential state of the photodiode PD and the MOS transistor T1 when each pixel is reset. 4A is a cross-sectional view showing the structure of the photodiode PD and the MOS transistor T1, and FIGS. 4B to 4E are parts corresponding to the cross-sectional view of FIG. 4A. FIG. In FIGS. 4B to 4E, the direction of the arrow indicates that the potential is high.
[0030]
Incidentally, in the photodiode PD, for example, as shown in FIG. 4A, an N-type well layer 11 is formed on a P-type semiconductor substrate (hereinafter referred to as “P-type substrate”) 10 and the N-type well layer 11 is formed. The well layer 11 is formed by providing a P-type diffusion layer 12. In the MOS transistor T1, N-type diffusion layers 13 and 14 are formed on the P-type substrate 10, and an oxide film 15 and a polysilicon layer 16 are sequentially formed on the channel between the N-type diffusion layers 13 and 14. It is composed by doing. Here, the N-type well layer 11 forms the cathode side of the photodiode PD, and the P-type diffusion layer 12 forms the anode side. The N-type diffusion layers 13 and 14 form the drain and source of the MOS transistor T1, respectively, and the oxide film 15 and the polysilicon layer 16 form the gate insulating film and the gate electrode, respectively. Here, in the P-type substrate 10, a region between the N-type diffusion layers 13 and 14 is referred to as an under-gate region.
[0031]
As described in (1), by applying a pulse φV to the gate of the MOS transistor T3, an electrical signal (output signal) logarithmically converted with respect to incident light is output from each pixel having a circuit configuration as shown in FIG. It is output to the signal line 6. When the output signal is output in this way and the pulse φV becomes low level, the reset operation starts. This reset operation will be described with reference to FIGS.
[0032]
First, after the pulse signal φV is applied to the gate of the transistor T3 and the output signal is output, the reset operation starts. That is, negative charges flow from the source side of the MOS transistor T1, and the positive charges accumulated in the gate and drain of the MOS transistor T1, the gate of the MOS transistor T2, and the anode of the photodiode PD are recombined. Therefore, as shown in FIG. 4B, the potential is reset to a certain extent, and the potential of the drain and lower gate region of the MOS transistor T1 is lowered.
[0033]
As described above, the potential of the drain and gate region of the MOS transistor T1 is to be reset to the original state. However, when the potential reaches a certain value, the reset speed is reduced. This tendency is particularly noticeable when a bright subject suddenly becomes dark. Therefore, next, the signal φVPS applied to the source of the MOS transistor T1 is set to the low level. Thus, by lowering the source voltage of the MOS transistor T1, the potential of the MOS transistor T1 changes as shown in FIG. Therefore, the amount of negative charge flowing in from the source of the MOS transistor T1 increases, and the positive charge accumulated in the gate and drain of the MOS transistor T1, the gate of the MOS transistor T2, and the anode of the photodiode PD is quickly regenerated. Combined.
[0034]
Therefore, as shown in FIG. 4D, the potential of the drain and under-gate region of the MOS transistor T1 is lower than that in the state of FIG. 4C. When the potential of the MOS transistor T1 changes as shown in FIG. 4D, the signal φVPS applied to the source of the MOS transistor T1 is set to the high level. Therefore, the potential state of the MOS transistor T1 is reset to the original state as shown in FIG. As described above, after resetting the potential state of the MOS transistor T1 to the original state, the voltage of the signal φD is set to the low level, the capacitor C is discharged, and the potential of the connection node a is reset to the original state. Thereafter, the voltage of the signal φD is returned to a high level so that an imaging operation can be performed.
[0035]
In this way, the responsiveness of each pixel of the solid-state imaging device is improved by performing a reset by manipulating the potential applied to the source of the MOS transistor T1 whose drain is electrically connected to the photodiode PD which is a photosensitive element. The Therefore, even when a dark subject is imaged or when a bright subject suddenly becomes dark, the occurrence of an afterimage can be prevented and good imaging can be performed.
[0036]
Note that signal readout from each pixel may be performed using a charge coupled device (CCD). In this case, it is only necessary to read out charges to the CCD by providing a potential barrier with a variable potential level corresponding to the MOS transistor T3 in FIG.
[0037]
<Second Example of Pixel Configuration>
FIG. 5 schematically shows a configuration of a part of a two-dimensional MOS solid-state imaging device according to another embodiment of the present invention. In the drawing, G11 to Gmn indicate pixels arranged in a matrix (matrix arrangement). Reference numeral 2 denotes a vertical scanning circuit, which sequentially scans rows (lines) 4-1, 4-2, ..., 4-n. A horizontal scanning circuit 3 sequentially reads out photoelectric conversion signals derived from the pixels to the output signal lines 6-1, 6-2, ..., 6-m in the horizontal direction for each pixel. Reference numeral 5 denotes a power supply line. For each pixel, not only the lines 4-1, 4-2,..., 4-n, output signal lines 6-1, 6-2,. (For example, a clock line, a bias supply line, and the like) are also connected. However, these are omitted in FIG. 5 and are shown in the embodiments from FIG.
[0038]
One set of N-channel MOS transistors Q1, Q2 is provided for each of the output signal lines 6-1, 6-2,. The MOS transistor Q1 has a gate connected to the DC voltage line 7, a drain connected to the output signal line 6-1 and a source connected to the line 8 of the DC voltage VPS '. On the other hand, the drain of the MOS transistor Q2 is connected to the output signal line 6-1, the source is connected to the final signal line 9, and the gate is connected to the horizontal scanning circuit 3.
[0039]
As will be described later, the pixels G11 to Gmn are provided with an N-channel MOS transistor Ta that outputs a signal based on the photocharge generated in these pixels. The connection relationship between the MOS transistor Ta and the MOS transistor Q1 is as shown in FIG. The MOS transistor Ta corresponds to the fourth MOS transistor T4 in the second and third embodiments, and corresponds to the second MOS transistor T2 in the fourth embodiment. Here, the relationship between the DC voltage VPS ′ connected to the source of the MOS transistor Q1 and the DC voltage VPD ′ connected to the drain of the MOS transistor Ta is VPD ′> VPS ′, and the DC voltage VPS ′ is, for example, the ground Voltage (ground). In this circuit configuration, a signal is input to the gate of the upper MOS transistor Ta, and a DC voltage DC is constantly applied to the gate of the lower MOS transistor Q1. Therefore, the lower MOS transistor Q1 is equivalent to a resistor or a constant current source, and the circuit of FIG. 6A is a source follower type amplifier circuit. In this case, it may be considered that the current amplified from the MOS transistor Ta is a current.
[0040]
The MOS transistor Q2 is controlled by the horizontal scanning circuit 3 and operates as a switch element. As will be described later, an N-channel third MOS transistor T3 for switching is also provided in the pixel of each of the embodiments from FIG. Including this MOS transistor T3, the circuit of FIG. 6A is exactly as shown in FIG. 6B. That is, the MOS transistor T3 is inserted between the MOS transistor Q1 and the MOS transistor Ta. Here, the MOS transistor T3 is for selecting a row, and the MOS transistor Q2 is for selecting a column. The configurations shown in FIGS. 5 and 6 are common to the second to fourth embodiments described below.
[0041]
By configuring as shown in FIG. 6, a large signal can be output. Therefore, when the pixel naturally converts the photocurrent generated from the photosensitive element to expand the dynamic range, the output signal is small as it is, but is amplified to a sufficiently large signal by this amplifier circuit. Therefore, the subsequent signal processing circuit (not shown) can be easily processed. Further, without providing the MOS transistor Q1 constituting the load resistance portion of the amplifier circuit in the pixel, the output signal lines 6-1, 6-2,... To which a plurality of pixels arranged in the column direction are connected. By providing every 6-m, the number of load resistors or constant current sources can be reduced, and the area occupied by the amplifier circuit on the semiconductor chip can be reduced.
[0042]
<Second Embodiment>
A second embodiment applied to each pixel of the second example of the pixel configuration shown in FIG. 5 will be described with reference to the drawings. FIG. 7 is a circuit diagram showing a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Note that elements and signal lines used for the same purpose as those of the pixel shown in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0043]
As shown in FIG. 7, in this embodiment, the pixel shown in FIG. 2 includes a fourth MOS transistor T4 whose gate is connected to the connection node a and performs current amplification according to the voltage of the connection node a, and the potential of the connection node a. The fifth MOS transistor T5 that performs initialization is added. The source of the MOS transistor T4 is connected to the drain of the MOS transistor T3, and the source of the MOS transistor T3 is the output signal line 6 (the output signal line 6 is 6-1, 6-2,... Corresponding to -m). The MOS transistors T4 and T5 are also N-channel MOS transistors, and the back gates are grounded, similarly to the MOS transistors T1 to T3.
[0044]
The DC voltage VPD is applied to the drain of the MOS transistor T4, and the signal φV is input to the gate of the MOS transistor T3. Further, the DC voltage VRB is applied to the source of the MOS transistor T5, and the signal φVRS is input to the gate thereof. Further, a DC voltage VPD is applied to the drain of the MOS transistor T2. In the present embodiment, the MOS transistors T1 to T3 and the capacitor C perform the same operation as in the first embodiment (FIG. 2), and output an electric signal (output signal) obtained by logarithmically converting incident light. be able to.
[0045]
(1) About the operation | movement which converts the incident light to each pixel into an electrical signal
In this embodiment, the voltage value of the signal φVPS is set to the high level, and the MOS transistor T1 is operated in the subthreshold region, so that the light output from the photodiode PD according to the incident light as in the first embodiment. An output signal obtained by natural logarithm conversion with respect to the current can be output to the output signal line 6. Hereinafter, the operation of each element in the pixel shown in FIG. 7 when outputting an output signal obtained by natural-logarithmically converting the photocurrent will be described.
[0046]
When light enters the photodiode PD, a photocurrent is generated. Due to the subthreshold characteristic of the MOS transistor, a voltage having a value obtained by natural logarithm conversion of the photocurrent is generated at the gates of the MOS transistors T1 and T2. This voltage causes a current to flow through the MOS transistor T2, and the capacitor C stores a charge equivalent to a value obtained by natural logarithmically converting the integrated value of the photocurrent. That is, a voltage proportional to a value obtained by natural logarithmically converting the integrated value of the photocurrent is generated at the connection node a between the capacitor C and the source of the MOS transistor T2. However, at this time, the MOS transistors T3 and T5 are in the OFF state.
[0047]
Next, when a pulse signal φV is applied to the gate of the MOS transistor T3 and the MOS transistor T3 is turned on, a current proportional to the voltage applied to the gate of the MOS transistor T4 passes through the MOS transistors T3 and T4 to the output signal line 6. Derived. Since the voltage applied to the gate of the MOS transistor T4 is the voltage applied to the connection node a, the current derived to the output signal line 6 is a value obtained by natural logarithmically converting the integrated value of the photocurrent. After reading a signal (output current) proportional to the logarithmic value of the incident light quantity in this way, the MOS transistor T3 is turned off.
[0048]
(2) Reset operation of each pixel
Hereinafter, the reset operation of the pixel having the circuit configuration as shown in FIG. 7 will be described with reference to the drawings. FIG. 8 is a timing chart of signals given to each signal line connected to each element in the pixel when performing the reset operation. As described in (1), by applying a pulse φV to the gate of the MOS transistor T3, an electric signal (output signal) obtained by logarithmically converting the incident light by each pixel having a circuit configuration as shown in FIG. Output to line 6. When the output signal is output in this way and the pulse φV becomes low level, the reset operation starts. Further, the potential state of the MOS transistor T1 when the pixel of this embodiment is reset is as shown in FIGS. 4B to 4E, as in the first embodiment. Therefore, the reset operation will be described with reference to FIGS.
[0049]
First, after the pulse signal φV is applied to the gate of the MOS transistor T3 and the output signal is output, the reset operation starts. Then, as in the first embodiment, negative charges flow from the source side of the MOS transistor T1, and the potential of the MOS transistor T1 becomes as shown in FIG. 4B.
[0050]
Next, the signal φVPS applied to the source of the MOS transistor T1 is set to a low level, and the MOS transistor T1 is brought into a conducting state as shown in FIG. Therefore, the amount of negative charge flowing in from the source of the MOS transistor T1 increases, and the positive charge accumulated in the gate and drain of the MOS transistor T1, the gate of the MOS transistor T2, and the anode of the photodiode PD is quickly regenerated. Combined.
[0051]
Therefore, as shown in FIG. 4D, the potentials of the drain and under-gate regions of the MOS transistor T1 are lowered. When the potential of the MOS transistor T1 changes in this way, the signal φVPS given to the source of the MOS transistor T1 is set to the high level. Therefore, the potential state of the MOS transistor T1 is reset to the original state as shown in FIG. After resetting the potential state of the MOS transistor T1 to the original state in this way, the pulse signal φVRS is given to the gate of the MOS transistor T5, the capacitor C is discharged through the MOS transistor T5, and the potential of the connection node a is set to the original value. Reset to state.
[0052]
<Third Embodiment>
A third embodiment will be described with reference to the drawings. FIG. 9 is a circuit diagram showing a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Note that elements and signal lines used for the same purpose as the pixel shown in FIG. 7 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0053]
As shown in FIG. 9, in the present embodiment, the potential of the capacitor C and the connection node a is initialized by giving a signal φD to the drain of the MOS transistor T2, thereby eliminating the MOS transistor T5. ing. Other configurations are the same as those of the second embodiment (FIG. 7). In the high level period of the signal φD, integration is performed by the capacitor C as in the first embodiment (FIG. 2). In the low level period, the charge of the capacitor C is discharged through the MOS transistor T2, and the capacitor C The voltage and the gate of the MOS transistor T4 become substantially the low level voltage of the signal φD (reset). In the present embodiment, the configuration is simplified because the MOS transistor T5 can be omitted.
[0054]
In this embodiment, when the imaging operation is performed, as in the second embodiment, the signal φVPS given to the source of the MOS transistor T1 is set to the high level so that the MOS transistor T1 operates in the subthreshold state. Further, the signal φD is set to the high level, and a charge equivalent to a value obtained by natural-logarithmically converting the integrated value of the photocurrent is accumulated in the capacitor C. Then, the MOS transistor T3 is turned on at a predetermined timing, and a current proportional to the voltage applied to the gate of the MOS transistor T4 is led to the output signal line 6 through the MOS transistors T3 and T4.
[0055]
When each pixel is reset, the signal is controlled at the timing shown in FIG. 3 as in the first embodiment. That is, first, as in the first embodiment, the reset operation starts after the pulse signal φV is given. Next, the signal φVPS applied to the source of the MOS transistor T1 is set to a low level to turn on the MOS transistor T1, thereby increasing the amount of negative charge flowing from the source of the MOS transistor T1. Therefore, as in the first embodiment, the positive charges accumulated in the gate and drain of the MOS transistor T1, the gate of the MOS transistor T2, and the anode of the photodiode PD are quickly recombined.
[0056]
Then, the signal φVPS given to the source of the MOS transistor T1 is set to the high level, and the potential state of the MOS transistor T1 is reset to the original state. As described above, after resetting the potential state of the MOS transistor T1 to the original state, the voltage of the signal φD is set to the low level, the capacitor C is discharged, and the potential of the connection node a is reset to the original state. Thereafter, the voltage of the signal φD is returned to a high level so that an imaging operation can be performed.
[0057]
<Fourth Embodiment>
A fourth embodiment will be described with reference to the drawings. FIG. 10 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Note that elements and signal lines used for the same purpose as those of the pixel shown in FIG. 9 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0058]
As shown in FIG. 10, in this embodiment, the DC voltage VPD is applied to the drain of the MOS transistor T2, and the capacitor C and the MOS transistor T4 are omitted. That is, the drain of the MOS transistor T3 is connected to the source of the MOS transistor T2. Other configurations are the same as those of the third embodiment (FIG. 9).
[0059]
In the circuit having such a configuration, when the imaging operation is performed, the signal φVPS applied to the source of the MOS transistor T1 is set to the high level so that the MOS transistor T1 operates in the subthreshold state, as in the third embodiment. To. By operating the MOS transistor T1 in this way, a drain current having a value proportional to the natural logarithm of the photocurrent flows through the MOS transistor T2.
[0060]
When the pulse signal φV is applied to the gate of the MOS transistor T3 to turn it on, a drain current having a value proportional to the natural logarithm of the photocurrent is derived to the output signal line 6 through the MOS transistor T3. At this time, the drain voltage of the MOS transistor Q1 determined by the resistance when the MOS transistor T2 and the MOS transistor Q1 (FIG. 5) are conductive and the current flowing therethrough appears on the output signal line 6 as a signal. After the signal is read in this way, the MOS transistor T3 is turned off.
[0061]
When resetting each pixel, as in the third embodiment, first, after the pulse signal φV is given, the reset operation starts. Next, the signal φVPS applied to the source of the MOS transistor T1 is set to a low level to turn on the MOS transistor T1, thereby increasing the amount of negative charge flowing from the source of the MOS transistor T1.
[0062]
Therefore, as in the first embodiment, the positive charges accumulated in the gate and drain of the MOS transistor T1, the gate of the MOS transistor T2, and the anode of the photodiode PD are quickly recombined. Then, the signal φVPS given to the source of the MOS transistor T1 is set to the high level, and the potential state of the MOS transistor T1 is reset to the original state. As described above, the potential state of the MOS transistor T1 is reset to the original state, and the imaging operation can be performed again.
[0063]
In the present embodiment, unlike the third embodiment, since the optical signal is not once integrated by the capacitor C, the integration time is unnecessary, and the resetting of the capacitor C is unnecessary. Accordingly, the speed of signal processing can be increased. Further, in the present embodiment, compared to the third embodiment, the configuration can be further simplified and the pixel size can be reduced by the amount that the capacitor C and the MOS transistor T4 can be omitted.
[0064]
In the first to fourth embodiments described above, the MOS transistors T1 to T5, which are active elements in the pixel, are all constituted by N-channel MOS transistors. However, these MOS transistors T1 to T5 are all P-channel. Alternatively, the MOS transistor may be used. 12 and 15 to 17 show fifth to eighth embodiments which are examples in which the first to fourth embodiments are configured by P-channel MOS transistors. Therefore, in FIGS. 11 to 17, the polarity of the connection and the polarity of the applied voltage are reversed. For example, in FIG. 12 (fifth embodiment), the photodiode PD has an anode connected to the DC voltage VPD, a cathode connected to the drain of the first MOS transistor T1, and a gate connected to the gate of the second MOS transistor T2. . A signal φVPS is input to the source of the MOS transistor T1.
[0065]
By the way, when the pixel as shown in FIG. 12 performs logarithmic conversion, the DC voltage VPS and the DC voltage VPD satisfy VPS> VPD, which is the reverse of FIG. 2 (first embodiment). The output voltage of the capacitor C has a high initial value and drops due to integration. Further, when turning on the third MOS transistor T3, a low voltage is applied to the gate. Further, in the embodiment of FIG. 15 (sixth embodiment), when turning on the fifth MOS transistor T5, a low voltage is applied to the gate. As described above, when a P-channel MOS transistor is used as compared with the case where an N-channel MOS transistor is used, the voltage relationship and the connection relationship are partially different, but the configuration is substantially the same, and the basic Since the operations are the same, FIG. 12 and FIGS. 15 to 17 are only shown in the drawings, and descriptions of the configurations and operations are omitted.
[0066]
FIG. 11 shows a block circuit configuration diagram for explaining the overall configuration of the solid-state imaging device including the pixels of the fifth embodiment, and the overall configuration of the solid-state imaging device including the pixels of the sixth to eighth embodiments is described. FIG. 13 shows a block circuit configuration diagram for this purpose. About FIG.11 and FIG.13, the same code | symbol is attached | subjected to the same part (same role part) as FIG.1 and FIG.5, and description is abbreviate | omitted. The configuration of FIG. 13 will be briefly described below. P-channel MOS transistor Q1 and P-channel MOS transistor Q2 are connected to output signal lines 6-1, 6-2,..., 6-m arranged in the column direction. The MOS transistor Q1 has a gate connected to the DC voltage line 7, a drain connected to the output signal line 6-1 and a source connected to the line 8 of the DC voltage VPS '.
[0067]
On the other hand, the drain of the MOS transistor Q2 is connected to the output signal line 6-1, the source is connected to the final signal line 9, and the gate is connected to the horizontal scanning circuit 3. Here, the MOS transistor Q1 forms an amplifier circuit as shown in FIG. 14A together with the P-channel MOS transistor Ta in the pixel. The MOS transistor Ta corresponds to the fourth MOS transistor T4 in the sixth and seventh embodiments, and corresponds to the second MOS transistor T2 in the eighth embodiment.
[0068]
In this case, the MOS transistor Q1 is a load resistance or a constant current source of the MOS transistor Ta. Therefore, the relationship between the DC voltage VPS ′ connected to the source of the MOS transistor Q1 and the DC voltage VPD ′ connected to the drain of the MOS transistor Ta is VPD ′ <VPS ′, and the DC voltage VPD ′ is, for example, Ground voltage (ground). The drain of the MOS transistor Q1 is connected to the MOS transistor Ta, and a DC voltage is applied to the gate. The P-channel MOS transistor Q 2 is controlled by the horizontal scanning circuit 3 and leads the output of the amplifier circuit to the final signal line 9. Considering the third MOS transistor T3 provided in the pixel as in the sixth to eighth embodiments, the circuit of FIG. 14A is represented as shown in FIG. 14B.
[0069]
【The invention's effect】
As described above, according to the solid-state imaging device of the present invention, each pixel can be reset quickly, so that responsiveness at the time of imaging can be improved and when a low-luminance subject is imaged. The generated afterimage can be eliminated. Further, if the active element is composed of MOS transistors, high integration is facilitated, and it can be formed on a single chip together with peripheral processing circuits (A / D converter, digital system processor, memory) and the like.
[Brief description of the drawings]
FIG. 1 is a block circuit diagram for explaining an overall configuration of a two-dimensional solid-state imaging device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration of one pixel according to the first embodiment of the present invention.
FIG. 3 is a timing chart of signals given to each element of a pixel used in the first embodiment.
FIG. 4 is a diagram illustrating the relationship between the configuration and potential of a pixel used in the present invention.
FIG. 5 is a block circuit diagram for explaining an overall configuration of a two-dimensional solid-state imaging device according to an embodiment of the present invention.
6 is a circuit diagram of a part of FIG.
FIG. 7 is a circuit diagram showing a configuration of one pixel according to a second embodiment of the present invention.
FIG. 8 is a timing chart of signals given to each element of a pixel used in the second embodiment.
FIG. 9 is a circuit diagram showing a configuration of one pixel according to a third embodiment of the present invention.
FIG. 10 is a circuit diagram showing a configuration of one pixel according to a fourth embodiment of the present invention.
FIG. 11 is a block circuit diagram for explaining the overall configuration of the two-dimensional solid-state imaging device of the present invention in the case where the active element in the pixel is configured by a P-channel MOS transistor.
FIG. 12 is a circuit diagram showing a configuration of one pixel according to a fifth embodiment of the present invention.
FIG. 13 is a block circuit diagram for explaining the entire configuration of the two-dimensional solid-state imaging device of the present invention in the case where the active element in the pixel is configured by a P-channel MOS transistor.
14 is a circuit diagram of a part of FIG.
FIG. 15 is a circuit diagram showing a configuration of one pixel according to a sixth embodiment of the present invention.
FIG. 16 is a circuit diagram showing a configuration of one pixel according to a seventh embodiment of the present invention.
FIG. 17 is a circuit diagram showing a configuration of one pixel according to an eighth embodiment of the present invention.
FIG. 18 is a circuit diagram showing a configuration of one pixel of a conventional example.
[Explanation of symbols]
G11 to Gmn pixels
2 Vertical scanning circuit
3 Horizontal scanning circuit
4-1 to 4-n row selection line
6-1 to 6-m output signal line
7 DC voltage line
8 lines
9 Signal line
10 P-type semiconductor substrate
11 N-type well layer
12 P-type diffusion layer
13,14 N-type diffusion layer
15 Oxide film
16 Polysilicon
PD photodiode
T1 to T5 First to fifth MOS transistors
C capacitor

Claims (18)

A solid-state imaging device having a plurality of pixels, including a photoelectric conversion unit that generates an output signal that is a natural number converted to the amount of incident light, and a lead-out path that leads the output signal of the photoelectric conversion unit to an output signal line In
The photoelectric conversion means is
A photoelectric conversion element in which a DC voltage is applied to the first electrode;
A first transistor comprising a first electrode, a second electrode, and a control electrode, wherein the first electrode and the control electrode are connected to the second electrode of the photoelectric conversion element, and an output current from the photoelectric conversion element flows;
A first electrode; a second electrode; and a control electrode, wherein a DC voltage is applied to the first electrode, the control electrode is connected to the first electrode and the control electrode of the first transistor, and an electric signal is transmitted from the second electrode. And a second transistor that outputs
The first voltage is applied to the second electrode of the first transistor, the first transistor is operated in a subthreshold region below a threshold, and imaging is performed.
Solid-state imaging characterized by applying a second voltage to the second electrode of the first transistor and performing a reset so that a larger current can flow than before applying the second voltage to the first transistor. apparatus. The solid-state imaging device according to claim 1, wherein the pixels are arranged in a matrix. 2. An integration circuit for integrating an electrical signal output from the photoelectric conversion means, and a signal integrated by the integration circuit is derived to the output signal line through the derivation path. Item 3. The solid-state imaging device according to Item 2. The solid-state imaging device according to claim 3, further comprising a reset unit that discharges the charge of the integration circuit after outputting the integrated signal to the output signal line. The reset means includes a transistor having a first electrode, a second electrode, and a control electrode, the first electrode being connected to the integrating circuit,
5. The solid-state imaging device according to claim 4, wherein when the level of the voltage applied to the control electrode of the transistor is changed to make the transistor conductive, the charge accumulated in the integrating circuit is released. Each of the pixels has an amplifying transistor that amplifies the output signal of the photoelectric conversion means, and outputs the output signal of the amplifying transistor to the output signal line through the lead-out path. The solid-state imaging device according to claim 1 or 2. The solid-state imaging device according to claim 6, further comprising a load resistor or a constant current source connected to the output signal line, wherein a total number of the load resistors or constant current sources is less than the total number of pixels. The load resistance or constant current source is a resistance transistor having a first electrode connected to the output signal line, a second electrode connected to a DC voltage, and a control electrode connected to a DC voltage. The solid-state imaging device according to claim 7. The amplifying transistor is an N-channel MOS transistor, and the DC voltage applied to the first electrode of the amplifying transistor is higher than the DC voltage connected to the second electrode of the resistance transistor. The solid-state imaging device according to claim 8. The amplifying transistor is a P-channel MOS transistor, and the DC voltage applied to the first electrode of the amplifying transistor is lower than the DC voltage connected to the second electrode of the resistance transistor. The solid-state imaging device according to claim 8. 3. The switch according to claim 1, wherein the derivation path includes a switch that sequentially selects a predetermined one from all the pixels and derives an output signal of the selected pixel to an output signal line. The solid-state imaging device according to any one of claims 6 to 10. In a solid-state imaging device having a plurality of pixels,
Each pixel is
A photodiode;
A first MOS transistor having a first electrode and a gate electrode connected to one electrode of the photodiode;
A second MOS transistor having a gate electrode connected to the first electrode and the gate electrode of the first MOS transistor;
When causing the pixel to perform an imaging operation, a first voltage is applied to the second electrode of the first MOS transistor so that an electric signal output from the photodiode is converted logarithmically, and the first MOS transistor is turned on. Operate in sub-threshold region below threshold,
When resetting the pixel, a second voltage is applied to the second electrode of the first MOS transistor so that a larger current can flow than before the second voltage is applied to the first transistor. A solid-state imaging device. The pixel includes a fourth MOS transistor having a first electrode connected to a second electrode of the second MOS transistor, a second electrode connected to an output signal line, and a gate electrode connected to a row selection line. The solid-state imaging device according to claim 12. In the pixel, a DC voltage is applied to the first electrode, a gate electrode is connected to the second electrode of the second MOS transistor, and a third MOS that amplifies an output signal output from the second electrode of the second MOS transistor The solid-state imaging device according to claim 12, further comprising a transistor. The pixel includes a fourth MOS transistor having a first electrode connected to a second electrode of the third MOS transistor, a second electrode connected to an output signal line, and a gate electrode connected to a row selection line. The solid-state imaging device according to claim 14. The pixel includes a capacitor having one end connected to the second electrode of the second MOS transistor and being reset via the second MOS transistor when a reset voltage is applied to the first electrode of the second MOS transistor. The solid-state imaging device according to claim 14 or 15, A DC voltage is applied to the first electrode of the second MOS transistor,
The pixel is
A fifth MOS transistor having a first electrode connected to the second electrode of the second MOS transistor and a DC voltage applied to the second electrode;
A capacitor having one end connected to the second electrode of the second MOS transistor and being reset via the fifth MOS transistor when a reset voltage is applied to the gate electrode of the fifth MOS transistor;
The solid-state imaging device according to claim 14, wherein the solid-state imaging device is provided. The MOS transistor which comprises the load resistance connected to the said pixel via the said output signal line, or a constant current source is provided.
Solid-state imaging device.

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