JPH11312799A - Solid-state image-pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image-pickup device which is capable of abtaing pixels of large output, satisfactory in S/N ratio, and wide in dynamic range. SOLUTION: Pixels are arranged in a matrix for the formation of a two-dimensional solid-state image-pickup device, in which the pixels are each composed of a photoelectric conversion photodiode PD, a MOS transistor T1 which logarithmically converts a current outputted from the photodiode PD into a voltage, a MOS transistor T2 to which a logarithmically converted output voltage is applied, a capacitor whose one terminal is so connected as to receive a current outputted from the second electrode of the MOS transistor T2, and other terminal is connected to a direct current voltage, a MOS transistor T3 which amplifies an output voltage of the capacitor C, and a means which leads an amplified voltage to an output signal line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device in which pixels are two-dimensionally arranged.

[0002]

2. Description of the Related Art A photoelectric conversion element such as a photodiode,
Two-dimensional solid-state imaging devices in which pixels including means for extracting photocharges generated by the photoelectric conversion elements to output signal lines are arranged in a matrix (in a matrix) are used for various purposes. By the way, such a solid-state imaging device is roughly classified into a CCD type and a MOS type by means for reading out (extracting) photocharges generated by a photoelectric conversion element. The CCD type has a drawback that the dynamic range is narrow because the photoelectric charge is transferred while being accumulated in the potential well. On the other hand, in the MOS type, charges accumulated in a pn junction capacitance of a photodiode are directly read out through a MOS transistor.

Here, one of the conventional MOS-type solid-state imaging devices is described.
The configuration per pixel is shown in FIG. 24 and described. In the figure, PD is a photodiode whose cathode is M
The gate of the OS transistor T1 and the MOS transistor T
2 drain. MOS transistor T
1 is connected to the drain of the MOS transistor T3, and the source of the MOS transistor T3 is connected to the output signal line V3.
connected to out. The DC voltage VDD is applied to the drain of the MOS transistor T1, and the DC voltage Vss is applied to the source of the MOS transistor T2 and the anode of the photodiode.

When light strikes the photodiode PD, photocharges are generated, and the charges are stored in the gate of the MOS transistor T1. Here, a pulse is given to the gate of the MOS transistor T3 to turn on the MOS transistor T3.
Then, a current proportional to the charge of the gate of the MOS transistor T1 is led to the output signal line through the MOS transistors T1 and T3. In this way, an output current proportional to the amount of incident light can be read. After reading the signal, the gate voltage of the MOS transistor T1 can be initialized by turning off the MOS transistor T3 and turning on the MOS transistor T2.

[0005]

As described above, the conventional M
The OS-type solid-state imaging device reads out the photocharge generated by the photodiode in each pixel and stored in the gate of the MOS transistor as it is, so the dynamic range is narrow, and the fluctuation component and noise component of the light source are included. Since it is output and the output signal is at a low level, there is a disadvantage that the S / N is poor and a high-quality image signal cannot be obtained as a whole.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a solid-state imaging device capable of obtaining a large output of a pixel. Another object of the present invention is to provide a solid-state imaging device capable of obtaining an imaging signal having a good S / N. Still another object is to provide a solid-state imaging device having a wide dynamic range.

[0007]

In order to achieve the above object, according to the first aspect of the present invention, in a two-dimensional solid-state imaging device in which pixels are arranged in a matrix, each pixel is provided with a photoelectric conversion unit. A capacitor for integrating the output signal of the photoelectric conversion means, an amplifier for amplifying the voltage of the output of the capacitor, and a lead-out path for leading the voltage-amplified voltage to an output signal line.

According to this configuration, since the photoelectric conversion output signal is integrated by the capacitor, the fluctuation component of the light source and high frequency noise contained in the photoelectric conversion output signal are absorbed and removed by the capacitor. Then, the photoelectric conversion output signal from which these fluctuation components and high-frequency noise have been removed is further amplified in voltage by an amplifier and output with a sufficient magnitude, so that an imaging signal with high sensitivity is obtained. Further, since the photoelectric conversion means, the capacitor, the amplifier, and the derivation means are provided for each pixel, more accurate and stable signal reading is possible.

According to a second aspect of the present invention, in the two-dimensional solid-state imaging device having pixels arranged in a matrix, each pixel includes a photoelectric conversion element; and an output current of the photoelectric conversion element is logarithmically converted. Logarithmic conversion means for converting to a converted voltage;
A transistor having a first electrode, a second electrode, and a control electrode, to which the output voltage of the logarithmic conversion means is applied; and a capacitor having one end connected to receive an output current from the second electrode of the transistor An amplifier for voltage-amplifying the output of the capacitor; and a lead-out path for leading the amplified voltage to an output signal line.

According to this configuration, since the photoelectric conversion output signal is integrated by the capacitor, the fluctuation component of the light source and high frequency noise contained in the photoelectric conversion output signal are absorbed and removed by the capacitor. Then, the photoelectric conversion output signal from which these fluctuation components and high-frequency noise have been removed is further amplified in voltage by an amplifier and output with a sufficient magnitude, so that an imaging signal with high sensitivity is obtained. Further, in this configuration, the dynamic range of the solid-state imaging device is widened by logarithmic compression conversion.

According to a third aspect of the present invention, the amplifier has the first configuration.
An amplifying transistor having an electrode, a second electrode, and a control electrode to which an output of the capacitor is applied, and a load resistor connected to an output line leading to a second electrode of the amplifying transistor. Good. This load resistance may be shared by some pixels. Therefore, as described in claim 4, the total number may be smaller than the total number of pixels. In the case where an amplifying transistor is used, the lead-out path may be connected to a second electrode of the amplifying transistor, and a signal may be derived from the second electrode.

As a load resistance, a first electrode connected to a second electrode of the amplifying transistor, a second electrode connected to a DC voltage, and a control electrode connected to a DC voltage. May be used. A MOS transistor may be used as the amplification transistor. When an n-channel MOS transistor is used, the DC voltage applied to the first electrode of the amplifying transistor may be lower than the DC voltage connected to the second electrode of the resistor transistor. I just need.

A p-channel M as an amplifying transistor
When an OS transistor is used, the DC voltage applied to the first electrode of the amplifying transistor may be higher than the DC voltage connected to the second electrode of the resistor transistor. . As the derivation route,
According to a ninth aspect of the present invention, a device including a switch for sequentially selecting a predetermined pixel from all the pixels and leading an amplified voltage from the selected pixel to an output signal line may be used. According to the tenth aspect of the invention, while the output of the first capacitor is derived, the second capacitor for performing the next integration is provided, so that the signal of the first capacitor is read out and the integration of the second capacitor is performed simultaneously. This makes it possible to support moving image capturing.

[0014] Further, according to the present invention, a switch is provided in a current input path to the capacitor, and this switch is simultaneously controlled in all the pixels to make the integration time of all the pixels the same. . According to the present invention, the readout timing of the electric charge stored in the capacitor does not shift sequentially for each row, and the integration time (and timing) of the capacitor is the same for all pixels. There is no signal error based on the above.

According to a twelfth aspect of the present invention, in the two-dimensional solid-state imaging device in which pixels are arranged in a matrix, each pixel includes a photodiode; and one electrode of the photodiode has a first electrode. A first MOS transistor connected to a gate electrode and operating in a sub-threshold region; a second MOS transistor having a gate connected to the gate of the first MOS transistor and a first electrode connected to a DC voltage and operating in a sub-threshold region; A capacitor connected to the second electrode of the 2MOS transistor and having the other end connected to a DC voltage and integrating a signal based on the photocharge generated by the photodiode; a gate connected to one end of the capacitor and the first electrode connected to the DC voltage; A third MOS transistor connected to operate as an amplifier;
A fourth MOS transistor having a first electrode connected to the one end of the capacitor, a second electrode connected to the DC voltage, and turned on when a reset signal is input to the gate to reset the capacitor to an initial state; 3M
The first electrode is connected to the second electrode of the OS transistor, and the second electrode
A fifth MOS transistor for reading has an electrode connected to the output signal line and a gate electrode connected to the row selection line.

According to such a configuration, the photocurrent generated by the photodiode is logarithmically converted by the first MOS transistor, and its gate voltage becomes a voltage proportional to the logarithmically converted current. This voltage charges the capacitor through the second MOS transistor. When the integration is completed, the fifth MOS transistor is turned on, and the output based on the electric charge of the capacitor is amplified by the third MOS transistor and is led to the output signal line. Thereafter, when a reset pulse is applied to the gate of the fourth MOS transistor, the capacitor is initialized, and integration by the capacitor is started again.

According to a thirteenth aspect of the present invention, in a two-dimensional solid-state imaging device having pixels arranged in a matrix, each pixel includes the following: a photodiode; A first MOS transistor having a first electrode and a gate electrode connected to one of the electrodes and operating in a sub-threshold region;
A second MOS transistor connected to the gate of the transistor and operating in the subthreshold region;
A capacitor connected to the second electrode of the OS transistor and having the other end connected to the DC voltage and being reset via the second MOS transistor when a reset voltage is applied to the first electrode of the second MOS transistor; A third MOS transistor having a gate connected to one end and a first electrode connected to a DC voltage to operate as an amplifier; a first electrode connected to a second electrode of the third MOS transistor, a second electrode connected to an output signal line, and a gate A fifth MOS transistor for reading whose electrode is connected to the row selection line.

In this configuration, the integration of the capacitor and the reading of the capacitor voltage are the same as in the case of the twelfth aspect.
When a reset voltage is applied to the first electrode of the MOS transistor, the charge of the capacitor is discharged through the second MOS transistor.

According to a fourteenth aspect of the present invention, in a two-dimensional solid-state imaging device having pixels arranged in a matrix, each pixel includes the following: a photodiode; A first MOS transistor having a first electrode and a gate electrode connected to one of the electrodes and operating in a sub-threshold region;
A second MOS connected to the gate of the transistor and having a first electrode connected to a DC voltage and operating in a subthreshold region
One end of a second MOS transistor;
A capacitor connected to the electrode and having the other end connected to a DC voltage and integrating a signal based on photocharge generated by the photodiode; a gate connected to one end of the capacitor and a first electrode connected to the DC voltage to function as an amplifier; An operating third MOS transistor; a first MOS transistor at one end of the capacitor;
A fourth MOS transistor having an electrode connected thereto, a second electrode connected to a DC voltage, and a DC voltage applied to a gate, which is always turned on; a first electrode connected to a second electrode of the third MOS transistor and a second electrode connected to an output signal line; A fifth MOS transistor for reading having a connected gate electrode connected to a row selection line;

In this configuration, the fourth MOS transistor which is always ON is equivalent to a resistor, and a capacitor having a predetermined value is connected to the capacitor. Therefore, the initial value of the capacitor is determined by its resistance. In other words, the initial value can be adjusted by changing the DC voltage applied to the gate electrode of the fourth MOS transistor.

According to a fifteenth aspect of the present invention, in the two-dimensional solid-state imaging device having pixels arranged in a matrix, each pixel includes a photodiode; and one electrode of the photodiode has a first electrode. A first MOS transistor connected to a gate electrode and operating in a sub-threshold region; a second MOS transistor having a gate connected to the gate of the first MOS transistor and having a first electrode connected to a DC voltage and operating in a sub-threshold region; A sixth electrode in which one electrode is connected to the second electrode of the second MOS transistor and a switching voltage is applied to the gate;
An S transistor; a capacitor having one end connected to the second electrode of the sixth MOS transistor and the other end connected to a DC voltage for integrating a signal based on a photocurrent generated by the photodiode; and a gate at one end of the capacitor. A third MOS transistor connected as a first electrode and connected to a DC voltage to operate as an amplifier; a first electrode connected to the one end of the capacitor, a second electrode connected to the DC voltage, and a reset signal applied to the gate; A fourth MOS transistor which is turned on when input and resets the capacitor to an initial state; a first electrode connected to a second electrode of the third MOS transistor, a second electrode connected to an output signal line, and a gate electrode connected to a row selection line And a fifth MOS transistor for reading connected to the second MOS transistor, and turning off the sixth MOS transistor. The so that read out voltage amplifies the voltage of the capacitor in a state of stopping the integration capacitor at the 3MOS transistor.

In this configuration, by simultaneously controlling the sixth MOS transistors of all the pixels, the integration time of all the pixels can be made the same.

According to a sixteenth aspect of the present invention, in the two-dimensional solid-state imaging device in which pixels are arranged in a matrix, each pixel includes a photodiode; and one electrode of the photodiode has a first electrode. A first MOS transistor connected to the gate electrode and operating in a sub-threshold region; a second MOS transistor having a gate connected to the gate of the first MOS transistor and applied with a clock to the first electrode to operate in the sub-threshold region; A capacitor connected to the second electrode of the second MOS transistor via a switch and having the other end connected to a DC voltage for integrating a signal based on a photocurrent generated by the photodiode; a gate connected to one end of the capacitor, Third electrode whose electrode is connected to a DC voltage and operates as an amplifier
An OS transistor; a second terminal having one end connected to the second electrode of the third MOS transistor and the other end connected to the output signal line;
The first switch is turned on, the output current of the second MOS transistor is supplied to the capacitor to integrate the signal, and the second switch is turned on while the first switch is turned off to turn off the capacitor. The signal is amplified by a third MOS transistor to be led to an output signal line, and then the first switch is turned ON and the second MO
During the reset voltage period of the clock applied to the first electrode of the S transistor, the capacitor is initialized through the second MOS transistor and the first switch.

In this configuration, the capacitor is initialized (reset) when the electric charge of the capacitor is changed to the first switch and the second MOS.
This is performed by discharging through a transistor.

According to a seventeenth aspect of the present invention, in the two-dimensional solid-state imaging device having pixels arranged in a matrix, each pixel includes a photodiode; and one electrode of the photodiode has a first electrode. A first MOS transistor connected to the gate electrode and operating in a sub-threshold region; a second MOS transistor having a gate connected to the gate of the first MOS transistor and applied with a clock to the first electrode to operate in the sub-threshold region; A capacitor connected to the second electrode of the second MOS transistor via a switch and having the other end connected to a DC voltage for integrating a signal based on a photocurrent generated by the photodiode; a gate connected to one end of the capacitor, Third electrode whose electrode is connected to a DC voltage and operates as an amplifier
An OS transistor; a fourth MOS transistor having one end connected to one end of the capacitor, the other end connected to a DC voltage, and a gate receiving a reset signal;
A second switch connected to the second electrode of the OS transistor and having the other end connected to the output signal line; turning off the first switch to amplify the voltage of the capacitor signal with the third MOS transistor to the output signal line; During reading, the pn junction capacitance related to the second electrode of the second MOS transistor is reset during the reset voltage period of the clock of the second electrode of the second MOS transistor, and the signal to the pn junction capacitance is reset during another level period of the clock. Is started, and after reading of the signal of the capacitor is completed, the first switch is turned on to transfer the accumulated charge of the pn junction capacitance to the capacitor and continue the integration of the capacitor.

According to the invention, in a two-dimensional solid-state imaging device having pixels arranged in a matrix, each pixel includes a photodiode; and one electrode of the photodiode has a first electrode. A first MOS transistor connected to the gate electrode and operating in the sub-threshold region; a second MOS transistor having a gate connected to the gate of the first MOS transistor, a DC voltage being applied to the first electrode and operating in the sub-threshold region; A first capacitor connected to the second electrode of the 2MOS transistor and having the other end connected to a DC voltage and integrating a signal based on a photocurrent generated by the photodiode;
A first switch connected to one end of the capacitor; a second capacitor having one end connected to the other end of the first switch and the other end connected to the DC voltage; a first switch having a gate connected to the one end of the second capacitor; A third MOS transistor having an electrode connected to a DC voltage and operating as an amplifier; a fourth MOS transistor having a first electrode connected to one end of the second capacitor, a second electrode connected to the DC voltage, and a reset signal input to the gate;
A transistor; one end of the second MOS transistor
A second switch connected to the electrode and having the other end connected to the output signal line.
When the voltage of the capacitor signal is amplified by the third MOS transistor and read out to the output signal line, the next integration is started by the first capacitor.
After the transistor is turned on to reset the second capacitor, the first switch is turned on to transfer the charge of the first capacitor to the second capacitor and continue the integration of the second capacitor.

[0027] According to the present invention, in the two-dimensional solid-state imaging device in which pixels are arranged in a matrix, each pixel includes a photodiode; and one electrode of the photodiode has a first electrode. A first MOS transistor connected to the gate electrode and operating in the sub-threshold region; a second MOS transistor having a gate connected to the gate of the first MOS transistor and applied with a clock to the first electrode to operate in the sub-threshold region; A first capacitor connected to the second electrode of the transistor and having the other end connected to a DC voltage and integrating a signal based on a photocurrent generated by the photodiode;
A first switch connected to one end of the capacitor; a second capacitor having one end connected to the other end of the first switch and the other end connected to the DC voltage; a first electrode having a gate connected to one end of the second capacitor; A third MOS transistor connected to a DC voltage and operating as an amplifier;
A second switch connected to the second electrode of the S transistor and having the other end connected to the output signal line. The voltage integrated by the first capacitor is turned on to transfer the voltage to the second capacitor. The first capacitor is reset, then the first switch is turned off, and the voltage based on the charge of the second capacitor is amplified by the third MOS transistor and read out to the output signal line. Is to be performed.

According to a twentieth aspect of the present invention, in the two-dimensional solid-state imaging device having pixels arranged in a matrix, each pixel includes a photodiode; and one electrode of the photodiode has a first electrode. A first MOS transistor connected to the gate electrode and operating in the sub-threshold region; a second MOS transistor having a gate connected to the gate of the first MOS transistor and applied with a clock to the first electrode to operate in the sub-threshold region; A first capacitor connected to the second electrode of the transistor and having the other end connected to a DC voltage and integrating a signal based on a photocurrent generated by the photodiode;
A first switch connected to one end of the capacitor; a second capacitor having one end connected to the other end of the first switch and the other end connected to the DC voltage; a first electrode having a gate connected to one end of the second capacitor; A third MOS transistor connected to a DC voltage and operating as an amplifier; a fourth MOS transistor having a first electrode connected to one end of the second capacitor, a second electrode connected to the DC voltage, and a reset voltage applied to the gate; A second switch having one end connected to the second electrode of the third MOS transistor and the other end connected to the output signal line, and amplifying the voltage of the signal of the second capacitor by the third MOS transistor with the first switch turned off. The first capacitor is reset during the reset voltage level period of the clock applied to the second electrode of the second MOS transistor during readout and reading. To start integration of the first capacitor in another level period of the clock, turn on the fourth MOS transistor to reset the second capacitor after reading is completed, and then turn on the first switch to turn on the first capacitor. Is transferred to the second capacitor and the integration of the second capacitor is continued.

According to a twenty-first aspect of the present invention, in the solid-state imaging device according to any one of the twelfth to twentieth aspects, the third MOS transistor is connected to the pixel via the output signal line. The third on the drain side
The present invention is characterized in that it comprises a MOS transistor forming a load resistance of the MOS transistor.

As described in claim 22 and claim 23, for each column of the pixel matrix, the first electrode connected to the fifth MOS transistor or the second switch of each pixel included in the column, A resistor MO having a second electrode connected thereto and a gate connected to a DC voltage
An S transistor may be further provided.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the solid-state imaging device according to the present invention will be described below with reference to the drawings. FIG. 1 schematically shows a configuration of a part of a two-dimensional MOS type solid-state imaging device embodying the present invention. In the figure, G11, G12,.
.., Gmn indicate pixels arranged in a matrix (matrix arrangement). 2 is a vertical scanning circuit, which is a row (line)
.., 4-n are sequentially scanned.
Reference numeral 3 denotes a horizontal scanning circuit, which outputs an output signal line 6-1 from a pixel;
The photoelectric conversion signals derived in 6-2,..., 6-m are sequentially read in the horizontal direction for each pixel. 5 is a power supply line. For each pixel, the lines 4-1 4-2,.
4-n, output signal lines 6-1, 6-2..., 6-m, power supply line 5, and other lines (for example, a clock line and a bias supply line) are also connected. 1
In these figures, these are omitted and shown in each embodiment after FIG.

Output lines 6-1, 6-2,..., 6-m
A pair of p-channel MOS transistors Q1 and n-channel MOS transistors Q2 are provided as shown in FIG. MOS transistor Q 1 has a gate connected to DC voltage line 7, a drain connected to output signal line 6-1, and a source connected to DC power supply line 8. On the other hand, the drain of the MOS transistor Q2 is connected to the output signal line 6-1, the source is connected to the final signal line 9, and the gate is connected to the horizontal scanning circuit 3.

As described later, the pixels G11 to Gmn have
A third MOS transistor T3 is provided for amplifying and outputting a voltage based on the photocharge generated in those pixels. FIG. 2A shows the connection relationship between the MOS transistor T3 for amplification and the MOS transistor Q1. Here, the relationship between the DC voltage VDD 'connected to the source of the MOS transistor Q1 and the DC voltage VSS' connected to the source of the third MOS transistor T3 is as follows.
VDD '>VSS', and the DC voltage VSS 'is, for example, a ground voltage (ground). In this circuit configuration, a signal is input to the gate of the lower MOS transistor T3,
A DC voltage is constantly applied to the gate of S transistor Q1. For this reason, the upper MOS transistor Q1 is equivalent to a resistor (load resistor), and the circuit in FIG. 2A is a source-grounded amplifier. In this case, what is amplified and output from the drain side of the MOS transistor T3 may be considered to be a voltage.

The MOS transistor Q2 is connected to the horizontal scanning circuit 3
And is operated as a switch element. still,
As described later, a fifth MOS transistor T5 for a switch is also provided in the pixel of each embodiment. This fifth
When the MOS transistor T5 is also included, FIG.
The circuit of FIG. 2 is exactly as shown in FIG. That is, the fifth
The MOS transistor is the MOS transistor Q1 and the third M
It is inserted between the OS transistor T3. Here, the fifth MOS transistor T5 is for selecting a row, and the transistor Q2 is for selecting a column. The configuration shown in FIGS. 1 and 2 is a configuration common to the first to ninth embodiments described below. In any case, by configuring the voltage amplifier circuit as shown in FIG. 2, a large signal gain can be output.

Therefore, in the case where the pixel performs logarithmic conversion of the photocurrent in order to expand the dynamic range, the output signal is small as it is, but is amplified to a sufficiently large signal by the amplifier circuit, so that the subsequent signal is amplified. Processing in a processing circuit (not shown) is facilitated. Also, the transistor Q1 forming the load resistance portion of the amplifier circuit is not provided in the pixel, and the output signal line 6 to which a plurality of pixels arranged in the column direction are connected is connected.
.., 6-m, the number of load resistors can be reduced, and the area occupied by the amplifier circuit on the semiconductor chip can be reduced.

Hereinafter, each embodiment will be described with reference to the configuration of a pixel portion. In each of the following embodiments, the signal is set to 3M
Although it has been described that the voltage is amplified by the OS transistor T3 and led to the output signal line, the voltage is amplified by a combination of the third MOS transistor T3 and the MOS transistor Q1 for the load resistance. It should be understood. It should be noted that, in this specification, "connection to a DC voltage" includes connection to a ground voltage, that is, "ground".

<First Embodiment> In FIG. 3, a pn photodiode PD forms a photosensitive portion (photoelectric conversion portion). The anode of the photodiode PD is the first MO
The drain and gate of the S transistor T1, and the second M
It is connected to the gate of the OS transistor T2. Second
The source of the MOS transistor T2 is connected to the gate of the third MOS transistor T3 and the drain of the fourth MOS transistor T4, and the DC voltage Vss2 is applied to the drain of the third MOS transistor T3. This voltage Vss2 is, for example, a ground voltage. Third MOS
The source of the transistor T3 is connected to the drain of the fifth MOS transistor T5. The source of the fifth MOS transistor T5 is connected to the output signal line 6.

Further, a DC voltage VDD is applied to the cathode of the pn photodiode PD and the drain of the second MOS transistor T2. On the other hand, the DC voltage Vss is applied to the source of the first MOS transistor T1, and the DC voltage Vss is also applied to the source of the second MOS transistor T2 via the capacitor (C). The DC voltage VRS is applied to the source of the fourth MOS transistor T4. A reset voltage ΦRS is applied to the gate of the fourth MOS transistor T4. Both the first and second MOS transistors T1 and T2 are biased to operate in the sub-threshold region.

When light strikes the photodiode PD, a photocurrent is generated, and a voltage having a value obtained by logarithmically converting the photocurrent is generated at the gate of the first MOS transistor T1 due to the subthreshold characteristic of the MOS transistor.
With this voltage, electric charge equivalent to a value obtained by logarithmically converting the integrated value of the photocurrent is accumulated in the capacitor C. Where the 5M
A pulse ΦV is given to the gate of the OS transistor T5,
When the MOS transistor T5 is turned on, a current proportional to the charge stored in the gate of the third MOS transistor T3 passes through the third and fifth MOS transistors T3 and T5,
It is led out to the output signal line 6 in the form of voltage amplification by the third MOS transistor T3. Thus, a signal (output voltage) proportional to the logarithmic value of the incident light amount can be read.
After reading the signal, turn off the fifth MOS transistor T5
By turning on the fourth MOS transistor T4 in this manner, the capacitor C and the gate voltage of the third MOS transistor T3 can be initialized.

Second Embodiment As shown in FIG. 4, in the second embodiment, a clock φD is applied to the drain of the second MOS transistor T2 to reset (initialize) the gate voltage of the capacitor C and the third MOS transistor T3. Thus, the configuration is such that the fourth MOS transistor T4 is omitted. Other configurations are the same as those of the first embodiment (FIG. 3). Note that the clock ΦD
In the high level period, integration is performed on the capacitor C. In the low level period, the charge of the capacitor C and the third
The charge of the gate of the MOS transistor is discharged through the MOS transistor T2, and the voltage of the capacitor C and the third
The gate of the MOS transistor T3 is initialized to approximately the low level voltage of the clock φD (reset). In the second embodiment, the configuration is simplified because the fourth MOS transistor T4 can be omitted.

<Third Embodiment> As shown in FIG.
The embodiment is characterized in that an n-channel type sixth MOS transistor T6 is inserted as a switch between the second MOS transistor T2 and the capacitor C with respect to the first embodiment (FIG. 3). The drain of the sixth MOS transistor T6 is connected to the source of the second MOS transistor T2, the source is connected to the capacitor C, and the integration time control voltage (switching voltage) ФINT is applied to the gate. The integration operation of the capacitor C is performed while the integration time control voltage ФINT is set to the high level and the sixth MOS transistor T6 is turned on. Then, when reading the signal of the capacitor C, the fifth MOS transistor T5 is turned on while the integration time control voltage ФINT is set to low level and the sixth MOS transistor T6 is turned off, and the third and fifth MOS transistors T3,
Third MOS transistor T to output signal line 6 through T5
The data is read out in the form of voltage amplification in step 3.

After the signal is read, the fifth MOS transistor T5 is turned off and the sixth MOS transistor T6
With the fourth MOS transistor T4 turned off.
By resetting N, the reset (initialization) of the capacitor C and the gate voltage of the third MOS transistor T3 is performed. Thereafter, the sixth MOS transistor T6 is turned on to perform the next integration by the capacitor C. In the third embodiment, when a pulse is applied to the gates of the sixth MOS transistors T6 of all the pixels arranged two-dimensionally at the same time and for the same time, all the pixels integrate the electric charge integrated for the same time and for the same time. It can be stored in the capacitor C of the pixel.

<Fourth Embodiment> As shown in FIG.
The embodiment is different from the first embodiment (FIG. 3) in that the fourth MOS
The difference is that the transistor T4 is omitted, the clock φD is applied to the drain of the second MOS transistor T2, and the sixth MOS transistor T6 is inserted as a switch between the source of the second MOS transistor and the capacitor C. Are the same. The drain of the sixth MOS transistor T6 is the second MO transistor.
The source of the S transistor T2 is connected, the source is connected to the capacitor, and the gate is connected to the integration time control voltage ФINT
Is applied.

When light strikes the photodiode PD, a photocurrent is generated, and the gate of the MOS transistor T1 has M
Due to the subthreshold characteristic of the OS transistor, a voltage having a value obtained by logarithmically converting the photocurrent is generated. Due to this voltage, an electric charge equivalent to the value obtained by logarithmically converting the integrated value of the photocurrent is accumulated in the capacitor C. When a pulse for turning ON for the same time is given, all the pixels can accumulate the electric charge integrated for the same time and for the same time in the capacitor C of each pixel.

Next, a pulse ΔV is applied to the gate of the fifth MOS transistor T5, and the fifth MOS transistor T5 is
When N is set, a voltage proportional to the charge stored in the gate of the third MOS transistor T3 (this charge depends on the charge amount of the capacitor C) passes through the third and fifth MOS transistors T3 and T5, and the signal output line 6 To the third MOS transistor T3. Thus, a signal proportional to the logarithmic value of the incident light amount can be read. After the signal is read, the fifth MOS transistor T5
Is turned off, the sixth MOS transistor T6 is turned on, and the low level of the clock ФD is applied to the drain of the second MOS transistor T2 to initialize the capacitor C, thereby initializing the gate voltages of the capacitor C and the third MOS transistor T3. Can be.

<Fifth Embodiment> As shown in FIG.
This embodiment differs from the third embodiment (FIG. 5) mainly in that a clock #D is applied to the drain of the second MOS transistor T2. Cs is the second MO
This is a pn junction capacitance related to the source of the S transistor T2 (the drain of the sixth MOS transistor T6).

The junction capacitance Cs is, as shown in FIG. 12, the P-well layer 10 formed on the n-type semiconductor substrate 100.
1 and the source region 102 of the second MOS transistor T2. However, the source region 102 is also used as the drain region 105 of the sixth MOS transistor T6. In FIG. 12, reference numeral 103 denotes a drain region of the second MOS transistor T2, and reference numeral 106 denotes a source region of the sixth MOS transistor T6. 10
4 and 107 are second and sixth MOS transistors T, respectively.
2. T6 gate electrode.

When light is applied to the photodiode PD to generate a photocurrent, a voltage having a value obtained by logarithmically converting the photocurrent is generated at the gate of the first MOS transistor T1 due to the subthreshold characteristic of the MOS transistor. Due to this voltage, an electric charge equivalent to a value obtained by logarithmically converting the integrated value of the photocurrent is accumulated in the capacitor C. Here, the sixth MOS transistors T of all the pixels arranged two-dimensionally are stored.
When a pulse is given to the gate 6 at the same time and the same time, all the pixels can accumulate the electric charge integrated at the same time and the same time in the capacitor C of each pixel.

Next, a pulse ΔV is applied to the gate of the fifth MOS transistor T5, and the fifth MOS transistor T5
Is turned on, a voltage proportional to the charge stored in the gate of the third MOS transistor T3 passes through the third and fifth MOS transistors T3 and T5, and is output to the output signal line 6 by the third MO.
It is derived in the form of voltage amplification by the S transistor T3. Thus, a signal proportional to the logarithmic value of the incident light amount can be read. At the end of integration of each pixel (6th MO
After the S transistor T6 is turned off), the second MOS
A low level of the clock #D is applied to the drain of the transistor T2, and the source of the second MOS transistor (the drain of the third MOS transistor) is initialized, that is, the junction capacitance Cs is initialized (reset). The integration into the junction capacitance Cs is started from when ФD becomes high level, and the signal of the next frame is accumulated in the junction capacitance Cs during the signal readout period.

After reading out the signals of all the pixels (the signals of the current frame), the fourth MOS transistor T4 is turned off.
N and the capacitor C and the third MOS transistor T3
Is initialized. Next, the fourth MOS transistor T4 is turned off and the sixth MOS transistor T6
Is turned on, the electric charge accumulated in the junction capacitance Cs is transferred to the capacitor C, and the integration of the capacitor C is continued. Thereby, it has an integration function at the same time and at the same time, and can cope with a moving image. In particular, by performing a part of the integration time (integration into the junction capacitance Cs) in parallel with the reading, the imaging time can be reduced, and the moving image can be captured at a TV rate. still,
The source of the fourth MOS transistor T4 has a reset voltage V
Connected to RS.

<Sixth Embodiment> As shown in FIG.
The embodiment is different from the first embodiment (FIG. 3) in that a predetermined DC voltage VB is always applied to the gate of the fourth MOS transistor T4 as a reset voltage, and the other configurations are the same as those of the first embodiment. This is the same as the embodiment. In the present embodiment, the fourth MOS transistor T4, which is always ON, is equivalent to a resistor, and a capacitor having a predetermined value is connected to the capacitor. Therefore, the initial value of the capacitor is
It will be determined by that resistance. In other words, the fourth
The initial value can be adjusted by changing the DC voltage applied to the gate electrode of the MOS transistor T4.

<Seventh Embodiment> As shown in FIG.
This embodiment differs from the first embodiment (FIG. 3) in that two capacitors C1 and C2 are provided as capacitors and a sixth MOS transistor T6 formed of an n-channel MOS transistor is connected as a switch between them. The other configuration is the same as that of the first embodiment. In FIG. 9, the second MOS transistor T2
A first capacitor C1 is connected between the source of the first capacitor C1 and the DC voltage Vss, and a sixth MOS as a switch is connected between one end of the first capacitor C1 and the source of the second MOS transistor T2.
The drain of the transistor T6 is connected. The second capacitor C2 is connected between the source of the sixth MOS transistor T6 and the DC voltage Vss3. Further, the gate of the third MOS transistor T3 for amplification is connected to the sources of the second capacitor C2 and the sixth MOS transistor T6.

When light is applied to the photodiode PD to generate a photocurrent, a voltage having a value obtained by logarithmically converting the photocurrent is generated at the gate of the first MOS transistor T1 due to the subthreshold characteristic of the MOS transistor. With this voltage, electric charge equivalent to a value obtained by logarithmically converting the integrated value of the photocurrent is accumulated in the first capacitor C1. And
When a pulse φG is applied to the gate of the sixth MOS transistor T6 and a pulse φG is applied to the gate of the transistor T6 to turn on the transistor T6, the electric charge integrated by the first capacitor C1 is transferred to the second capacitor C2. . At this time, if the capacity of the second capacitor C2 is selected to be sufficiently larger than the capacity of the first capacitor C1, most of the charge of the first capacitor C1 is transferred to the second capacitor C2. Therefore, the first capacitor C1 is equivalent to being reset. The charge is transferred to the second capacitor C2
After the transfer, integration is continued.

Next, the sixth MOS transistor is turned off, and the pulse of the voltage ΔV is applied to the gate of the fifth MOS transistor T5.
When the fifth MOS transistor T5 is turned on, a voltage proportional to the charge accumulated in the gate of the third MOS transistor T3 (this charge depends on the charge amount of the second capacitor C2) is applied to the third and fifth MOS transistors T5. Transistor T
3, through T5, to the output signal line 6. In this way, the output voltage proportional to the logarithmic value of the incident light amount is
The data can be read out in a form amplified by the S transistor T3. After the signal is read, the fifth MOS transistor T5
Is turned off and the fourth MOS transistor T4 is turned on, whereby the second capacitor C2 and the MOS transistor T3 are turned on.
Can be initialized. In this embodiment, the control of the sixth MOS transistor T6 of all the pixels is performed in the same manner, so that the integration timing (and therefore the integration time) of all the pixels can be made the same.

<Eighth Embodiment> As shown in FIG. 10, the eighth embodiment is different from the seventh embodiment (FIG. 9) in the 2nd embodiment.
The fourth embodiment differs from the seventh embodiment only in that the fourth MOS transistor T4 is eliminated by applying the clock #D to the drain of the OS transistor T2, and the other connection configurations are the same. In this embodiment, the integration of the first capacitor C1 and the integration of the second capacitor C2
The transfer to the memory and the reading of the contents of the second capacitor C2 are the same as in the seventh embodiment.

After the signal reading is completed, the capacitor C2
Reset, the sixth MOS transistor T6
Is turned on, the low level voltage of the clock #D is applied to the drain of the second MOS transistor T2, whereby the charge of the first capacitor C1 is discharged through the second MOS transistor T2 and the second capacitor C2
Is discharged through the sixth MOS transistor T6 and the second MOS transistor T2, and the first and second capacitors C1 and C2 are simultaneously set (initialized) to the low level voltage of the clock #D.

<Ninth Embodiment> As shown in FIG. 11, the ninth embodiment is different from the seventh embodiment (FIG. 9) in the 2nd embodiment.
The other part is the same as that of the seventh embodiment except that the clock ФD is applied instead of the DC voltage to the drain of the OS transistor T2. In this embodiment, the reset (initialization) of the first and second capacitors C1 and C2 is performed independently of each other. That is, the reset of the first capacitor C1 is performed by applying a low level voltage of the clock $ D to the drain of the second MOS transistor T2, and the reset of the second capacitor C2 is performed by resetting the fourth capacitor.
This is performed by turning on the MOS transistor T4.

When light is applied to the photodiode PD to generate a photocurrent, a voltage having a value obtained by logarithmically converting the photocurrent is generated at the gate of the first MOS transistor T1 due to the subthreshold characteristic of the MOS transistor. With this voltage, electric charge equivalent to a value obtained by logarithmically converting the integrated value of the photocurrent is accumulated in the first capacitor C1. Therefore, the drains T2 of all the second MOS transistors T2
At the same time and for the same time, to start the integration into the capacitor C1.
When the MOS transistor T6 is turned on, the first capacitor C
The charge integrated by 1 is transferred to the second capacitor C2. Here, the sixth MO of all the pixels arranged two-dimensionally
When a pulse is applied to the gate of the S transistor T6 at the same time and the same time, all the pixels can accumulate the electric charge integrated at the same time and the same time in the second capacitor C2 of each pixel.

Next, a pulse ΦV is applied to the gate of the fifth MOS transistor T5 to turn on the MOS transistor T5.
Then, a voltage proportional to the charge stored in the gate of the third MOS transistor T3 (this charge depends on the charge amount of the second capacitor C2) passes through the third and fifth MOS transistors T3 and T5, and the output signal line The voltage is led out to 6 in the form of voltage amplification by the third MOS transistor T3. Thus, a voltage proportional to the logarithmic value of the incident light amount can be read. Also, at the end of integration of each pixel (after the sixth MOS transistor T6 is turned off), a low level voltage of the clock #D is applied to the drain of the second MOS transistor T2 to initialize the first capacitor C1, The signal of the next frame is stored in the first capacitor C1 during the readout period.

After reading the signals of all the pixels, the fourth MOS transistor T4 is turned on to initialize the gate voltages of the second capacitor C2 and the third MOS transistor T3. Next, the sixth MOS transistor T6 is turned on.
Then, the electric charge accumulated in the first capacitor C1 is transferred to the second capacitor C2, and the integration is continued. Thus, all the pixels have an integration function at the same time and at the same time, and can cope with a moving image.

In the first to ninth embodiments described above, the MOS transistors T1 to T6, which are active elements in the pixel, are all constituted by n-channel MOS transistors. All may be constituted by p-channel type MOS transistors. FIGS. 15 to 23 show tenth to eighteenth embodiments in which the first to ninth embodiments are configured by p-channel MOS transistors. Therefore, the polarity of the connection and the polarity of the applied voltage are reversed in FIGS. For example, FIG.
At 5, the photodiode PD has an anode connected to the DC voltage Vss, a cathode connected to the drain and gate of the first MOS transistor T1, and a gate connected to the gate of the second MOS transistor. The source of the first MOS transistor T1 is connected to the DC voltage VDD.

In this case, the DC voltages Vss and Vdd satisfy Vss>
VDD, which is the reverse of FIG. 3 (first embodiment). The output voltage of the capacitor C is a voltage having a high initial value and drops by integration. When turning on the fourth MOS transistor T4 and the fifth MOS transistor T5, a low voltage is applied to the gate. Also, the third MO
The power supply voltage VDD2 is applied to the source of the S transistor T3. As described above, when the p-channel MOS transistor is used, the voltage relationship and the connection relationship are partially different from those in the case where the n-channel MOS transistor is used, but the configuration is substantially the same. 15 to 23 are only shown in the drawings, and description of the configuration and operation is omitted.

FIG. 13 is a block diagram showing the overall configuration of the solid-state imaging device including the pixels according to the tenth to eighteenth embodiments. FIG. Is shown. Referring to FIG.
The same portions (same role portions) as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. As shown in FIG. 13, the output signal lines 6-1, 6-2,...
The transistor Q2 is connected. MOS transistor Q 1 has a gate connected to DC voltage line 7, a drain connected to output signal line 6-1, and a source connected to DC power supply line 8. On the other hand, the drain of the MOS transistor Q2 is connected to the output signal line 6-1, the source is connected to the final signal line 9, and the gate is connected to the horizontal scanning circuit. Here, the transistor Q1 is connected to the p-channel third MOS transistor T3 in the pixel as shown in FIG.
A common source type voltage amplifier circuit as shown in FIG.

In this case, the MOS transistor Q1 is connected to the third
This is the load resistance of the MOS transistor T3. Therefore, the relationship between the DC voltage VDD 'connected to the source of the transistor Q1 and the DC voltage VSS' connected to the source of the third MOS transistor T3 is VDD '<VSS', and the DC voltage VDD 'is, for example, This is the ground voltage (ground). The drain is connected to the transistor Q3, and the DC voltage is applied to the gate. The p-channel MOS transistor Q2 is controlled by the horizontal scanning circuit 3 and leads the output of the amplifier circuit to the final output line 9. Considering the fifth MOS transistor T5 in the pixel, FIG.
The circuit of (a) is represented as shown in FIG.

[0065]

As described above, according to the present invention, since a large signal voltage can be obtained from the pixel, the signal processing in the subsequent circuit becomes easy. In addition, since integration is performed by a capacitor, a fluctuation component and a noise component of a light source can be removed, and a desired signal can be largely obtained by voltage amplification, so that a high-quality imaging signal with improved S / N can be obtained. Can be. Also, the dynamic range is widened by logarithmically converting the photocurrent. Further, by configuring the active element with a MOS transistor, a peripheral processing circuit (A /
It can be formed on one chip together with a D converter, a digital system processor, a memory, etc., and is useful for realizing, for example, a one-chip camera.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram for explaining an overall configuration of a two-dimensional solid-state imaging device according to an embodiment of the present invention in a case where an active element in a pixel is configured by an n-channel MOS transistor;

FIG. 2 is a partial circuit diagram thereof.

FIG. 3 is a circuit diagram illustrating a configuration of one pixel according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of one pixel according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of one pixel according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of one pixel according to a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of one pixel according to a fifth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of one pixel according to a sixth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a configuration of one pixel according to a seventh embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration of one pixel according to an eighth embodiment of the present invention.

FIG. 11 is a circuit diagram showing a configuration of one pixel according to a ninth embodiment of the present invention.

FIG. 12 is a view showing a structure of a junction capacitance according to the fifth embodiment.

FIG. 13 is a block circuit diagram for explaining the overall configuration of a two-dimensional solid-state imaging device according to the present invention in the case of an embodiment in which active elements in pixels are configured by p-channel MOS transistors;

FIG. 14 is a partial circuit diagram thereof.

FIG. 15 is a circuit diagram showing a configuration of one pixel according to a tenth embodiment of the present invention.

FIG. 16 is a circuit diagram showing a configuration of one pixel according to an eleventh embodiment of the present invention.

FIG. 17 is a circuit diagram showing a configuration of one pixel according to a twelfth embodiment of the present invention.

FIG. 18 is a circuit diagram showing a configuration of one pixel according to a thirteenth embodiment of the present invention.

FIG. 19 is a circuit diagram showing a configuration of one pixel according to a fourteenth embodiment of the present invention.

FIG. 20 is a circuit diagram showing a configuration of one pixel according to a fifteenth embodiment of the present invention.

FIG. 21 is a circuit diagram showing a configuration of one pixel according to a sixteenth embodiment of the present invention.

FIG. 22 is a circuit diagram showing a configuration of one pixel according to a seventeenth embodiment of the present invention.

FIG. 23 is a circuit diagram showing a configuration of one pixel according to an eighteenth embodiment of the present invention.

FIG. 24 is a circuit diagram showing a configuration of one pixel of a conventional example.

[Explanation of symbols]

 G11 to Gmn Pixel 2 Vertical scanning circuit 3 Horizontal scanning circuit 4-1, 4-2 Row selection line 6-1, 6-2 Output signal line PD Photodiode T1 to T6 First to sixth MOS transistors C Capacitor C1, C2 1. Second capacitor Cs junction capacitance

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kenji Takada 2-3-13 Azuchicho, Chuo-ku, Osaka City Inside Osaka International Building Minolta Co., Ltd. (72) Inventor Shigehiro Miyatake 2-3-3 Azuchicho, Chuo-ku, Osaka-shi No. 13 Osaka International Building Minolta Co., Ltd.

Claims (23)

[Claims] In a two-dimensional solid-state imaging device having pixels arranged in a matrix, each pixel has a photoelectric conversion unit, a capacitor for integrating an output signal of the photoelectric conversion unit, and a voltage output from the capacitor. A solid-state imaging device comprising: an amplifier for amplifying; and a lead-out path for leading a voltage-amplified voltage to an output signal line. 2. A two-dimensional solid-state imaging device in which pixels are arranged in a matrix, wherein each pixel comprises the following: a solid-state imaging device: a photoelectric conversion element; and the photoelectric conversion device. A first electrode, a second electrode, and a control electrode; a transistor to which an output voltage of the logarithmic conversion means is applied to the control electrode; A capacitor connected to receive an output current from a second electrode of the transistor; an amplifier for voltage-amplifying an output of the capacitor; and a lead-out path for leading the amplified voltage to an output signal line. 3. The amplifier is connected to an amplifying transistor having a first electrode, a second electrode, and a control electrode to which an output of the capacitor is applied, and an output line leading to a second electrode of the amplifying transistor. And a load resistance.
Or the solid-state imaging device according to claim 2. 4. The solid-state imaging device according to claim 3, wherein a total number of said load resistors is smaller than a total number of pixels. 5. The solid-state imaging device according to claim 3, wherein the lead-out path is connected to a second electrode of the amplifying transistor. 6. The load resistor has a first electrode connected to a second electrode of the amplifying transistor, a second electrode connected to a DC voltage, and a control electrode connected to a DC voltage. The solid-state imaging device according to claim 3, wherein the solid-state imaging device is a transistor for use. 7. An amplifying transistor comprising: an n-channel transistor;
7. An OS transistor, wherein a DC voltage applied to a first electrode of the amplification transistor is lower in potential than a DC voltage connected to a second electrode of the resistance transistor. The solid-state imaging device according to claim 1. 8. The transistor according to claim 1, wherein said amplifying transistor is a p-channel transistor.
7. An OS transistor, wherein a DC voltage applied to a first electrode of the amplification transistor is higher in potential than a DC voltage connected to a second electrode of the resistance transistor. The solid-state imaging device according to claim 1. 9. The method according to claim 1, wherein the derivation path includes a switch for sequentially selecting a predetermined one from all the pixels and deriving an amplified voltage from the selected pixel to an output signal line.
The solid-state imaging device according to claim 8. 10. The solid-state imaging device according to claim 1, further comprising a second capacitor that performs the following integration while deriving the output of said capacitor. 11. A method according to claim 1, wherein a switch is provided in a current input path to said capacitor, and said switch is simultaneously controlled in all pixels to make the integration time of all pixels equal. A solid-state imaging device according to any one of claims 1 to 3. 12. A two-dimensional solid-state imaging device in which pixels are arranged in a matrix, wherein each pixel includes the following: a solid-state imaging device: a photodiode; and one of the photodiodes The first electrode and the gate electrode are connected to the first electrode and the first electrode operates in the sub-threshold region.
A MOS transistor; a second MOS transistor having a gate connected to the gate of the first MOS transistor and a first electrode connected to a DC voltage and operating in a subthreshold region; one end connected to the second electrode of the second MOS transistor and the other end connected to the DC A capacitor connected to a voltage and integrating a signal based on the photocharge generated by the photodiode; a third MOS transistor having a gate connected to one end of the capacitor and a first electrode connected to a DC voltage to operate as an amplifier; A fourth MOS transistor having a first electrode connected to the one end of the capacitor, a second electrode connected to the DC voltage, and turned on when a reset signal is input to the gate to reset the capacitor to an initial state; The first electrode is connected to the second electrode of the transistor. The 5MOS transistor for electrode is connected to the gate electrode to the output signal line connected to the row select line read. 13. A two-dimensional solid-state imaging device in which pixels are arranged in a matrix, wherein each pixel comprises the following: a solid-state imaging device: a photodiode; and one of the photodiodes The first electrode and the gate electrode are connected to the first electrode and the first electrode operates in the sub-threshold region.
A MOS transistor; a second MOS transistor having a gate connected to the gate of the first MOS transistor and operating in a subthreshold region; one end connected to a second electrode of the second MOS transistor and the other end connected to a DC voltage; When a reset voltage is applied to the first electrode of the second
A capacitor reset via a MOS transistor, a third MOS transistor having a gate connected to one end of the capacitor, a first electrode connected to a DC voltage and operating as an amplifier, a first electrode being a second electrode of the third MOS transistor A fifth MOS transistor for reading in which the second electrode is connected to the output signal line and the gate electrode is connected to the row selection line. 14. A two-dimensional solid-state imaging device in which pixels are arranged in a matrix, wherein each pixel comprises the following: a solid-state imaging device: a photodiode; and one of the photodiodes. The first electrode and the gate electrode are connected to the first electrode and the first electrode operates in the sub-threshold region.
A MOS transistor; a second MOS transistor having a gate connected to the gate of the first MOS transistor and a first electrode connected to a DC voltage and operating in a subthreshold region; one end connected to the second electrode of the second MOS transistor and the other end connected to the DC A capacitor connected to a voltage and integrating a signal based on the photocharge generated by the photodiode; a third MOS transistor having a gate connected to one end of the capacitor and a first electrode connected to a DC voltage to operate as an amplifier; A first electrode is connected to one end of the capacitor, a second electrode is connected to a DC voltage, a DC voltage is applied to a gate, and a fourth MOS transistor is always on when a DC voltage is applied to the gate; a first electrode is connected to a second electrode of the third MOS transistor; The electrode is connected to the output signal line and the gate electrode is connected to the row selection line. The 5MOS transistor for the out. 15. A two-dimensional solid-state imaging device having pixels arranged in a matrix, wherein each pixel has a photodiode, a first electrode and a gate electrode connected to one electrode of the photodiode, and a sub-threshold region. Works with the first
A MOS transistor, a gate connected to the gate of the first MOS transistor, a first electrode connected to a DC voltage, a second MOS transistor operating in a subthreshold region, and a first electrode connected to a second electrode of the second MOS transistor. A sixth MOS transistor having a gate to which a switching voltage is applied; a capacitor having one end connected to the second electrode of the sixth MOS transistor and the other end connected to a DC voltage, for integrating a signal based on a photocurrent generated by the photodiode; A third MOS transistor having a gate connected to one end of the capacitor and a first electrode connected to a DC voltage to operate as an amplifier; a first electrode connected to the one end of the capacitor and a second electrode connected to the DC voltage; And when a reset signal is input to the gate A fourth MOS transistor for resetting the capacitor to an initial state, and a read operation in which a first electrode is connected to a second electrode of the third MOS transistor, a second electrode is connected to an output signal line, and a gate electrode is connected to a row selection line. And a third MOS transistor for amplifying and reading out the voltage of the capacitor in a state where the integration of the capacitor is stopped by turning off the sixth MOS transistor. apparatus. 16. A two-dimensional solid-state imaging device having pixels arranged in a matrix, wherein each pixel includes a photodiode, a first electrode and a gate electrode connected to one electrode of the photodiode, and a sub-threshold region. Works with the first
A MOS transistor, a second MOS transistor having a gate connected to the gate of the first MOS transistor and a clock applied to the first electrode and operating in a subthreshold region, and one end connected to the second electrode of the second MOS transistor via the first switch And a capacitor having the other end connected to a DC voltage and integrating a signal based on the photocurrent generated by the photodiode, a gate connected to one end of the capacitor and a first electrode connected to the DC voltage to operate as an amplifier. A third MOS transistor, a second switch having one end connected to the second electrode of the third MOS transistor and the other end connected to the output signal line, and turning on the first switch to output the output of the second MOS transistor to the capacitor. Supply current to integrate the signal and turn off the first switch In the state the second
A switch is turned on to output the signal of the capacitor to the third MOS
The voltage is amplified by the transistor and led out to the output signal line. Thereafter, the first switch is turned on to pass the second MOS transistor and the first switch during the reset voltage period of the clock applied to the first electrode of the second MOS transistor. A solid-state imaging device characterized by performing initialization of a capacitor. 17. In a two-dimensional solid-state imaging device having pixels arranged in a matrix, each pixel includes a photodiode, a first electrode and a gate electrode connected to one electrode of the photodiode, and a sub-threshold region. Works with the first
A MOS transistor, a second MOS transistor having a gate connected to the gate of the first MOS transistor and a clock applied to the first electrode and operating in a subthreshold region, and one end connected to the second electrode of the second MOS transistor via the first switch And a capacitor having the other end connected to a DC voltage and integrating a signal based on the photocurrent generated by the photodiode, a gate connected to one end of the capacitor and a first electrode connected to the DC voltage to operate as an amplifier. A third MOS transistor having one end connected to one end of the capacitor, the other end connected to a DC voltage, and a reset signal input to a gate;
An S transistor, and a second switch having one end connected to the second electrode of the third MOS transistor and the other end connected to the output signal line. The first switch is turned off, and the signal of the capacitor is turned on by the third MOS transistor. When the voltage is amplified and read to the output signal line, the second MOS transistor is reset during the reset voltage period of the clock of the second electrode of the second MOS transistor.
Resetting a pn junction capacitance related to a second electrode of the transistor, starting integration of a signal to the pn junction capacitance during another level of the clock, turning on a first switch after reading of the signal of the capacitor is completed, and A solid-state imaging device, wherein the charge stored in a pn junction capacitance is transferred to the capacitor and integration of the capacitor is continued. 18. A two-dimensional solid-state imaging device having pixels arranged in a matrix, wherein each pixel includes a photodiode, a first electrode and a gate electrode connected to one electrode of the photodiode, and a sub-threshold region. Works with the first
A MOS transistor, a second MOS transistor having a gate connected to the gate of the first MOS transistor, a DC voltage being applied to the first electrode and operating in a sub-threshold region, one end connected to the second electrode of the second MOS transistor, and the other end connected to the DC A first capacitor connected to a voltage for integrating a signal based on a photocurrent generated by the photodiode, a first switch having one end connected to one end of the first capacitor, and one end connected to the other end of the first switch; A second capacitor having the other end connected to a DC voltage, a third MO connected to a gate of the second capacitor and having a first electrode connected to the DC voltage, and operating as an amplifier;
An S transistor, a fourth MOS transistor having a first electrode connected to one end of the second capacitor, a second electrode connected to the DC voltage, and a gate receiving a reset signal, and one end connected to a second electrode of the third MOS transistor A second switch having the other end connected to the output signal line, wherein the first switch is turned off to amplify the voltage of the second capacitor by the third MOS transistor and read the signal to the output signal line. The next integration is started by the capacitor, and after the end of the reading, the fourth MOS transistor is turned off.
After resetting the second capacitor by N, the first switch is turned on to transfer the charge of the first capacitor to the second capacitor and continue integration of the second capacitor. 19. A two-dimensional solid-state imaging device having pixels arranged in a matrix, wherein each pixel includes a photodiode, a first electrode and a gate electrode connected to one electrode of the photodiode, and a sub-threshold region. Works with the first
A MOS transistor; a second MOS transistor having a gate connected to the gate of the first MOS transistor and applied to the first electrode to operate in the subthreshold region with a clock applied to the first electrode; one end connected to the second electrode of the second MOS transistor and the other end connected to a DC voltage A first capacitor that is connected to the first switch and that integrates a signal based on a photocurrent generated by the photodiode; a first switch that has one end connected to one end of the first capacitor; and a first switch that has one end connected to the other end of the first switch. A second capacitor having an end connected to a DC voltage, a third MOS transistor having a gate connected to one end of the second capacitor, and a first electrode connected to the DC voltage to operate as an amplifier, and an end connected to a second MOS transistor A second switch connected to the electrode and having the other end connected to the output signal line. The first capacitor is reset by transferring the voltage integrated by the first switch to the second capacitor by turning on the first switch, and then setting the first switch to O
FF and the voltage based on the charge of the second capacitor is changed to the third MO.
A solid-state imaging device wherein the following integration is performed by a first capacitor when voltage is amplified by an S transistor and read to the output signal line. 20. In a two-dimensional solid-state imaging device in which pixels are arranged in a matrix, each pixel includes a photodiode, a first electrode and a gate electrode connected to one electrode of the photodiode, and a sub-threshold region. Works with the first
A MOS transistor; a second MOS transistor having a gate connected to the gate of the first MOS transistor and applied to the first electrode to operate in the subthreshold region with a clock applied to the first electrode; one end connected to the second electrode of the second MOS transistor and the other end connected to a DC voltage A first capacitor that is connected to the first switch and that integrates a signal based on a photocurrent generated by the photodiode; a first switch that has one end connected to one end of the first capacitor; and a first switch that has one end connected to the other end of the first switch. A second capacitor having an end connected to a DC voltage, a third MOS transistor having a gate connected to one end of the second capacitor and having a first electrode connected to the DC voltage to operate as an amplifier, and a first MOS transistor connected to one end of the second capacitor. A fourth MOS transistor to which an electrode is connected, a second electrode is connected to a DC voltage, and a reset voltage is applied to a gate. And a second switch having one end connected to the second electrode of the third MOS transistor and the other end connected to the output signal line. When the first switch is turned off, the signal of the second capacitor is supplied to the third MOS transistor. During the reset voltage level period of the clock applied to the second electrode of the second MOS transistor when the voltage is amplified and read at
The capacitor is reset, integration of the first capacitor is started during another level period of the clock, and after the reading is completed, the fourth MOS transistor is turned on to reset the second capacitor, and then the first switch is turned on to reset the first capacitor. A solid-state imaging device that transfers charge of a capacitor to a second capacitor and continues integration of the second capacitor. 21. The semiconductor device according to claim 12, further comprising a MOS transistor connected to said pixel via said output signal line, said MOS transistor forming a load resistance of said third MOS transistor on a drain side of said third MOS transistor. The solid-state imaging device according to claim 20. 22. For each column of the pixel matrix, a first electrode connected to the fifth MOS transistor of each pixel included in the column, a second electrode connected to the DC voltage, and a gate connected to the DC voltage. 16. The solid-state imaging device according to claim 12, further comprising a resistance MOS transistor having the following. 23. For each column of a pixel matrix, a first electrode connected to a second switch of each pixel included in the column;
21. The solid-state imaging device according to claim 16, further comprising a resistance MOS transistor having a second electrode connected to a DC voltage and a gate connected to the DC electrode. .