JP2001094878A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device capable of highly accurately picking up an image of a subject in a wide luminance range from a high luminance area up to a low luminance area and having high responsiveness capable of quickly resetting each pixel to an original state even in the low luminance area. SOLUTION: In the case of allowing each pixel to execute image pickup operation, MOS transistors(TRs) T1, T5 are turned on, a MOS TR T6 is turned off and a MOS TR T2 is driven in a subthreshold area. In the case of allowing each pixel to execute reset operation, the MOS TRs T1, T5 are turned off, the MOS TR T6 is turned on and the gate voltage of the MOS TR T2 is fixed. When a signal ϕVPS is turned to a high level and cut off after turning the MOS TR T2 to a conductive state, a signal corresponding to the threshold of the MOS TR T2 is outputted as correction data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device having a plurality of pixels.

[0002]

2. Description of the Related Art Solid-state imaging devices are not only compact, lightweight and low power consumption, are free from image distortion and image sticking, and are resistant to environmental conditions such as vibration and magnetic fields. LSI (Large Scale)
Since it can be manufactured by a process common to or similar to that of an integrated circuit, it has high reliability and is suitable for mass production. For this reason, solid-state imaging devices having pixels arranged in a line are widely used in facsimile and flatbed scanners, and solid-state imaging devices having pixels arranged in a matrix are widely used in video cameras, digital cameras, and the like. By the way, such a solid-state imaging device is roughly classified into a CCD type and a MOS type by means for reading out (extracting) photocharges generated by a photoelectric conversion element. The CCD type has a drawback that the dynamic range is narrow because the photoelectric charge is transferred while being accumulated in the potential well. On the other hand, the MOS type uses the charge accumulated in the pn junction capacitance of the photodiode as M
Reading is performed through an OS transistor.

Here, one of the conventional MOS-type solid-state imaging devices is described.
The configuration per pixel is shown in FIG. 54 and described. In the figure, PD is a photodiode whose cathode is M
The gate of the OS transistor T1 and the MOS transistor T
2 drain. MOS transistor T
1 is connected to the drain of the MOS transistor T3, and the source of the MOS transistor T3 is connected to the output signal line V3.
connected to out. The DC voltage VPD is applied to the drain of the MOS transistor T1 and the source of the MOS transistor T2, and the DC voltage VPS is applied to the anode of the photodiode.

When light enters the photodiode PD,
Photocharge is generated, and the charge is stored in the gate of the MOS transistor T1. Here, the MOS transistor T3
When the MOS transistor T3 is turned on by applying a pulse signal φV to the gate of the MOS transistor T1, a current proportional to the charge of the gate of the MOS transistor T1 is led to the output signal line Vout through the MOS transistors T1 and T3. In this way, an output current proportional to the amount of incident light can be read.
After reading the signal, the MOS transistor T3 is turned off and the signal φ is applied to the gate of the MOS transistor T2.
By applying RS to turn on the MOS transistor T2, the gate voltage of the MOS transistor T1 can be initialized.

[0005]

As described above, the conventional M
The OS-type solid-state imaging device reads out the photocharge generated by the photodiode in each pixel and stored in the gate of the MOS transistor as it is, so the dynamic range is narrow, and therefore, the exposure amount must be precisely controlled. In addition, even if the exposure amount is precisely controlled, dark portions are blackened and bright portions are saturated. On the other hand, the present applicant has disclosed a photosensitive means capable of generating a photocurrent corresponding to the amount of incident light, a MOS transistor for inputting the photocurrent, and a bias means for biasing the MOS transistor to a state in which a subthreshold current can flow. Prepared,
A solid-state imaging device that converts the photocurrent into a logarithm has been proposed (see Japanese Patent Application Laid-Open No. 3-192664). Although such a solid-state imaging device has a wide dynamic range, the threshold characteristics of MOS transistors provided for each pixel may be different, and the sensitivity may be different for each pixel. Therefore, it is necessary to take measures such as holding the output obtained by previously irradiating bright light (uniform light) with uniform luminance as correction data for correcting the output of each pixel when the subject is imaged. .

However, there are problems that it is complicated for the operator to irradiate each pixel using an external light source, and that the exposure cannot be uniformly performed well. Further, when the uniform light irradiation mechanism is provided in the imaging device, there is a problem that the configuration of the imaging device becomes complicated. In order to solve such a problem, the inventors of the present invention have made various studies on a circuit configuration that can eliminate the variation in sensitivity of each pixel without previously irradiating uniform light. The present invention has been made in view of such a point, and a solid-state imaging device capable of accurately obtaining correction data for correcting an output of each pixel at the time of imaging a subject without previously irradiating uniform light. The purpose is to provide. It is another object of the present invention to provide a solid-state imaging device in which the initial state of each pixel is set to be substantially the same, thereby suppressing variation in sensitivity of each pixel.

[0007]

According to a first aspect of the present invention, there is provided a solid-state imaging device, comprising: a photosensitive element for generating an electric signal corresponding to an amount of incident light; and a first electrode connected to the photosensitive element. Photoelectric conversion means for converting the electrical signal into a natural logarithm by operating the first transistor in a sub-threshold region, and an output signal of the photoelectric conversion means. In a solid-state imaging device having a plurality of pixels having a lead-out path leading to a line, a switch is provided between the photosensitive element and a first electrode of the first transistor, and the switch is turned on. The first transistor is operated in a sub-threshold region to perform imaging, and the switch means is turned off and the first transistor is used for imaging. Way current can flow larger and performing a reset Ri.

According to a second aspect of the present invention, there is provided a solid-state imaging device having a photosensitive element for generating an electric signal according to the amount of incident light and a first transistor having a first electrode electrically connected to the photosensitive element. A plurality of photoelectric conversion means for operating the first transistor in a sub-threshold region to convert the electrical signal into a natural logarithm; and an output path for outputting an output signal of the photoelectric conversion means to an output signal line. In the solid-state imaging device having pixels, the photosensitive element and the first
Switch means between the first transistor and the first electrode of the transistor, turning on the switch means, operating the first transistor in a subthreshold region to perform imaging, and turning off the switch means Each pixel is set to the same initial state by performing reset so that a current larger than that at the time of imaging can flow through the first transistor.

A solid-state image pickup device according to the first or second aspect of the present invention provides a photosensitive element when a moving image is picked up by repeatedly performing an image pickup operation and a reset operation like an image pickup device such as a video movie. By turning off the switch means even when light is incident on the photoelectric conversion element, the influence of the electric output from the photosensitive element is cut, and the photoelectric conversion means can be accurately reset. By resetting the first transistor so that a current larger than that at the time of imaging can flow, each pixel is in the same initial state, and sensitivity variation of each pixel can be suppressed.

According to a third aspect of the present invention, there is provided a solid-state imaging device for generating an output signal obtained by natural logarithmically converting an incident light amount, and leading an output signal of the photoelectric conversion unit to an output signal line. In a solid-state imaging device having a plurality of pixels including a lead-out path, the photoelectric conversion unit includes a photoelectric conversion element in which a DC voltage is applied to a first electrode, and one contact connected to a second electrode of the photoelectric conversion element. A first transistor having a first switch connected thereto, a first electrode, a second electrode, and a control electrode, a first transistor having the first electrode connected to the other contact of the switch, a first electrode and a second electrode, A second transistor for applying a DC voltage to the first electrode, the control electrode being connected to a first electrode of the first transistor, and outputting an electric signal from a second electrode; 1
A second switch connected between a first electrode and a control electrode of the transistor, and turning on the first switch and the second switch to cause each pixel to perform an imaging operation; A switch and the second switch are turned off, and a control electrode of the first transistor is connected to a second electrode.
Variations in the sensitivity of each pixel are detected by changing the voltage applied to the electrodes.

In the solid-state imaging device, one of the contacts is connected to the control electrode of the first transistor, and the other is a DC voltage applied to the other contact. A configuration in which a switch is provided to turn off the third switch when each of the pixels performs an imaging operation, and to turn on the third switch when detecting variation in the sensitivity of each of the pixels. You may do it. Further, the third switch may be a transistor. According to a sixth aspect of the present invention, a capacitor having one end connected to the control electrode of the first transistor is provided to detect a variation in sensitivity between each of the pixels when the pixel performs an imaging operation. A solid-state imaging device may be used in which the voltage applied to the other end of the capacitor is different from time to time. Also, the second switch may be a transistor.

According to another aspect of the present invention, there is provided a solid-state imaging device for generating an output signal obtained by natural logarithmically converting an incident light amount, and leading an output signal of the photoelectric conversion unit to an output signal line. In a solid-state imaging device having a plurality of pixels including a lead-out path, the photoelectric conversion unit includes a photoelectric conversion element in which a DC voltage is applied to a first electrode, and one contact connected to a second electrode of the photoelectric conversion element. A first switch, a first electrode, a second electrode, and a control electrode are connected. The first electrode and the control electrode are connected to the other contact of the first switch, and a DC voltage is applied to the second electrode. A first transistor, a first electrode, a second electrode, and a control electrode; and a DC voltage is applied to the first electrode, and the control electrode is connected to the first electrode and the control electrode of the first transistor. Connected to the second electrode A second transistor that outputs an electric signal; and a reset capacitor having one end connected to a control electrode of the first transistor. When each pixel performs an imaging operation, the first switch is turned on. When the voltage applied to the other end of the reset capacitor is set as a first voltage, the first transistor is operated in a sub-threshold region, and when resetting each pixel, the first switch is turned off and the reset is performed. A voltage applied to the other end of the capacitor for use as a second voltage so that a current larger than that at the time of imaging can flow through the first transistor.

In such a solid-state imaging device, when each pixel is reset by setting the second voltage applied to the other end of the reset capacitor of each pixel to a constant voltage value, the second voltage of each pixel is reset. Can be set to almost the same initial state. Therefore, it is possible to suppress a variation in sensitivity that occurs for each pixel.

According to a ninth aspect of the present invention, there is provided a solid-state imaging device which generates an output signal obtained by natural logarithmically converting an incident light amount, and derives an output signal of the photoelectric conversion unit to an output signal line. In a solid-state imaging device having a plurality of pixels including a lead-out path, the photoelectric conversion unit includes a photoelectric conversion element in which a DC voltage is applied to a first electrode, and one contact connected to a second electrode of the photoelectric conversion element. A first transistor having a first switch connected thereto, a first electrode, a second electrode, and a control electrode, wherein the first electrode and the control electrode are connected to the other contact of the first switch; A DC electrode is applied to the first electrode, the control electrode is connected to the first electrode and the control electrode of the first transistor, and an electric signal is output from the second electrode. With the second transistor When each pixel performs an imaging operation, the first switch is turned on and the voltage applied to the second electrode of the first transistor is set as a first voltage, and the first transistor is set in a sub-threshold region. When operating and resetting each pixel, the first switch is turned off, and the voltage applied to the second electrode of the first transistor is set as a second voltage, and the second voltage is applied to the first transistor. It is characterized in that a larger current can flow than before.

In such a solid-state image pickup device, when each pixel is reset by setting the second voltage applied to the second electrode of the second transistor of each pixel to a constant voltage value, when each pixel is reset, The control voltage of the second transistor can be set to almost the same initial state. Therefore,
Variations in sensitivity that occur for each pixel can be suppressed.

According to a tenth aspect of the present invention, there is provided a solid-state imaging device for generating an output signal obtained by natural logarithmically converting an incident light amount, and leading an output signal of the photoelectric conversion unit to an output signal line. In a solid-state imaging device having a plurality of pixels including a lead-out path, the photoelectric conversion unit includes a photoelectric conversion element in which a DC voltage is applied to a second electrode, and one contact point connected to a first electrode of the photoelectric conversion element. A first transistor having a first switch connected thereto, a first electrode, a second electrode, and a control electrode, a second transistor having a second electrode connected to the other contact of the first switch; An electrode and a control electrode, a DC voltage is applied to the first electrode, and the control electrode is connected to the second electrode of the first transistor;
A second transistor for outputting an electric signal from an electrode, turning on the first switch and operating the first transistor in a subthreshold region to cause each pixel to perform an imaging operation; One switch is OF
By changing the voltage to F and changing the voltage applied to the first electrode of the first transistor, a variation in the sensitivity of each pixel is detected.

In such a solid-state imaging device, the photoelectric conversion means may perform logarithmic conversion by applying a voltage to the first transistor control electrode so that the first transistor operates in a subthreshold region. it can. In addition, by applying a voltage to the control electrode so that the first transistor is turned off, electric charges are accumulated in the control electrode of the second transistor, and the photoelectric conversion unit can perform a linear conversion operation. .

According to an eleventh aspect of the present invention, in the solid-state imaging device according to any one of the third to ninth aspects, the first switch is a transistor having a polarity opposite to that of the first transistor. It is characterized by. According to a twelfth aspect of the present invention, in the solid-state imaging device according to any one of the third to tenth aspects, the first switch is a transistor.

A solid-state imaging device according to a thirteenth aspect is the solid-state imaging device according to any one of the first to twelfth aspects,
The pixels are arranged in a matrix.

A solid-state imaging device according to a fourteenth aspect of the present invention is a solid-state imaging device having a plurality of pixels, wherein each pixel includes a photodiode and a first MOS transistor having a first electrode connected to one electrode of the photodiode. And the first
A second MOS transistor having a first electrode connected to the second electrode of the MOS transistor; a third MOS transistor having a gate electrode connected to the first electrode of the second MOS transistor; and a first MOS transistor having a first electrode connected to the first electrode of the second MOS transistor. A fourth MOS transistor having an electrode connected thereto and a second electrode connected to a gate electrode of the second MOS transistor;
A transistor, and a fifth MOS transistor having a first electrode connected to the gate electrode of the second MOS transistor and a DC voltage applied to the second electrode, turning on the first and fourth MOS transistors, , The fifth MOS transistor is turned off, and the second
Operating the MOS transistor in a sub-threshold region equal to or less than a threshold to cause each pixel to perform an imaging operation, turning off the first and fourth MOS transistors, turning on the fifth MOS transistor, and then turning on the second MOS transistor The variation in the sensitivity of each pixel due to the threshold voltage of the second MOS transistor is detected by changing the voltage applied to the second electrode.

According to a fifteenth aspect of the present invention, in the solid-state imaging device having a plurality of pixels, each pixel includes a photodiode and a first MOS transistor having a first electrode connected to one electrode of the photodiode. And the first
A second MOS transistor having a first electrode connected to the second electrode of the MOS transistor; a third MOS transistor having a gate electrode connected to the first electrode of the second MOS transistor; and a first MOS transistor having a first electrode connected to the first electrode of the second MOS transistor. A fourth MOS transistor having an electrode connected thereto and a second electrode connected to a gate electrode of the second MOS transistor;
A first capacitor having one end connected to a gate electrode of the second MOS transistor, turning on the first and fourth MOS transistors, and applying a first voltage to the other end of the first capacitor. Operating the second MOS transistor in a sub-threshold region equal to or less than a threshold to cause each pixel to perform an imaging operation;
The first and fourth MOS transistors are turned off, a second voltage is applied to the other end of the first capacitor, and then a voltage applied to a second electrode of the second MOS transistor is changed. It is characterized in that a variation in sensitivity of each pixel due to a threshold voltage is detected.

A solid-state imaging device according to claim 16, wherein each pixel has a photodiode and a first MOS transistor in which a first electrode is connected to one electrode of the photodiode. And the first
A second MOS transistor having a first electrode and a gate electrode connected to a second electrode of the MOS transistor;
A third MOS transistor having a gate electrode connected to a first electrode and a gate electrode of the OS transistor;
A first capacitor having one end connected to a first electrode and a gate electrode of an OS transistor; and when the pixel performs an imaging operation, the first MOS transistor is turned on and the other end of the first capacitor is turned on. When the first MOS transistor is turned off, the first MOS transistor is turned off, and the other end of the first capacitor is connected to the other end of the first capacitor. It is characterized in that a second voltage is applied so that a larger current can flow through the second MOS transistor than during imaging.

A solid-state imaging device according to claim 17, wherein each pixel has a photodiode and a first MOS transistor having a first electrode connected to one electrode of the photodiode in the solid-state imaging device having a plurality of pixels. And the first
A second MOS transistor having a first electrode and a gate electrode connected to a second electrode of the MOS transistor;
A third MOS transistor having a gate electrode connected to the first electrode and the gate electrode of the OS transistor; and when the pixel performs an imaging operation, the first MOS transistor is turned on and a second MOS transistor of the second MOS transistor is turned on. When the first voltage is applied to the two electrodes to operate the second MOS transistor in a sub-threshold region equal to or less than a threshold value and reset the pixel, the first MOS transistor is used.
While turning off the S transistor, the second MO
A second voltage is applied to the second electrode of the S transistor so that a larger current can flow than before applying the second voltage to the second MOS transistor.

Further, in the pixel, a first electrode is connected to a second electrode of the third MOS transistor, a second electrode is connected to an output signal line, and a gate electrode is connected to a row selection line. A seventh MOS transistor connected to the line may be provided. 20. The solid-state imaging device according to claim 19, wherein a DC voltage is applied to a first electrode of the pixel, a gate electrode is connected to a second electrode of the third MOS transistor, and the third MOS transistor is connected to the pixel. MO that amplifies the output signal output from the second electrode of
An S transistor may be provided.

According to a twentieth aspect of the present invention, in the solid-state imaging device according to the nineteenth aspect, the pixel has a first electrode connected to a second electrode of the sixth MOS transistor, and a second electrode connected to an output. A seventh MOS transistor is connected to the signal line and has a gate electrode connected to the row selection line.

The solid-state imaging device according to claim 21 is the solid-state imaging device according to claim 19 or 20,
The pixel includes a capacitor having one end connected to a second electrode of the third MOS transistor and being reset via the third MOS transistor when a reset voltage is applied to a first electrode of the third MOS transistor. It is characterized by the following.

The solid-state imaging device according to claim 22 is the solid-state imaging device according to claim 19 or 20,
A DC voltage is applied to a first electrode of the third MOS transistor, and the pixel includes an eighth MOS transistor having a first electrode connected to a second electrode of the third MOS transistor and a DC voltage connected to a second electrode. , The eighth
A capacitor connected at one end to the second electrode of the MOS transistor and resetting via the eighth MOS transistor when a reset voltage is applied to the gate electrode of the eighth MOS transistor. .

According to a twenty-third aspect of the present invention, in the solid-state imaging device according to any one of the fourteenth to twenty-second aspects, the first MOS transistor is a depletion type MOS transistor. or,
The solid-state imaging device according to claim 24 is the solid-state imaging device according to any one of claims 14 to 22, wherein the first MOS transistor is a MOS transistor having a polarity opposite to that of the second MOS transistor. And

A solid-state imaging device according to claim 25, wherein in each solid-state imaging device having a plurality of pixels, each pixel has a photodiode and a first MOS transistor in which a second electrode is connected to one electrode of the photodiode. And the first
A second MOS transistor having a second electrode connected to a first electrode of the MOS transistor; and a third MOS transistor having a gate electrode connected to a second electrode of the second MOS transistor, wherein the first MOS transistor is turned on.
In addition, the second MOS transistor is operated in a sub-threshold region equal to or less than a threshold to cause each pixel to perform an imaging operation, and the first MOS transistor is turned off.
F, and by changing the voltage applied to the first electrode of the second MOS transistor,
It is characterized in that a variation in sensitivity of each pixel due to a threshold voltage of a transistor is detected.

According to a twenty-sixth aspect of the present invention, in the solid-state imaging device according to the twenty-sixth aspect, the pixel has a first electrode connected to a second electrode of the third MOS transistor, and a second electrode connected to an output signal line. And a fifth MOS transistor whose gate electrode is connected to a row selection line may be provided.

According to a twenty-seventh aspect of the present invention, in the pixel, the pixel has a first electrode connected to a DC voltage, a gate electrode connected to a second electrode of the third MOS transistor, and The second of the third MOS transistor
A configuration in which a fourth MOS transistor for amplifying the output signal output from the electrode may be provided. In the solid-state imaging device having such a configuration, a first electrode is connected to the second electrode of the fourth MOS transistor, and a second electrode is connected to an output signal line. And a fifth MOS having a gate electrode connected to a row selection line.
A transistor may be provided.

In the solid-state imaging device according to claim 27 or claim 28, as described in claim 29, one end of the pixel is connected to the second electrode of the third MOS transistor, and the other end is connected to a direct current. A capacitor that is connected to a voltage and that is reset via the third MOS transistor when a reset voltage is applied to a first electrode of the third MOS transistor may be provided. With such a configuration, the signal output from the pixel is
Since the signal is once integrated by the capacitor, the fluctuation component of the light source and high-frequency noise are absorbed and removed by the capacitor. Further, by applying a reset voltage to a first electrode of the third MOS transistor, the third MOS transistor
The charge in the capacitor is released via the transistor and reset.

In the solid-state imaging device having such a configuration,
The third MOS transistor may be a MOS transistor having a polarity opposite to that of the first and second MOS transistors.

Also, in the pixel, the first electrode of the third MOS transistor is connected to a DC voltage, and the pixel is connected to the third MOS transistor.
A sixth MOS transistor having a first electrode connected to the second electrode of the MOS transistor and a DC voltage connected to the second electrode; one end connected to the second electrode of the third MOS transistor and the other end connected to the DC voltage; Together with the sixth
And a capacitor that is reset via the sixth MOS transistor when a reset voltage is applied to the gate electrode of the MOS transistor. With such a configuration, the signal output from the pixel becomes a signal once integrated by the capacitor, so that the fluctuation component of the light source and high-frequency noise are absorbed and removed by the capacitor. Further, by applying a reset voltage to the gate electrode of the sixth MOS transistor,
The charge in the capacitor is released through the MOS transistor and reset.

In the solid-state imaging device having such a configuration,
33. The third and sixth MOS transistors as recited in claim 32.
The transistor may be a MOS transistor having a polarity opposite to that of the first and second MOS transistors.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment of Pixel Configuration Each embodiment of the solid-state imaging device of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows a partial configuration of a two-dimensional MOS solid-state imaging device according to an embodiment of the present invention. In the figure, G11 to Gmn are arranged in a matrix (matrix arrangement).
FIG. Reference numeral 2 denotes a vertical scanning circuit, which sequentially scans rows (lines) 4-1, 4-2,..., 4-n. Reference numeral 3 denotes a horizontal scanning circuit, which sequentially reads out the photoelectric conversion signals derived from the pixels to the output signal lines 6-1, 6-2,..., 6-m for each pixel in the horizontal direction. 5 is a power supply line. For each pixel, the lines 4-1 and 4-
, 4-n and output signal lines 6-1, 6-2,.
6-m, not only the power supply line 5 but also other lines (for example, a clock line and a bias supply line) are connected, but these are omitted in FIG.

The output signal lines 6-1, 6-2,.
As shown, one N-channel MOS transistor Q2 is provided for each m. MOS transistor Q2
Is connected to the output signal line 6-1, the source is connected to the final signal line 9, and the gate is connected to the horizontal scanning circuit 3. As described later, an N-channel fourth MOS transistor T4 for switching is also provided in each pixel. Here, the MOS transistor T4 selects a row, and the MOS transistor Q2 selects a column.

<First Embodiment> A first embodiment applied to each pixel of the first example of the pixel configuration shown in FIG. 1 (FIG. 2)
Will be described with reference to the drawings.

In FIG. 2, a pn photodiode PD
Form a photosensitive portion (photoelectric conversion portion). The anode of the photodiode PD is connected to a first MOS transistor T1.
The source of the MOS transistor T1 is connected to the drain of the second MOS transistor,
It is connected to the gate of the OS transistor T3 and the drain of the fifth MOS transistor T5. The source of the MOS transistor T3 is connected to the drain of the fourth MOS transistor T4 for row selection. The source of the MOS transistor T4 is an output signal line 6 (this output signal line 6 is
6-1, 6-2,..., 6-m). Each of the MOS transistors T1 to T6 is an N-channel MOS transistor and has a back gate grounded.

The DC voltage VPD is applied to the cathode of the photodiode PD. On the other hand, M
The signal φVPS is input to the source of the OS transistor T2, and the other end of the capacitor C1 to which the DC voltage VPS is applied is connected to the other end of the MOS transistor T3. The DC voltage V RB is applied to the source of the MOS transistor T6, the signal φVRS is input to its gate, and the drain is connected to the gate of the MOS transistor T2 and the source of the MOS transistor T5. MO
Signal φD is input to the drain of S transistor T3.

The signal φSW is input to the gate of the MOS transistor T5, and the signal φS is input to the gate of the MOS transistor T1. Further, the MOS transistor T
The signal φV is input to the gate of No. 4. In this embodiment, the signal φVPS changes ternarily.
For example, a voltage substantially equal to the DC voltage VPD is set to a high level, for example, the ground is set to a low level, and the MOS transistor T2
Is set to an intermediate level which is an intermediate voltage between the two to operate in the sub-threshold region. At the intermediate level, for example, the voltage is substantially equal to the DC voltage VPS.

(1) Operation for converting incident light to each pixel into an electric signal First, the signal φS and the signal φSW are set to the high level, and the MO
While conducting the S transistors T1 and T5,
Signal φVPS is set to an intermediate level so that S transistor T2 operates in the subthreshold region. At this time,
The low level signal φVRS is applied to the gate of the MOS transistor T6, and the MOS transistor T6
F, which is equivalent to substantially not existing. At this time, when light enters the photodiode PD, a photocurrent is generated, and a voltage having a value obtained by natural logarithmically converting the photocurrent is generated at the gates of the MOS transistors T2 and T3 due to the subthreshold characteristic of the MOS transistor. With this voltage, a current flows through the MOS transistor T3,
An electric charge equivalent to a value obtained by converting the integral value of the photocurrent into a natural logarithm is stored in the capacitor C1. That is, a voltage proportional to the natural logarithmically converted value of the photocurrent is generated at the connection node a between the capacitor C1 and the source of the MOS transistor T3. However, at this time, it is assumed that the MOS transistor T4 is in the OFF state.

Next, a pulse signal φV is applied to the gate of the MOS transistor T4 to turn on the MOS transistor T4.
When N is set, the electric charge accumulated in the capacitor C1 is led out to the output signal line 6 as an output current. The current led out to the output signal line 6 is a value obtained by natural logarithmically converting the integrated value of the photocurrent. In this manner, a signal (output current) proportional to the logarithmic value of the incident light amount can be read.
After reading the signal, the MOS transistor T4 is turned off.
I do. When the output current is naturally logarithmically converted with respect to the amount of incident light, the signal φVRS always remains at the low level.

(2) Method of Detecting Variation in Sensitivity of Pixels Hereinafter, an operation of detecting variation in sensitivity of pixels having a circuit configuration as shown in FIG. 2 will be described with reference to the drawings. FIG.
5 is a timing chart of signals applied to each signal line connected to each element in a pixel when performing a reset operation.
FIG. 4 is a diagram showing the state of the potential of the MOS transistor T2 when each pixel is reset. still,
FIG. 4A is a diagram showing the structure of the MOS transistor T2, and FIGS. 4B and 4C are diagrams showing the potential relationship of the MOS transistor T2. Also, FIG.
The directions of the arrows shown in the potential diagrams of (b) and (c) are as follows.
Indicates the direction in which the potential increases.

The MOS transistor T2 is, for example, a P-type semiconductor substrate (hereinafter, referred to as FIG. 4A).
It is called "P-type substrate". ) 10, N-type diffusion layers 11 and 12 are formed, and an oxide film 13 and a polysilicon layer 14 are sequentially formed on a channel between the N-type diffusion layers 11 and 12. Here, the N-type diffusion layer 11,
12, a drain of the MOS transistor T2,
While forming the source, the oxide film 13 and the polysilicon layer 14 form a gate insulating film and a gate electrode, respectively. Here, in the P-type substrate 10, the N-type diffusion layer 1
The region between 1 and 12 is referred to as a region under the gate.

As described in (1), the pulse signal φV
Is applied to the gate of the MOS transistor T4 to output an output signal. First, the voltage of the signal φS is set to low level to turn off the MOS transistor T1, and the voltage of the signal φSW is set to low level to set the MOS transistor T5. To OFF. Thus, the connection between the MOS transistor T2 and the photodiode PD and the connection between the gate of the MOS transistor T2 and the gate of the MOS transistor T3 are cut off. And the signal φVRS
Of the MOS transistor T6 to the high level
By setting N, the DC voltage V RB is applied to the gate of the MOS transistor T2. At this time, the signal φD
Is a high level (a potential equal to or close to the DC voltage VPD).

Here, by setting the voltage of the signal φVPS to the low level, the potential relationship in the MOS transistor T2 is changed to the potential in the drain, the region under the gate, and the source of the MOS transistor T2 as shown in FIG. , The area under the gate, and the source in this order. Therefore, the negative charge E flows from the source of the MOS transistor T2 into the MOS transistor T2. At this time, since the path to the photodiode PD is blocked, no positive charge flows toward the drain of the MOS transistor T2. Therefore, negative charges are accumulated between the drain and the source of the MOS transistor T2.

Then, by setting the voltage of the signal φVPS to a high level, that is, to a potential equal to or close to the DC voltage VPD, as shown in FIG.
The potential of the source of the transistor T2 is made higher than the potential of the region under the gate. Therefore, negative charges accumulated between the drain and source of the MOS transistor T2 flow out to the signal line φVPS. However, MOS
Since the potential of the drain of the transistor T2 is higher than the potential of the region under the gate, a part E 'of the negative charge accumulated in the drain of the MOS transistor T2 remains at the drain of the MOS transistor T2. This MOS
Negative charges E ′ accumulated in the drain of the transistor T2
Is determined by the threshold voltage of the MOS transistor T2, and becomes a value proportional to this threshold voltage.

At this time, the drain voltage of the MOS transistor T2 becomes a voltage corresponding to the negative charge E 'accumulated in the drain, and the drain voltage of the MOS transistor T2 appears at the gate of the MOS transistor T3. The voltage appearing at the gate of the MOS transistor T3 is M
Since it is proportional to the negative charge E ′ accumulated in the drain of the OS transistor T2, it is understood that it is proportional to the threshold voltage of the MOS transistor T2. MOS transistor T2
When T3 is in such a state, the signal φD is set to the low level, the potential of the capacitor C1 and the connection node a is reset, and then the signal φD is returned to the high level again.

Then, due to the gate voltage of the MOS transistor T3, a current flows through the MOS transistor T3,
Electric charges are accumulated in the reset capacitor C1, and the potential of the connection node a rises. Next, the signal φV is set to the high level to turn on the MOS transistor T4, whereby the electric charge accumulated in the capacitor C1 is led out to the output signal line 6 as an output current. In this way, for each pixel, a current proportional to the threshold voltage of the MOS transistor T2 is led out to the output signal line 6, and can be detected as correction data for correcting the output from each pixel.

More specifically, the current proportional to the threshold voltage is serially output from the signal line 9 in FIG. 1 for each pixel, and is stored in a subsequent circuit as correction data for each pixel in a memory. Then, if the output current at the time of actual imaging is corrected for each pixel using the stored correction data, it is possible to remove components due to pixel variations from the output signal. A specific example of this correction method is shown in FIG. 53 described later. This correction method can also be realized by providing a memory such as a line memory in a pixel.

After detecting the correction data and turning off the MOS transistor T4 as described above, the signal φVPS is returned to an intermediate level to reset the MOS transistor T2, and the signal φVRS is set to low level to turn on the MOS transistor T6. Turn off. Then, the signal φS and the signal φSW are set to the high level, and the MOS transistor T
1, after turning on T5, the signal φD is changed to low level to discharge the electric charge accumulated in the capacitor C1 to the signal line of the signal φD through the MOS transistor T3, thereby initializing the potential of the capacitor C1 and the connection node a. Is done. In this way, a state where the next imaging can be performed is set.

<Second Embodiment> A second embodiment will be described with reference to the drawings. FIG. 5 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 5, a MOS transistor T
1 to T5 and the capacitor C1 have the same configuration as the pixel of the first embodiment (FIG. 2).
The circuit configuration uses a capacitor C2 instead of the MOS transistor T6. That is, one end of the capacitor C2 is connected to a connection node between the gate of the MOS transistor T2 and the source of the MOS transistor T5, and the signal φVRS is applied to the other end. The signal φVRS
Is a binary voltage signal, the ground level is set to a low level, and the voltage for applying a voltage higher than the low level to the gate is set to a high level.

(1) Operation for converting incident light to each pixel into an electric signal In a pixel having a circuit configuration as shown in FIG. 5, the MOS transistor T2 operates in a sub-threshold region.
The signal φVRS applied to the capacitor C2 is set to low level. Also, the signal φS and the signal φSW are set to high level,
The MOS transistors T1 and T5 are turned on. As described above, by setting the signal φVRS to the low level, the capacitor C2 is connected to the gates of the MOS transistors T2 and T3.
It functions similarly to a capacitor formed of an insulating oxide film in the back gate. By operating the MOS transistor T2 in the sub-threshold region in this manner, a voltage obtained by logarithmically converting the photocurrent flowing from the photodiode PD appears at the connection node a. Then, by turning on the MOS transistor T4, the logarithmically converted output signal is output to the output signal line 6.

(2) Method of Detecting Variation in Sensitivity of Pixels The operation for detecting variation in sensitivity of each pixel is shown in the timing chart of FIG. 3 as in the first embodiment. This is performed while the reset operation is performed. The operation at this time will be described below with reference to the timing chart of FIG. 3 and the potential transition diagram of FIG. First, after the pulse signal φV is applied, the signal φS and the signal φSW are set to low level to set the MOS transistor T
By turning off T1 and T5, a reset operation starts. Then, the potential of the region under the gate of the MOS transistor T2 is raised by raising the signal φVRS to a high level, and further, the potential of the MOS transistor T2 is lowered by lowering the voltage of the signal φVPS to a low level in FIG. In this state, negative charges are caused to flow from the source into the MOS transistor T2.

After the negative charge E flowing into the MOS transistor T2 is accumulated as shown in FIG.
VPS is set to a high level whose value is substantially equal to the DC voltage VPD. At this time, since the potential of the source of the MOS transistor T2 becomes higher than the potential of the region under the gate, a part of the accumulated negative charges E flows out of the drain. Therefore, as shown in FIG. 4C, a state where the negative charges E ′ are accumulated in the drain of the MOS transistor T2 and the gate of the MOS transistor T2. Since the negative charge E 'is thus stored, the gate voltage of the MOS transistor T2 is determined by the negative charge E' determined by the threshold voltage of the MOS transistor T1.

While maintaining this state, first, the signal φD
Is set to low level, and the capacitor C1 is reset once. Then, the signal φD is returned to the original high level, and
The current amplified by the gate voltage of the S transistor T3 charges the capacitor C1. By charging the capacitor C1 in this manner, the voltage appearing at the connection node a is supplied to the pulse signal φV, so that M
The signal is output to the output signal line 6 via the OS transistor T4.

Furthermore, the current proportional to the threshold voltage is serially output from the signal line 9 in FIG. 1 for each pixel, and is stored in a memory in a subsequent circuit as correction data for each pixel. Then, if the output current at the time of actual imaging is corrected for each pixel using the stored correction data, it is possible to remove components due to pixel variations from the output signal. A specific example of this correction method is shown in FIG. 53 described later. This correction method can also be realized by providing a memory such as a line memory in a pixel.

As described above, after outputting a signal having a value proportional to the threshold voltage of the MOS transistor T2 which causes a variation in sensitivity of each pixel, the signal φVPS is set to an intermediate level to reset the MOS transistor T2. Thereafter, the signal φVRS is set to low level. And the signal φS
After the signal φSW is set to the high level to turn on the MOS transistors T1 and T5, the signal φD is set to the low level and then to the high level, whereby the capacitor C1 is set.
Reset.

<Third Embodiment> A third embodiment will be described with reference to the drawings. FIG. 6 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 6, the circuit configuration is such that the MOS transistor T5 is deleted from the pixel of the second embodiment (FIG. 5). That is, the MOS transistors T2,
The gate of T3 is connected, and the MOS transistor T2
Is applied with a DC voltage VPS.

(1) Operation for converting incident light to each pixel into an electric signal The imaging operation of the pixel having such a configuration is the same as that of the second embodiment (FIG. 5). That is, the signal φS
To a high level to make the MOS transistor T1 conductive and the signal φVRS to a low level, thereby operating the MOS transistor T2 in the sub-threshold region. By operating the MOS transistor T2 in the sub-threshold region in this manner, a voltage obtained by logarithmically converting the photocurrent flowing from the photodiode PD appears at the connection node a. Then, by turning on the MOS transistor T4, the logarithmically converted output signal is output to the output signal line 6.

(2) Reset Operation of Each Pixel The reset operation of the pixel having the circuit configuration shown in FIG. 6 will be described below with reference to the drawings. FIG. 7 is a timing chart of signals applied to each signal line connected to each element in a pixel when performing a reset operation. Also, FIG.
FIG. 9 is a diagram illustrating a potential state of a MOS transistor T2 when resetting each pixel. In addition, FIG.
In (d), the direction of the arrow indicates that the potential is high.

As described in (1), by applying the pulse signal φV to the gate of the MOS transistor T4, each pixel having a circuit configuration as shown in FIG. Signal) is output to the output signal line 6. When the output signal is output and the pulse signal φV goes low, the reset operation starts.
This reset operation will be described with reference to FIGS.

First, when the pulse signal φV is applied to the gate of the MOS transistor T4 and an output signal is output, the signal φS is set to a low level to set the MOS transistor T4.
Turn 1 off. At this time, the MOS transistor T2
Charge flows from the source side of the MOS transistor T2, and the gate and drain of the MOS transistor T2 and the MOS transistor T3
And the positive charge stored in the capacitor C2 is recombined. Therefore, as shown in FIG. 8A, the potential of the region under the drain and the gate of the MOS transistor T2 decreases to some extent.

As described above, the potential of the region under the drain and the gate of the MOS transistor T2 is about to be reset to the original state, but when the potential reaches a certain value, the speed of resetting is reduced. In particular, this tendency becomes remarkable when a bright subject suddenly becomes dark. Therefore, next, the voltage φVRS applied to the capacitor C2
And the gate voltage of the MOS transistor T2 is increased. As described above, by increasing the gate voltage of the MOS transistor T2, the MOS transistor T2
8B changes as shown in FIG. 8B, and the potentials of the region under the gate and the drain increase. Therefore,
The amount of negative charges flowing from the source of the MOS transistor T2 increases, and the positive charges stored in the gate and drain of the MOS transistor T2, the gate of the MOS transistor T3, and the capacitor C2 are quickly recombined.

Therefore, as shown in FIG. 8C, the potential of the region under the drain and the gate of the MOS transistor T2 is lower than that in the state of FIG. 8B. When the potential of the MOS transistor T2 changes as shown in FIG. 8C, the voltage φVRS applied to the capacitor C2 is set to a low level, and the gate voltage of the MOS transistor T2 is reduced. Accordingly, the potential of the region under the drain and the gate of the MOS transistor T2 is reset to the original state as shown in FIG. Thus, MOS
After resetting the potential state of the transistor T2 to the original state, the voltage of the signal φD is changed to low level, the capacitor C1 is discharged, and the potential of the connection node a is reset to the original state. Then, the voltage of the signal φD is returned to the high level.

Thereafter, the pulse signal φV is applied to the MOS transistor T4, the output current at the time of resetting is led out to the output signal line 6, and detected as correction data for correcting the output from each pixel. it can. And
Again, the voltage of the signal φD is changed to low level,
After resetting 1 to its original state, the voltage of the signal φD is returned to the high level. After that, the signal φS is set to a high level,
The MOS transistor T1 is turned on so that the imaging operation can be performed. Also, as in the first embodiment, the output signal read at the time of this reset is serially output for each pixel from the signal line 9 in FIG. 1 and stored in a subsequent circuit as correction data for each pixel in a memory. . Then, if the output current at the time of actual imaging is corrected for each pixel using the stored correction data, it is possible to remove components due to pixel variations from the output signal. A specific example of this correction method is shown in FIG. 53 described later. This correction method can also be realized by providing a memory such as a line memory in a pixel.

As described above, in the present embodiment, by setting the signal φVRS given to the capacitor C2 connected to the gate of the MOS transistor T2 to a high level, the MO
The gate voltage of the S transistor T2 can be quickly initialized, and the responsiveness of the solid-state imaging device can be improved. Therefore, even when a dark subject is imaged, or when a bright subject suddenly becomes dark, the occurrence of an afterimage is prevented and good imaging is possible. Further, by applying the signal φVRS to each pixel in common, the gate voltage of the MOS transistor T2 provided for each pixel is initialized to a substantially constant value,
In the initial state, the variation in sensitivity of each pixel is canceled.

<Fourth Embodiment> A fourth embodiment will be described with reference to the drawings. FIG. 9 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 9, the circuit configuration is such that the capacitor C2 is removed from the pixel of the third embodiment (FIG. 6). The signal φVPS is input to the source of the MOS transistor T2. The signal .phi.VPS is a binary voltage signal. The voltage for operating the MOS transistor T2 in the sub-threshold region at a voltage substantially equal to the DC voltage VPS is set to a high level.
A voltage that allows a larger current to flow than when a high-level voltage is applied to the S transistor T2 is set to a low level.

(1) Operation for converting incident light to each pixel into an electric signal The imaging operation of the pixel having such a configuration is the same as that of the third embodiment (FIG. 6). That is, the signal φS
To a high level to make the MOS transistor T1 conductive, and the signal φVPS to a high level to operate the MOS transistor T2 in the sub-threshold region. By operating the MOS transistor T2 in the sub-threshold region in this manner, a voltage obtained by logarithmically converting the photocurrent flowing from the photodiode PD appears at the connection node a. Then, by turning on the MOS transistor T4, the logarithmically converted output signal is output to the output signal line 6.

(2) Reset Operation of Each Pixel Hereinafter, a reset operation of a pixel having a circuit configuration as shown in FIG. 9 will be described with reference to the drawings. FIG. 10 is a timing chart of signals applied to each signal line connected to each element in a pixel when performing a reset operation. FIG.
Is a MOS transistor T for resetting each pixel.
FIG. 4 is a diagram showing a state of a potential of No. 2; Note that FIG.
In (a) to (d), the direction of the arrow indicates that the potential is high.

As described in (1), by applying the pulse signal φV to the gate of the MOS transistor T4, each pixel having the circuit configuration as shown in FIG. Signal) is output to the output signal line 6. When the output signal is output and the pulse signal φV goes low, the reset operation starts.
This reset operation will be described with reference to FIGS.

First, the pulse signal φV is applied to the transistor T4
And the output signal is output, the signal φS is set to low level to turn on the MOS transistor T1.
Change to F. At this time, negative charges flow from the source side of the MOS transistor T2, and the positive charges stored in the gate and drain of the MOS transistor T2 and the gate of the MOS transistor T3 are recombined. Therefore,
As shown in FIG.
The potential of the region under the drain and the gate of the MOS transistor T2 decreases.

As described above, the potential of the region under the drain and the gate of the MOS transistor T2 is about to be reset to the original state, but when the potential reaches a certain value, the resetting speed becomes slow. In particular, this tendency becomes remarkable when a bright subject suddenly becomes dark. Therefore, next, the signal φVPS applied to the source of the MOS transistor T2 is set to the low level. Thus, M
By lowering the source voltage of the OS transistor T2, the potential of the MOS transistor T2 increases as shown in FIG.
(B), the amount of the negative charge flowing from the source of the MOS transistor T2 increases, and the positive charge stored in the gate and drain of the MOS transistor T2 and the gate of the MOS transistor T3 quickly changes. Recombined.

Therefore, as shown in FIG. 11C, the potential of the region under the drain and the gate of the MOS transistor T2 is lower than that in the state of FIG. 11B. FIG.
When the potential of the MOS transistor T2 changes as in (c), the signal φVPS applied to the source of the MOS transistor T2 is set to a high level. Therefore, the potential state of the MOS transistor T2 is reset to the original state as shown in FIG. in this way,
After resetting the potential state of the MOS transistor T2 to the original state, the voltage of the signal φD is changed to low level, the capacitor C1 is discharged, and the potential of the connection node a is reset to the original state. Then, the voltage of the signal φD is returned to the high level.

Thereafter, the pulse signal φV is applied to the MOS transistor T4, the output current at the time of resetting is led out to the output signal line 6, and detected as correction data for correcting the output from each pixel. it can. And
Again, the voltage of the signal φD is changed to low level,
After resetting 1 to its original state, the voltage of the signal φD is returned to the high level. After that, the signal φS is set to a high level,
The MOS transistor T1 is turned on so that the imaging operation can be performed. Also, as in the first embodiment, the output signal read at the time of this reset is serially output for each pixel from the signal line 9 in FIG. 1 and stored in a subsequent circuit as correction data for each pixel in a memory. . Then, if the output current at the time of actual imaging is corrected for each pixel using the stored correction data, it is possible to remove components due to pixel variations from the output signal. A specific example of this correction method is shown in FIG. 53 described later. This correction method can also be realized by providing a memory such as a line memory in a pixel.

As described above, in the present embodiment, by setting the signal φVPS applied to the source of the MOS transistor T2 to low level, the gate voltage of the MOS transistor T2 can be quickly initialized, and the response of the solid-state imaging device can be improved. Performance can be improved. Therefore, even when a dark subject is imaged, or when a bright subject suddenly becomes dark, the occurrence of an afterimage is prevented and good imaging is possible. or,
By applying the signal φVPS to each pixel in common, the gate voltage of the MOS transistor T2 provided in each pixel is initialized to a substantially constant value, and the sensitivity variation of each pixel is canceled in the initial state.

In the first to fourth embodiments, the signal reading from each pixel may be performed using a charge-coupled device (CCD). In this case, the charge can be read out to the CCD by providing a potential barrier having a variable potential level corresponding to the MOS transistor T4 in FIGS. 2, 5, 6, and 9.

<Second Example of Pixel Configuration> FIG. 12 schematically shows a partial configuration of a two-dimensional MOS solid-state imaging device according to another embodiment of the present invention. In the figure, G11 to G
mn indicates pixels arranged in a matrix (matrix arrangement). Reference numeral 2 denotes a vertical scanning circuit, which is a row (line) 4-1;
,..., 4-n are sequentially scanned. Reference numeral 3 denotes a horizontal scanning circuit which outputs output signal lines 6-1 and 6-2,
..., the photoelectric conversion signals derived in 6-m are sequentially read out in the horizontal direction for each pixel. 5 is a power supply line. .., 4-n, output signal lines 6-1, 6-2..., 6-m, power supply line 5, and other lines. (For example, a clock line and a bias supply line) are also connected, but these are omitted in FIG.

Output signal lines 6-1, 6-2,..., 6
As shown in the figure, a set of N-channel MOS transistors Q1 and Q2 is provided for each m. MOS transistor Q1 has a gate connected to DC voltage line 7, a drain connected to output signal line 6-1, and a source connected to DC voltage VPS '.
Is connected to the line 8. On the other hand, the drain of the MOS transistor Q2 is connected to the output signal line 6-1, the source is connected to the final signal line 9, and the gate is connected to the horizontal scanning circuit 3.

As described later, the pixels G11 to Gmn have
An N-channel MOS transistor Ta for outputting a signal based on photocharges generated in those pixels is provided. FIG. 13A shows a connection relationship between the MOS transistor Ta and the MOS transistor Q1. This M
The OS transistor Ta includes the fifth, sixth, eleventh, and twelfth
In the embodiment, the seventh MOS transistor T7 has the seventh MOS transistor T7.
In the tenth to thirteenth embodiments, this corresponds to the third MOS transistor T3. Here, the MOS transistor Q1
The relationship between the DC voltage VPS 'connected to the source of the MOS transistor Ta and the DC voltage VPD' connected to the drain of the MOS transistor Ta is VPD '>VPS', and the DC voltage VPS 'is, for example, a ground voltage (ground). . This circuit configuration is based on the upper M
A signal is input to the gate of the OS transistor Ta, and a DC voltage DC is constantly applied to the gate of the lower MOS transistor Q1. Therefore, the lower MOS transistor Q
Reference numeral 1 is equivalent to a resistor or a constant current source, and the circuit in FIG. 13A is a source follower type amplifier circuit. In this case, what is amplified and output from the MOS transistor Ta may be a current.

The MOS transistor Q2 is connected to the horizontal scanning circuit 3
And is operated as a switch element. still,
As described later, an N-channel fourth MOS transistor T4 for switching is also provided in the pixel of each of the embodiments shown in FIG. 14 and thereafter. When this MOS transistor T4 is also included, the circuit of FIG.
become that way. That is, the MOS transistor T4 is
It is inserted between the transistor Q1 and the MOS transistor Ta. Here, the MOS transistor T4 selects a row, and the MOS transistor Q2 selects a column. The configurations shown in FIGS. 12 and 13 are common to the fifth to thirteenth embodiments described below.

With the configuration shown in FIG. 13, a large signal can be output. Therefore, when the pixel converts the photocurrent generated from the photosensitive element in a natural logarithmic manner to expand the dynamic range, the output signal is small as it is, but is amplified to a sufficiently large signal by the present amplifier circuit. Therefore, processing in a subsequent signal processing circuit (not shown) is facilitated. Also, without providing the MOS transistor Q1 constituting the load resistance portion of the amplifier circuit in the pixel,
By providing the output signal lines 6-1, 6-2,..., 6 -m connected to a plurality of pixels arranged in the column direction, the number of load resistances or constant current sources can be reduced, and The area occupied by the amplifier circuit on the chip can be reduced.

<Fifth Embodiment> A fifth embodiment applied to each pixel of the second example of the pixel configuration shown in FIG. 12 will be described with reference to the drawings. FIG. 14 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 14, in the present embodiment, in the pixel shown in FIG. 2, a seventh MOS transistor T7 having a gate connected to the connection node a and performing current amplification according to the voltage of the connection node a, A fourth MOS transistor T4 for row selection in which the drain is connected to the source of the transistor T7, and an eighth M transistor whose drain is connected to the connection node a and initializes the potentials of the capacitor C1 and the connection node a.
The configuration is such that an OS transistor T8 is added. MO
The source of the S transistor T4 is connected to an output signal line 6 (the output signal line 6 corresponds to 6-1 to 6-m in FIG. 12). The MOS transistors T7 and T8 are also N-channel MOS transistors and have a back gate grounded, similarly to the MOS transistors T1 to T6.

Further, DC voltage VPD is applied to the drain of MOS transistor T7, and signal φV is input to the gate of MOS transistor T4. The DC voltage V RB2 is applied to the source of the MOS transistor T8, and the signal φVRS2 is input to the gate of the MOS transistor T8. Further, the DC voltage V is applied to the drain of the MOS transistor T3.
PD is applied. Note that, in the present embodiment, the MOS transistors T1 to T6 and the capacitor C1 perform the same operation as in the first embodiment (FIG. 2), and can perform the operation of detecting the variation in sensitivity of each pixel and the operation of imaging. The operation will be described below.

(1) Operation for converting incident light to each pixel into an electric signal First, the signal φS and the signal φSW are set to the high level, and the MO
When the S transistors T1 and T5 are turned on, the signal φ
VPS is set to an intermediate level, and MOS transistors T2, T3
Will be described when the is biased to operate in the sub-threshold region. At this time, M
Since the low-level signal φVRS is applied to the gate of the OS transistor T6 as in the first embodiment,
The S transistor T6 is turned off, which is equivalent to substantially not being present.

When light enters the photodiode PD, a photocurrent is generated, and a voltage having a value obtained by natural logarithmically converting the photocurrent is generated at the gates of the MOS transistors T2 and T3 due to the subthreshold characteristic of the MOS transistor. Due to this voltage, a current flows through the MOS transistor T3, and a charge equivalent to a value obtained by natural logarithmically converting the integrated value of the photocurrent is accumulated in the capacitor C1. That is,
At the connection node a between the capacitor C1 and the source of the MOS transistor T3, a voltage proportional to the natural logarithmically converted value of the photocurrent is generated. However,
At this time, the MOS transistors T4 and T8 are off.

Next, a pulse signal φV is applied to the gate of the MOS transistor T4 to turn on the MOS transistor T4.
When N is set, a current proportional to the voltage applied to the gate of the MOS transistor T7 is led out to the output signal line 6 through the MOS transistors T4 and T7. Since the voltage applied to the gate of the MOS transistor T4 is a voltage applied to the connection node a, the current led out to the output signal line 6 is a value obtained by natural logarithmically converting the integrated value of the photocurrent. In this manner, a signal (output current) proportional to the logarithmic value of the incident light amount can be read.

(2) Method of Detecting Variation in Sensitivity of Pixels Hereinafter, an operation of detecting variation in sensitivity of pixels having a circuit configuration as shown in FIG. 14 will be described with reference to the drawings. FIG.
5 is a timing chart of signals applied to each signal line connected to each element in a pixel when performing a reset operation.

As described in (1), the pulse signal φV
Is applied to the gate of the MOS transistor T4 to output an output signal. First, the voltage of the signal φS is set to low level to turn off the MOS transistor T1, and the voltage of the signal φSW is set to low level to set the MOS transistor T5. To OFF. Thus, the connection between the MOS transistor T2 and the photodiode PD and the connection between the gate of the MOS transistor T2 and the gate of the MOS transistor T3 are cut off. And the signal φVRS
Of the MOS transistor T6 to the high level
By setting N, the DC voltage V RB is applied to the gate of the MOS transistor T2. Here, by setting the voltage of the signal φVPS to a low level, negative charges flow from the source of the MOS transistor T2 into the MOS transistor T2, and negative charges are accumulated between the drain and the source of the MOS transistor T2.

Next, by setting the voltage of the signal φVPS to a high level, that is, to a potential equal to or close to the DC voltage VPD, the drain voltage of the MOS transistor T2 is reduced.
A part of the negative charges accumulated between the sources is transferred to the signal line φVPS
Leaked to However, since the potential of the drain of the MOS transistor T2 is higher than the potential of the region under the gate, a part of the negative charge stored in the drain of the MOS transistor T2 is reduced.
Remains in the drain. The negative charge stored in the drain of the MOS transistor T2 is
And is a value proportional to this threshold voltage.

At this time, the drain voltage of the MOS transistor T2 becomes a voltage corresponding to the negative charge stored in the drain, and the drain voltage of the MOS transistor T2 appears at the gate of the MOS transistor T3. This M
The voltage appearing at the gate of the OS transistor T3 is MOS
Since it is proportional to the negative charge accumulated in the drain of the transistor T2, it can be seen that it is proportional to the threshold voltage of the MOS transistor T2. When the MOS transistors T2 and T3 are in such a state, the signal φVRS2 is set to the high level, the potential of the capacitor C1 and the connection node a is reset, and then the signal φVRS2 is returned to the low level again.

Then, due to the gate voltage of the MOS transistor T3, a current flows through the MOS transistor T3,
Electric charges are accumulated in the reset capacitor C1, and the potential of the connection node a rises. Next, by setting the signal φV to high level and turning on the MOS transistor T4, the voltage of the connection node a is current-amplified by the MOS transistor T7 and is led out to the output signal line 6. In this way, for each pixel, a current proportional to the threshold voltage of the MOS transistor T2 is led out to the output signal line 6, and can be detected as correction data for correcting the output from each pixel.

After detecting the correction data and turning off the MOS transistor T4 as described above, the signal φVPS is set to the intermediate level to reset the MOS transistor T2, and the signal φVRS is returned to the low level to turn on the MOS transistor T6. Turn off. Then, the signal φS and the signal φSW are set to the high level, and the MOS transistor T
After turning on T1 and T5, the signal φVRS2 is set to the high level to discharge the electric charge accumulated in the capacitor C1 through the MOS transistor T8.
1 and the potential of the connection node a are initialized. In this way, the state where the next imaging can be performed is set.

<Sixth Embodiment> A sixth embodiment will be described with reference to the drawings. FIG. 16 is a circuit diagram illustrating a configuration of a pixel provided in a solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 14 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 16, in the present embodiment, M
By applying the signal φD to the drain of the OS transistor T3, the potentials of the capacitor C1 and the connection node a are initialized, whereby the MOS transistor T3
8 is deleted. Other configurations are the same as those of the fifth embodiment (FIG. 14). During the high-level period of the signal φD, integration is performed by the capacitor C1 in the same manner as in the first embodiment (FIG. 2). During the low-level period, the charge of the capacitor C1 is discharged through the MOS transistor T3. The voltage and the gate of the MOS transistor T7 substantially become the low level voltage of the signal φD (reset). In the present embodiment, the configuration is simplified because the MOS transistor T8 can be omitted.

In this embodiment, when the imaging operation is performed, as in the fifth embodiment, the MOS transistors T1 and T5 are turned on, and the signal φVRS is set to low level to turn off the MOS transistor T6. , The MOS transistor T2 operates in the sub-threshold state. Further, the signal φD is set to the high level, and the electric charge equivalent to the value obtained by natural logarithmically converting the integrated value of the photocurrent is stored in the capacitor C1. Then, the MOS transistor T4 is turned on at a predetermined timing, and M
A current proportional to the voltage applied to the gate of the OS transistor T7 is led out to the output signal line 6 through the MOS transistors T4 and T7.

When resetting each pixel, the signals are controlled at the timing shown in FIG. 3 as in the first embodiment.
That is, first, similarly to the first embodiment, the pulse signal φV
Is given, the signal φS and the signal φSW are set to low level to turn off the MOS transistors T1 and T5,
The reset operation starts. Next, the signal φVRS is set to the high level, and the DC voltage V is applied to the gate of the MOS transistor T2.
Apply RB. Then, after the signal φVPS is once set to the low level, the signal φVPS is set to the high level, and negative charges are accumulated in the drain of the MOS transistor T2. This negative charge is determined by the threshold voltage of the MOS transistor T2.

At this time, the signal φD is once set to the low level to reset the capacitor C1 and the connection node a.
The MOS transistor T2 is connected to the capacitor C1.
A current proportional to the threshold voltage flows through the MOS transistor T3, and the voltage appearing at the connection node a becomes a voltage proportional to the threshold voltage. A pulse signal φV is applied to the gate of MOS transistor T4, and an output signal obtained by amplifying the voltage appearing at connection node a by MOS transistor T7 is output. Thus, for each pixel, its MOS
A current proportional to the threshold voltage of the transistor T2 is led out to the output signal line 6, and can be detected as correction data for correcting the output from each pixel.

After the correction data is detected and the MOS transistor T4 is turned off, the signal φVPS is set to an intermediate level to reset the MOS transistor T2.
When the signal φVRS is set to low level, the MOS transistor T6
To OFF. Then, the signal φS and the signal φSW are set to the high level to turn on the MOS transistors T1 and T5.
After that, the signal φD is set to low level to discharge the electric charge accumulated in the capacitor C1 through the MOS transistor T3, whereby the capacitor C1 and the connection node a
Is initialized.

<Seventh Embodiment> A seventh embodiment will be described with reference to the drawings. FIG. 17 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 16 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 17, in this embodiment, M
The DC voltage VPD is applied to the drain of the OS transistor T3, and the capacitor C1 and the MOS transistor T7 are omitted. That is, the drain of the MOS transistor T4 is connected to the source of the MOS transistor T3. Other configurations are the same as those of the sixth embodiment (FIG. 16).

When the imaging operation is performed in the circuit having such a configuration, as in the sixth embodiment, the MOS transistors T1 and T5 are turned on, and the signal φVRS is set to low level to turn off the MOS transistor T6. Thus, the MOS transistor T2 operates in the sub-threshold state. By operating the MOS transistor T2 in this manner, a drain current having a value that is proportional to the logarithm of the photocurrent in a natural logarithmic manner flows through the MOS transistor T3.

When a pulse signal φV is applied to the gate of the MOS transistor T4 to turn on the MOS transistor T4, the drain current having a value proportional to the logarithm of the photocurrent in natural logarithm is obtained.
It is led to the output signal line 6 through the S transistor T4. At this time, the drain voltage of the MOS transistor Q1 determined by the resistance at the time of conduction of the MOS transistor T3 and the MOS transistor Q1 (FIG. 13) and the current flowing therethrough appears on the output signal line 6 as a signal. After the signal is read out in this manner, the MOS transistor T4 is turned off.

Also, when resetting each pixel, FIG.
The operation is performed as shown in the timing chart of FIG. First, after the pulse signal φV is applied, the signal φS and the signal φSW are set to low level to turn off the MOS transistors T1 and T5.
Then, the reset operation starts. Next, the signal φVRS is set to the high level, and the DC voltage VRB is applied to the gate of the MOS transistor T2. Then, after the signal φVPS is once set to a low level, the signal φVPS is set to a high level, and M
Negative charges are accumulated in the drain of the OS transistor T2. This negative charge is determined by the threshold voltage of the MOS transistor T2.

At this time, the pulse signal φV is applied to the gate of the MOS transistor T4, and for each pixel, a current proportional to the threshold voltage of the MOS transistor T2 is led out to the output signal line 6, and the output from each pixel is output. It can be detected as correction data for correction. After detecting the correction data and turning off the MOS transistor T4, the signal φVPS is set to the intermediate level to reset the MOS transistor T2, and then the signal φVRS is set to the low level to turn off the MOS transistor T6. After a while
The signal φS and the signal φSW are set to a high level, the MOS transistors T1 and T5 are turned on, and a configuration for performing an imaging operation is provided.

In this embodiment, unlike the sixth embodiment, the optical signal is not once integrated by the capacitor C1, so that the integration time is not required, and the reset of the capacitor C1 is not required. As a result, the signal processing can be speeded up accordingly. Also, in the present embodiment, compared to the sixth embodiment, the capacitor C1 and the MOS transistor T
7 can be omitted, the configuration is further simplified, and the pixel size can be reduced.

<Eighth Embodiment> An eighth embodiment will be described with reference to the drawings. FIG. 19 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixels shown in FIGS. 5 and 17 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 19, this embodiment has a circuit configuration in which the pixel shown in the seventh embodiment (FIG. 17) uses a capacitor C2 instead of the MOS transistor T6. That is, one end of the capacitor C2 is a MOS
Connected to a connection node between the gate of the transistor T2 and the source of the MOS transistor T5, a signal φVRS is applied to the other end. Incidentally, as in the second embodiment (FIG. 5), the signal φVRS is a binary voltage signal, the ground level is set to a low level, and a voltage higher than this low level is set to a high level.

As described above, the relationship between the configuration of the present embodiment and the configuration of the second embodiment is the same as the configuration of the seventh embodiment and the configuration of the first embodiment.
In the embodiment (FIG. 2). Therefore, as in the second embodiment, the signal φVRS given to the capacitor C2 is set to low level, and the MOS transistors T1 and T5 are turned on, thereby operating the MOS transistor T2 in the sub-threshold region.
Therefore, a voltage obtained by logarithmically converting the photocurrent flowing from the photodiode PD appears at the connection node a. And MOS
By turning on the transistor T4, an output signal that is logarithmically converted is output. The reset operation is performed in the seventh
By changing the value of each signal at the timing shown in the timing chart of FIG. 18, the variation in the sensitivity of each pixel can be detected as correction data, as in the embodiment.

According to the pixels having the circuit configurations of the fifth to eighth embodiments, after each pixel performs an imaging operation, the pixel voltage is proportional to the threshold voltage of the MOS transistor which causes a variation in sensitivity of each pixel. The signal can be detected as correction data for correcting the output from each pixel. More specifically, in the subsequent circuit, the image data output at the time of imaging is stored in the memory for each pixel in advance, and a current proportional to the threshold voltage of the MOS transistor in each pixel is supplied from the signal line 9 in FIG. , And stored as correction data for each pixel in another memory of the subsequent circuit. Then, if this image data is corrected for each pixel with the correction data, it is possible to remove components due to pixel variations from the output signal. A specific example of this correction method is shown in FIG. 53 described later. This correction method can also be realized by providing a memory such as a line memory in a pixel.

<Ninth Embodiment> A ninth embodiment will be described with reference to the drawings. FIG. 20 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixels shown in FIGS. 6 and 19 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 20, the circuit configuration is such that the MOS transistor T5 is deleted from the pixel of the eighth embodiment (FIG. 19). That is, the MOS transistor T
2, the gate of T3 is connected, and the DC voltage VPS is applied to the source of the MOS transistor T2.

As described above, the relationship between the configuration of the present embodiment and the configuration of the third embodiment (FIG. 6) is the same as that of the configuration of the eighth embodiment and the configuration of the second embodiment (FIG. 5). Respond to relationships. Therefore, similarly to the third embodiment, the capacitor C2
The signal φVRS to be supplied to the
Turning on the transistor T1 causes the MOS transistor T2 to operate in the sub-threshold region. Therefore, a voltage obtained by logarithmically converting the photocurrent flowing from the photodiode PD appears at the connection node a. And M
When the OS transistor T4 is turned on, the logarithmically converted output signal is output.

When resetting each pixel, the operation shown in FIG.
The operation is performed as shown in the timing chart of FIG. First, after the pulse signal φV is applied, the signal φS is set to low level to turn off the MOS transistor T1, and the reset operation starts. Next, the signal φVRS is set to a high level, and M
By increasing the gate voltage of the OS transistor T2, the amount of charge flowing from the source of the MOS transistor T2 is increased.

Thus, MOS transistor T2
, The gate of the MOS transistor T3, and the positive charge stored in the capacitor C2 are quickly recombined. Then, the signal φVRS is set to the low level to reset the potential of the MOS transistor T2 to the initial state. At this time, the pulse signal φV is
The output voltage at the time of resetting is applied to the gate of the S-transistor T4 for each pixel, is output to the output signal line 6, and can be detected as correction data for correcting the output from each pixel. Thus, the correction data is detected and M
After turning off the OS transistor T4, the signal φS is set to the high level, and the MOS transistor T1 is turned on.
Prepare for the next imaging operation.

<Tenth Embodiment> A tenth embodiment will be described with reference to the drawings. FIG. 22 is a circuit diagram illustrating a configuration of a pixel provided in a solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixels shown in FIGS. 9 and 20 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 22, the circuit configuration is such that the capacitor C2 is removed from the pixel of the ninth embodiment (FIG. 20). The signal φVPS is input to the source of the MOS transistor T2. The signal φVPS is a binary voltage signal similar to the fourth embodiment (FIG. 9), and is a voltage substantially equal to the DC voltage VPS and is a high level voltage for operating the MOS transistor T2 in the sub-threshold region. And the MOS transistor T lower than this voltage
The voltage at which a larger current can flow than when a high-level voltage is applied to 2 is set to a low level.

As described above, the relationship between the configuration of the present embodiment and the configuration of the fourth embodiment is the same as that of the ninth embodiment and the third configuration.
Corresponds to the configuration of the embodiment (FIG. 6). Therefore, similarly to the fourth embodiment, the MOS transistor T2
The signal .phi.VPS applied to the source is set to a high level, and the MOS transistor T1 is turned on to operate the MOS transistor T2 in the subthreshold region. Therefore, a voltage obtained by logarithmically converting the photocurrent flowing from the photodiode PD appears at the connection node a.
Then, by turning on the MOS transistor T4, the logarithmically converted output signal is output.

When resetting each pixel, FIG.
The operation is performed as shown in the timing chart of FIG. First, after the pulse signal φV is applied, the signal φS is set to low level to turn off the MOS transistor T1, and the reset operation starts. Next, the signal φVPS is set to low level, and M
By reducing the source voltage of the OS transistor T2, the amount of charge flowing from the source of the MOS transistor T2 is increased.

Thus, MOS transistor T2
Gate and drain of the MOS transistor T3
The positive charges stored in the gates of the transistors are quickly recombined. Then, the signal φVPS is set to the high level to reset the potential of the MOS transistor T2 to the initial state. At this time, the pulse signal φV is supplied to the gate of the MOS transistor T4, and for each pixel, the output voltage at the time of resetting is led out to the output signal line 6 and detected as correction data for correcting the output from each pixel. can do. After detecting the correction data and turning off the MOS transistor T4, the signal φS is set to the high level,
The MOS transistor T1 is turned on to prepare for the next imaging operation.

In the ninth and tenth embodiments, similarly to the fifth to eighth embodiments, the output signal read at the time of resetting is serially output for each pixel from the signal line 9 in FIG. In a subsequent circuit, correction data for each pixel is stored in a memory. Then, if the output current at the time of actual imaging is corrected for each pixel using the stored correction data, it is possible to remove components due to pixel variations from the output signal. A specific example of this correction method is shown in FIG. 53 described later. This correction method can also be realized by providing a memory such as a line memory in a pixel.

In the eighth to tenth embodiments (FIGS. 19, 20, and 22), as in the fifth embodiment (FIG. 14), the source of the MOS transistor T3 has a DC voltage VPS connected to the other end. Is connected to the gates of the capacitor C1 and the MOS transistor T7, to which the drain of the MOS transistor T8 for resetting the capacitor C1 is connected, and the source of the MOS transistor T7 is connected to the MOS.
It may be configured to be connected to the drain of the transistor T4. Further, as in the sixth embodiment (FIG. 16), M
The configuration may be such that the signal φD is applied to the drain of the OS transistor T3, and the MOS transistor T8 is omitted from the configuration as in the above-described fifth embodiment (FIG. 14).

<Pixel Having Configuration Combined with Depletion-Type MOS Transistor> Also, in the first to tenth embodiments (FIGS. 2, 5, 6, 9, 14, 16, and 1)
7, 19, 20, and 22), the first MOS transistor T1 is connected to a depletion-type N-channel M
An OS transistor may be used. The configuration of this pixel is described in the seventh to tenth embodiments (FIGS. 17, 19, 20,
FIGS. 24 to 27 show the pixel of FIG. 22) as an example. As shown in FIGS. 24 to 27, the MOS transistors T2 to T6 other than the MOS transistor T1 are enhancement-type N-channel MOS transistors.

As shown in FIGS. 17, 19, 20, and 22, when all the MOS transistors provided in the pixel are constituted by enhancement type MOS transistors, the MOS transistors T1 and T2 are connected in series. Therefore, the high-level voltage of the signal φS applied to the gate of the MOS transistor T1 is normally higher than the voltage supplied to this pixel. Therefore, it is usually necessary to provide another power supply for supplying signal φS to MOS transistor T1.

On the other hand, as described above, this MO
By making the S transistor T1 a depletion type MOS transistor, the high level voltage of the signal φS applied to its gate can be reduced, and the other M
The same voltage as a high-level signal applied to the OS transistor can be obtained. This is because the threshold value of the depletion type MOS transistor is a negative value, and therefore, the transistor can be turned on with a lower gate voltage than that of the enhancement type MOS transistor.

<Pixel Having Combination of P-Channel MOS Transistors> Further, in the first to tenth embodiments, the first MOS transistor T1 is connected to the P-channel MOS
It may be an S transistor. The configuration of this pixel is
FIGS. 28 to 31 show the pixels of the seventh to tenth embodiments as examples. As shown in FIGS. 28 to 31, the MOS transistors T2 to T6 other than the MOS transistor T1 are:
This is an N-channel MOS transistor. The source of the MOS transistor T1 is connected to the anode of the photodiode PD, and the drain is connected to the drain of the MOS transistor T2.

In such a configuration, the MOS transistor T1 turns on when the voltage difference between the gate and the drain is larger than the threshold, and turns off when the voltage difference between the gate and the drain is smaller than the threshold. Therefore, MOS
The signal φS given to the gate of the transistor T1 is
The ON / OFF operation can be performed without being affected by the MOS transistor T2 connected in series to the drain of the MOS transistor T1 while the timing of the signal φS of the tenth embodiment and its timing are reversed.

Also, ON / OF of MOS transistor T1
Since the F operation is not affected by the MOS transistor T2, there is no need to provide another power supply for supplying the signal φS. Further, by doing so, the MOS transistor T1 can be an enhancement type MOS transistor like the other MOS transistors, so that the MOS transistor T1 can be generated in the same process as the other MOS transistors. It is possible. Therefore, as described above, the production process is simplified as compared with the case where only the first MOS transistor T1 is a depression type MOS transistor.

<Eleventh Embodiment> An eleventh embodiment will be described with reference to the drawings. FIG. 55 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 14 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 55, in this embodiment, the MOS transistors T3, T4,
T7, T8 and capacitor C1 have the same configuration as the pixel of FIG. In such a pixel of FIG. 55,
The DC voltage VPS is applied to the anode of the photodiode PD, and the signal φVPD is applied to the drain of the MOS transistor T2.
And its source is connected to the gate of MOS transistor T3. Also, the MOS transistor T
A first MOS having a drain connected to the source of the second MOS transistor and a source connected to the cathode of the photodiode PD;
A transistor T1 is provided. Further, signal φVPG is applied to the gate of MOS transistor T2, and signal φS is applied to the gate of MOS transistor T1.

(1) A case where a photocurrent is converted into a natural logarithm and output. At this time, the voltage for operating the MOS transistor T2 in the sub-threshold region is set to the first voltage,
In order to detect the variation in the threshold value of the transistor T2,
A voltage having a value substantially equal to the DC voltage VPS is defined as a second voltage.

(1-a) Imaging Operation Using the signal φVPD as the first voltage, the MOS transistor T2
Is operated in the sub-threshold region and MO
The signal φS applied to the gate of the S transistor T1 is set to a high level, and the MOS transistor T1 is turned on. At this time, when light enters the photodiode PD, a photocurrent is generated, and a voltage of a value obtained by natural logarithmically converting the photocurrent is applied to the source of the MOS transistor T2 and the gate of the MOS transistor T3 due to the subthreshold characteristic of the MOS transistor. appear. At this time, since the negative photocharge generated in the photodiode PD flows into the source of the MOS transistor T2, the source voltage of the MOS transistor T2 becomes lower as more intense light enters.

When a voltage which has changed in a natural logarithmic manner with respect to the photocurrent appears at the gate of the MOS transistor T3, first, a high-level signal φVRS2 is applied to the gate of the MOS transistor T8, and the MOS transistor T8
Is turned on to reset the voltage of the capacitor C1 and the connection node a. At this time, the voltage of the connection node a is set to MO
The voltage is reset to a voltage lower than the surface potential determined by the gate voltage of the MOS transistor T3 so that the S transistor T3 can operate. Next, the signal φVRS2 is set to low level to turn off the MOS transistor T8, and then the signal φV is set to high level to turn on the MOS transistor T4.

At this time, the voltage of the connection node a is reset by the MOS transistor T8, so that the MOS
The transistor T3 operates and the MOS transistor T
A voltage obtained by sampling the surface potential determined by the gate voltage of No. 3 is applied to the gate of the MOS transistor T7. Therefore, since the gate voltage of the MOS transistor T7 becomes a value proportional to the value obtained by logarithmically converting the incident light amount, when the MOS transistor T4 is turned on, the current or voltage that becomes a value obtained by natural logarithmically converting the photocurrent becomes ,
The output signal is output to the output signal line 6 via the MOS transistors T7 and T4. When the signal (output current) proportional to the logarithmic value of the incident light amount is read in this way, the MOS transistor T4 is turned off.

(1-b) Sensitivity Variation Detection FIG. 56 shows a timing chart of each signal when detecting the sensitivity variation of each pixel. As described above, after the pulse signal φVRS2 is supplied to the MOS transistor T8 to reset the voltage of the connection node a, the pulse signal φVRS2 is reset.
When V is applied to the gate of the MOS transistor T4 and the output signal is read, first, the signal φS is set to low level to turn off the MOS transistor T1. Then, the signal φVPD is set to the second voltage, and negative charges are accumulated between the drain and the source of the MOS transistor T2.

Next, when the signal φVPD is returned to the first voltage, the accumulated negative charge flows out to the signal line of the signal φVPD, and the state where the negative charge is accumulated in the source of the MOS transistor T2 is obtained. The amount of this negative charge is
It is determined by the threshold voltage between the sources. Thus, MO
When negative charge is accumulated in the source of the S transistor T2, the pulse signal φV is applied to the gate of the MOS transistor T8.
After giving RS2 and resetting the voltage of the connection node a,
The pulse signal φV is applied to the gate of the MOS transistor T4 to read the output signal.

At this time, the read output signal is
Since the value corresponds to the threshold voltage of the S transistor T2,
As a result, it is possible to detect variations in the sensitivity of each pixel. Finally, the signal φS is set to a high level to turn on the MOS transistor T1 so that the imaging operation can be performed.
Set to N. A signal obtained by detecting the variation in sensitivity thus detected is stored as correction data in a memory such as a line memory, and an output signal at the time of actual imaging is corrected for each pixel using the correction data. Accordingly, it is possible to remove components due to pixel variations from the output signal. This correction method can also be realized by providing a memory such as a line memory in a pixel.

(2) A case where a photocurrent is linearly converted and output. At this time, the voltage of the signal φVPD is
3 (the voltage of the signal φVPD can be the first voltage if the circuit configuration is optimized so that the MOS transistor T3 operates properly). is there.). At this time, the signal φS is always at the high level, and the signal φS is applied to the gate of the MOS.
The transistor T1 is always on. With this configuration, the MOS transistor T2 corresponds to the reset MOS transistor T2 in FIG. 54, and the MOS transistor T3 corresponds to the signal amplifying MOS transistor T1 in FIG.

(2-a) Imaging Operation First, the signal φVPG is set to low level, and the reset M
The OS transistor T2 is turned off. As described above, when the reset MOS transistor T2 is turned off, a photocurrent flows through the photodiode PD, so that the gate voltage of the MOS transistor T3 changes. That is, the negative photocharge is more than MO from the photodiode PD.
The gate voltage of the MOS transistor T3, which is applied to the gate of the S transistor T3, has a value linearly changed with respect to the photocurrent. At this time, the photodiode PD
The negative photo-charge generated in the above flows into the gate of the MOS transistor T3, so that the stronger the light is incident, the lower the gate voltage of the MOS transistor T3 becomes.

When the voltage linearly changed with respect to the photocurrent appears at the gate of the MOS transistor T3, first, a high-level signal φVRS2 is applied to the gate of the MOS transistor T8 to turn on the MOS transistor T8.
N, resetting the voltage of the capacitor C1 and the connection node a. At this time, the voltage of the connection node a is reset to a voltage lower than the surface potential determined by the gate voltage of the MOS transistor T3 so that the MOS transistor T3 can operate. Next, the signal φV
Set RS2 to low level and set MOS transistor T8 to OF
After that, the signal φV is changed to high level to turn on the MOS transistor T4.

At this time, the voltage of the connection node a is reset by the MOS transistor T8, so that the MOS
The transistor T3 operates and the MOS transistor T
A voltage obtained by sampling the surface potential determined by the gate voltage of No. 3 is applied to the gate of the MOS transistor T7. Therefore, the gate voltage of the MOS transistor T7 becomes a value proportional to the value obtained by integrating the amount of incident light.
When the MOS transistor T4 is turned on, a current having a value obtained by linearly converting the photocurrent is led out to the output signal line 6 via the MOS transistors T7 and T4. When a signal (output current) proportional to the value of the amount of incident light is read in this way, the MOS transistor T4 is turned off.

(2-b) Reset operation FIG. 57 shows a timing chart of each signal when each pixel is reset. As described above, the pulse signal φV
After RS2 is applied to MOS transistor T8 and the voltage at connection node a is reset, pulse signal φV is
When the output signal is read by being applied to the gate of the transistor T4, first, the signal φVPG is set to a high level,
Turn on the MOS transistor T2. In this way MO
When the S transistor T2 is turned on, the third voltage is applied to the gate of the MOS transistor T3, and the gate voltage of the MOS transistor T3 is reset. Then, the signal φVPG is set to low level again, and the MOS transistor T
2 is turned off.

Next, after applying the pulse signal φVRS2 to the gate of the MOS transistor T8 to reset the voltage at the connection node a, the pulse signal φV is applied to the gate of the MOS transistor T4 to read the output signal. At this time, the output signal has a value corresponding to the gate voltage of the MOS transistor T3, and is read as an output signal when initialized. When the output signal is read, the above-described imaging operation is performed again.

The signal thus initialized is stored in a memory such as a line memory as correction data, and the output signal at the time of actual image pickup is corrected for each pixel using this correction data. A component due to pixel variation can be removed from the output signal. This correction method can also be realized by providing a memory such as a line memory in a pixel. Incidentally, as in the sixth embodiment (FIG. 16), a structure is adopted in which a pulse signal (for example, φVPD ′) is applied to the drain of the MOS transistor T3. Of the MOS transistor T8 from the pixel having the configuration of FIG.
May be omitted.

<Twelfth Embodiment> A twelfth embodiment will be described with reference to the drawings. FIG. 58 is a circuit diagram illustrating a configuration of a pixel provided in a solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 55 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 58, in this embodiment, the MOS transistors T3 and T8 in the pixel of FIG.
As a channel MOS transistor, the DC voltage VPS is applied to the drain of the MOS transistor T3, and the DC voltage VPD is applied to the other end of the capacitor C1 having one end connected to the source of the MOS transistor T3. A DC voltage V RB2 is applied to the drain of the MOS transistor T8, and the source of the MOS transistor T
7 are connected. Other configurations are the same as those of the pixel in FIG. The DC voltage V RB2 applied to the source of the MOS transistor T8 is higher than V PS.

(1) A case where a photocurrent is converted into a natural logarithm and output. At this time, as in the eleventh embodiment, the voltage for operating the MOS transistor T2 in the sub-threshold region is set to the first voltage, and is substantially equal to the DC voltage VPS in order to detect the variation in the threshold value of the MOS transistor T2. The value voltage is defined as a second voltage.

(1-a) Imaging Operation Using the signal φVPD as the first voltage, the MOS transistor T2
Is operated in the sub-threshold region and MO
The signal φS applied to the gate of the S transistor T1 is set to a high level, and the MOS transistor T1 is turned on. Note that the voltage of the capacitor C1 and the connection node a is
It is assumed that the reset has been performed by the MOS transistor T8. At this time, when light is incident on the photodiode PD, a photocurrent is generated. Due to the sub-threshold characteristic of the MOS transistor, a voltage obtained by natural logarithmically converting the photocurrent is applied to the source and the MOS of the MOS transistor T2.
It occurs at the gate of transistor T3. At this time,
Since the negative photocharge generated in the photodiode PD flows into the source of the MOS transistor T2, the source voltage of the MOS transistor T2 becomes lower as more intense light enters.

When a voltage which changes in a natural logarithmic manner with respect to the photocurrent appears at the gate of the MOS transistor T3, the connection node a is reset and is higher than the surface potential determined by the gate voltage of the MOS transistor T3. Since the voltage is a voltage, a positive charge flows from the capacitor C1 through the MOS transistor T3. At this time, the amount of positive charge flowing from the capacitor C1 is determined by the gate voltage of the MOS transistor T3. That is, strong light enters and the MOS transistor T2
The lower the source voltage is, the more positive charge flows from the capacitor C1.

As described above, the positive charge flows from the capacitor C1, and the voltage at the connection node a becomes a value proportional to the value obtained by logarithmically converting the integrated value of the incident light amount. When the pulse signal φV is applied to turn on the MOS transistor T4, a current that is a value obtained by converting the integral value of the photocurrent into a natural logarithm is derived to the output signal line 6 via the MOS transistors T7 and T4. Is done. When the signal (output current) proportional to the logarithmic value of the incident light amount is read in this way, the MOS transistor T4 is turned off.

(1-b) Sensitivity variation detection FIG. 59 shows a timing chart of each signal when detecting the sensitivity variation of each pixel. As described above, when the pulse signal φV is supplied to the gate of the MOS transistor T4 and the output signal is read, first, as in the eleventh embodiment (FIG. 56), the signal φS is set to low level, The transistor T1 is turned off. And
When the signal φVPD is set to the second voltage, the MOS transistor T2
Negative charge is accumulated between the drain and the source of the transistor.

Next, when the signal φVPD is returned to the first voltage, the accumulated negative charges flow out to the signal line of the signal φVPD, and the state where the negative charges are accumulated in the source of the MOS transistor T2 is obtained. The amount of this negative charge is
It is determined by the threshold voltage between the sources. Thus, MO
When negative charge is accumulated in the source of the S transistor T2, the pulse signal φV is applied to the gate of the MOS transistor T8.
After giving RS2 and resetting the voltage of the connection node a,
The pulse signal φV is applied to the gate of the MOS transistor T4 to read the output signal. The MOS transistor T8
Is a low level pulse signal.

At this time, the read output signal is
Since the value corresponds to the threshold voltage of the S transistor T2,
As a result, it is possible to detect variations in the sensitivity of each pixel. Finally, the signal φS is set to a high level to turn on the MOS transistor T1 so that the imaging operation can be performed.
After setting the voltage to N, a pulse signal φVRS2 is applied to the gate of the MOS transistor T8 to reset the voltage of the connection node a. A signal obtained by detecting the variation in sensitivity thus detected is stored as correction data in a memory such as a line memory, and an output signal at the time of actual imaging is corrected for each pixel using the correction data. Accordingly, it is possible to remove components due to pixel variations from the output signal. This correction method can also be realized by providing a memory such as a line memory in a pixel.

(2) A case where a photocurrent is linearly converted and output. At this time, as in the eleventh embodiment, the voltage of the signal φVPD is the third voltage which is the voltage that becomes the operating point of the MOS transistor T3. At this time, the signal φS is always at the high level, and the MOS transistor T1 to which the signal φS is applied to the gate is always on. With this configuration, the MOS transistor T2 corresponds to the reset MOS transistor T2 in FIG. 54, and the MOS transistor T3 corresponds to the signal amplifying MOS transistor T1 in FIG.

(2-a) Imaging Operation First, as in the eleventh embodiment, the signal φVPG is set to low level, and the reset MOS transistor T2 is turned on.
Set to the state of FF. It is assumed that the voltages of the capacitor C1 and the connection node a have been reset by the MOS transistor T8. Thus, the reset MO
When the S transistor T2 is turned off, a photocurrent flows through the photodiode PD, so that the gate voltage of the MOS transistor T3 changes. That is, a negative photocharge is given to the gate of the MOS transistor T3 from the photodiode PD, and the gate voltage of the MOS transistor T3 becomes a value linearly changed with respect to the photocurrent. At this time, since the negative photocharge generated in the photodiode PD flows into the gate of the MOS transistor T3, the gate voltage of the MOS transistor T3 becomes lower as more intense light enters.

When a voltage linearly changed with respect to the photocurrent appears at the gate of the MOS transistor T3, the connection node a is reset and a voltage higher than the surface potential determined by the gate voltage of the MOS transistor T3 is obtained. , A positive charge flows from the capacitor C1 via the MOS transistor T3. At this time, the amount of positive charge flowing from the capacitor C1 is determined by the gate voltage of the MOS transistor T3. That is, the more positive light is incident and the lower the gate voltage of the MOS transistor T3, the larger the amount of positive charges flowing from the capacitor C1.

As described above, positive charges flow from the capacitor C1, and the voltage at the connection node a becomes a value proportional to the integral of the amount of incident light. Then, a pulse signal φV is applied to
When the S-transistor T4 is turned on, a current that is a value obtained by linearly converting the integrated value of the photocurrent is led out to the output signal line 6 via the MOS transistors T7 and T4.
When a signal (output current) proportional to the integral value of the incident light amount is read out in this manner, the MOS transistor T4 is turned off.
To

(2-b) Reset Operation FIG. 60 shows a timing chart of each signal when each pixel is reset. As described above, the pulse signal φV
Is supplied to the gate of the MOS transistor T4, and the output signal is read, first, the signal φVPG is set to the high level, and the MOS transistor T2 is turned on. As described above, when the MOS transistor T2 is turned on, the third voltage is applied to the gate of the MOS transistor T3,
The gate voltage of the transistor T3 is reset. Then, the signal φVPG is set to low level again, and the MOS transistor T2 is turned off.

Next, after a pulse signal φVRS2 is applied to the gate of the MOS transistor T8 to reset the voltage of the connection node a, a pulse signal φV is applied to the gate of the MOS transistor T4 to read an output signal. At this time, the output signal has a value corresponding to the gate voltage of the MOS transistor T3, and is read as an output signal when initialized. When the output signal is read, the pulse signal φVRS2 is again applied to the gate of the MOS transistor T8.
To reset the voltage of the connection node a, and then the above-described imaging operation is performed again. Note that the pulse signal φVRS2
Is a low-level pulse signal.

The signal thus initialized is stored in a memory such as a line memory as correction data, and an output signal at the time of actual image pickup is corrected for each pixel using this correction data. A component due to pixel variation can be removed from the output signal. This correction method can also be realized by providing a memory such as a line memory in a pixel. Incidentally, as in the sixth embodiment (FIG. 16), a structure is adopted in which a pulse signal (for example, φVPS) is applied to the drain of the MOS transistor T3.
By allowing the voltage of the connection node a to be reset, a configuration in which the MOS transistor T8 is omitted from the pixel having the configuration in FIG. 58 may be employed. In this case, the MO
Pulse signal φV applied to the drain of S transistor T3
PS is supplied from a power supply line different from the DC voltage VPS applied to the anode of the photodiode PD.

<Thirteenth Embodiment> A thirteenth embodiment will be described with reference to the drawings. FIG. 61 is a circuit diagram illustrating a configuration of a pixel provided in a solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 55 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 61, in this embodiment, M
The DC voltage VPD is applied to the drain of the OS transistor T3, and the capacitor C1 and the MOS transistors T7 and T8 are omitted. Other configurations are the same as those of the eleventh embodiment (FIG. 55).

(1) A case where a photocurrent is converted into a natural logarithm and output. At this time, as in the eleventh embodiment, the voltage for operating the MOS transistor T2 in the sub-threshold region is set to the first voltage, and is substantially equal to the DC voltage VPS in order to detect the variation in the threshold value of the MOS transistor T2. The value voltage is defined as a second voltage.

(1-a) Imaging Operation Using the signal φVPD as the first voltage, the MOS transistor T2
Is operated in the sub-threshold region and MO
The signal φS applied to the gate of the S transistor T1 is set to a high level, and the MOS transistor T1 is turned on. At this time, when light enters the photodiode PD, a photocurrent is generated, and a voltage of a value obtained by natural logarithmically converting the photocurrent is applied to the source of the MOS transistor T2 and the gate of the MOS transistor T3 due to the subthreshold characteristic of the MOS transistor. appear. At this time, since the negative photocharge generated in the photodiode PD flows into the source of the MOS transistor T2, the source voltage of the MOS transistor T2 becomes lower as more intense light enters.

When a voltage which has changed in a natural logarithmic manner with respect to the photocurrent appears at the gate of the MOS transistor T3, a pulse signal φV is supplied to turn on the MOS transistor T4, and the photocurrent is naturally logarithmically changed. Is output to the output signal line 6 via the MOS transistors T3 and T4. When a signal (output current) proportional to the logarithmic value of the incident light amount is read out in this manner,
Turn off the MOS transistor T4.

(1-b) Sensitivity Variation Detection FIG. 62 shows a timing chart of each signal when detecting the sensitivity variation of each pixel. As described above, when the pulse signal φV is supplied to the gate of the MOS transistor T4 and the output signal is read, first, as in the eleventh embodiment (FIG. 56), the signal φS is set to low level, The transistor T1 is turned off. And
When the signal φVPD is set to the second voltage, the MOS transistor T2
Negative charge is accumulated between the drain and the source of the transistor.

Next, when the signal φVPD is returned to the first voltage, the accumulated negative charge flows out to the signal line of the signal φVPD, and the state where the negative charge is accumulated in the source of the MOS transistor T2 is obtained. The amount of this negative charge is
It is determined by the threshold voltage between the sources. Thus, MO
When a negative charge is accumulated in the source of the S transistor T2, the pulse signal φV is applied to the gate of the MOS transistor T4.
And read the output signal.

At this time, the read output signal is
Since the value corresponds to the threshold voltage of the S transistor T2,
As a result, it is possible to detect variations in the sensitivity of each pixel. Finally, the signal φS is set to a high level to turn on the MOS transistor T1 so that the imaging operation can be performed.
Set to N. A signal obtained by detecting the variation in sensitivity thus detected is stored as correction data in a memory such as a line memory, and an output signal at the time of actual imaging is corrected for each pixel using the correction data. Accordingly, it is possible to remove components due to pixel variations from the output signal. This correction method can also be realized by providing a memory such as a line memory in a pixel.

(2) A case where a photocurrent is linearly converted and output. At this time, as in the eleventh embodiment, the voltage of the signal φVPD is the third voltage which is the voltage that becomes the operating point of the MOS transistor T3. At this time, the signal φS is always at the high level, and the MOS transistor T1 to which the signal φS is applied to the gate is always on. With this configuration, the MOS transistor T2 corresponds to the reset MOS transistor T2 in FIG. 54, and the MOS transistor T3 corresponds to the signal amplifying MOS transistor T1 in FIG.

(2-a) Imaging Operation First, as in the eleventh embodiment, the signal φVPG is set to low level, and the reset MOS transistor T2 is turned on.
Set to the state of FF. As described above, when the reset MOS transistor T2 is turned off, the photodiode P
When a photocurrent flows through D, the gate voltage of the MOS transistor T3 changes. That is, a negative photocharge is given from the photodiode PD to the gate of the MOS transistor T3, and the gate voltage of the MOS transistor T3 is
The value changes linearly with the photocurrent. At this time, the negative photocharge generated in the photodiode PD is MO
Since the light flows into the gate of the S transistor T3, the gate voltage of the MOS transistor T3 decreases as the intensity of the incident light increases.

When a voltage linearly changed with respect to the photocurrent appears at the gate of the MOS transistor T3, a pulse signal φV is supplied to the MOS transistor T3.
Turn 4 ON. At this time, a current that is a value obtained by linearly converting the integrated value of the photocurrent is a MOS transistor T
3, and output to the output signal line 6 via T4. When the signal (output current) proportional to the integral value of the incident light amount is read in this way, the MOS transistor T4 is turned off.

(2-b) Reset Operation FIG. 63 shows a timing chart of each signal when each pixel is reset. As described above, the pulse signal φV
Is supplied to the gate of the MOS transistor T4, and the output signal is read, first, the signal φVPG is set to the high level, and the MOS transistor T2 is turned on. As described above, when the MOS transistor T2 is turned on, the third voltage is applied to the gate of the MOS transistor T3,
The gate voltage of the transistor T3 is reset. Then, the signal φVPG is set to low level again, and the MOS transistor T2 is turned off.

Next, a pulse signal φV is supplied to the gate of the MOS transistor T4 to read an output signal. At this time, the output signal has a value corresponding to the gate voltage of the MOS transistor T3, and is read as an output signal when initialized. When the output signal is read, the above-described imaging operation is performed again. The signal initialized at this time is stored as correction data in a memory such as a line memory, and for each pixel, the output signal at the time of actual imaging is corrected using this correction data, so that the output signal is Components due to pixel variations can be removed. A specific example of this correction method is shown in FIG. 53 described later. This correction method can also be realized by providing a memory such as a line memory in a pixel.

In the embodiments described above, the signal reading from each pixel may be performed using a charge-coupled device (CCD). In this case, the charge can be read out to the CCD by providing a potential barrier having a variable potential level corresponding to the MOS transistor T4.

In the first to eleventh and thirteenth embodiments described above, all of the MOS transistors T1 to T8, which are active elements in the pixel, are constituted by N-channel MOS transistors. ~ T8
May be constituted by P-channel MOS transistors. In the twelfth embodiment, the N-channel MOS transistor in the pixel may be replaced with a P-channel MOS transistor, and the P-channel MOS transistor may be replaced with an N-channel MOS transistor.

FIGS. 33 to 36 and FIGS. 39 to 44 show:
Fourteenth to twenty-third embodiments are shown as examples in which the first to tenth embodiments are configured by P-channel MOS transistors. FIGS. 64 to 66 show the first to eleventh parts.
The twenty-fourth to the second examples in which the MOS transistors of the pixel according to the thirteenth embodiment are constituted by MOS transistors of opposite polarity.
6 shows the sixth embodiment. FIGS. 45 to 48 show the twentieth to twenty-third embodiments in which the first MOS transistor T1 is a depletion-type P-channel MOS transistor. Further, FIGS.
In the twentieth to twenty-third embodiments, the first MOS transistor T1 is an N-channel MOS transistor. Therefore, the polarity of the connection and the polarity of the applied voltage are reversed in FIGS. 32 to 52 and FIGS. 64 to 66. For example, in FIG. 33 (the fourteenth embodiment), the photodiode PD has an anode connected to the DC voltage VPD, a cathode connected to the drain of the first MOS transistor T1, and a source of the MOS transistor T1 connected to the second MOS transistor T2. Drain and third MOS
It is connected to the gate of transistor T3. Signal φVPS is applied to the source of MOS transistor T2.

When a pixel as shown in FIG. 33 performs logarithmic conversion, the DC voltage VPS and the DC voltage VPD satisfy VPS> V.
PD, which is the reverse of FIG. 2 (first embodiment). The output voltage of the capacitor C1 has a high initial value and drops by integration. Further, the first MOS transistor T1, the fourth MOS transistor T4, the fifth MOS transistor
Turn on transistor T5 and sixth MOS transistor T6
When this is done, a low voltage is applied to the gate. Furthermore,
The embodiment of FIGS. 34 to 36 and FIGS.
In the twenty-fourth embodiment), at the time of the eighth MOS transistor T8, a low voltage is applied to the gate. Also, FIG.
In the pixels having the configurations shown in FIGS.
When turning on the first MOS transistor T1 serving as the OS transistor, a high voltage is applied to the gate. Further, in the embodiment of FIG. 65 (25th embodiment),
When turning on the fourth MOS transistor T4, a low voltage is applied to the gate, and when turning on the eighth MOS transistor T8, a high voltage is applied to the gate. As described above, when MOS transistors having opposite polarities are used, the voltage relationship and the connection relationship are partially different, but since the configuration is substantially the same and the basic operation is the same, FIGS. 39 to 52 and FIGS. 64 to 66 are only shown in the drawings, and the description of the configuration and operation is omitted.

FIG. 32 is a block circuit diagram illustrating the overall configuration of the solid-state imaging device including the pixels according to the fourteenth to seventeenth embodiments. The solid-state imaging device including the pixels according to the eighteenth to twenty-sixth embodiments is shown in FIG. FIG. 37 is a block circuit configuration diagram for explaining the overall configuration of the device. 32 and 37
, The same portions (same role portions) as those in FIGS. 1 and 12 are denoted by the same reference numerals, and description thereof is omitted. Hereinafter, FIG.
The configuration of No. 7 will be briefly described. P for output signal lines 6-1, 6-2, ..., 6-m arranged in the column direction.
Channel MOS transistor Q1 and P channel MO
The S transistor Q2 is connected. MOS transistor Q1 has a gate connected to DC voltage line 7, a drain connected to output signal line 6-1, and a source connected to DC voltage VP.
Connected to line 8 of S '.

On the other hand, the drain of the MOS transistor Q2 is connected to the output signal line 6-1, the source is connected to the final signal line 9, and the gate is connected to the horizontal scanning circuit 3. Here, the MOS transistor Q1 forms an amplification circuit as shown in FIG. 38A together with the P-channel MOS transistor Ta in the pixel. Note that the MOS transistor Ta corresponds to the seventh MOS transistor T7 in the eighteenth, nineteenth, twenty-fourth, and twenty-fifth embodiments.
In the twentieth to twenty-third and twenty-sixth embodiments, it corresponds to the third MOS transistor T3.

In this case, MOS transistor Q1 is connected to MO
It serves as a load resistance or a constant current source for the S transistor Ta. Accordingly, the relationship between the DC voltage VPS 'connected to the source of the MOS transistor Q1 and the DC voltage VPD' connected to the drain of the MOS transistor Ta is VP
D ′ <VPS ′, and the DC voltage VPD ′ is, for example, a ground voltage (ground). The drain of the MOS transistor Q1 is connected to the MOS transistor Ta, and a DC voltage is applied to the gate. The P-channel MOS transistor Q2 is controlled by the horizontal scanning circuit 3, and leads the output of the amplifier circuit to the final signal line 9. 18th to 26th
Considering the fourth MOS transistor T4 provided in the pixel as in the embodiment, the circuit in FIG. 38A is represented as shown in FIG.

<Method of Correcting Image Data>
An example in which a solid-state imaging device provided with a pixel having a circuit configuration as in the twenty-sixth embodiment is used for an image input device such as a digital camera will be described with reference to the drawings.

The image input device shown in FIG. 53 includes an objective lens 51, a solid-state imaging device 52 that outputs an electric signal in accordance with the amount of light incident through the objective lens 51, and a solid-state imaging device 52 at the time of imaging. A memory 53 to which an electric signal (hereinafter, referred to as “image data”) is input and temporarily stored.
And the electric signal of the solid-state imaging device 52 at the time of reset (hereinafter, referred to as
It is called “correction data”. ) Is inputted and temporarily stored, a correction operation circuit 55 for correcting the correction data stored from the memory 54 from the image data sent from the memory 53, and a correction operation circuit 55 A processing unit 56 for performing arithmetic processing on the corrected image data and outputting the processed data to the outside. The solid-state imaging device 52 is a solid-state imaging device provided with pixels having a circuit configuration as in the first to twenty-sixth embodiments.

The image input device having such a configuration is as follows.
The imaging operation is performed, and the image data is output from the solid-state imaging device 52 to the memory 53 for each pixel. Then, when each pixel has completed the imaging operation and performed the reset operation, as described above, the variation in the sensitivity of each pixel is examined,
The correction data is output to the memory 54. And the memory 5
The image data of each pixel in 3 and the correction data of each pixel in the memory 54 are sent to the correction arithmetic circuit 55 for each pixel.

In the correction operation circuit 55, from the image data transmitted from the memory 53, the correction data transmitted from the memory 54 of the same pixel which has output this image data is corrected and calculated for each pixel. Image data on which the correction data has been corrected and calculated is sent to the processing unit 56, subjected to a calculation process, and then output to the outside. In such an image input device, a line memory for recording data transmitted from the solid-state imaging device 52 line by line is used as the memories 53 and 54, respectively. Therefore, the memories 53 and 54
Can be easily incorporated into a solid-state imaging device.

In the other embodiments, the reset substantially cancels the variation in the sensitivity of each pixel by performing the resetting. However, in order to more accurately perform the resetting, the memory and the correction calculation described in FIG. A correction circuit including a circuit and the like may be provided.

[0191]

As described above, according to the solid-state imaging device according to any one of claims 1, 2, 8, 9, 16 and 17, of the present invention, the photosensitive element and A switch is provided between the first transistor and the first transistor to which the first electrode is electrically connected, and the switch is turned off.
At the same time, the reset is performed by allowing a larger current to flow through the first transistor than at the time of imaging. Therefore, the light incident on the photosensitive element is prevented from affecting the reset operation, and the reset operation can be performed accurately. In addition, each pixel is brought into the same initial state by the reset, and the variation in sensitivity of each pixel can be suppressed.

Further, claim 3, claim 10, claim 14,
Two switches provided between the photoelectric conversion element and the first transistor and between the control electrode of the first transistor and the first electrode,
Alternatively, two MOS transistors provided between the photodiode and the second MOS transistor and between the gate electrode of the second MOS transistor and the first electrode are turned off.
F and the control electrode of the first transistor and the second
By detecting the variation in sensitivity of each pixel by changing the voltage applied to the electrode or the gate electrode of the second MOS transistor and the second electrode, it is possible to accurately detect the variation in sensitivity of each pixel. Further, by configuring the active element by a MOS transistor, high integration is facilitated, and the active element can be formed on a single chip together with peripheral processing circuits (A / D converter, digital system processor, memory) and the like.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram for explaining the overall configuration of a two-dimensional solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of one pixel according to the first embodiment of the present invention.

FIG. 3 is a timing chart of a signal applied to each element of a pixel used in the first embodiment.

FIG. 4 is a diagram illustrating a relationship between a configuration and a potential of the pixel in FIG. 2;

FIG. 5 is a circuit diagram showing a configuration of one pixel according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of one pixel according to a third embodiment of the present invention.

FIG. 7 is a timing chart of a signal applied to each element of a pixel used in the third embodiment.

FIG. 8 is a diagram illustrating a relationship between a configuration and a potential of the pixel in FIG. 6;

FIG. 9 is a circuit diagram showing a configuration of one pixel according to a fourth embodiment of the present invention.

FIG. 10 is a timing chart of signals applied to each element of a pixel used in the fourth embodiment.

FIG. 11 is a diagram illustrating a relationship between a configuration and a potential of the pixel in FIG. 9;

FIG. 12 is a block circuit diagram for explaining the overall configuration of a two-dimensional solid-state imaging device according to an embodiment of the present invention.

FIG. 13 is a circuit diagram of a part of FIG.

FIG. 14 is a circuit diagram showing a configuration of one pixel according to a fifth embodiment of the present invention.

FIG. 15 is a timing chart of signals applied to each element of a pixel used in the fifth embodiment.

FIG. 16 is a circuit diagram showing a configuration of one pixel according to a sixth embodiment of the present invention.

FIG. 17 is a circuit diagram showing a configuration of one pixel according to a seventh embodiment of the present invention.

FIG. 18 is a timing chart of signals applied to each element of a pixel used in the seventh embodiment.

FIG. 19 is a circuit diagram showing a configuration of one pixel according to an eighth embodiment of the present invention.

FIG. 20 is a circuit diagram showing a configuration of one pixel according to a ninth embodiment of the present invention.

FIG. 21 is a timing chart of signals applied to each element of a pixel used in the ninth embodiment.

FIG. 22 is a circuit diagram showing a configuration of one pixel according to a tenth embodiment of the present invention.

FIG. 23 is a timing chart of a signal applied to each element of a pixel used in the tenth embodiment.

FIG. 24 shows a configuration 1 of one pixel according to the seventh embodiment of the present invention.
FIG. 4 is a circuit diagram showing an example.

FIG. 25 illustrates one configuration of one pixel according to the eighth embodiment of the present invention.
FIG. 4 is a circuit diagram showing an example.

FIG. 26 illustrates one configuration of one pixel according to the ninth embodiment of the present invention.
FIG. 4 is a circuit diagram showing an example.

FIG. 27 is a circuit diagram showing an example of a configuration of one pixel according to the tenth embodiment of the present invention.

FIG. 28 illustrates one configuration of one pixel according to the seventh embodiment of the present invention.
FIG. 4 is a circuit diagram showing an example.

FIG. 29 illustrates one configuration of one pixel according to the eighth embodiment of the present invention.
FIG. 4 is a circuit diagram showing an example.

FIG. 30 shows one configuration of one pixel according to the ninth embodiment of the present invention.
FIG. 4 is a circuit diagram showing an example.

FIG. 31 is a circuit diagram showing an example of a configuration of one pixel according to the tenth embodiment of the present invention.

FIG. 32 is a block circuit diagram for explaining the overall configuration of the two-dimensional solid-state imaging device according to the present invention in the case of an embodiment in which active elements in pixels are configured by P-channel MOS transistors.

FIG. 33 is a circuit diagram showing a configuration of one pixel according to a fourteenth embodiment of the present invention.

FIG. 34 is a circuit diagram showing a configuration of one pixel according to a fifteenth embodiment of the present invention.

FIG. 35 is a circuit diagram showing a configuration of one pixel according to a sixteenth embodiment of the present invention.

FIG. 36 is a circuit diagram showing a configuration of one pixel according to a seventeenth embodiment of the present invention.

FIG. 37 is a block circuit diagram for explaining the overall configuration of a two-dimensional solid-state imaging device according to the present invention in the case where an active element in a pixel is configured by a P-channel MOS transistor;

FIG. 38 is a circuit diagram of part of FIG. 37;

FIG. 39 is a circuit diagram showing a configuration of one pixel according to an eighteenth embodiment of the present invention.

FIG. 40 is a circuit diagram showing a configuration of one pixel according to a nineteenth embodiment of the present invention.

FIG. 41 is a circuit diagram showing a configuration of one pixel according to a twentieth embodiment of the present invention.

FIG. 42 is a circuit diagram showing a configuration of one pixel according to a twenty-first embodiment of the present invention.

FIG. 43 is a circuit diagram showing a configuration of one pixel according to a twenty-second embodiment of the present invention.

FIG. 44 is a circuit diagram showing a configuration of one pixel according to a twenty-third embodiment of the present invention.

FIG. 45 is a circuit diagram showing an example of the configuration of one pixel according to the twentieth embodiment of the present invention.

FIG. 46 is a circuit diagram showing an example of a configuration of one pixel according to the twenty-first embodiment of the present invention.

FIG. 47 is a circuit diagram showing an example of the configuration of one pixel according to the twenty-second embodiment of the present invention.

FIG. 48 is a circuit diagram showing an example of the configuration of one pixel according to the twenty-third embodiment of the present invention.

FIG. 49 is a circuit diagram showing an example of the configuration of one pixel according to the twentieth embodiment of the present invention.

FIG. 50 is a circuit diagram showing an example of the configuration of one pixel according to the twenty-first embodiment of the present invention.

FIG. 51 is a circuit diagram showing an example of a configuration of one pixel according to a twenty-second embodiment of the present invention.

FIG. 52 is a circuit diagram showing an example of a configuration of one pixel according to the twenty-third embodiment of the present invention.

FIG. 53 is a block diagram showing the internal structure of an image input device provided with a solid-state imaging device using pixels according to the embodiments.

FIG. 54 is a circuit diagram showing a configuration of one pixel of a conventional example.

FIG. 55 is a circuit diagram showing a configuration of one pixel according to an eleventh embodiment of the present invention.

FIG. 56 is a timing chart of signals applied to each element of a pixel used in the eleventh embodiment.

FIG. 57 is a timing chart of signals applied to each element of a pixel used in the eleventh embodiment.

FIG. 58 is a circuit diagram showing a configuration of one pixel according to a twelfth embodiment of the present invention.

FIG. 59 is a timing chart of signals applied to each element of a pixel used in the twelfth embodiment.

FIG. 60 is a timing chart of signals applied to each element of a pixel used in the twelfth embodiment.

FIG. 61 is a circuit diagram showing a configuration of one pixel according to a thirteenth embodiment of the present invention.

FIG. 62 is a timing chart of signals applied to each element of a pixel used in the thirteenth embodiment.

FIG. 63 is a timing chart of signals applied to each element of a pixel used in the thirteenth embodiment.

FIG. 64 is a circuit diagram showing an example of a configuration of one pixel according to a twenty-fourth embodiment of the present invention.

FIG. 65 is a circuit diagram showing an example of the configuration of one pixel according to the twenty-fifth embodiment of the present invention.

FIG. 66 is a circuit diagram showing an example of the configuration of one pixel according to the twenty-sixth embodiment of the present invention.

[Explanation of symbols]

 G11 to Gmn pixel 2 vertical scanning circuit 3 horizontal scanning circuit 4-1 to 4-n row selection line 6-1 to 6-m output signal line 7 DC voltage line 8 line 9 signal line 10 P-type semiconductor substrate 11, 12 N Diffusion layer 13 Oxide film 14 Polysilicon 51 Objective lens 52 Solid-state imaging device 53, 54 Memory 55 Correction operation circuit 56 Processing unit PD Photodiode T1 to T8 First to eighth MOS transistors C1, C2 Capacitor

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M118 AA02 AA10 AB01 AB10 BA10 BA14 CA02 DB09 DB11 DD09 DD12 FA06 5C024 AA01 CA14 FA01 FA11 GA31 GA33 JA04

Claims (32)

[Claims] 1. A semiconductor device comprising: a photosensitive element for generating an electric signal corresponding to an amount of incident light; a first transistor having a first electrode electrically connected to the photosensitive element; and the first transistor in a sub-threshold region. A solid-state imaging device having a plurality of pixels, comprising: a photoelectric conversion unit that operates to convert the electrical signal into a natural logarithm; Switch means between the element and the first electrode of the first transistor; turning on the switch means and operating the first transistor in a subthreshold region to perform imaging; Is turned off and the first
Wherein the reset is performed such that a larger current can flow through the transistor than during imaging. 2. A semiconductor device comprising: a photosensitive element for generating an electric signal corresponding to an amount of incident light; a first transistor having a first electrode electrically connected to the photosensitive element; and the first transistor in a sub-threshold region. A solid-state imaging device having a plurality of pixels, comprising: a photoelectric conversion unit that operates to convert the electrical signal into a natural logarithm; and a lead-out path that leads an output signal of the photoelectric conversion unit to an output signal line. Switch means between the element and the first electrode of the first transistor; turning on the switch means and operating the first transistor in a subthreshold region to perform imaging; Is turned off and the first
A solid-state imaging device, wherein each pixel is set to the same initial state by resetting the transistor so that a larger current than that at the time of imaging can flow. 3. A plurality of pixels each comprising: photoelectric conversion means for generating an output signal obtained by natural logarithmic conversion of an incident light amount; and a derivation path for deriving an output signal of the photoelectric conversion means to an output signal line. In the solid-state imaging device having: a photoelectric conversion element having a DC voltage applied to a first electrode; a first switch having one contact connected to a second electrode of the photoelectric conversion element; A first transistor including a first electrode, a second electrode, and a control electrode; a first transistor having the first electrode connected to the other contact of the switch; a first electrode including a first electrode, a second electrode, and a control electrode; A DC voltage is applied to the first transistor, a control electrode is connected to the first electrode of the first transistor, and a second transistor that outputs an electric signal from the second electrode; Connect between electrodes A second switch, wherein the first switch and the second switch are turned on to cause each of the pixels to perform an imaging operation, and the first switch and the second switch are turned off and the first switch is turned off. A variation in sensitivity of each pixel by changing a voltage applied to a control electrode and a second electrode of the transistor. And a third switch having one contact connected to a control electrode of the first transistor and a DC voltage applied to the other contact, wherein each pixel performs an imaging operation. 4. The solid-state imaging device according to claim 3, wherein the third switch is turned off, and the third switch is turned on when detecting a variation in sensitivity of each pixel. 5. The solid-state imaging device according to claim 4, wherein said third switch is a transistor. 6. A capacitor having one end connected to a control electrode of the first transistor, wherein the capacitor is connected between when each pixel performs an imaging operation and when a variation in sensitivity of each pixel is detected. The solid-state imaging device according to claim 3, wherein a voltage applied to the other end is made different. 7. The solid-state imaging device according to claim 3, wherein said second switch is a transistor. 8. A plurality of pixels each comprising: a photoelectric conversion unit for generating an output signal obtained by natural logarithmic conversion of an incident light amount; and a lead-out path for leading an output signal of the photoelectric conversion unit to an output signal line. In the solid-state imaging device having: a photoelectric conversion element having a DC voltage applied to a first electrode; a first switch having one contact connected to a second electrode of the photoelectric conversion element; A first transistor including a first electrode, a second electrode, and a control electrode, wherein the first electrode and the control electrode are connected to the other contact of the first switch, and a DC voltage is applied to the second electrode; A first electrode, a second electrode, and a control electrode; a DC voltage is applied to the first electrode; the control electrode is connected to the first electrode and the control electrode of the first transistor; The second to output And a reset capacitor having one end connected to a control electrode of the first transistor. When each of the pixels performs an imaging operation, the first switch is turned on and the reset capacitor is turned on. When the voltage applied to the other end is set as a first voltage, the first transistor is operated in a sub-threshold region, and when resetting each pixel, the first switch is turned on.
A solid-state imaging device, wherein the FF is used and a voltage applied to the other end of the reset capacitor is set as a second voltage so that a larger current can flow through the first transistor than during imaging. 9. A plurality of pixels comprising: photoelectric conversion means for generating an output signal obtained by natural logarithmically converting the amount of incident light; and a derivation path for deriving an output signal of the photoelectric conversion means to an output signal line. In the solid-state imaging device having: a photoelectric conversion element having a DC voltage applied to a first electrode; a first switch having one contact connected to a second electrode of the photoelectric conversion element; A first transistor including a first electrode, a second electrode, and a control electrode, wherein the first electrode and the control electrode are connected to the other contact of the first switch; and a first electrode, a second electrode, and a control electrode. A second transistor that is connected to a first electrode and a control electrode of the first transistor while a DC voltage is applied to the first electrode, and outputs an electric signal from a second electrode; Each pixel performs an imaging operation Is performed, the first switch is turned on, the voltage applied to the second electrode of the first transistor is set as a first voltage, the first transistor is operated in a subthreshold region, and each pixel is reset. When the first switch is set to O
A FF is provided, and a voltage applied to a second electrode of the first transistor is set as a second voltage so that a larger current can flow than before applying the second voltage to the first transistor. Solid-state imaging device. 10. A plurality of pixels each comprising: a photoelectric conversion unit for generating an output signal obtained by natural logarithmically converting an incident light amount; and a lead-out path for leading an output signal of the photoelectric conversion unit to an output signal line. In the solid-state imaging device having: a photoelectric conversion element having a DC voltage applied to a second electrode; a first switch having one contact connected to a first electrode of the photoelectric conversion element; A first transistor having a first electrode, a second electrode, and a control electrode, a second electrode connected to the other contact of the first switch, a first transistor, a second electrode, and a control electrode; A second transistor for applying a DC voltage to one electrode and having a control electrode connected to a second electrode of the first transistor and outputting an electric signal from the second electrode; And the said One transistor is operated in a sub-threshold region to cause each of the pixels to perform an imaging operation. The first switch is turned off, and the voltage applied to the first electrode of the first transistor is changed. A solid-state imaging device for detecting variation in pixel sensitivity. 11. The solid-state imaging device according to claim 3, wherein the first switch is a transistor having a polarity opposite to that of the first transistor. 12. The solid-state imaging device according to claim 3, wherein the first switch is a transistor. 13. The solid-state imaging device according to claim 1, wherein the pixels are arranged in a matrix. 14. In a solid-state imaging device having a plurality of pixels, each pixel includes a photodiode, a first MOS transistor having a first electrode connected to one electrode of the photodiode, and a second MOS transistor of the first MOS transistor. A second MOS transistor having an electrode connected to a first electrode; a third MOS transistor having a gate electrode connected to a first electrode of the second MOS transistor; and a first electrode connected to a first electrode of the second MOS transistor A fourth MOS transistor in which a second electrode is connected to a gate electrode of the second MOS transistor; and a fourth MOS transistor in which a first electrode is connected to the gate electrode of the second MOS transistor and a DC voltage is applied to the second electrode. A first MOS transistor and a fourth MOS transistor. At the same time, the fifth MOS transistor is turned off, the second MOS transistor is operated in a sub-threshold region equal to or less than a threshold to cause each pixel to perform an imaging operation, and the first and fourth MOS transistors are turned off. After turning on the 5 MOS transistor,
A solid-state imaging device, wherein a variation in sensitivity of each pixel due to a threshold voltage of the second MOS transistor is detected by changing a voltage applied to a second electrode of the second MOS transistor. 15. A solid-state imaging device having a plurality of pixels, wherein each pixel includes a photodiode, a first MOS transistor having a first electrode connected to one electrode of the photodiode, and a second MOS transistor of the first MOS transistor. A second MOS transistor having an electrode connected to a first electrode; a third MOS transistor having a gate electrode connected to a first electrode of the second MOS transistor; and a first electrode connected to a first electrode of the second MOS transistor A fourth MOS transistor having a second electrode connected to a gate electrode of the second MOS transistor; and a first capacitor having one end connected to a gate electrode of the second MOS transistor. Is turned on, and a first voltage is applied to the other end of the first capacitor. ,
Operating the second MOS transistor in a sub-threshold region equal to or less than a threshold to cause each pixel to perform an imaging operation; turning off the first and fourth MOS transistors; and applying a second voltage to the other end of the first capacitor. A solid-state imaging device, characterized in that, after the application, the voltage applied to the second electrode of the second MOS transistor is changed to detect the variation in sensitivity of each pixel due to the threshold voltage of the second MOS transistor. 16. In a solid-state imaging device having a plurality of pixels, each pixel includes a photodiode, a first MOS transistor having a first electrode connected to one electrode of the photodiode, and a second MOS transistor of the first MOS transistor. A second MOS transistor having a first electrode and a gate electrode connected to the electrode; a third MOS transistor having a gate electrode connected to the first electrode and the gate electrode of the second MOS transistor; a first electrode and a gate of the second MOS transistor A first capacitor having one end connected to the electrode; when the pixel performs an imaging operation, the first MOS transistor is turned on, and a first voltage is applied to the other end of the first capacitor; Operating the second MOS transistor in a sub-threshold region below a threshold, When performing a power cut, the first MOS transistor is turned off, and a second voltage is applied to the other end of the first capacitor so that a larger current can flow through the second MOS transistor than during imaging. A solid-state imaging device characterized by the above-mentioned. 17. A solid-state imaging device having a plurality of pixels, wherein each pixel includes a photodiode, a first MOS transistor having a first electrode connected to one electrode of the photodiode, and a second MOS transistor of the first MOS transistor. A second MOS transistor having a first electrode and a gate electrode connected to the electrode; and a third MOS transistor having a gate electrode connected to the first electrode and the gate electrode of the second MOS transistor, and causing the pixel to perform an imaging operation. At this time, the first MOS transistor is turned ON, and a first voltage is applied to a second electrode of the second MOS transistor, so that the second MOS transistor is turned on.
When the S transistor is operated in a sub-threshold region equal to or less than a threshold value, and the pixel is reset, the first MOS transistor is turned off, and a second voltage is applied to a second electrode of the second MOS transistor. 2MO
A solid-state imaging device wherein a current larger than before applying the second voltage to the S transistor can flow. 18. The pixel according to claim 18, wherein the first electrode is the third MO.
18. The semiconductor device according to claim 14, further comprising a seventh MOS transistor connected to a second electrode of the S transistor, the second electrode connected to an output signal line, and a gate electrode connected to a row selection line. 20. The solid-state imaging device according to 19. An output signal of the pixel, wherein a DC voltage is applied to a first electrode, a gate electrode is connected to a second electrode of the third MOS transistor, and an output signal is output from a second electrode of the third MOS transistor. The sixth that amplifies
2. The semiconductor device according to claim 1, further comprising a MOS transistor.
The solid-state imaging device according to claim 4. 20. The pixel, wherein the first electrode is the sixth MO.
20. The solid-state imaging device according to claim 19, further comprising a seventh MOS transistor connected to a second electrode of the S transistor, the second electrode connected to an output signal line, and a gate electrode connected to a row selection line. . 21. The pixel, wherein one end of the pixel is connected to a second electrode of the third MOS transistor, and
21. The solid-state imaging device according to claim 19, further comprising a second capacitor that is reset via the third MOS transistor when a reset voltage is applied to a first electrode of the MOS transistor. 22. A DC voltage is applied to a first electrode of the third MOS transistor, and the pixel has a first electrode connected to a second electrode of the third MOS transistor, and a DC voltage connected to a second electrode. An eighth MOS transistor, one end of which is connected to a second electrode of the third MOS transistor, and a second electrode that is reset via the eighth MOS transistor when a reset voltage is applied to a gate electrode of the eighth MOS transistor. The solid-state imaging device according to claim 19, further comprising: a capacitor. 23. The solid-state imaging device according to claim 14, wherein said first MOS transistor is a depletion type MOS transistor. 24. The solid-state imaging device according to claim 14, wherein said first MOS transistor is a MOS transistor having a polarity opposite to that of said second MOS transistor. 25. In a solid-state imaging device having a plurality of pixels, each pixel includes a photodiode, a first MOS transistor having a second electrode connected to one electrode of the photodiode, and a first MOS transistor of the first MOS transistor. A second MOS transistor having an electrode connected to a second electrode; and a third MOS transistor having a gate electrode connected to a second electrode of the second MOS transistor. The first MOS transistor is turned on, and the second MOS transistor is turned on. By operating a transistor in a sub-threshold region equal to or less than a threshold to cause each of the pixels to perform an imaging operation, turning off the first MOS transistor, and then changing a voltage applied to a first electrode of the second MOS transistor, Of the sensitivity of each pixel by the threshold voltage of the second MOS transistor Solid-state image pickup device and detecting the variability. 26. The pixel, wherein the first electrode is the third MO.
26. The solid-state imaging device according to claim 25, further comprising a fifth MOS transistor connected to a second electrode of the S transistor, the second electrode connected to an output signal line, and a gate electrode connected to a row selection line. . 27. An output signal output from a second electrode of the third MOS transistor, the pixel having a first electrode connected to a DC voltage, a gate electrode connected to a second electrode of the third MOS transistor, The fourth that amplifies
3. A semiconductor device comprising a MOS transistor.
6. The solid-state imaging device according to 5. 28. The pixel according to claim 28, wherein the first electrode is the fourth MO.
28. The solid-state imaging device according to claim 27, further comprising a fifth MOS transistor connected to a second electrode of the S transistor, the second electrode connected to an output signal line, and a gate electrode connected to a row selection line. . 29. When the pixel has one end connected to a second electrode of the third MOS transistor and the other end connected to a DC voltage, and a reset voltage is applied to a first electrode of the third MOS transistor. 29. The solid-state imaging device according to claim 27, further comprising a capacitor reset via the third MOS transistor. 30. The solid-state imaging device according to claim 29, wherein the third MOS transistor is a MOS transistor having a polarity opposite to that of the first and second MOS transistors. 31. A first electrode of the third MOS transistor is connected to a DC voltage, and the pixel has a first electrode connected to a second electrode of the third MOS transistor, and a DC voltage connected to a second electrode. One end is connected to the second electrode of the third MOS transistor, and the other end is connected to the DC voltage.
29. The solid-state imaging device according to claim 27, further comprising: a capacitor that is reset via the sixth MOS transistor when a reset voltage is applied to a gate electrode of the S transistor. 32. The third and sixth MOS transistors have an M polarity opposite to that of the first and second MOS transistors.
The solid-state imaging device according to claim 31, wherein the solid-state imaging device is an OS transistor.