JP2001230399A - Solid-state image sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image sensor of which the output from a pixel is high and that can obtain a high quality imaging signal. SOLUTION: When light is incident on a phototransistor PTr, a current that matches an amount of incident light based on the phototransistor PTr by the base-emitter PN junction. an emitter current in which this base current is amplified flows as a photocurrent and a logarithmically converted voltage appears at a gate of a MOS transistor T1 that performs an operation in a sub-threshold region. Subsequently, when an integrated voltage appears at a connection node (a) in accordance with this logarithmically converted voltage and a MOS T6 is set to ON, and output current that corresponds the voltage of this connection node (a) is outputted to an output signal line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device in which pixels are two-dimensionally arranged.

[0002]

2. Description of the Related Art Pixels each including a photoelectric conversion element (photosensitive element) such as a photodiode and a means for extracting photocharges generated by the photoelectric conversion element to an output signal line are arranged in a matrix. Two-dimensional solid-state imaging devices are used for various purposes. By the way, such a solid-state imaging device is roughly classified into a CCD type and a MOS type by means for reading out (extracting) photocharges generated by a photoelectric conversion element. C
The CD type is designed to transfer a photocharge while accumulating it in a potential well, and has a drawback that a dynamic range is narrow. On the other hand, in the MOS type, the charge accumulated in the pn junction capacitance of the photodiode is directly read out through a MOS transistor.

Here, one of the conventional MOS-type solid-state imaging devices is described.
A configuration per pixel is shown in FIG. 19 and described. In the figure, PD is a photodiode whose cathode is M
The gate of the OS transistor T1 and the MOS transistor T
2 sources. MOS transistor T1
Is connected to the drain of the MOS transistor T3, and the source of the MOS transistor T3 is connected to the output signal line Vou.
Connected to t. The DC voltage VPD is applied to the drain of the MOS transistor T1 and the drain of the MOS transistor T2, and the DC voltage VPS is applied to the anode of the photodiode.

When light enters the photodiode PD,
Photocharge is generated, and the charge is stored in the gate of the MOS transistor T1. Here, the MOS transistor T3
When the MOS transistor T3 is turned on by applying a pulse signal φV to the gate of the MOS transistor T1, a current proportional to the charge of the gate of the MOS transistor T1 is led out to the output signal line through the MOS transistors T1 and T3. In this way, an output current proportional to the amount of incident light can be read. After the signal is read, the MOS transistor T3 is turned off and the MO
By turning on the S transistor T2, the gate voltage of the MOS transistor T1 can be initialized.

[0005]

As described above, the conventional M
The OS-type solid-state imaging device reads out the photocharge generated by the photodiode in each pixel and stored in the gate of the MOS transistor as it is, so the dynamic range is narrow, and therefore, the exposure amount must be precisely controlled. In addition, even if the exposure amount is precisely controlled, dark portions are blackened and bright portions are saturated. or,
Since the amplification factor of the photoelectric conversion by the photodiode to the electric signal is small, the output signal is at a low level, so that the S / N ratio is poor and a high-quality image signal as a whole cannot be obtained.

Accordingly, the present applicant has proposed a photodiode capable of generating a photocurrent corresponding to the amount of incident light, a MOS transistor for inputting the photocurrent, and a bias for biasing the MOS transistor to a state where a subthreshold current can flow. And a means for converting the photocurrent into a logarithmic value.
Reference). With such a solid-state imaging device, the dynamic range can be expanded. However, such a solid-state imaging device has a problem that the characteristics and the S / N ratio in the case of low luminance are not sufficient.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a solid-state imaging device which has a large output from a pixel and can obtain a high-quality imaging signal. Another object of the present invention is to provide a solid-state imaging device having a wide dynamic range.

[0008]

According to a first aspect of the present invention, there is provided a solid-state imaging device, comprising: a photoelectric conversion unit having a photosensitive element for generating an electric signal corresponding to an amount of incident light; A solid-state imaging device having a deriving path for deriving an output signal of a conversion unit to an output signal line, wherein the photosensitive element amplifies a photocurrent corresponding to a light amount incident on a control electrode to generate the electric signal. A first photo-transistor, wherein the photoelectric conversion unit linearly converts the electric signal generated by the photo-transistor;
It is characterized in that the state can be switched between a state and a second state in which natural logarithmic conversion is performed.

According to the solid-state imaging device having such a configuration,
An output signal can be obtained by logarithmically converting an electric signal amplified by a phototransistor having a larger amplification factor with respect to the incident light amount than a photodiode. Therefore, while the dynamic range of the solid-state imaging device is widened,
An output signal having a large signal level is obtained.

Further, the dynamic range can be changed according to the luminance state of the subject and the environment at the time of imaging.
For example, a photocharge generated by a phototransistor is
When conversion is performed using a transistor, when this MOS transistor is operated in a sub-threshold region equal to or smaller than a threshold value, a logarithmic conversion state (second state) is obtained, and a large dynamic range can be obtained. However, when capturing an image of a moving subject with low luminance, an afterimage becomes conspicuous in the logarithmic conversion operation.

In the logarithmic conversion operation, the electric signal generated by the phototransistor is logarithmically converted in real time and output from the MOS transistor when the MOS transistor is in the ON state. This is because the electric charge accumulated in the phototransistor connected to the device is not discharged, and the previous information remains. This is particularly noticeable when the brightness is low.
In the logarithmic conversion, since the conversion output is generally small, S /
Poor N ratio (signal / noise ratio).

On the other hand, when the MOS transistor is
In the linear conversion state (first state) in the F state, although the dynamic range is narrow, a large signal output from the photoelectric conversion unit is obtained, so that the S / N ratio is good. Therefore,
The photoelectric conversion unit is switched to the second state (logarithmic conversion) and used for imaging an object over a wide range from low luminance to high luminance, and the photoelectric conversion unit is used for imaging a low-luminance object and an object having a narrow luminance range. It is preferable to switch the means to the first state (linear conversion).

According to a second aspect of the present invention, there is provided a solid-state imaging device, comprising: a photoelectric conversion unit having a photosensitive element for generating an electric signal according to the amount of incident light; and a lead-out path for leading an output signal of the photoelectric conversion unit to an output signal line. In a two-dimensional solid-state imaging device having pixels having a matrix arranged in a matrix,
A phototransistor that amplifies a photocurrent according to the amount of light incident on the control electrode to generate the electric signal, and the photoelectric conversion unit linearly converts the electric signal generated by the phototransistor; It can be switched between a first state and a second state in which natural logarithmic conversion is performed.

In such a solid-state image pickup device, since it is possible to switch between the first state in which the electric signal is converted linearly and the second state in which the electric signal is converted logarithmically, the luminance state of the subject and the image pickup A digital camera or a video camera whose dynamic range can be changed according to a time environment can be realized.

Further, as set forth in claim 3, reset means for initializing the photoelectric conversion means after the photoelectric conversion means operates in the first state and outputs an electric signal to the output signal line. May be provided.

According to such a configuration, for example, when photocharges generated in a phototransistor are converted by using a MOS transistor, when the image is taken in a linear conversion state in which the MOS transistor is in an OFF state, the phototransistor is not used. By resetting the electric charge stored in the MOS transistor and the reset means by the reset unit, the phototransistor and the MOS transistor can be initialized.

According to a fourth aspect of the present invention, each of the pixels has an amplifying transistor for amplifying an output signal of the photoelectric conversion means, and the output signal of the amplifying transistor is derived. When the signal is output to the output signal line via the path, the signal from each pixel is read in a large and stable state.

Further, according to a fifth aspect of the present invention, in the solid-state imaging device according to the fourth aspect, the total number of the output signal lines connected to the output signal line is smaller than the total number of pixels. It may be a solid-state imaging device. By providing the load resistance or the constant current source, a current signal output from each pixel can be read as a voltage signal. In such a solid-state imaging device, the load resistor or the constant current source is connected to the first signal line connected to the output signal line.
The transistor may have an electrode, a second electrode connected to a DC voltage, and a control electrode connected to the DC voltage.

The output path may include a switch for sequentially selecting a predetermined pixel from all the pixels and outputting an amplified signal from the selected pixel to an output signal line. Thus, signals output from the pixels to the output signal line can be sequentially read and output as serial data.

According to a sixth aspect of the present invention, in the solid-state imaging device according to any one of the first to fifth aspects, the photoelectric conversion means includes a control electrode in a floating state and a first electrode. DC voltage is applied to the electrodes,
A phototransistor for amplifying a photocurrent generated by the amount of light incident on the control electrode; a first electrode, a second electrode, and a control electrode, wherein the first electrode and the control electrode are connected to the second electrode of the phototransistor; A first transistor into which an output current from the phototransistor flows,
A second electrode including a first electrode, a second electrode, and a control electrode, wherein a DC voltage is applied to the first electrode, the control electrode is connected to a control electrode of the first transistor, and an electric signal is output from the second electrode. And a transistor, wherein the first transistor is operated in a sub-threshold region to convert an output current flowing from the phototransistor into a natural logarithm.

According to a seventh aspect of the present invention, in the solid-state imaging device according to any one of the first to fifth aspects, a constant current source is provided, and A DC voltage is applied to the electrodes, and the phototransistor amplifies a photocurrent generated by the amount of light incident on the control electrode; and a first electrode, a second electrode, and a control electrode. A first transistor to which a first electrode and a control electrode are connected and into which an output current from the phototransistor flows;
A second transistor having an electrode and a control electrode, wherein a DC voltage is applied to the first electrode, the control electrode is connected to a control electrode of the first transistor, and an electric signal is output from the second electrode; And a first switch electrically connected and disconnected between the control electrode of the phototransistor and the constant current source while being connected between the control electrode and the constant current source. When performing the operation, the first switch is turned off and the first transistor is operated in a sub-threshold region, so that the output current flowing from the phototransistor is converted into a natural logarithm. When the variation in sensitivity is detected, the first switch is turned on.

According to the solid-state imaging device having such a configuration,
The control electrode of the phototransistor provided for each pixel,
By flowing a constant current that is sufficiently larger than the constant current source and reading the output signal at this time, it is possible to detect variations in the sensitivity of each pixel due to the difference in the amplification factor of the phototransistor.

Further, the solid-state imaging device repeatedly performs an imaging operation and a reset operation as in an imaging device for a video movie, for example, to capture a moving image even when light is incident on the photoelectric conversion element. By turning on the first switch connected to the constant current source, the phototransistor can be made less susceptible to light incident on the photoelectric conversion element, and the sensitivity variation of each pixel can be detected quickly. Can be. Therefore, in order to obtain correction data for correcting the output of each pixel at the time of imaging the subject, it is not necessary to irradiate uniform light as in the related art, and it is obtained when irradiating uniform light. There is no need to keep recording correction data.

8. The solid-state imaging device according to claim 6, wherein said photoelectric conversion means is provided between a connection node between a first electrode and a control electrode of said first transistor and a control electrode of said second transistor. The second switch in each of the photoelectric conversion units provided in the solid-state imaging device has a second switch connected thereto, and operates at the same timing, so that an electric signal imaged at the same time is generated by the second switch. It may be output from the photoelectric conversion means.

According to the solid-state imaging device having such a configuration,
By turning on the second switch at the same timing, an electric signal for the same time can be sampled and held on the control electrode of the second transistor. As described above, since an electric signal serving as video information at the same time can be obtained, even when the operation of sequentially outputting each pixel is performed and the output signal is output as serial data, the video information of this output signal is output. Are video information at the same time, so that a time error can be eliminated.

The solid-state imaging device according to any one of claims 1 to 7, further comprising: a capacitor for integrating an electric signal output from the photoelectric conversion means, wherein the signal integrated by the capacitor is supplied to the output path. Alternatively, the signal may be led to the output signal line via the output signal line.

According to the solid-state imaging device having such a configuration,
By using the signal integrated by the capacitor as the output signal, the fluctuation component of the light source and high-frequency noise are absorbed and removed by the capacitor.

According to an eighth aspect of the present invention, in the two-dimensional solid-state imaging device having pixels arranged in a matrix, each pixel has a base electrode in a floating state and a direct current applied to a first electrode. A phototransistor to which a voltage is applied and amplifies a photocurrent generated by the amount of light incident on a base electrode; a first MOS transistor having a first electrode and a gate electrode connected to a second electrode of the phototransistor; A second MOS transistor having a gate electrode connected to the gate electrode of the transistor, and operating the first MOS transistor in a sub-threshold region equal to or less than a threshold value, so that an electric signal output from the phototransistor is expressed in a natural logarithmic manner. And output from the second electrode of the second MOS transistor. .

According to a ninth aspect of the present invention, in the two-dimensional solid-state imaging device in which pixels are arranged in a matrix, the solid-state imaging device includes a constant current source for supplying a constant current to each pixel. A phototransistor for applying a DC voltage to the first electrode and amplifying a photocurrent generated by the amount of light incident on the base electrode;
A first MOS transistor having a first electrode and a gate electrode connected to the electrode, a second MOS transistor having a gate electrode connected to the gate electrode of the first MOS transistor,
A third MOS transistor having a first electrode connected to the constant current source and a second electrode connected to a base electrode of the phototransistor; and when performing an imaging operation, turning off the third MOS transistor. And operating the first MOS transistor in a sub-threshold region equal to or less than a threshold value, whereby an electrical signal output from the phototransistor is converted into a natural logarithm and output from the second electrode of the second MOS transistor. When detecting variation in the sensitivity of the pixel, the third MOS transistor is turned on.

[0030] In the solid-state imaging device according to claim 8 or 9, as described in claim 10, a first electrode is connected to the gate electrode of the first MOS transistor, and a second electrode is connected to the pixel. A fourth MOS transistor may be provided which is connected to a DC voltage and releases the charge accumulated in the gate electrode of the first MOS transistor by switching the level of the voltage input to the gate electrode. According to such a configuration,
By changing the potential difference between the first electrode and the second electrode of the first transistor, the operation of the photoelectric conversion means can be changed to a first state in which an electric signal output from the phototransistor is linearly converted and output. The dynamic state can be changed by switching to the second state in which the electrical signal output from the phototransistor is converted into a natural logarithm and output.

When the pixel operates in the first state, the potential of the second electrode of the first MOS transistor and the potential of the first electrode of the phototransistor are brought close to each other to bring the first MOS transistor into an inactive state. In addition, after outputting the electric signal, the level of the voltage input to the gate electrode of the fourth MOS transistor is switched to make the fourth MOS transistor conductive, and at least the first MOS transistor of the first MOS transistor is turned on.
The charge stored in the electrode and the gate electrode is released to reset. When the pixel operates in the second state, the first MOS transistor operates in a sub-threshold region equal to or less than a threshold.

[0032] In the solid-state imaging device according to claim 8 or 9, as described in claim 11, a first electrode is connected to a connection node between a first electrode and a gate electrode of the first MOS transistor. And a fifth MOS transistor having a second electrode connected to the gate electrode of the second MOS transistor.
According to the solid-state imaging device having such a configuration, the fifth MOS transistor in each pixel provided in the solid-state imaging device operates at the same timing, so that an electric signal imaged at the same time is output to each of the pixels. Output from

Further, in the solid-state imaging device according to any one of claims 8 to 11, as described in claim 12, the pixel has a first electrode connected to a second electrode of the second MOS transistor.
By providing a sixth MOS transistor connected to the electrode, the second electrode connected to the output signal line, and the gate electrode connected to the row selection line, the sixth MOS transistor can be used as a row selection switch.

According to a thirteenth aspect of the present invention, in the solid-state imaging device according to any one of the eighth to tenth aspects, the pixel has a first electrode connected to a DC voltage;
A gate electrode connected to the second electrode of the second MOS transistor, a seventh MOS transistor for amplifying an output signal output from the second electrode of the second MOS transistor, and a first electrode connected to the second electrode of the seventh MOS transistor. A sixth MOS transistor connected to the electrode, the second electrode connected to the output signal line, and the gate electrode connected to the row selection line.

According to a thirteenth aspect of the present invention, in the solid-state imaging device, the pixel includes the second MOS transistor.
One end is connected to the second electrode of the transistor, the other end is connected to a signal line to which the second electrode of the first MOS transistor is connected, and a reset voltage is applied to the first electrode of the second MOS transistor. The second MO
A capacitor that is reset via an S transistor may be provided. With such a configuration, the signal output from the pixel becomes a signal once integrated by the capacitor, so that the fluctuation component of the light source and high-frequency noise are absorbed and removed by the capacitor. Further, the second MOS
By applying a reset voltage to the first electrode of the transistor, the charge in the capacitor is released through the second MOS transistor and reset.

In the pixel, a first electrode of the second MOS transistor is connected to a DC voltage, and a first electrode is connected to a second electrode of the second MOS transistor. An eighth MOS transistor having a DC voltage connected to a second electrode;
One end is connected to the second electrode of the MOS transistor, the other end is connected to a signal line to which the second electrode of the first MOS transistor is connected, and a reset voltage is applied to the gate electrode of the eighth MOS transistor. And a capacitor reset via the eighth MOS transistor. With such a configuration, the signal output from the pixel becomes a signal once integrated by the capacitor, so that the fluctuation component of the light source and high-frequency noise are absorbed and removed by the capacitor. Further, by applying a reset voltage to the gate electrode of the eighth MOS transistor, the charge in the capacitor is released through the eighth MOS transistor and reset.

According to a sixteenth aspect of the present invention, there is provided a solid-state imaging device according to any one of the eighth to fifteenth aspects, wherein the pixel is connected to the pixel via the output signal line or a constant current source. Characterized in that the MOS transistor is provided.

The solid-state imaging device according to claim 17 is
The solid-state imaging device according to any one of claims 8 to 16, wherein the MOS transistors are all N-channel MOS transistors, and the phototransistors are npn-type phototransistors.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Example of Pixel Configuration> FIG. 1 schematically shows a partial configuration of a two-dimensional MOS solid-state imaging device according to another embodiment of the present invention. In FIG.
11 to Gmn indicate pixels arranged in a matrix (matrix arrangement). Reference numeral 2 denotes a vertical scanning circuit, and a row (line) 4
-1, 4-2,..., 4-n are sequentially scanned. Three
Denotes a horizontal scanning circuit, which outputs output signal lines 6-1 and 6 from a pixel.
The photoelectric conversion signals derived in -2,..., 6-m are sequentially read in the horizontal direction for each pixel. 5 is a power supply line. For each pixel, the lines 4-1 4-2,.
4-n, output signal lines 6-1, 6-2..., 6-m, power supply line 5, and other lines (for example, a clock line and a bias supply line) are also connected. 1
In these figures, these are omitted and shown in each embodiment after FIG.

The output signal lines 6-1, 6-2,..., 6
As shown in the figure, a set of N-channel MOS transistors Q1 and Q2 is provided for each m. Output signal line 6-1
The gate of the MOS transistor Q1 is connected to the DC voltage line 11, the drain is connected to the output signal line 6-1, and the source is connected to the line 12 of the DC voltage VPS '. On the other hand, MOS transistor Q2
Is connected to the output signal line 6-1, the source is connected to the final signal line 7, and the gate is connected to the horizontal scanning circuit 3.

As described later, the pixels G11 to Gmn have
An N-channel MOS transistor Ta for outputting a signal based on photocharges generated in those pixels is provided. FIG. 2A shows the connection between the MOS transistor Ta and the MOS transistor Q1. This MO
The S transistor Ta is, in the first and second embodiments,
The seventh MOS transistor T7 corresponds to the second MOS transistor T2 in the third to fifth embodiments. Here, the relationship between the DC voltage VPS 'connected to the source of the MOS transistor Q1 and the DC voltage VPD' connected to the drain of the MOS transistor Ta is VPD '>VPS', and the DC voltage VPS 'is, for example, ground. Voltage (ground). In this circuit configuration, a signal is input to the gate of the upper MOS transistor Ta, and the lower MOS transistor Q1
A DC voltage DC is always applied to the gate of. Therefore, the lower-stage MOS transistor Q1 is equivalent to a resistor or a constant current source, and the circuit in FIG. 2A is a source follower-type amplifier circuit. In this case, the MOS transistor Ta
It can be considered that what is amplified and output from is a current.

The MOS transistor Q2 is connected to the horizontal scanning circuit 3
And is operated as a switch element. still,
As will be described later, an N-channel sixth MOS transistor T6 for switching is also provided in the pixel of each of the embodiments shown in FIG. If the sixth MOS transistor T6 is also included, the circuit of FIG. 2A is exactly as shown in FIG. 2B. That is, the MOS transistor T6 is inserted between the MOS transistor Q1 and the MOS transistor Ta. Here, the MOS transistor T6 selects a row, and the transistor Q2 selects a column. The configuration shown in FIGS. 1 and 2 is a configuration common to the first to fifth embodiments described below.

With the configuration as shown in FIG. 2, a large signal gain can be output. Therefore, when the pixel converts the photocurrent generated from the photosensitive element in a natural logarithmic manner to expand the dynamic range, the output signal is small as it is, but is amplified to a sufficiently large signal by the present amplifier circuit. Therefore, processing in a subsequent signal processing circuit (not shown) is facilitated. Also, without providing the transistor Q1 constituting the load resistance part of the amplifier circuit in the pixel,
By providing the output signal lines 6-1, 6-2,..., 6 -m connected to a plurality of pixels arranged in the column direction, the number of load resistances or constant current sources can be reduced, and The area occupied by the amplifier circuit on the chip can be reduced.

<First Embodiment> A first embodiment applied to each pixel of the first example of the pixel configuration shown in FIG. 1 will be described with reference to the drawings. FIG. 3 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment.

In FIG. 3, an npn-type phototransistor PTr forms a photosensitive portion (photoelectric conversion portion). The emitter of the phototransistor PTr is connected to the drain and gate of the first MOS transistor T1 and the gate of the second MOS transistor T2. The source of the MOS transistor T2 is connected to the gate of the seventh MOS transistor T7 and the drain of the eighth MOS transistor T8, and the source of the MOS transistor T7 is connected to the sixth MOS transistor T8.
It is connected to the drain of transistor T6. MOS
The source of the transistor T6 is connected to the output signal line 6 (the output signal line 6 corresponds to 6-1 to 6-m in FIG. 1). Incidentally, the MOS transistor T
1, T2, T6 to T8 are N-channel MOS transistors whose back gates are grounded.

A DC voltage VPD is applied to the collector of the phototransistor PTr and the drains of the MOS transistors T2 and T7. On the other hand, the DC voltage VPS is applied to the source of the MOS transistor T1, and the DC voltage VPS is also applied to the source of the MOS transistor T2 via the capacitor C. MO
The DC voltage VRG is applied to the source of the S transistor T8. The signal φ is applied to the gate of the MOS transistor T8.
VRS is input. The signal φV is input to the gate of the MOS transistor T6. MOS transistor T
1 and T2 are both biased to operate in the sub-threshold region.

The base of the phototransistor PTr is in a floating state where no voltage is applied. In the phototransistor PTr, a base current is generated according to the amount of light incident on the PN junction between the base and the emitter, and the emitter current obtained by amplifying the base current is referred to as an electric signal (hereinafter, referred to as “photocurrent”). ) To the drain of the MOS transistor T1. The phototransistor PTr amplifies the base current to an emitter current whose magnitude is approximately 100 times larger, so that a larger photocurrent can be obtained as compared to a photodiode.

When light enters the phototransistor PTr, a photocurrent is generated, and a voltage having a value obtained by natural logarithmically converting the photocurrent is generated at the gates of the MOS transistors T1 and T2 due to the subthreshold characteristic of the MOS transistor. With this voltage, a current flows through the MOS transistor T2, and a charge equivalent to a value obtained by natural logarithmically converting the integrated value of the photocurrent is accumulated in the capacitor C. That is, a voltage proportional to a value obtained by natural logarithmically converting the integrated value of the photocurrent is generated at the connection node a between the capacitor C and the source of the MOS transistor T2. However, at this time, the MOS transistors T6 and T8 are OFF.
State.

Next, a pulse signal φV is applied to the gate of the MOS transistor T6 to turn on the MOS transistor T6.
When N is set, a current proportional to the voltage applied to the gate of the MOS transistor T7 is led out to the output signal line 6 through the MOS transistors T6 and T7. Since the voltage applied to the gate of the MOS transistor T7 is the voltage applied to the connection node a, the current led out to the output signal line 6 is a value obtained by natural logarithmically converting the integrated value of the photocurrent.

In this manner, a signal (output current) proportional to the logarithmic value of the incident light amount can be read. After the signal is read, the MOS transistor T6 is turned off, and the MOS transistor T8 is turned on by applying a high-level signal φVRS to the gate of the MOS transistor T8.
To initialize the potentials of the capacitor C and the connection node a to prepare for the next imaging operation.

As shown in FIG. 4, capacitors C and M
Between the OS transistor T8, a MOS transistor T9 having a drain connected to the capacitor C and a source connected to the drain of the MOS transistor T8, and a capacitor C2 having one end connected to the source of the MOS transistor T9 may be provided. good. In this case, the MOS transistor T9 is turned on by the signal φV1 applied to the gate of the MOS transistor T9, and the charge of the capacitor C is
After the transfer to 2, the next integration operation by the capacitor C can be started while the signal is read out by the MOS transistor T6 by turning off the MOS transistor T9. Therefore, integration can be performed for all pixels at the same time.

<Second Embodiment> A second embodiment applied to each pixel of the first example of the pixel configuration shown in FIG. 1 will be described with reference to the drawings. FIG. 5 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 5, in this embodiment, the MO
By applying the signal φD to the drain of the S transistor T2, the voltages of the capacitor C and the connection node a are initialized, thereby eliminating the MOS transistor T8. Other configurations are the same as those of the first embodiment (FIG. 3). Note that during the high level period of the signal φD, integration is performed by the capacitor C.
2 and the voltage of the capacitor C and the gate of the MOS transistor T7 are initialized to substantially the low level voltage of the signal φD (reset). In the present embodiment, the MOS
Since the transistor T8 can be omitted, the configuration is simplified.

In this embodiment, first, the signal φD is set to a high level (for example, a voltage substantially equal to the DC voltage VPD), and a charge equivalent to a value obtained by natural-logarithmically converting the integrated value of the photocurrent is stored in the capacitor C. accumulate. Then, the MOS transistor T6 is turned on at a predetermined timing, and the MOS transistor T6 is turned on.
The current proportional to the voltage applied to the gate of the transistor T7 is applied to the output signal line 6 through the MOS transistors T6 and T7.
Is derived. After that, the MOS transistor T6 is turned off.
At the same time, when the signal φD is set to a low level (a voltage lower than the DC voltage VPS), the charge of the capacitor C is discharged to the signal line of the signal φD through the MOS transistor T2, whereby the voltages of the capacitor C and the connection node a are initialized. Be transformed into

<Third Embodiment> A third embodiment applied to each pixel in the first example of the pixel configuration shown in FIG. 1 will be described with reference to the drawings. FIG. 6 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 6, in this embodiment, the MO
DC voltage VPD is applied to the drain of S transistor T2, and capacitor C and MOS transistor T
7 is deleted. Then, the source of the MOS transistor T2 is connected to the drain of the MOS transistor T6. Other configurations are the same as those of the second embodiment (FIG. 5).

In the circuit having such a configuration, the gate voltage of the MOS transistor T2 is changed to the phototransistor PT.
By changing the photocurrent generated at r in a natural logarithmic manner, a drain current having a value proportional to the logarithm of the photocurrent flows through the MOS transistor T2.
When the signal .phi.V is applied to the gate of the MOS transistor T6 to turn on the MOS transistor T6, a drain current having a value which is logarithmically proportional to the photocurrent is generated by the MOS transistor T6.
2, and output to the output signal line 6 through T6. At this time, the MOS transistor T2 and the MOS transistor Q
1 (FIG. 2) and the drain voltage of the MOS transistor Q1 determined by the current flowing therethrough and the current flowing therethrough appear on the output signal line 6 as a signal. After the signal is read out in this manner, the MOS transistor T6 is turned off.

In this embodiment, since the integration of the optical signal with the capacitor C is not performed as in the second embodiment, the integration time is not required, and the reset of the capacitor C is not required. As a result, the signal processing can be speeded up accordingly. Further, in the present embodiment, as compared with the second embodiment, since the capacitor C and the MOS transistor T7 can be omitted, the configuration is further simplified and the pixel size can be reduced.

<Fourth Embodiment> A fourth embodiment applied to each pixel of the first example of the pixel configuration shown in FIG. 1 will be described with reference to the drawings. FIG. 7 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 7, in this embodiment, the MO
The drain is connected to the connection node between the drain and the gate of the S-transistor T1, and the fifth MOS transistor T5 whose source is connected to the gate of the MOS transistor T2 is newly provided. MOS
Signal φS is input to the gate of transistor T5. Other configurations are the same as those of the third embodiment (FIG. 6). The MOS transistor T5 is an N-channel MOS transistor and has a back gate grounded, like the MOS transistor T1.

In the circuit having such a configuration, first, the signal φS is set to the low level, and the MOS provided in the pixels G11 to Gmn (FIG. 1) in the solid-state imaging device having the configuration as shown in FIG.
All the transistors T5 are turned off. At this time, the phototransistor PTr generates a photocurrent corresponding to the amount of incident light, and the gate voltage of the MOS transistor T1 becomes a voltage corresponding to a value obtained by logarithmically converting the photocurrent. Next, at the same timing, M in the pixels G11 to Gmn
The pulse signal φS is applied to the gate of the OS transistor T5. The MOS transistor T5 is turned on when the pulse signal φS is at a high level. At this time, a voltage corresponding to a value obtained by logarithmically converting the photocurrent appearing in the MOS transistor T1 is sampled and held at the gate of the MOS transistor T2. That is, the video information captured at the same time is sampled and held by the output side circuit of each pixel. When sampled and held at the gate of the MOS transistor T2 in this manner, the MOS transistor T5 is turned off.
It becomes F.

Then, the vertical scanning circuit 2 (FIG. 1) and the horizontal scanning circuit 3 (FIG. 1) apply the pulse signal φV to the gate of the MOS transistor T6 provided in the pixels G11 to Gmn.
Are sequentially applied, and the MOS transistor T6 is turned on, so that an output current obtained by logarithmically converting the photocurrent is output to the output signal line 6. At this time, in each pixel, when the MOS transistor T6 is turned on, a drain current proportional to a voltage obtained by logarithmically converting the photocurrent sampled and held at the gate of the MOS transistor T2 is output as an output current through the MOS transistors T2 and T6. It is led to the signal line 6. Then, the on-state resistance of the MOS transistor T2 and the MOS transistor Q1 (FIG. 2) and the drain voltage of the MOS transistor Q1 determined by the current flowing through them appear on the output signal line 6 as a signal. After the signal is read out in this manner, the MOS transistor T6 is turned off.

As described above, in the present embodiment, after all the pixels in the solid-state imaging device perform the imaging operation at the same time, the vertical scanning circuit and the horizontal scanning circuit operate each pixel.
Each pixel sequentially outputs an output signal having video information at the time of imaging. Therefore, since the solid-state imaging device can output an output signal of video information at the same time as serial data, when reproducing such an output signal that becomes serial data, the video information may include a temporal error. Disappears.

<Fifth Embodiment> A fifth embodiment applied to each pixel of the first example of the pixel configuration shown in FIG. 1 will be described with reference to the drawings. FIG. 8 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 8, in this embodiment, the MO
The drain is connected to the connection node between the drain and gate of the S transistor T1 and the gate of the MOS transistor T2, and a fourth MOS transistor T4 having a source to which the DC voltage VPG2 is applied is newly provided. Signal φVRS2 is input to the gate of MOS transistor T4. Also, the MOS transistor T1
Is supplied with a signal φVPS. Other configurations are the same as those of the third embodiment (FIG. 6). The MOS transistor T4 has N
The back gate is grounded by the MOS transistor of the channel.

In the present embodiment, the case where the voltage of the signal φVPS is switched to change the bias of the MOS transistor T1 so that the output signal led out to the output signal line 6 is naturally logarithmically converted into the photocurrent is considered. , And a case of linear conversion. Note that the signal φ
VPS changes in a binary manner. The voltage for operating the MOS transistors T1 and T2 in the subthreshold region is set to a low level, and a voltage substantially equal to the DC voltage VPD is set to a high level. The operation in each of these cases will be described below.

(1) When the Photocurrent is Naturally Logarithmically Converted and Output First, the operation when the signal φVPS is at a low level and the MOS transistors T1 and T2 are biased to operate in the sub-threshold region. ,explain.
At this time, since the low-level signal φVRS2 is supplied to the gate of the MOS transistor T4, the MOS transistor T4 is turned off, which is equivalent to the fact that the MOS transistor T4 does not substantially exist.

When light enters the phototransistor PTr, a photocurrent is generated, and a voltage having a value obtained by natural logarithmically converting the photocurrent is generated at the gates of the MOS transistors T1 and T2 due to the subthreshold characteristic of the MOS transistor. With this voltage, the MOS transistor T2
A drain current equivalent to a value obtained by natural logarithmically converting the photocurrent tends to flow. However, at this time, the MOS transistor T6 is in the OFF state.

Next, a pulse signal φV is applied to the gate of the MOS transistor T6 to turn on the MOS transistor T6.
N, the drain current proportional to the voltage applied to the gate of the MOS transistor T2 becomes
2, and is led to the output signal line 6 through T6. Therefore,
The current led out to the output signal line 6 is a value obtained by natural logarithmically converting the photocurrent. When a signal (output current) proportional to the logarithmic value of the incident light amount is read in this way, the MOS transistor T6 is turned off. When the output current is naturally logarithmically converted with respect to the incident light amount,
Signal φVRS2 always remains at the low level.

(2) When the Photocurrent is Linearly Converted and Output Next, the operation when the signal φVPS is set to the high level and the MOS transistor T1 is cut off will be described. At this time, a low-level signal φVRS2 is applied to the gate of the MOS transistor T4 to turn off the MOS transistor T4. In such a state, when light enters the phototransistor PTr, a photocurrent is generated. At this time, since a capacitor is formed between the back gate and the gate of the MOS transistor T1 and the phototransistor PTr, a charge due to a photocurrent is accumulated in the gate and the drain of the MOS transistor T1. Therefore,
The gate voltages of the MOS transistors T1 and T2 have a value proportional to a value obtained by integrating the photocurrent.

Next, a pulse signal φV is applied to the gate of the MOS transistor T6 to turn on the MOS transistor T6.
N, the drain current proportional to the voltage applied to the gate of the MOS transistor T2 becomes
2, and is led to the output signal line 6 through T6. Since the voltage applied to the gate of the MOS transistor T2 is a voltage proportional to the value obtained by integrating the photocurrent, the output current led out to the output signal line 6 is obtained by linearly converting the integrated value of the photocurrent. Value.

In this manner, a signal (output current) proportional to the amount of incident light can be read. After the signal is read, first, the MOS transistor T6 is turned off, and a high-level signal φVRS2 is applied to the gate of the MOS transistor T4.
Is turned on to initialize the phototransistor PTr, the drain voltage of the MOS transistor T1, and the gate voltages of the MOS transistors T1 and T2.

As described above, in the present embodiment, it is possible to switch a plurality of output characteristics in the same pixel by a simple potential operation. When switching from a state in which the signal is logarithmically converted and output to a state in which the signal is linearly converted and output is performed, first, the output is switched by adjusting the potential of φVPS2, and then the MOS transistor T4 is used to reset the MOS transistor T1 and the like. It is preferred to do so. On the other hand, when switching from a state in which the signal is linearly converted and output to a state in which the signal is logarithmically converted and output, it is not particularly necessary to reset the MOS transistor T1 and the like by the MOS transistor T4. This is because carriers accumulated in the MOS transistor T1 are erased by carriers of the opposite polarity due to the fact that the MOS transistor T1 is not in a completely OFF state.

In this embodiment, as in the first or second embodiment, a capacitor C (see FIG. 3 or FIG. 5) having one end connected to the source of the MOS transistor T2,
And a MOS transistor T7 whose gate is connected to the source of the MOS transistor T2 and whose source is connected to the drain of the MOS transistor T6 (FIG. 3 or FIG. 5).
) And an integration circuit on the output side.

At this time, when the output current is output by the logarithmic conversion operation, the MOS transistor T8 (see FIG. 3)
Alternatively, the connection node a and the capacitor C are reset by the MOS transistor T2 (see FIG. 5). When the output current is output by the linear conversion operation, first, M
The MOS transistor T1 is generated by the OS transistor T4.
After resetting the MOS transistor T8
(See FIG. 3) or MOS transistor T2 (see FIG. 5)
Resets the connection node a and the capacitor C.

In this embodiment, as in the fourth embodiment, a MOS transistor in which the source is connected to the connection node between the gate and the drain of the MOS transistor T1 and the drain is connected to the gate of the MOS transistor T2.
A transistor T5 (see FIG. 7) may be provided. At this time, a linear conversion operation is performed, and the MOS transistor T
When the reset of the MOS transistor T1 and the like by 4 is performed, the MOS transistor T5 is turned on. Then, when the reset of the MOS transistor T1 and the like is completed, the MOS transistor T5 is turned off to prepare for the next imaging operation. The drain of the MOS transistor T4 is the source of the MOS transistor T5,
It may be connected to any of the drains.

<Second Example of Pixel Configuration> FIG. 9 schematically shows a partial configuration of a two-dimensional MOS solid-state imaging device according to an embodiment of the present invention. The two-dimensional MOS shown in FIG.
In some configurations of the solid-state imaging device, elements and signal lines used for the same purpose are denoted by the same reference numerals,
Detailed description is omitted.

The solid-state imaging device in FIG. 9 is different from the solid-state imaging device in FIG. 1 in that constant current sources 9-1, 9-2,.
, 8-m, and constant current sources 9-1, 9-2,..., 9-m are provided with current supply lines 8-1, 8-2,. Supply lines 8-1, 8-2, ..., 8-
, G, G11 to G1n, G21 to G2n,.
A current is supplied to m1 to Gmn. .., 4-n and output signal lines 6-1 and 6 are provided for each pixel.
-2, -m, current supply lines 8-1, 8-2, ...
, 8-m, not only the power supply line 5 but also other lines (for example, a clock line and a bias supply line) are connected, but these are omitted in FIG.

The output signal lines 6-1, 6-2,.
As shown in the figure, a set of N-channel MOS transistors Q1 and Q2 is provided for each m. Output signal line 6-1
The gate of the MOS transistor Q1 is connected to the DC voltage line 11, the drain is connected to the output signal line 6-1, and the source is connected to the line 12 of the DC voltage VPS '. On the other hand, MOS transistor Q2
Is connected to the output signal line 6-1, the source is connected to the final signal line 7, and the gate is connected to the horizontal scanning circuit 3.

As will be described later, the pixels G11 to Gmn have
An N-channel MOS transistor Ta for outputting a signal based on photocharges generated in those pixels is provided. The connection relationship between the MOS transistor Ta and the MOS transistor Q1 is the same as in the case of FIG.
The circuit shown in FIG. 2A is a source follower-type amplifier circuit. This MOS transistor Ta has a sixth
In the embodiment, the seventh MOS transistor T7 has the seventh MOS transistor T7.
In the ninth to ninth embodiments, this corresponds to the second MOS transistor T2.

The MOS transistor Q2 is connected to the horizontal scanning circuit 3
And is operated as a switch element. still,
As described later, an N-channel sixth MOS transistor T6 for switching is also provided in the pixel of each of the embodiments shown in FIG. 10 and thereafter. If this MOS transistor T6 is also included, the circuit of FIG. 2A is exactly as shown in FIG. 2B. That is, the MOS transistor T6 is inserted between the MOS transistor Q1 and the MOS transistor Ta. Here, the MOS transistor T6 selects a row, and the MOS transistor Q2 selects a column. The configuration shown in FIGS. 9 and 2 is a configuration common to the sixth to ninth embodiments described below.

With the configuration shown in FIG. 2, a large signal gain can be output. Therefore, when the pixel converts the photocurrent generated from the photosensitive element in a natural logarithmic manner to expand the dynamic range, the output signal is small as it is, but is amplified to a sufficiently large signal by the present amplifier circuit. Therefore, processing in a subsequent signal processing circuit (not shown) is facilitated. Further, the output signal lines 6-1, 6-2,... To which a plurality of pixels arranged in the column direction are connected without providing the MOS transistor Q1 constituting the load resistance portion of the amplifier circuit in the pixel. The provision of each 6-m can reduce the number of load resistances or constant current sources, and reduce the area occupied by the amplifier circuit on the semiconductor chip.

<Sixth Embodiment> A sixth embodiment applied to each pixel of the second example of the pixel configuration shown in FIG. 9 will be described with reference to the drawings. FIG. 10 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 10, in the present embodiment, a source is connected to the base of the phototransistor PTr, and a constant current source 9 (this constant current source 9
1, 9-2,..., 9-m) and current supply lines 8 (the current supply lines 8 are 8-1, 8-2,.
, Corresponding to 8-m) is newly provided with a third MOS transistor T3 to which a drain is connected. The signal φSW is input to the gate of the MOS transistor T3. Other configurations are the same as those of the first embodiment (FIG. 3). The MOS transistor T3
Is an N-channel MO, like the MOS transistor T1.
The back gate is grounded in the S transistor.

In such a configuration, when the pixel performs an imaging operation, the base of the phototransistor PTr is brought into a floating state by turning off the MOS transistor T3 by setting the signal φSW to low level.
When detecting the variation in sensitivity of the pixel, the signal φSW
Is set to a high level to turn on the MOS transistor T3.
A constant current is applied to the base of r. Hereinafter, the imaging operation and the detection operation of the sensitivity variation will be described.

(1) Imaging operation First, a low-level signal φSW is applied to the MOS transistor T
By applying the voltage to the gate of the MOS transistor T3, the MOS transistor T3 is turned off, and the base of the phototransistor PTr is brought into a floating state. At this time, the phototransistor PTr and the MOS transistors T1, T2, T6 to T
8 and the capacitor C perform the same operation as in the first embodiment, so that the logarithmically converted output current is output to the output signal line 6.
Is output to

That is, when light is incident on the phototransistor PTr, a photocurrent is generated, and a voltage having a value obtained by natural logarithmically converting the photocurrent is generated at the gates of the MOS transistors T1 and T2 due to the subthreshold characteristic of the MOS transistor. I do. Due to this voltage, an electric charge equivalent to a value obtained by natural logarithmically converting the integrated value of the photocurrent is accumulated in the capacitor C. Then, by applying a pulse signal φV to the gate of the MOS transistor T6 to turn on the MOS transistor T6, an output current equal to a value obtained by natural logarithmically converting the integrated value of the photocurrent is obtained.
6, and is led to the output signal line 6 through T7.

(2) Pixel Sensitivity Variation Detection The pixel sensitivity variation detection operation will be described with reference to FIG. When the pulse signal φV is applied to output an output current as described above, first, the pulse signal φVRS is applied to the gate of the MOS transistor T8 to reset the capacitor C and the connection node a. Next, a high level signal φSW is applied to the gate of the MOS transistor T3 to
The S transistor T3 is turned ON so that a constant current flows from the constant current source 9 to the base of the phototransistor PTr via the current supply line 8.

As described above, when a constant current flows from each pixel to the constant current source 9, the constant current source 9 makes the base current of the phototransistor PTr constant. At this time, the base current is a current sufficiently larger than a current generated according to the amount of light incident on the PN junction between the base and the emitter of the phototransistor PTr. Therefore, the photocurrent that is the emitter current of the phototransistor PTr is determined by the current supplied from the constant current source 9. The value of the photocurrent at this time indicates the amplification factor of the phototransistor PTr which causes the variation in sensitivity.

Therefore, a voltage having a value obtained by logarithmically converting the photocurrent determined by the constant current source 9 appears at the gates of the MOS transistors T1 and T2. Due to this voltage, an electric charge equivalent to a value obtained by natural logarithmically converting the integrated value of the photocurrent is accumulated in the capacitor C. Then, by applying a pulse signal φV to the gate of the MOS transistor T6 to turn on the MOS transistor T6, an output current equal to the natural logarithmically converted value of the photocurrent passes through the MOS transistors T6 and T7. To the output signal line 6. Since this photocurrent indicates the amplification factor of the phototransistor PTr causing the variation in sensitivity, the output signal output to the output signal line 6 is a signal representing the variation in sensitivity of each pixel.

As described above, when the pulse signal φV is applied and the variation in sensitivity of each pixel is detected, the signal φSW is set to low level, and the MOS transistor T3 is turned off again.
Then, the base of the phototransistor PTr is brought into a floating state. After that, the pulse signal φVRS is
This is applied to the gate of the transistor T8 to reset the capacitor C and the connection node a to prepare for the next imaging operation.

Incidentally, in the present embodiment, similarly to the second embodiment (FIG. 5), a pixel having a configuration in which the signal φD is applied to the drain of the MOS transistor T2 and the MOS transistor T8 is omitted may be used. At this time, by applying a low-level pulse signal to the signal φD at the same timing as the signal φVRS in FIG.
And reset the connection node a.

<Seventh Embodiment> A seventh embodiment applied to each pixel of the second example of the pixel configuration shown in FIG. 9 will be described with reference to the drawings. FIG. 12 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 12, in the present embodiment, similar to the sixth embodiment (FIG. 10), the phototransistor P
A third transistor whose source is connected to the base of Tr and whose drain is connected to the constant current source 9 via the current supply line 8
The configuration is such that an OS transistor T3 is newly provided. The signal φS is applied to the gate of the MOS transistor T3.
W is input. Other configurations are the same as those of the third embodiment (FIG. 6). Note that the MOS transistor T3 is
Similar to the OS transistor T1, an N-channel MOS transistor has a back gate grounded.

In such a configuration, as in the sixth embodiment, when the pixel performs an imaging operation, the base of the phototransistor PTr is floated by setting the signal φSW to low level and turning off the MOS transistor T3. State. When detecting a variation in the sensitivity of the pixel, the signal φSW is set to a high level to turn on the MOS transistor T3, thereby supplying a constant current from the constant current source 9 to the base of the phototransistor PTr. Hereinafter, the imaging operation and the detection operation of the sensitivity variation will be described.

(1) Imaging operation First, a low-level signal φSW is applied to the MOS transistor T
By applying the voltage to the gate of the MOS transistor T3, the MOS transistor T3 is turned off, and the base of the phototransistor PTr is brought into a floating state. At this time, the phototransistor PTr and the MOS transistors T1, T2, T6 are:
By performing the same operation as in the third embodiment, the logarithmically converted output current is output to the output signal line 6.

That is, when light is incident on the phototransistor PTr, a photocurrent is generated, and a voltage having a value obtained by natural logarithmically converting the photocurrent is generated at the gates of the MOS transistors T1 and T2 due to the subthreshold characteristic of the MOS transistor. I do. With this voltage, a drain current having a value proportional to the logarithm of the photocurrent in a natural logarithmic manner flows through the MOS transistor T2. When the signal φV is applied to the gate of the MOS transistor T6 to turn on the MOS transistor T6, the drain current having a value proportional to the logarithm of the photocurrent in a natural logarithmic manner is obtained.
It is led to the output signal line 6 through the S transistors T2 and T6. After the signal is read out in this manner, the MOS
The transistor T6 turns off.

(2) Pixel Sensitivity Variation Detection The pixel sensitivity variation detection operation will be described with reference to FIG. When the output current is output by giving the pulse signal φV as described above, first, the high-level signal φSW is set to M
The MOS transistor T3 is turned on by being applied to the gate of the OS transistor T3 so that a constant current flows from the constant current source 9 via the current supply line 8 to the base of the phototransistor PTr.

As described above, when a constant current flows from the constant current source 9 to each pixel, the photocurrent determined by the current supplied from the constant current source 9 becomes the phototransistor PTr.
More flowing. The value of the photocurrent at this time indicates the amplification factor of the phototransistor PTr which causes the variation in sensitivity. Therefore, a voltage having a value obtained by logarithmically converting the photocurrent determined by the constant current source 9 appears at the gates of the MOS transistors T1 and T2. With this voltage, a drain current having a value that is proportional to the logarithm of the photocurrent in a natural logarithm tends to flow through the MOS transistor T2.

When the signal φV is applied to the gate of the MOS transistor T6 to turn it on, a drain current having a value proportional to the logarithm of the photocurrent in natural logarithm is derived to the output signal line 6 through the MOS transistors T2 and T6. Is done. Since this photocurrent indicates the amplification factor of the phototransistor PTr causing the variation in sensitivity, the output signal output to the output signal line 6 is a signal representing the variation in sensitivity of each pixel. Thus, by giving the pulse signal φV,
When the sensitivity variation of each pixel is detected, the signal φSW is set to low level, and the MOS transistor T3 is turned off again.
Set to F to prepare for the next imaging operation.

<Eighth Embodiment> An eighth embodiment applied to each pixel of the second example of the pixel configuration shown in FIG. 9 will be described with reference to the drawings. FIG. 14 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 7 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 14, in the present embodiment, similar to the sixth embodiment (FIG. 10), the phototransistor P
A third transistor whose source is connected to the base of Tr and whose drain is connected to the constant current source 9 via the current supply line 8
The configuration is such that an OS transistor T3 is newly provided. The signal φS is applied to the gate of the MOS transistor T3.
W is input. Other configurations are the same as those of the fourth embodiment (FIG. 7). Incidentally, the MOS transistor T3 is
Similar to the OS transistor T1, an N-channel MOS transistor has a back gate grounded.

In such a configuration, as in the sixth embodiment, when the pixel performs an imaging operation, the base of the phototransistor PTr is floated by setting the signal φSW to low level and turning off the MOS transistor T3. State. When detecting a variation in the sensitivity of the pixel, the signal φSW is set to the high level to turn on the MOS transistor T3, so that a constant current is supplied from the constant current source 9 to the base of the phototransistor PTr. Hereinafter, the imaging operation and the detection operation of the sensitivity variation will be described.

(1) Imaging operation First, a low-level signal φSW is applied to the MOS transistor T
By applying the voltage to the gate of the MOS transistor T3, the MOS transistor T3 is turned off, and the base of the phototransistor PTr is brought into a floating state. At this time, the phototransistor PTr and the MOS transistors T1, T2, T5, T
6 performs the same operation as in the fourth embodiment, so that the logarithmically converted output current is output to the output signal line 6.

First, the signal φS is set to the low level, and FIG.
All the MOS transistors T5 provided in the pixels G11 to Gmn (FIG. 9) in the solid-state imaging device having the above configuration are turned off.
State. At this time, the phototransistor PTr generates a photocurrent corresponding to the amount of incident light, and the gate voltage of the MOS transistor T1 becomes a voltage corresponding to a value obtained by logarithmically converting the photocurrent. Next, a pulse signal φS is applied to the gates of the MOS transistors T5 in the pixels G11 to Gmn at the same timing, and a voltage corresponding to a logarithmically converted value of the photocurrent appearing in the MOS transistor T1 is sampled and held in the gate of the MOS transistor T2. I do. When sampled and held in this manner, the MOS transistor T
Turn 5 OFF.

Then, the vertical scanning circuit 2 (FIG. 1) and the horizontal scanning circuit 3 (FIG. 1) apply the pulse signal φV to the gate of the MOS transistor T6 provided in the pixels G11 to Gmn.
Are sequentially applied, and when the MOS transistor T6 is turned on, an output current proportional to a voltage obtained by logarithmically converting the photocurrent sampled and held at the gate of the MOS transistor T2 is output to the output signal line 6. After the signal is read out in this manner, the MOS transistor T6 is turned off.
It becomes F.

(2) Pixel Sensitivity Variation Detection The pixel sensitivity variation detection operation will be described with reference to FIG. Note that the timing chart of FIG. 15 shows the operation of each signal in one pixel. As described above, after the pulse signal φS is supplied to all the pixels, the pulse signal φV is sequentially supplied to each pixel, and the output current is output from all the pixels. First, the high-level signal φSW is supplied to the MOS transistor T3. Apply to gate to turn on MOS transistor T3
Then, a constant current flows from the constant current source 9 to the base of the phototransistor PTr via the current supply line 8.

As described above, when a constant current flows from the constant current source 9 to each pixel, the photocurrent determined by the current supplied from the constant current source 9 becomes the phototransistor PTr.
More flowing. The value of the photocurrent at this time indicates the amplification factor of the phototransistor PTr which causes the variation in sensitivity. Accordingly, a voltage having a value obtained by logarithmically converting the photocurrent determined by the constant current source 9 appears at the gate of the MOS transistor T1.

Next, the pulse signal φS is applied to the gates of the MOS transistors T5 of all the pixels, thereby
A MOS transistor T1 is connected to the gate of the transistor T2.
The voltage of the value obtained by logarithmically converting the photocurrent determined by the constant current source 9 to be the gate voltage is sampled and held. With this voltage, a drain current having a value that is proportional to the logarithm of the photocurrent in a natural logarithm tends to flow through the MOS transistor T2. Then, as described above, the MOS transistor T2
, The MOS transistor T5 is turned off.

Then, the signal φSW is set to the low level to set M
The OS transistor T3 is turned off. Thereafter, a signal φV is applied to the gate of the MOS transistor T6 for each pixel to turn on the MOS transistor T6, and the drain current having a value which is logarithmically proportional to the photocurrent is supplied to the MOS transistors T2 and T6.
Through to the output signal line 6. Since this photocurrent indicates the amplification factor of the phototransistor PTr causing the variation in sensitivity, the output signal output to the output signal line 6 is:
This is a signal representing the variation in the sensitivity of each pixel. As described above, when the signal representing the sensitivity variation of each pixel sampled and held at the same time is sequentially output from each pixel and output as serial data, the MOS transistor T
6 is turned off to prepare for the next imaging operation.

<Ninth Embodiment> A ninth embodiment applied to each pixel of the second example of the pixel configuration shown in FIG. 9 will be described with reference to the drawings. FIG. 16 is a circuit diagram illustrating a configuration of a pixel provided in a solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 8 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 16, in the present embodiment, similar to the sixth embodiment (FIG. 10), the phototransistor P
A third transistor whose source is connected to the base of Tr and whose drain is connected to the constant current source 9 via the current supply line 8
The configuration is such that an OS transistor T3 is newly provided. The signal φS is applied to the gate of the MOS transistor T3.
W is input. Other configurations are the same as those of the fifth embodiment (FIG. 8). Incidentally, the MOS transistor T3 is
As with the OS transistors T1, T2, T4, and T6, an N-channel MOS transistor has a back gate grounded. The signal φVPS changes in a binary manner, a voltage for operating the MOS transistors T1 and T2 in the subthreshold region is set to a low level, and a voltage substantially equal to the DC voltage VPD is set to a high level. The operation in each of these cases will be described below.

(1) When the Photocurrent is Naturally Logarithmically Converted and Output (1−a) Imaging Operation First, a low-level signal φSW is applied to the MOS transistor T
By applying the voltage to the gate of the MOS transistor T3, the MOS transistor T3 is turned off, and the base of the phototransistor PTr is brought into a floating state. At this time, the phototransistor PTr and the MOS transistors T1, T2, T4, T
6 performs the same operation as in the fifth embodiment, so that the logarithmically converted output current is output to the output signal line 6.

That is, first, the signal φVPS is set to low level to bias the MOS transistors T1 and T2 so that they operate in the subthreshold region.
VRS2 is set to low level, and the MOS transistor T4 is turned off. At this time, when light is incident on the phototransistor PTr, a photocurrent is generated. Due to the subthreshold characteristic of the MOS transistor, a voltage obtained by natural logarithmic conversion of the photocurrent is applied to the MOS transistors T1 and T2.
Occurs at the gate. With this voltage, a drain current equivalent to a value obtained by natural logarithmically converting the photocurrent tends to flow through the MOS transistor T2.

Next, a pulse signal φV is applied to the gate of MOS transistor T6 to turn on MOS transistor T6.
N, the drain current proportional to the voltage applied to the gate of the MOS transistor T2 becomes
2, and is led to the output signal line 6 through T6. Therefore,
The current led out to the output signal line 6 is a value obtained by natural logarithmically converting the integrated value of the photocurrent. When a signal (output current) proportional to the logarithmic value of the incident light amount is read out in this manner,
The MOS transistor T6 is turned off.

(1-b) Detection of Variation in Sensitivity of Pixels The operation of detecting variation in sensitivity of pixels will be described with reference to FIG. When the output current is output by giving the pulse signal φV as described above, first, the high-level signal φSW is set to M
The MOS transistor T3 is turned on by being applied to the gate of the OS transistor T3 so that a constant current flows from the constant current source 9 via the current supply line 8 to the base of the phototransistor PTr.

As described above, when a constant current flows from the constant current source 9 to each pixel, the photocurrent determined by the current supplied from the constant current source 9 becomes the phototransistor PTr.
More flowing. The value of the photocurrent at this time indicates the amplification factor of the phototransistor PTr which causes the variation in sensitivity. Therefore, a voltage having a value obtained by logarithmically converting the photocurrent determined by the constant current source 9 appears at the gates of the MOS transistors T1 and T2. With this voltage, a drain current having a value that is proportional to the logarithm of the photocurrent in a natural logarithm tends to flow through the MOS transistor T2.

When the signal φV is applied to the gate of the MOS transistor T6 and turned on, a drain current having a value proportional to the logarithm of the photocurrent is derived to the output signal line 6 through the MOS transistors T2 and T6. Is done. Since this photocurrent indicates the amplification factor of the phototransistor PTr causing the variation in sensitivity, the output signal output to the output signal line 6 is a signal representing the variation in sensitivity of each pixel. Thus, by giving the pulse signal φV,
When the sensitivity variation of each pixel is detected, the signal φSW is set to low level, and the MOS transistor T3 is turned off again.
Set to F to prepare for the next imaging operation. At this time, MO
The S transistor T4 is off.

(2) In the case where photocurrent is linearly converted and output (2-a) Imaging operation First, a low-level signal φSW is applied to the MOS transistor T
By applying the voltage to the gate of the MOS transistor T3, the MOS transistor T3 is turned off, and the base of the phototransistor PTr is brought into a floating state. At this time, the phototransistor PTr and the MOS transistors T1, T2, T4, T
6 performs the same operation as in the fifth embodiment, so that the output current that has been linearly converted is output to the output signal line 6.

That is, first, the signal φVPS is set to the high level, the MOS transistor T1 is cut off, and the low-level signal φVRS2 is applied to the gate of the MOS transistor T4.
FF. At this time, when light enters the phototransistor PTr to generate a photocurrent, the charge due to the photocurrent becomes M
By being stored in the gate and the drain of the OS transistor T1, the gate voltage of the MOS transistors T1 and T2 becomes a value proportional to the integrated value of the photocurrent.

Next, a pulse signal φV is applied to the gate of MOS transistor T6 to turn on MOS transistor T6.
N, the drain current proportional to the voltage applied to the gate of the MOS transistor T2 becomes
2, and is led to the output signal line 6 through T6. In this way, a signal (output current) proportional to the amount of incident light can be read. After reading the signal, the MOS transistor T6 is turned off.

(2-b) Detection of Variation in Sensitivity of Pixel The operation of detecting variation in sensitivity of a pixel will be described with reference to FIG. When the pulse signal φV is applied to output an output current as described above, first, the pulse signal φVRS2 is applied to turn on the MOS transistor T4, thereby resetting the MOS transistor T1 and the like. Then, a high-level signal φSW is applied to the gate of the MOS transistor T3 to turn on the MOS transistor T3, and the current supply line 8 is supplied from the constant current source 9 to the base of the phototransistor PTr.
To allow a constant current to flow.

As described above, when a constant current flows from the constant current source 9 to each pixel, the photocurrent determined by the current supplied from the constant current source 9 becomes the phototransistor PTr.
More flowing. The value of the photocurrent at this time indicates the amplification factor of the phototransistor PTr which causes the variation in sensitivity. Therefore, a voltage having a value obtained by linearly converting the photocurrent determined by the constant current source 9 appears at the gates of the MOS transistors T1 and T2. With this voltage, a drain current having a value linearly proportional to the photocurrent tends to flow through the MOS transistor T2.

When the signal φV is applied to the gate of the MOS transistor T6 to turn it on, a drain current having a value linearly proportional to the photocurrent is led out to the output signal line 6 through the MOS transistors T2 and T6. You. Since this photocurrent indicates the amplification factor of the phototransistor PTr causing the variation in sensitivity, the output signal output to the output signal line 6 is a signal representing the variation in sensitivity of each pixel.

As described above, when the variation in sensitivity of each pixel is detected by applying the pulse signal φV, the signal φSW is set to low level, and the MOS transistor T3 is turned off again.
To Thereafter, the pulse signal φVRS2 is applied to reset the MOS transistor T1 and the like, thereby preparing for the next imaging operation.

In this embodiment, as in the first or second embodiment, a capacitor C (see FIG. 3 or FIG. 5) having one end connected to the source of the MOS transistor T2,
And a MOS transistor T7 whose gate is connected to the source of the MOS transistor T2 and whose source is connected to the drain of the MOS transistor T6 (FIG. 3 or FIG. 5).
) And an integration circuit on the output side. In the present embodiment, as in the fourth embodiment, a MOS transistor in which the source is connected to the connection node between the gate and the drain of the MOS transistor T1 and the drain is connected to the gate of the MOS transistor T2.
A transistor T5 (see FIG. 7) may be provided.

In the above-described sixth to ninth embodiments, when a signal when the variation in sensitivity is detected is output to the output signal line 6 for each pixel, the signal at the time of this detection is serially output. In a subsequent circuit, correction data for each pixel is stored in a memory. Then, if the signal at the time of actual imaging is corrected for each pixel using the stored correction data, it is possible to remove variations for each pixel from the output signal. This correction method can also be realized by providing a memory such as a line memory in the element.

In the first to ninth embodiments, the signal reading from each pixel may be performed using a charge-coupled device (CCD). In this case, the charge can be read out to the CCD by providing a potential barrier having a variable potential level corresponding to the MOS transistor T6 serving as a row selection switch.

The MOS transistors T1 to T9 are N-channel MOS transistors, and the phototransistor PTr is an npn transistor.
The OS transistors T1 to T9 may be P-channel MOS transistors, and the phototransistor PTr may be a pnp transistor. At this time, in the pixel configuration of FIG. 1 or FIG.
S transistors Q1 and Q2 are also formed of P-channel MOS transistors. Thus, the P-channel MOS
When a solid-state imaging device is configured by a transistor and a pnp-type transistor, although the configuration and operation are reversed,
The configuration is substantially the same.

[0130]

According to the solid-state imaging device of the present invention, the photocurrent is amplified and output as an electric signal by using a phototransistor as the photosensitive element of the photoelectric conversion means, so that high sensitivity is obtained. Imaging can be performed. In addition, the output state of the photoelectric conversion means can be freely set to a natural logarithmic output state and a linear output state independently of the luminance of the subject. For example, a linear output state can be selectively used for selecting a target output state and imaging a low-luminance subject or a subject having a narrow luminance range. Therefore, a wide range of subjects from low luminance to high luminance can be imaged with high quality.

According to the solid-state imaging device of the present invention, a phototransistor is used as the photosensitive element, and the first electrode and the gate electrode of the first MOS transistor are connected to the second electrode of the phototransistor. The gate electrode of the second MOS transistor is connected to the gate electrode of the first MOS transistor, and the first MOS transistor is operated in the sub-threshold region to convert the electrical signal from the phototransistor into a natural logarithm, thereby obtaining the second MO transistor.
Since the output is made from the second electrode of the S transistor, a solid-state imaging device having a high sensitivity and a wide dynamic range can be obtained with a simple circuit configuration and a high degree of freedom in design. In particular, according to the solid-state imaging device of claim 9 of the present application, by providing a constant current source for supplying a constant current to the base electrode of the phototransistor, the same constant current is supplied to the control electrode of the phototransistor of each pixel. An output signal indicating the amplification factor of the phototransistor is obtained.
Therefore, it is possible to detect a variation in pixels due to a variation in the amplification factor of the phototransistor without giving uniform light as in the related art. Therefore, it is possible to perform high-quality imaging in which variation in pixel sensitivity is canceled.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram for explaining the overall configuration of a two-dimensional solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a part of FIG. 1;

FIG. 3 is a circuit diagram showing a configuration of one pixel according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing another configuration of one pixel according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of one pixel according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of one pixel according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of one pixel according to a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of one pixel according to a fifth embodiment of the present invention.

FIG. 9 is a block circuit diagram for explaining the overall configuration of a two-dimensional solid-state imaging device according to an embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration of one pixel according to a sixth embodiment of the present invention.

FIG. 11 is a timing chart of a signal applied to each element of a pixel used in the sixth embodiment.

FIG. 12 is a circuit diagram showing a configuration of one pixel according to a seventh embodiment of the present invention.

FIG. 13 is a timing chart of a signal applied to each element of a pixel used in the seventh embodiment.

FIG. 14 is a circuit diagram showing a configuration of one pixel according to an eighth embodiment of the present invention.

FIG. 15 is a timing chart of signals applied to each element of a pixel used in the eighth embodiment.

FIG. 16 is a circuit diagram showing a configuration of one pixel according to a ninth embodiment of the present invention.

FIG. 17 is a timing chart of signals applied to each element of a pixel used in the ninth embodiment.

FIG. 18 is a timing chart of signals applied to each element of a pixel used in the ninth embodiment.

FIG. 19 is a circuit diagram showing a configuration of one pixel in a conventional example.

[Explanation of symbols]

 G11 to Gmn pixel 2 vertical scanning circuit 3 horizontal scanning circuit 4-1 to 4-n row selection line 6-1 to 6-m output signal line 7 signal line 8-1 to 8-m current supply line 9-1 to 9 −m Constant current source 10 DC voltage line 11 line PTr Phototransistors T1 to T8 First to eighth MOS transistors C Capacitor

Claims (17)

[Claims] 1. A solid-state imaging device comprising: a photoelectric conversion unit having a photosensitive element for generating an electric signal corresponding to an amount of incident light; and a lead-out path for leading an output signal of the photoelectric conversion unit to an output signal line. The photosensitive element is a phototransistor that amplifies a photocurrent according to the amount of light incident on the control electrode to generate the electric signal, and the photoelectric conversion unit converts the electric signal generated by the phototransistor into an electric signal. A solid-state imaging device capable of switching between a first state in which linear conversion is performed and a second state in which natural logarithm conversion is performed. 2. A pixel comprising a photoelectric conversion means having a photosensitive element for generating an electric signal corresponding to the amount of incident light and a lead-out path for leading an output signal of the photoelectric conversion means to an output signal line. In the two-dimensional solid-state imaging device, the photosensitive element is a phototransistor that amplifies a photocurrent according to a light amount incident on a control electrode to generate the electric signal, and the photoelectric conversion unit includes: A solid-state imaging device, wherein a first state in which the electric signal generated by the phototransistor is converted linearly and a second state in which the electric signal is converted logarithmically are switchable. 3. A reset unit for initializing the photoelectric conversion unit after the photoelectric conversion unit operates in the first state and outputs an electric signal to the output signal line is provided. The solid-state imaging device according to claim 1. 4. Each of the pixels has an amplifying transistor for amplifying an output signal of the photoelectric conversion means, and outputs an output signal of the amplifying transistor to the output signal line via the output path. The solid-state imaging device according to claim 2, wherein: 5. The solid according to claim 4, further comprising a load resistor or a constant current source connected to the output signal line, wherein the total number of the load resistors or the constant current sources is smaller than the total number of pixels. Imaging device. 6. The photoelectric conversion means, wherein a control electrode is set in a floating state,
A phototransistor to which a DC voltage is applied to the electrode and amplifies a photocurrent generated by the amount of light incident on the control electrode; and a first electrode, a second electrode, and a control electrode. A first transistor to which a first electrode and a control electrode are connected and into which an output current from the phototransistor flows; and a first electrode, a second electrode, and a control electrode, wherein a DC voltage is applied to the first electrode and control is performed. An electrode connected to a control electrode of the first transistor, and a second transistor for outputting an electric signal from a second electrode; operating the first transistor in a sub-threshold region to generate an output flowing from the phototransistor; The solid-state imaging device according to claim 1, wherein the current is converted into a natural logarithm. 7. A photo-transistor, wherein a constant current source is provided, and wherein the photoelectric conversion unit is configured to apply a DC voltage to a first electrode and amplify a photocurrent generated by an amount of light incident on a control electrode; A first transistor having a first electrode, a second electrode, and a control electrode, wherein the first electrode and the control electrode are connected to the second electrode of the phototransistor, and an output current from the phototransistor flows; A second transistor including a two-electrode and a control electrode, wherein a DC voltage is applied to the first electrode, the control electrode is connected to the control electrode of the first transistor, and an electric signal is output from the second electrode; It is connected between the control electrode of the transistor and the constant current source, and electrically connects and disconnects the control electrode of the phototransistor and the constant current source. That the first
When performing an imaging operation, the first switch is turned off and the first transistor is operated in a sub-threshold region, so that the output current flowing from the phototransistor is logarithmically calculated. The solid-state imaging device according to any one of claims 1 to 5, wherein the first switch is turned on when converting and detecting a variation in sensitivity of the photoelectric conversion unit. 8. In a two-dimensional solid-state imaging device having pixels arranged in a matrix, each pixel has a base electrode in a floating state, a DC voltage is applied to a first electrode, and a light is applied to the base electrode. A phototransistor that amplifies a photocurrent generated by the generated light amount, a first MOS transistor having a first electrode and a gate electrode connected to a second electrode of the phototransistor, and a gate electrode connected to a gate electrode of the first MOS transistor And operating the first MOS transistor in a sub-threshold region equal to or less than a threshold value, thereby converting an electric signal output from the phototransistor into a natural logarithm, and converting the electric signal output from the phototransistor into a natural logarithm. A solid-state imaging device for outputting from a second electrode. 9. A two-dimensional solid-state imaging device having pixels arranged in a matrix, comprising a constant current source for supplying a constant current to each pixel, and each pixel having a DC voltage applied to a first electrode. A phototransistor that amplifies a photocurrent generated by the amount of light incident on a base electrode; a first MOS transistor having a first electrode and a gate electrode connected to a second electrode of the phototransistor; a gate electrode of the first MOS transistor And a third MOS transistor having a first electrode connected to the constant current source and a second electrode connected to a base electrode of the phototransistor. When performing the operation, the third MOS transistor is turned off and the first MOS transistor is set to a threshold or less. By operating in a sub-threshold region, an electrical signal output from the phototransistor is converted into a natural logarithm and output from the second electrode of the second MOS transistor. When detecting variation in sensitivity of the pixel, 3M
A solid-state imaging device characterized by turning on an OS transistor. 10. The pixel, wherein a first electrode is connected to a gate electrode of the first MOS transistor, a second electrode is connected to a DC voltage,
A fourth MOS transistor that resets by discharging the charge accumulated in the gate electrode of the first MOS transistor by switching the level of the voltage input to the gate electrode; When the first MOS transistor is output from the second electrode of the second MOS transistor, the first MOS transistor is operated in a sub-threshold region equal to or less than a threshold value, while the electric signal output from the phototransistor is linearly converted. And the second MOS transistor
When outputting from the electrode, the first MOS transistor is inactivated by bringing the potential of the second electrode of the first MOS transistor close to the potential of the first electrode of the phototransistor, and after outputting an electric signal,
Switching the level of the voltage input to the gate electrode of the fourth MOS transistor to make the fourth MOS transistor conductive, releasing at least the electric charge accumulated in the first electrode and the gate electrode of the first MOS transistor, and resetting the same; The solid-state imaging device according to claim 8 or 9, wherein: 11. The pixel according to claim 1, wherein a first electrode is connected to a connection node between a first electrode and a gate electrode of the first MOS transistor, and a second electrode is connected to a gate electrode of the second MOS transistor. A fifth MOS transistor in each pixel provided in the solid-state imaging device.
The solid-state imaging device according to claim 8, wherein the OS transistor operates at the same timing to output an electric signal captured at the same time from each of the pixels. 12. The pixel according to claim 1, wherein the first electrode is the second MO.
12. The semiconductor device according to claim 8, further comprising a sixth MOS transistor connected to a second electrode of the S transistor, the second electrode connected to an output signal line, and a gate electrode connected to a row selection line. A solid-state imaging device according to any one of claims 1 to 3. 13. The pixel, wherein a first electrode is connected to a DC voltage and a gate electrode is connected to the second electrode.
Connected to the second electrode of the MOS transistor,
A seventh MOS transistor for amplifying an output signal output from a second electrode of the second MOS transistor; a first electrode connected to a second electrode of the seventh MOS transistor; a second electrode connected to an output signal line; The solid-state imaging device according to any one of claims 8 to 10, further comprising: a sixth MOS transistor whose electrode is connected to a row selection line. 14. The pixel has one end connected to a second electrode of the second MOS transistor and the other end connected to the first MOS transistor.
A capacitor is connected to a signal line to which a second electrode of the transistor is connected, and is reset via the second MOS transistor when a reset voltage is applied to a first electrode of the second MOS transistor. The solid-state imaging device according to claim 13. 15. A first electrode of the second MOS transistor is connected to a DC voltage, and the pixel has a first electrode connected to a second electrode of the second MOS transistor, and a DC voltage connected to a second electrode. An eighth MOS transistor, one end of which is connected to a second electrode of the second MOS transistor, and the other end of which is connected to a signal line to which a second electrode of the first MOS transistor is connected, and to a gate electrode of the eighth MOS transistor. The solid-state imaging device according to claim 13, further comprising: a capacitor that is reset via the eighth MOS transistor when a reset voltage is applied. 16. The device according to claim 8, further comprising a MOS transistor forming a load resistor or a constant current source connected to said pixel via said output signal line. Solid-state imaging device. 17. The solid-state imaging device according to claim 8, wherein said MOS transistors are all N-channel MOS transistors, and said phototransistors are npn-type phototransistors. apparatus.