JP4360041B2 - Imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is a solid that can be switched between a first state that outputs an electric signal that linearly changes with respect to the amount of incident light and a second state that outputs an electric signal that naturally changes logarithm with respect to the amount of incident light. The present invention relates to an imaging apparatus having an imaging element.
[0002]
[Prior art]
Conventionally, in a solid-state imaging device that linearly converts the amount of incident light, its dynamic range is as narrow as two orders of magnitude, so when imaging a subject that constitutes a luminance distribution in a wide luminance range, luminance information in a range other than the dynamic range Is not output. On the other hand, a solid-state imaging device that performs logarithmic conversion with respect to the amount of incident light has a wide dynamic range of 5 to 6 digits. All luminance information in the distribution can be converted into an electrical signal and output.
[0003]
However, generally, the luminance range of a subject is often about 2 to 3 digits, so in the case of a solid-state image sensor that performs logarithmic conversion with a dynamic range of 5 to 6 digits, it is possible to image the luminance distribution of the subject. Since the area becomes wide, an area without luminance data is formed in the low luminance area or the high luminance area in the imageable area. Therefore, when an image of a subject having the luminance distribution is reproduced using an electrical signal from a solid-state imaging device that performs logarithmic conversion, the black with the lowest luminance is reproduced as dark gray and the white with the highest luminance is reproduced as light gray. In some cases, an image with insufficient contrast is reproduced as a whole.
[0004]
In order to solve such a problem, after converting the electrical signal output from the solid-state imaging device into a digital signal, the luminance distribution is measured, and the minimum value of the luminance distribution becomes the minimum value of the dynamic range of the digital output. There has been proposed a method of converting the value of a digital signal so that the maximum value of the luminance distribution matches the maximum value of the dynamic range of the digital output so that the luminance distribution matches the dynamic range of the digital output.
[0005]
[Problems to be solved by the invention]
In this way, by processing the digital signal in which the output from the solid-state image sensor is digitally converted, the luminance distribution of the subject and the dynamic range of the digital output obtained by digitally converting the output from the solid-state image sensor are matched. In this case, a bit drop occurs in the digital output, resulting in a drop in gradation. Therefore, there is a risk that the change in luminance of the reproduced image will be unstable and lose smoothness.
[0006]
In view of such a problem, an object of the present invention is to provide an imaging apparatus capable of adapting the dynamic range of a subject to the dynamic range of a solid-state imaging element without degrading gradation.
[0007]
[Means for Solving the Problems]
  In order to achieve the above object, an imaging apparatus according to claim 1 includes a photosensitive element that outputs an electrical signal corresponding to an incident light amount and a transistor to which an electrical signal from the photosensitive element is applied, and performs linear conversion. In an imaging apparatus having a solid-state imaging device composed of a plurality of pixels that can be automatically switched between a first state to be output and a second state in which an electrical signal corresponding to the amount of incident light is logarithmically converted and output, A bias adjustment unit is provided that changes the potential state of the transistor according to the state of the luminance distribution of the subject imaged by the solid-state imaging device.The bias adjusting unit adjusts the potential state of the transistor immediately after the reset by switching the length of time for applying the bias voltage applied to the transistor at the time of resetting.It is characterized by that.
[0008]
In such an imaging apparatus, when the luminance distribution of the subject is wide, the potential state of the transistor at the time of reset is adjusted so that the transistor can operate in the subthreshold region with low luminance. When the luminance distribution of the object is narrow, the potential state of the transistor at the time of reset is adjusted so that the transistor can operate in a cutoff state up to a high luminance.
[0013]
  Claims2Described inThe image pickup apparatus includes a photosensitive element that outputs an electric signal corresponding to the amount of incident light and a transistor that receives the electric signal from the photosensitive element, and also performs linear conversion and outputs the first state and an electric signal corresponding to the amount of incident light. In an imaging apparatus having a solid-state imaging device composed of a plurality of pixels that can be automatically switched between a second state that is logarithmically converted and output, the potential state of the transistor immediately after resetting is imaged by the solid-state imaging device A bias adjusting unit that changes the luminance distribution of the subject to be detected, the pixel serving as the photosensitive element, and a DC voltage applied to the first electrode, and a first of the photodiodes A first electrode and a gate electrode connected to the two electrodes, and a MOS transistor that outputs an electrical signal from the gate electrode, When the luminance range of the luminance distribution of the subject is narrow by the bias adjustment unit, the potential state of the MOS transistor immediately after the reset so that the potential difference between the gate electrode and the second electrode of the MOS transistor becomes large. When the brightness range of the brightness distribution of the subject is wide, the MOS transistor immediately after resetting is reduced so that the potential difference between the gate electrode and the second electrode of the MOS transistor is reduced. The potential state is adjusted,The pixel is reset by switching the voltage applied to the second electrode of the MOS transistor, and the bias adjusting unit is reset by adjusting the time for switching the voltage value applied to the second electrode of the MOS transistor at the time of resetting. Adjust the potential state of the MOS transistor immediately afterIt is characterized by that.
[0014]
At this time, when the MOS transistor is an N-channel MOS transistor, when the luminance range of the subject is wide, the time for switching the voltage value applied to the second electrode of the MOS transistor at the time of reset is set short, and the luminance range of the subject is narrow The time for switching the voltage value applied to the second electrode of the MOS transistor at the time of reset is set to be long.
[0017]
  , Claims3Described inThe image pickup apparatus includes a photosensitive element that outputs an electric signal corresponding to the amount of incident light and a transistor that receives the electric signal from the photosensitive element, and also performs linear conversion and outputs the first state and an electric signal corresponding to the amount of incident light. In an imaging apparatus having a solid-state imaging device composed of a plurality of pixels that can be automatically switched between a second state that is logarithmically converted and output, the potential state of the transistor immediately after resetting is imaged by the solid-state imaging device A bias adjusting unit that changes the luminance distribution of the subject to be detected, the pixel serving as the photosensitive element, and a DC voltage applied to the first electrode, and a first of the photodiodes A first electrode and a gate electrode connected to the two electrodes, and a MOS transistor that outputs an electrical signal from the gate electrode, When the luminance range of the luminance distribution of the subject is narrow by the bias adjustment unit, the potential state of the MOS transistor immediately after the reset so that the potential difference between the gate electrode and the second electrode of the MOS transistor becomes large. Is adjusted and the potential of the MOS transistor immediately after resetting is reduced so that the difference in potential between the gate electrode and the second electrode of the MOS transistor becomes small when the luminance range of the luminance distribution of the subject is wide. Condition is adjusted,The pixel is reset by switching a voltage applied to the gate electrode and the second electrode of the MOS transistor, and the bias adjustment unit adjusts a voltage value applied to the gate electrode and the second electrode of the MOS transistor at the time of reset. To adjust the potential state of the MOS transistor immediately after resettingIt is characterized by that.
[0018]
At this time, when the MOS transistor is an N-channel MOS transistor, when the luminance range of the subject is wide, the voltage value applied to the gate electrode and the second electrode of the MOS transistor at the time of reset is set high, and the luminance range of the subject is narrow The voltage value applied to the gate electrode and the second electrode of the MOS transistor during reset is set low.
[0020]
  Claims4Described inThe image pickup apparatus includes a photosensitive element that outputs an electric signal corresponding to the amount of incident light and a transistor that receives the electric signal from the photosensitive element, and also performs linear conversion and outputs the first state and an electric signal corresponding to the amount of incident light. In an imaging apparatus having a solid-state imaging device composed of a plurality of pixels that can be automatically switched between a second state that is logarithmically converted and output, the potential state of the transistor immediately after resetting is imaged by the solid-state imaging device A bias adjusting unit that changes the luminance distribution of the subject to be detected, the pixel serving as the photosensitive element, and a DC voltage applied to the second electrode, and a second of the photodiode A first transistor connected to the second electrode and outputting an electric signal from the second electrode; Thus, when the luminance range of the luminance distribution of the subject is narrow, the potential state of the MOS transistor immediately after reset is adjusted so that the potential difference between the gate electrode and the second electrode of the MOS transistor becomes large. In addition, when the luminance range of the luminance distribution of the subject is wide, the potential state of the MOS transistor immediately after the reset is small so that the potential difference between the gate electrode and the second electrode of the MOS transistor is small. Adjusted,The pixel is reset by switching the voltage applied to each of the first electrode and the gate electrode of the MOS transistor, and the bias adjustment unit is reset by adjusting the voltage value applied to the gate electrode of the MOS transistor at the time of reset. Adjust the potential state of the MOS transistor immediately afterIt is characterized by that.
[0021]
At this time, if the MOS transistor is an N-channel MOS transistor, the voltage value applied to the gate electrode of the MOS transistor at the time of resetting is set low when the luminance range of the subject is wide. The voltage value applied to the gate electrode of the MOS transistor is set high.
[0022]
  Claims5Described inThe imaging apparatus includes a photosensitive element that outputs an electrical signal corresponding to the amount of incident light and a transistor that receives the electrical signal from the photosensitive element, and performs linear conversion and outputs an electrical signal corresponding to the amount of incident light. In an imaging device having a solid-state imaging device composed of a plurality of pixels that can be automatically switched between a second state logarithmically converted and output, the potential state of the transistor immediately after reset is imaged by the solid-state imaging device. A photodiode that has a bias adjustment unit that changes in accordance with a state of luminance distribution of the subject to be photographed, the pixel serves as the photosensitive element, and a DC voltage is applied to the second electrode, and a first of the photodiode And a MOS transistor that is connected to the second electrode and outputs an electric signal from the second electrode. When the luminance range of the luminance distribution of the subject is narrow, the potential state of the MOS transistor immediately after reset is adjusted so that the potential difference between the gate electrode and the second electrode of the MOS transistor becomes large. In addition, when the luminance range of the luminance distribution of the subject is wide, the potential state of the MOS transistor immediately after the reset is adjusted so that the potential difference between the gate electrode and the second electrode of the MOS transistor becomes small. AndThe pixel is reset by switching the voltage applied to each of the first electrode and the gate electrode of the MOS transistor, and the bias adjustment unit adjusts the time for switching the voltage value applied to the gate electrode of the MOS transistor at the time of reset. To adjust the potential state of the MOS transistor immediately after resettingIt is characterized by that.
[0023]
At this time, when the MOS transistor is an N-channel MOS transistor, when the luminance range of the subject is wide, the time for switching the voltage value applied to the gate electrode of the MOS transistor at the time of reset is set short, and when the luminance range of the subject is narrow, The time for switching the voltage value applied to the gate electrode of the MOS transistor at the time of resetting is set to be long.
[0026]
  Claims6Described inThe imaging apparatus includes a photosensitive element that outputs an electrical signal corresponding to the amount of incident light and a transistor that receives the electrical signal from the photosensitive element, and performs linear conversion and outputs an electrical signal corresponding to the amount of incident light. In an imaging device having a solid-state imaging device composed of a plurality of pixels that can be automatically switched between a second state logarithmically converted and output, the potential state of the transistor immediately after reset is imaged by the solid-state imaging device. A photodiode that has a bias adjustment unit that changes in accordance with a state of luminance distribution of the subject to be photographed, the pixel serves as the photosensitive element, and a DC voltage is applied to the second electrode, and a first of the photodiode And a MOS transistor that is connected to the second electrode and outputs an electric signal from the second electrode. When the luminance range of the luminance distribution of the subject is narrow, the potential state of the MOS transistor immediately after reset is adjusted so that the potential difference between the gate electrode and the second electrode of the MOS transistor becomes large. In addition, when the luminance range of the luminance distribution of the subject is wide, the potential state of the MOS transistor immediately after the reset is adjusted so that the potential difference between the gate electrode and the second electrode of the MOS transistor becomes small. BeforeThe pixel is reset by switching the voltage applied to the gate electrode and the second electrode of the MOS transistor, and the bias adjustment unit adjusts the voltage value applied to the gate electrode of the MOS transistor at the time of reset, immediately after the reset. Adjusting the potential state of the MOS transistorIt is characterized by that.
[0027]
At this time, if the MOS transistor is an N-channel MOS transistor, the voltage value applied to the gate electrode of the MOS transistor at the time of resetting is set low when the luminance range of the subject is wide. The voltage value applied to the gate electrode of the MOS transistor is set high.
[0028]
  Claims7Described inThe imaging apparatus includes a photosensitive element that outputs an electrical signal corresponding to the amount of incident light and a transistor that receives the electrical signal from the photosensitive element, and performs linear conversion and outputs an electrical signal corresponding to the amount of incident light. In an imaging device having a solid-state imaging device composed of a plurality of pixels that can be automatically switched between a second state logarithmically converted and output, the potential state of the transistor immediately after reset is imaged by the solid-state imaging device. A photodiode that has a bias adjustment unit that changes in accordance with a state of luminance distribution of the subject to be photographed, the pixel serves as the photosensitive element, and a DC voltage is applied to the second electrode, and a first of the photodiode And a MOS transistor that is connected to the second electrode and outputs an electric signal from the second electrode. When the luminance range of the luminance distribution of the subject is narrow, the potential state of the MOS transistor immediately after reset is adjusted so that the potential difference between the gate electrode and the second electrode of the MOS transistor becomes large. In addition, when the luminance range of the luminance distribution of the subject is wide, the potential state of the MOS transistor immediately after the reset is adjusted so that the potential difference between the gate electrode and the second electrode of the MOS transistor becomes small. AndBy switching the voltage applied to the gate electrode and the second electrode of the MOS transistor, the pixel is reset, and the bias adjusting unit adjusts the time for switching the voltage value applied to the gate electrode of the MOS transistor at the time of resetting. Adjust the potential state of the MOS transistor immediately after resetIt is characterized by that.
[0029]
At this time, when the MOS transistor is an N-channel MOS transistor, when the luminance range of the subject is wide, the time for switching the voltage value applied to the gate electrode of the MOS transistor at the time of reset is set short, and when the luminance range of the subject is narrow, The time for switching the voltage value applied to the gate electrode of the MOS transistor at the time of resetting is set to be long.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below.
[0031]
<Configuration example of solid-state imaging device>
First, a configuration example of a solid-state imaging device provided in the imaging apparatus of the present invention will be described. FIG. 1 schematically shows the structure of a part of the two-dimensional MOS solid-state imaging device of the present invention. In the drawing, G11 to Gmn indicate pixels arranged in a matrix (matrix arrangement). Reference numeral 2 denotes a vertical scanning circuit, which sequentially scans rows (lines) 4-1, 4-2,. A horizontal scanning circuit 3 sequentially reads out photoelectric conversion signals derived from the pixels to the output signal lines 6-1, 6-2, ..., 6-m in the horizontal direction for each pixel. Reference numeral 5 denotes a power supply line. For each pixel, not only the lines 4-1, 4-2, ..., 4-n, the output signal lines 6-1, 6-2, ..., 6-m, and the power supply line 5, but also other lines (for example, , Clock lines, etc.) are also connected, but these are omitted in FIG.
[0032]
One set of N-channel MOS transistors Q1 is provided for each of the output signal lines 6-1, 6-2,. Taking the output signal line 6-1 as an example, the gate of the MOS transistor Q1 is connected to the DC voltage line 7, the drain is connected to the output signal line 6-1 and the source is connected to the line 8 of the DC voltage VPS '. ing. Then, image data at the time of imaging and correction data at the time of resetting of each pixel output through the output signal lines 6-1, 6-2,.
[0033]
Image data and correction data are output to the sample and hold circuit 9 for each row and sampled and held. The sampled and held image data and correction data are output to the output circuit 10 for each column, and the image data is corrected based on the correction data so that noise components due to sensitivity variations are removed by the output circuit 10. The Therefore, the image data in which the sensitivity variation of each pixel is corrected is output serially from the output circuit 10 for each pixel.
[0034]
As will be described later, the pixels G11 to Gmn are provided with an N-channel MOS transistor T2 that outputs a signal based on the photocharge generated in these pixels. The connection relationship between the MOS transistor T2 and the MOS transistor Q1 is as shown in FIG. Here, the relationship between the DC voltage VPS ′ connected to the source of the MOS transistor Q1 and the DC voltage VPD ′ connected to the drain of the MOS transistor T2 is VPD ′> VPS ′, and the DC voltage VPS ′ is, for example, the ground Voltage (ground).
[0035]
In this circuit configuration, a signal is input to the gate of the upper MOS transistor T2, and a DC voltage DC is constantly applied to the gate of the lower MOS transistor Q1. Therefore, the lower MOS transistor Q1 is equivalent to a resistor or a constant current source, and the circuit of FIG. 2 is a source follower type amplifier circuit. In this case, it may be considered that a current is amplified and output from the MOS transistor T2. The configuration shown in FIGS. 1 and 2 is common to the first to sixth examples of pixels described below.
[0036]
By configuring as shown in FIG. 2, a large signal can be output. Therefore, when the pixel naturally converts the photocurrent generated from the photosensitive element to expand the dynamic range, the output signal is small as it is, but is amplified to a sufficiently large signal by this amplifier circuit. Therefore, the subsequent signal processing circuit (not shown) can be easily processed. Further, without providing the MOS transistor Q1 constituting the load resistance portion of the amplifier circuit in the pixel, output signal lines 6-1, 6-2,..., 6 to which a plurality of pixels arranged in the column direction are connected. By providing for each m, the number of load resistors or constant current sources can be reduced, and the area occupied by the amplifier circuit on the semiconductor chip can be reduced.
[0037]
<First Example of Pixel Configuration>
A first example applied to each pixel of the solid-state imaging device shown in FIG. 1 will be described with reference to the drawings. FIG. 3 is a circuit diagram showing the configuration of the pixels provided in the solid-state imaging device used in this example.
[0038]
In FIG. 3, a pn photodiode PD forms a photosensitive portion (photoelectric conversion portion). The anode of the photodiode PD is connected to the drain of the MOS transistor T4, and the source of the MOS transistor T4 is connected to the drain and gate of the MOS transistor T1 and the gate of the MOS transistor T2. The source of the MOS transistor T2 is connected to the drain of the row selection MOS transistor T3. The source of the MOS transistor T3 is connected to the output signal line 6 (the output signal line 6 corresponds to 6-1, 6-2,..., 6-m in FIG. 1). Each of the MOS transistors T1 to T4 is an N-channel MOS transistor and the back gate is grounded.
[0039]
A DC voltage VPD is applied to the cathode of the photodiode PD and the drain of the MOS transistor T2. On the other hand, the signal φVPS is applied to the source of the MOS transistor T1. The signal φS is input to the gate of the MOS transistor T4, and the signal φV is input to the gate of the MOS transistor T3. The signal φVPS is a binary voltage signal, and when the amount of incident light exceeds a predetermined value, the voltage for operating the MOS transistor T1 in the subthreshold region is VH, and the voltage lower than this voltage is used to set the MOS transistor T1. Let VL be a voltage for conducting. The operation of the pixel having such a configuration will be described below.
[0040]
As shown in the timing chart of FIG. 4, when the pulse signal φV is applied to the gate of the MOS transistor T3 and the output signal is read, first, the signal φS is set to the low level to turn off the MOS transistor T4, thereby resetting it. Perform the action. At this time, negative charges flow in from the source side of the MOS transistor T1, and the positive charges accumulated in the gate and drain of the MOS transistor T1, the gate of the MOS transistor T2, and the source of the MOS transistor T4 are recombined. Therefore, it is reset to a certain extent, and the potential of the drain and under-gate region of the MOS transistor T1 is lowered.
[0041]
As described above, the potential of the drain and gate region of the MOS transistor T1 is to be reset to the original state. However, when the potential reaches a certain value, the reset speed is reduced. This tendency is particularly noticeable when a bright subject suddenly becomes dark. Therefore, next, the signal φVPS given to the source of the MOS transistor T1 is set to VL. Thus, by lowering the source voltage of the MOS transistor T1, the amount of negative charge flowing from the source of the MOS transistor T1 increases, and the gate and drain of the MOS transistor T1, the gate of the MOS transistor T2, and the photodiode The positive charge stored on the PD anode is quickly recombined.
[0042]
After resetting with the signal φVPS set to VL in this way, the signal φVPS is set to VH, and a high level pulse signal φV is applied to the gate of the MOS transistor T3, thereby reading correction data at the time of reset. At this time, the reset gate voltage of the MOS transistor T1 is applied to the gate of the MOS transistor T2, and the gate voltage of the MOS transistor T1 is amplified by the MOS transistor T2, and is output to the output signal line 6 via the MOS transistor T3. Is output.
[0043]
Further, the drain voltage of the MOS transistor Q1 determined by the resistance of the MOS transistor T2 and the MOS transistor Q1 (FIG. 2) and the current flowing therethrough appears on the output signal line 6 as correction data. When the correction data is read out in this manner, after the MOS transistor T3 is turned off, the signal φS is set to the high level to prepare for the next imaging operation.
[0044]
When the imaging operation is started by setting the signal φS to the high level, photocharge corresponding to the amount of incident light flows from the photodiode PD into the MOS transistor T1. Now, since the MOS transistor T1 is in the cut-off state, photocharge is accumulated in the gate of the MOS transistor T1. Therefore, when the brightness of the subject to be imaged is low and the amount of incident light incident on the photodiode PD is small, a voltage corresponding to the amount of photocharge accumulated at the gate of the MOS transistor T1 appears at the gate of the MOS transistor T1, A voltage linearly proportional to the integrated value of the light quantity appears at the gate of the MOS transistor T2.
[0045]
Also, when the luminance of the object to be imaged is high and the amount of incident light entering the photodiode PD is large, and the voltage according to the amount of photocharge accumulated at the gate of the MOS transistor T1 increases, the MOS transistor T1 operates in the subthreshold region. Therefore, a voltage that is naturally logarithmically proportional to the amount of incident light appears at the gate of the MOS transistor T1.
[0046]
In this way, a voltage linearly or naturally logarithmically proportional to the amount of incident light appears at the gates of the MOS transistors T1 and T2, and, as before, by applying the pulse signal φV to the gate of the MOS transistor T3. The gate voltage of the MOS transistor T1 that is linearly or naturally logarithmically proportional to the amount of incident light is amplified by the MOS transistor T2 and output to the output signal line 6 via the MOS transistor T3. Further, the drain voltage of the MOS transistor Q1 determined by the resistance of the MOS transistor T2 and the MOS transistor Q1 and the current flowing therethrough appears on the output signal line 6 as image data.
[0047]
At this time, the amount of photoelectric charge flowing into the MOS transistor T1 before reaching the gate voltage of the MOS transistor T1 when changing to the logarithmic conversion operation becomes equal in all the pixels. In this way, since the amount of photocharge generated from the photodiode PD when the conversion operation in each pixel is switched to the logarithmic conversion operation is the same, it is incident on the photodiode PD when the conversion operation in each pixel is switched to the logarithmic conversion operation. The amount of incident light is also equal. That is, in all the pixels, the luminance of the subject becomes the same when the conversion operation is switched from the linear conversion operation to the logarithmic conversion operation, and the difference in threshold voltage of the MOS transistor T1 affects the switching of the conversion operation of each pixel. Can be reduced.
[0048]
In addition, the gate voltage of the MOS transistor T1 immediately after the reset is changed by changing the voltage value VL of the signal φVPS at the time of reset or the time for applying the signal φVPS to be the voltage value VL (corresponding to the time ta in FIG. 4). Thus, the potential between the gate and the source of the MOS transistor T1 can be changed. FIG. 5 shows the relationship between the subject luminance and the output of the solid-state imaging device when the voltage value VL is changed, and FIG. 6 shows the change in the time for applying the signal φVPS that becomes the voltage value VL. The relationship between the subject brightness and the output of the solid-state imaging device is shown.
[0049]
As the voltage value VL decreases, the potential difference between the gate and the source of the MOS transistor T1 increases, so that the ratio of subject luminance at which the MOS transistor T1 operates in the cutoff state increases. Therefore, as shown in FIG. 5, the lower the voltage value VL, the larger the ratio of subject luminance to be linearly converted. Therefore, it is understood that the voltage value VL should be lowered as the luminance range of the subject is narrow, and the voltage value VL should be increased as the luminance range of the subject is wide.
[0050]
Further, as the time ta for applying the signal φVPS having the voltage value VL becomes longer, the gate voltage of the MOS transistor T1 becomes lower and the potential difference between the gate and the source of the MOS transistor T1 becomes larger, so that the MOS transistor T1 is cut off. The ratio of the subject brightness operating in the state increases. Therefore, as shown in FIG. 6, as the time ta for applying the signal φVPS having the voltage value VL is longer, the ratio of the subject luminance to be linearly converted becomes larger. Therefore, it can be understood that the time ta for applying the signal φVPS having the voltage value VL becomes longer as the luminance range of the subject becomes narrower, and the time ta for giving the signal φVPS having the voltage value VL becomes shorter as the luminance range of the subject becomes wider. .
[0051]
<Second Example of Pixel Configuration>
A second example applied to each pixel of the solid-state imaging device shown in FIG. 1 will be described with reference to the drawings. FIG. 7 is a circuit diagram showing the configuration of the pixels provided in the solid-state imaging device used in this example. Note that elements and signal lines used for the same purpose as the pixel shown in FIG. 3 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0052]
In the pixel shown in FIG. 7, the MOS transistor T5 whose source is connected to the gate and drain connection node of the MOS transistor T1 is added to the pixel having the configuration of the first example (FIG. 3), and the MOS transistor T4 is deleted. It becomes the composition which was done. At this time, the DC voltage VPS is applied to the source of the MOS transistor T1, and the gate and drain thereof are connected to the anode of the photodiode PD. A DC voltage RL is applied to the drain of the MOS transistor T5. A signal φSW is applied to the gate of the MOS transistor T5. Other configurations are the same as those of the pixel of FIG. Note that the MOS transistor T5 is an N-channel MOS transistor, like the MOS transistors T1 to T3, and has a back gate grounded.
[0053]
As shown in the timing chart of FIG. 8, when the pulse signal φV is applied to the gate of the MOS transistor T3 and the output signal is read, first, the signal φSW is set to the high level to turn on the MOS transistor T5, thereby resetting it. Perform the action. At this time, the DC voltage RL is applied to the gate voltage of the MOS transistor T1, and negative charges flow from the drain of the MOS transistor T5. The gate and drain of the MOS transistor T1, the gate of the MOS transistor T2, and the anode of the photodiode PD The positive charges stored in the are recombined. Therefore, the MOS transistor T1 is reset, and the potential of the drain and gate region of the MOS transistor T1 is lowered.
[0054]
When reset is performed with the signal φSW at the high level as described above, the correction data at the time of reset is read by applying the high-level pulse signal φV to the gate of the MOS transistor T3. At this time, the reset gate voltage of the MOS transistor T1 is applied to the gate of the MOS transistor T2, and the gate voltage of the MOS transistor T1 is amplified by the MOS transistor T2, and is output to the output signal line 6 via the MOS transistor T3. Is output. When the correction data is read out, the signal φSW is set to the low level to turn off the MOS transistor T5 to prepare for the next imaging operation.
[0055]
In this way, when the imaging operation is started, as in the first example, when the luminance of the subject to be imaged is low and the amount of incident light entering the photodiode PD is small, the amount of photocharge accumulated at the gate of the MOS transistor T1 Therefore, a voltage linearly proportional to the integral value of the incident light quantity appears at the gate of the MOS transistor T2.
[0056]
Also, when the luminance of the object to be imaged is high and the amount of incident light entering the photodiode PD is large, and the voltage according to the amount of photocharge accumulated at the gate of the MOS transistor T1 increases, the MOS transistor T1 operates in the subthreshold region. Therefore, a voltage that is naturally logarithmically proportional to the amount of incident light appears at the gate of the MOS transistor T1.
[0057]
In this way, a voltage linearly or naturally logarithmically proportional to the amount of incident light appears at the gates of the MOS transistors T1 and T2, and, as before, by applying the pulse signal φV to the gate of the MOS transistor T3. The gate voltage of the MOS transistor T1 that is linearly or proportional to the natural logarithm with respect to the amount of incident light is amplified by the MOS transistor T2, and the image data is output to the output signal line 6 via the MOS transistor T3.
[0058]
Further, by changing the voltage value of the DC voltage RL at the time of resetting, the gate voltage of the MOS transistor T1 immediately after resetting can be changed, and the potential between the gate and source of the MOS transistor T1 can be changed.
[0059]
The lower the DC voltage RL, the greater the potential difference between the gate and source of the MOS transistor T1, and the greater the ratio of subject brightness at which the MOS transistor T1 operates in the cutoff state. Therefore, the DC voltage RL may be decreased as the luminance range of the subject is narrow, and the DC voltage RL may be increased as the luminance range of the subject is wide.
[0060]
<Third example of pixel configuration>
A third example applied to each pixel of the solid-state imaging device shown in FIG. 1 will be described with reference to the drawings. FIG. 9 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in this example. Note that elements and signal lines used for the same purpose as the pixel shown in FIG. 7 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0061]
The pixel shown in FIG. 9 has a configuration in which MOS transistors T6 and T7 each having a drain connected to the source of the MOS transistor T1 are added to the pixel having the configuration of the second example (FIG. 7). At this time, the DC voltage VPSH is applied to the source of the MOS transistor T6 and the signal φS1 is applied to the gate, and the DC voltage VPSL is applied to the source of the MOS transistor T7 and the signal φS2 is applied to the gate. Other configurations are the same as those of the pixel in FIG.
[0062]
The MOS transistors T6 and T7 are N-channel MOS transistors, and the back gates are grounded, like the MOS transistors T1 to T3 and T5. The DC voltage VPSH is a voltage for operating the MOS transistor T1 in the subthreshold region when the amount of incident light exceeds a predetermined value, and a voltage lower than this voltage to make the MOS transistor T1 conductive is VPSL. And
[0063]
As shown in the timing chart of FIG. 10, when the pulse signal φV is applied to the gate of the MOS transistor T3 and the output signal is read, first, the signal φS1 is set to the low level and the MOS transistor T6 is turned off. The signal φS2 is set to the high level, the MOS transistor T7 is turned on, and the DC voltage VPSL is applied to the source of the MOS transistor T1. Then, the reset operation is performed by setting the signal φSW to a high level and turning on the MOS transistor T5.
[0064]
At this time, the DC voltage RL is applied to the gate voltage of the MOS transistor T1, and negative charges flow from the drain of the MOS transistor T5. The gate and drain of the MOS transistor T1, the gate of the MOS transistor T2, and the anode of the photodiode PD The positive charges stored in the are recombined. Therefore, the MOS transistor T1 is reset, and the potential of the drain and gate region of the MOS transistor T1 is lowered.
[0065]
When reset is performed with the signal φSW at the high level as described above, the correction data at the time of reset is read by applying the high-level pulse signal φV to the gate of the MOS transistor T3. When the correction data is read, the signal φSW is set to a low level to turn off the MOS transistor T5. Thereafter, the signal φS1 is set to the low level to turn off the MOS transistor T6, the signal φS2 is set to the high level to turn on the MOS transistor T7, and the DC voltage VPSH is applied to the source of the MOS transistor T1 to prepare for the next imaging operation. .
[0066]
Thus, when the imaging operation is started, as in the second example, when the luminance of the subject to be imaged is low and the incident light amount incident on the photodiode PD is small, it is linearly proportional to the integral value of the incident light amount. This voltage appears at the gate of the MOS transistor T2. In addition, when the luminance of a subject to be imaged is high and the amount of incident light incident on the photodiode PD is large, and the voltage corresponding to the amount of photocharge accumulated in the gate of the MOS transistor T1 increases, A proportional voltage appears at the gate of the MOS transistor T2. Then, by applying the pulse signal φV to the gate of the MOS transistor T3, image data that is linearly or naturally logarithmically proportional to the amount of incident light is output.
[0067]
Further, by changing the voltage values of the DC voltage RL and the DC voltage VPSL at the time of resetting, the gate voltage of the MOS transistor T1 immediately after the resetting is changed, thereby changing the potential between the gate and the source of the MOS transistor T1. it can.
[0068]
As both the DC voltage RL and the DC voltage VPSL are lowered, the potential difference between the gate and the source of the MOS transistor T1 increases, so that the ratio of subject luminance at which the MOS transistor T1 operates in the cutoff state increases. Therefore, the DC voltage RL and the DC voltage VPSL may both be lowered as the subject brightness range is narrow, and both the DC voltage RL and the DC voltage VPSL may be increased as the subject brightness range is widened.
[0069]
<Fourth Example of Pixel Configuration>
A fourth example applied to each pixel of the solid-state imaging device shown in FIG. 1 will be described with reference to the drawings. FIG. 11 is a circuit diagram illustrating a configuration of a pixel provided in a solid-state imaging device used in this example. Note that elements and signal lines used for the same purpose as the pixel shown in FIG. 3 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0070]
In the pixel shown in FIG. 11, the source of the MOS transistor T4 is connected to the cathode of the photodiode PD, and the gate of the MOS transistor T2 and the source of the MOS transistor T8 are connected to the drain of the MOS transistor T4. A DC voltage VPS is applied to the anode of the photodiode PD. In the MOS transistor T8, the signal φVPD is applied to its drain and the signal φVPG is applied to its gate. Other configurations are the same as those of the pixel of the first embodiment (FIG. 3). The MOS transistor T8 is an N-channel MOS transistor, and the back gate is grounded, like the MOS transistors T2 to T4.
[0071]
The signal φVPG is a binary voltage signal, and when the incident light quantity exceeds a predetermined value, the voltage for operating the MOS transistor T4 in the subthreshold region is Va, and the voltage of the MOS transistor T4 is higher than this voltage. The voltage Vb for initializing the source voltage is used. The signal φVPD is a binary voltage signal. The higher one is a voltage higher than Vb, and the lower one is a voltage lower than Va. The operation of the pixel having such a configuration will be described below.
[0072]
As shown in the timing chart of FIG. 12, when the pulse signal φV is applied to the gate of the MOS transistor T3 and the output signal is read, first, the signal φS is set to the low level and the MOS transistor T4 is turned off. The reset operation is performed by setting the signal φVPD to the low level. Immediately after the imaging operation is finished, the MOS transistor T8 has, for example, a potential state in which the source, the lower gate region, and the drain are higher in order than the source, or a potential state in which the lower gate region, the source, and the drain are higher in this order. It is in. In any of these cases, when the signal φVPD is set to the low level, charges are injected from the drain side of the MOS transistor T8 into the region under the gate and the source of the MOS transistor T8, and the drain, the region under the gate, the source Becomes a potential corresponding to the low level of the signal φVPD. At this time, the voltage value of the signal φVPG is Va.
[0073]
Thereafter, when the signal φVPD is returned to the high level, the drain of the MOS transistor T8 becomes a potential corresponding to the high level of the signal φVPD, and the region under the gate and the source of the MOS transistor T8 correspond to the voltage value Va of the signal φVPG. It becomes potential. Further, from this state, the voltage of the signal φVPG applied to the gate of the MOS transistor T8 is switched from Va to Vb, so that the region under the gate and the source of the MOS transistor T8 have a potential corresponding to the voltage value Vb of the signal φVPG.
[0074]
Then, by applying a high level pulse signal φV to the gate of the MOS transistor T3, correction data at the time of resetting is output. At this time, the reset source voltage of the MOS transistor T8 is applied to the gate of the MOS transistor T2, and the source voltage of the MOS transistor T8 is current-amplified by the MOS transistor T2, and is output to the output signal line 6 via the MOS transistor T3. Is output.
[0075]
Then, by again switching the voltage of the signal φVPG applied to the gate of the MOS transistor T8 from Vb to Va, the region under the gate of the MOS transistor T8 has a potential corresponding to the voltage value Va of the signal φVPG. At this time, the potential of the source of the MOS transistor T8 becomes higher than the potential of the region under the gate. Thus, by operating the signals φVPD and φVPG, the potential state of the MOS transistor T8 is reset. Thereafter, the signal φS is set to a high level to prepare for the next imaging operation.
[0076]
When the imaging operation is started with the signal φS at the high level, photocharge corresponding to the amount of incident light flows into the MOS transistor T8 from the photodiode PD. Now, since the gate voltage of the MOS transistor T8 is lower than the source voltage, the MOS transistor T8 enters a cut-off state, and photocharge is accumulated in the source of the MOS transistor T8. Therefore, when the brightness of the subject to be imaged is low and the amount of incident light incident on the photodiode PD is small, a voltage corresponding to the amount of photocharge accumulated in the source of the MOS transistor T8 appears at the source of the MOS transistor T8. A voltage linearly proportional to the integrated value of the light amount appears at the source of the MOS transistor T8. At this time, since the photoelectric charge generated in the photodiode PD is a negative photoelectric charge, the source voltage of the MOS transistor T8 becomes lower as the intense light is incident.
[0077]
In addition, when the luminance of a subject to be imaged is high and the amount of incident light incident on the photodiode PD increases, the MOS transistor T8 operates in the subthreshold region. Appears in T8 source.
[0078]
In this way, when a voltage linearly or naturally logarithmically proportional to the amount of incident light appears at the gate of the MOS transistor T2, the pulse signal φV is applied to the gate of the MOS transistor T3 as before, and the incident light is incident. The source voltage of the MOS transistor T8 that is linearly or proportional to the natural logarithm with respect to the amount of light is amplified by the MOS transistor T2 and output to the output signal line 6 via the MOS transistor T3. Further, the drain voltage of the MOS transistor Q1 determined by the resistance of the MOS transistor T2 and the MOS transistor Q1 and the current flowing therethrough appears on the output signal line 6 as image data. After the image data is read in this way, the reset operation described above is performed.
[0079]
At this time, the amount of photoelectric charge flowing into the MOS transistor T8 before reaching the source voltage of the MOS transistor T8 when changing to the logarithmic conversion operation becomes equal in all the pixels. In this way, since the amount of photocharge generated from the photodiode PD when the conversion operation in each pixel is switched to the logarithmic conversion operation is the same, it is incident on the photodiode PD when the conversion operation in each pixel is switched to the logarithmic conversion operation. The amount of incident light is also equal. That is, in all the pixels, the luminance of the subject becomes the same when the conversion operation is switched from the linear conversion operation to the logarithmic conversion operation, and the difference in threshold voltage of the MOS transistor T8 has an effect on the switching of the conversion operation of each pixel. Can be reduced.
[0080]
Further, the source voltage of the MOS transistor T8 immediately after the reset is changed by changing the voltage value Vb of the signal φVPG at the time of reset or the time for applying the signal φVPG to be the voltage value Vb (corresponding to the time tb in FIG. 12). Thus, the potential between the gate and the source of the MOS transistor T8 can be changed.
[0081]
As the voltage value Vb increases, the potential difference between the gate and the source of the MOS transistor T8 increases, and therefore the proportion of subject brightness at which the MOS transistor T8 operates in the cutoff state increases. Therefore, it can be seen that the voltage value Vb should be increased as the luminance range of the subject is narrow, and the voltage value Vb should be decreased as the luminance range of the subject is wide.
[0082]
Further, as the time tb for applying the signal φVPG having the voltage value Vb becomes longer, the potential difference between the gate and the source of the MOS transistor T8 becomes larger. Therefore, the ratio of the subject luminance at which the MOS transistor T8 operates in the cutoff state increases. Become. Therefore, it can be understood that the time tb for applying the signal φVPG having the voltage value Vb is lengthened as the luminance range of the subject is narrow, and the time tb for providing the signal φVPG having the voltage value Vb is shortened as the luminance range of the subject is wide. .
[0083]
<Fifth Example of Pixel Configuration>
A fifth example applied to each pixel of the solid-state imaging device shown in FIG. 1 will be described with reference to the drawings. FIG. 13 is a circuit diagram illustrating a configuration of a pixel provided in a solid-state imaging device used in this example. Note that elements and signal lines used for the same purpose as the pixel shown in FIG. 11 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0084]
In the pixel shown in FIG. 13, a MOS transistor T9 having a drain connected to a connection node between the source of the MOS transistor T8 and the gate of the MOS transistor T2 is added to the pixel having the configuration of the fourth example (FIG. 11). The MOS transistor T4 is removed. At this time, the DC voltage VPG is applied to the gate of the MOS transistor T8, and the cathode of the photodiode PD is connected to the source. In the MOS transistor T9, the signal φSW is applied to the gate, and the DC voltage RL is applied to the source. A DC voltage VPD is applied to the drain of the MOS transistor T8. The MOS transistor T9 is an N-channel MOS transistor and the back gate is grounded, like the MOS transistors T2, T3, and T8.
[0085]
As shown in the timing chart of FIG. 14, when the pulse signal φV is applied to the gate of the MOS transistor T3 and the output signal is read, the signal φSW is set to the high level to perform the reset operation. Therefore, the DC voltage RL is applied to the source of the MOS transistor T8, and the source voltage of the MOS transistor T8 is reset by the DC voltage RL. At this time, by applying a high level pulse signal φV to the gate of the MOS transistor T3, correction data at the time of resetting is output. Then, by again setting the signal φSW to the low level, the MOS transistor T9 is turned off to prepare for the next imaging operation.
[0086]
In this way, when the imaging operation is started, as in the fourth example, when the luminance of the subject to be imaged is low and the incident light amount incident on the photodiode PD is small, it is linearly proportional to the integral value of the incident light amount. This voltage appears at the gate of the MOS transistor T2. Further, when the luminance of the object to be imaged is high and the amount of incident light incident on the photodiode PD is large, and the voltage according to the amount of photocharge accumulated in the source of the MOS transistor T8 increases, the logarithm of the incident light amount is natural logarithmically. A proportional voltage appears at the gate of the MOS transistor T2. Then, by applying the pulse signal φV to the gate of the MOS transistor T3, image data that is linearly or naturally logarithmically proportional to the amount of incident light is output.
[0087]
Further, by changing the voltage value of the DC voltage RL at the time of resetting, the source voltage of the MOS transistor T8 immediately after resetting can be changed to change the potential between the gate and source of the MOS transistor T8.
[0088]
The higher the DC voltage RL, the greater the potential difference between the gate and source of the MOS transistor T8, so the proportion of subject brightness at which the MOS transistor T8 operates in the cutoff state increases. Therefore, the DC voltage RL may be increased as the luminance range of the subject is narrow, and the DC voltage RL may be decreased as the luminance range of the subject is wide.
[0089]
<Sixth Example of Pixel Configuration>
A sixth example applied to each pixel of the solid-state imaging device shown in FIG. 1 will be described with reference to the drawings. FIG. 15 is a circuit diagram illustrating a configuration of a pixel provided in a solid-state imaging device used in this example. Note that elements and signal lines used for the same purpose as the pixel shown in FIG. 11 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0090]
The pixel shown in FIG. 13 has a configuration in which a MOS transistor T9 having a drain connected to a connection node between the source of the MOS transistor T8 and the gate of the MOS transistor T2 is added to the pixel having the configuration of the fourth example (FIG. 11). Is done. At this time, the MOS transistor T9 is supplied with the signal φSW at its gate and applied with the DC voltage RL at its source. A DC voltage VPD is applied to the drain of the MOS transistor T8. The MOS transistor T9 is an N-channel MOS transistor and the back gate thereof is grounded, like the MOS transistors T2 to T4 and T8.
[0091]
As shown in the timing chart of FIG. 16, when the pulse signal φV is applied to the gate of the MOS transistor T3 and the output signal is read, first, after the signal φS is set to the low level and the MOS transistor T4 is turned off. The signal φSW is set to the high level, the MOS transistor T9 is turned on, and the reset operation is performed. At this time, the voltage value of the signal φVPG is Va.
[0092]
Thereafter, when the signal φSW is returned to the low level and the MOS transistor T9 is turned off, the region under the gate and the source of the MOS transistor T8 have a potential corresponding to the voltage value Va of the signal φVPG. Further, from this state, the voltage of the signal φVPG applied to the gate of the MOS transistor T8 is switched from Va to Vb, so that the region under the gate and the source of the MOS transistor T8 have a potential corresponding to the voltage value Vb of the signal φVPG.
[0093]
Then, by applying a high level pulse signal φV to the gate of the MOS transistor T3, correction data at the time of resetting is output. Then, after switching the voltage of the signal φVPG applied to the gate of the MOS transistor T8 from Vb to Va, the signal φS is set to the high level to prepare for the next imaging operation.
[0094]
In this way, when the imaging operation is started, as in the fourth example, when the luminance of the subject to be imaged is low and the incident light amount incident on the photodiode PD is small, it is linearly proportional to the integral value of the incident light amount. This voltage appears at the gate of the MOS transistor T2. Further, when the luminance of the object to be imaged is high and the amount of incident light incident on the photodiode PD is large, and the voltage according to the amount of photocharge accumulated in the source of the MOS transistor T8 increases, the logarithm of the incident light amount is natural logarithmically. A proportional voltage appears at the gate of the MOS transistor T2. Then, by applying the pulse signal φV to the gate of the MOS transistor T3, image data that is linearly or naturally logarithmically proportional to the amount of incident light is output.
[0095]
Further, the source voltage of the MOS transistor T8 immediately after the reset is changed by changing the voltage value Vb of the signal φVPG at the time of resetting or the time for applying the signal φVPG that becomes the voltage value Vb (corresponding to the time tb in FIG. 16). Thus, the potential difference between the gate and source of the MOS transistor T8 can be changed. Therefore, as in the fourth example, the voltage value Vb may be increased as the subject luminance range is narrower and the voltage value Vb may be decreased as the subject luminance range is wider. As for the time tb, similarly to the fourth example, the time tb may be lengthened as the luminance range of the subject is narrow, and the time tb may be shortened as the luminance range of the subject is wide.
[0096]
<First Embodiment>
A first embodiment of an imaging apparatus having a solid-state imaging device having the pixels of each example described above will be described with reference to the drawings. FIG. 17 is a block diagram illustrating an internal configuration of the imaging apparatus according to the present embodiment.
[0097]
The image pickup device shown in FIG. 17 includes the solid-state image pickup device 100 configured as described above and having pixels that can be automatically switched from a linear conversion operation to a logarithmic conversion operation, and an output circuit 10 of the solid-state image pickup device 100 (FIG. 1). The A / D converter 101 that converts the image data corrected with the correction data output from the digital data to the digital data, the arithmetic circuit 102 that obtains the luminance distribution of the subject from the digital data from the A / D converter 101, and the arithmetic circuit 102 The reset bias supply circuit 104 for controlling the reset bias supply circuit 104 on the basis of the luminance distribution obtained in step (2), and the reset bias supply circuit for switching and supplying the bias voltage when the solid-state imaging device 102 is reset according to the control signal of the arithmetic circuit 103. 104.
[0098]
Hereinafter, in order to simplify the description, it is assumed that the solid-state imaging device 100 is a solid-state imaging device having pixels having the configuration of the first example (FIG. 3) described above. Therefore, in this embodiment, the voltage switched by the reset bias supply voltage 104 is the voltage value VL of the signal φVPS. Further, in order to measure the luminance distribution of the subject, the voltage value VL of the signal φVPS is increased once every predetermined time so that a wide luminance range can be measured. At this time, the output from the solid-state imaging device 100 is A / It is assumed that the data is converted to digital data by the D converter 101 and then sent to the arithmetic circuit 102.
[0099]
In the imaging apparatus configured as described above, when the output for luminance distribution measurement output from the solid-state imaging device 100 every predetermined time is converted into digital data by the A / D converter 101 and sent to the arithmetic circuit 102. The frequency of each luminance is obtained, and the luminance distribution is obtained. Then, the highest luminance and the lowest luminance are obtained from the obtained luminance distribution.
[0100]
At this time, whenever the digital data for each pixel sent from the A / D converter 101 is given to the arithmetic circuit 101, the digital data with the highest luminance and the digital data with the lowest luminance are obtained, Hold as luminance and minimum luminance. Then, compare the digital data value of the next given pixel with the digital data value held as the maximum luminance and the minimum luminance, respectively, and if it is higher than the maximum luminance, the maximum luminance instead of the maximum luminance held If the luminance is lower than the lowest luminance, the luminance is held as the lowest luminance instead of the lowest luminance held. Further, when the luminance is lower than the highest luminance and higher than the lowest luminance, the held highest luminance and the lowest luminance are held as they are.
[0101]
Thus, when the arithmetic circuit 102 obtains the maximum luminance and the minimum luminance in the luminance distribution of the subject from the digital data for one field, the obtained maximum luminance and the minimum luminance are sent to the arithmetic circuit 103. The arithmetic circuit 103 first obtains the luminance range of the subject by obtaining the difference between the given maximum luminance and the minimum luminance. A control signal for controlling the reset bias supply circuit 104 is sent out according to the obtained luminance range.
[0102]
That is, when the arithmetic circuit 103 determines that the difference between the maximum luminance and the minimum luminance is large and the luminance range of the subject is wide, the potential state of the MOS transistor T1 is switched to the logarithmic conversion operation with low luminance. Therefore, a control signal for increasing the voltage value VL of the reset signal φVPS is sent to the reset bias supply circuit 104. On the contrary, when the difference between the maximum luminance and the minimum luminance is small and the luminance range of the subject is determined to be narrow, the potential state of the MOS transistor T1 is determined so that the switching to the logarithmic conversion operation is performed with high luminance. Then, a control signal for lowering the voltage value VL of the signal φVPS at the time of resetting is sent to the reset bias supply circuit 104.
[0103]
Therefore, if the arithmetic circuit 103 determines that the luminance range is wide, the reset bias supply circuit 104 sets the voltage value VL of the reset signal φVPS to a low value until it is determined that the luminance range is next narrow. And supplied to the solid-state imaging device 100. If the arithmetic circuit 103 determines that the luminance range is narrow, the reset bias supply circuit 104 sets the voltage value VL of the reset signal φVPS to a high value until it is determined that the luminance range is next wide. And supplied to the solid-state imaging device 100. This luminance range is compared with a threshold value in a plurality of stages, and the voltage value VL of the reset signal φVPS supplied from the reset bias supply circuit 104 is switched according to the threshold value range including the value. .
[0104]
<Second Embodiment>
A second embodiment of an imaging apparatus having a solid-state imaging device having the pixels of each example described above will be described with reference to the drawings. FIG. 18 is a block diagram illustrating an internal configuration of the imaging apparatus according to the present embodiment. In the imaging apparatus of FIG. 18, parts used for the same purpose as those of the imaging apparatus shown in FIG. 17 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0105]
The imaging apparatus in FIG. 18 has a configuration in which a timing generator 105 is provided instead of the reset bias supply circuit 104 in the imaging apparatus of the first embodiment (FIG. 17). The timing generator 105 determines the timing of each signal given to each pixel of the solid-state imaging device 100. In addition, the timing generator 105 switches the time for applying a bias voltage to each pixel at the time of reset in each of the above-described examples. In addition, about the other blocks 100-103, while the connection relationship is the same as that of 1st Embodiment, it becomes the same also about the operation | movement.
[0106]
Hereinafter, in order to simplify the description, it is assumed that the solid-state imaging device 100 is a solid-state imaging device having pixels having the configuration of the above-described first example (FIG. 3), as in the first embodiment. To do. Therefore, in the present embodiment, at the time of resetting, the voltage of the signal φVPS is switched to the voltage value VL. Further, in order to measure the luminance distribution of the object, the time ta (FIG. 4) for applying the voltage value VL of the signal φVPS at the time of reset is shortened once every predetermined time, and a wide luminance range can be measured. Assume that the output from the solid-state imaging device 100 is converted into digital data by the A / D converter 101 and then sent to the arithmetic circuit 102.
[0107]
According to the imaging apparatus configured as described above, as in the first embodiment, the image data output from the solid-state imaging device 100 is converted into digital data by the A / D converter 101, and is equivalent to one field every predetermined time. When given to the arithmetic circuit 102, the maximum luminance and the minimum luminance of the subject are obtained and sent to the arithmetic circuit 103. Then, the arithmetic circuit 103 obtains the luminance range of the luminance distribution of the subject from the difference between the transmitted maximum luminance and minimum luminance. The arithmetic circuit 103 gives a control signal corresponding to the width of the luminance range to the timing generator 105.
[0108]
That is, when the arithmetic circuit 103 determines that the difference between the maximum luminance and the minimum luminance is large and the luminance range of the subject is wide, the potential state of the MOS transistor T1 is switched to the logarithmic conversion operation with low luminance. Therefore, a control signal is sent to the timing generator 105 to shorten the time ta for applying the voltage value VL of the signal φVPS at the time of reset. On the contrary, when the difference between the maximum luminance and the minimum luminance is small and the luminance range of the subject is determined to be narrow, the potential state of the MOS transistor T1 is determined so that the switching to the logarithmic conversion operation is performed with high luminance. Then, a control signal is sent to the timing generator 105 so as to lengthen the time ta for applying the voltage value VL of the signal φVPS at the time of reset.
[0109]
Therefore, when the arithmetic circuit 103 determines that the luminance range is wide, the timing generator 105 sets the time ta to apply the voltage value VL of the signal φVPS at the reset time until it is determined that the luminance range is next narrow. Thus, the voltage VL of the signal φVPS is supplied to the solid-state imaging device 100. If the arithmetic circuit 103 determines that the luminance range is narrow, the timing generator 105 sets the time ta to apply the voltage value VL of the reset signal φVPS until the next determination that the luminance range is wide. Thus, the voltage value VL of the signal φVPS is supplied to the solid-state imaging device 100. As in the first embodiment, this luminance range is compared with a threshold value of a plurality of stages, and the reset signal φVPS supplied from the timing generator 105 is compared with the threshold value range including the value. The time ta for giving the voltage value VL is switched.
[0110]
Further, the reset signal φVPS given from the timing generator 105 may be given as a plurality of pulse signals as shown in FIG. 19 instead of one pulse signal as shown in FIG. At this time, if the arithmetic circuit 103 determines that the luminance range is wide, the timing generator 105 sets the number of occurrences of the pulse signal φVPS of the voltage value VL at the time of reset until it is determined that the luminance range is next narrow. And supplied to the solid-state imaging device 100. If the arithmetic circuit 103 determines that the luminance range is narrow, the timing generator 105 sets the number of occurrences of the pulse signal φVPS at the reset voltage value VL until the next determination that the luminance range is wide. And supplied to the solid-state imaging device 100.
[0111]
【The invention's effect】
According to the present invention, it is possible to adjust the dynamic range of the output from the solid-state imaging device by adjusting the potential state of the transistor without each pixel provided in the solid-state imaging device according to the luminance of the subject. Therefore, unlike the conventional case, the dynamic range is adjusted by adjusting the digital data, and the bit loss of the digital data can be prevented. Therefore, the dynamic range of the luminance distribution of the subject can be adjusted without degrading the gradation. Therefore, high-definition image data corresponding to the luminance distribution of the subject can be obtained.
[Brief description of the drawings]
FIG. 1 is a block circuit diagram showing a configuration of a solid-state image sensor.
2 is a circuit diagram showing a part of the solid-state imaging device of FIG. 1;
3 is a circuit diagram showing an example of a pixel configuration in the solid-state imaging device of FIG. 1. FIG.
4 is a timing chart showing the operation of the pixel having the configuration shown in FIG. 3;
FIG. 5 is a graph showing the relationship between the luminance of a subject and the output of a solid-state image sensor.
FIG. 6 is a graph showing the relationship between the luminance of a subject and the output of a solid-state image sensor.
7 is a circuit diagram showing an example of a pixel configuration in the solid-state imaging device of FIG. 1;
8 is a timing chart showing the operation of the pixel having the configuration shown in FIG.
9 is a circuit diagram showing an example of a pixel configuration in the solid-state imaging device of FIG. 1. FIG.
10 is a timing chart showing the operation of the pixel having the configuration shown in FIG. 9;
11 is a circuit diagram illustrating an example of a pixel configuration in the solid-state imaging device of FIG. 1;
12 is a timing chart showing the operation of the pixel having the configuration shown in FIG.
13 is a circuit diagram showing an example of a pixel configuration in the solid-state imaging device of FIG. 1. FIG.
14 is a timing chart showing the operation of the pixel having the configuration shown in FIG.
15 is a circuit diagram showing an example of a pixel configuration in the solid-state image sensor of FIG. 1;
16 is a timing chart showing the operation of the pixel having the configuration shown in FIG.
FIG. 17 is a block diagram showing an internal configuration of the imaging apparatus according to the first embodiment.
FIG. 18 is a block diagram showing an internal configuration of the imaging apparatus according to the second embodiment.
FIG. 19 is a timing chart showing the operation of the pixel having the configuration of FIG. 3;
[Explanation of symbols]
100 Solid-state image sensor
101 A / D converter
102 Arithmetic circuit
103 arithmetic circuit
104 Reset bias supply circuit
105 Timing generator

Claims (7)

A first state that includes a photosensitive element that outputs an electrical signal corresponding to the amount of incident light and a transistor that is supplied with the electrical signal from the photosensitive element, and logarithmically converts the electrical signal corresponding to the amount of incident light that is linearly converted and output. In an imaging apparatus having a solid-state imaging device composed of a plurality of pixels that can be automatically switched between a second state to be output,
The potential state of the transistor immediately after the reset, have a bias adjustment portion that changes according to the state of the luminance distribution of the subject to be imaged by the solid-state image pickup element,
The imaging apparatus , wherein the bias adjusting unit adjusts the potential state of the transistor immediately after resetting by switching a length of time for applying a bias voltage to be applied to the transistor at the time of resetting . A first state that includes a photosensitive element that outputs an electrical signal corresponding to the amount of incident light and a transistor that is supplied with the electrical signal from the photosensitive element, and logarithmically converts the electrical signal corresponding to the amount of incident light that is linearly converted and output. In an imaging apparatus having a solid-state imaging device composed of a plurality of pixels that can be automatically switched between a second state to be output,
A bias adjusting unit that changes a potential state of the transistor immediately after reset according to a state of a luminance distribution of a subject imaged by the solid-state imaging device;
The pixel is
A photodiode having a DC voltage applied to the first electrode, and the photosensitive element;
A MOS transistor for connecting the first electrode and the gate electrode to the second electrode of the photodiode and outputting an electric signal from the gate electrode;
Have
By the bias adjustment unit,
When the luminance range of the luminance distribution of the subject is narrow, the potential state of the MOS transistor immediately after reset is adjusted so that the potential difference between the gate electrode and the second electrode of the MOS transistor is increased. ,
When the luminance range of the luminance distribution of the subject is wide, the potential state of the MOS transistor immediately after the reset is adjusted so that the potential difference between the gate electrode and the second electrode of the MOS transistor is small.
By switching the voltage applied to the second electrode of the MOS transistor, the pixel is reset,
The image pickup apparatus, wherein the bias adjustment unit adjusts a potential state of the MOS transistor immediately after the reset by adjusting a time for switching a voltage value applied to the second electrode of the MOS transistor at the time of reset. A first state that includes a photosensitive element that outputs an electrical signal corresponding to the amount of incident light and a transistor that is supplied with the electrical signal from the photosensitive element, and logarithmically converts the electrical signal corresponding to the amount of incident light that is linearly converted and output. In an imaging apparatus having a solid-state imaging device composed of a plurality of pixels that can be automatically switched between a second state to be output,
A bias adjusting unit that changes a potential state of the transistor immediately after reset according to a state of a luminance distribution of a subject imaged by the solid-state imaging device;
The pixel is
A photodiode having a DC voltage applied to the first electrode, and the photosensitive element;
A MOS transistor for connecting the first electrode and the gate electrode to the second electrode of the photodiode and outputting an electric signal from the gate electrode;
Have
By the bias adjustment unit,
When the luminance range of the luminance distribution of the subject is narrow, the potential state of the MOS transistor immediately after reset is adjusted so that the potential difference between the gate electrode and the second electrode of the MOS transistor is increased. ,
When the luminance range of the luminance distribution of the subject is wide, the potential state of the MOS transistor immediately after the reset is adjusted so that the potential difference between the gate electrode and the second electrode of the MOS transistor is reduced,
By switching the voltage applied to the gate electrode and the second electrode of the MOS transistor, the pixel is reset,
The imaging apparatus, wherein the bias adjusting unit adjusts a potential value of the MOS transistor immediately after resetting by adjusting a voltage value applied to the gate electrode and the second electrode of the MOS transistor at resetting. A first state that includes a photosensitive element that outputs an electrical signal corresponding to the amount of incident light and a transistor that is supplied with the electrical signal from the photosensitive element, and logarithmically converts the electrical signal corresponding to the amount of incident light that is linearly converted and output. In an imaging apparatus having a solid-state imaging device composed of a plurality of pixels that can be automatically switched between a second state to be output,
A bias adjusting unit that changes a potential state of the transistor immediately after reset according to a state of a luminance distribution of a subject imaged by the solid-state imaging device;
The pixel is
A photodiode in which a direct-current voltage is applied to the second electrode;
A MOS transistor connected to the first electrode of the photodiode and connected to the second electrode and outputting an electric signal from the second electrode;
Have
By the bias adjustment unit,
When the luminance range of the luminance distribution of the subject is narrow, the potential state of the MOS transistor immediately after reset is adjusted so that the potential difference between the gate electrode and the second electrode of the MOS transistor is increased. ,
When the luminance range of the luminance distribution of the subject is wide, the potential state of the MOS transistor immediately after the reset is adjusted so that the potential difference between the gate electrode and the second electrode of the MOS transistor is reduced,
By switching the voltage applied to each of the first electrode and the gate electrode of the MOS transistor, the pixel is reset,
The imaging apparatus, wherein the bias adjusting unit adjusts a potential value of the MOS transistor immediately after resetting by adjusting a voltage value applied to the gate electrode of the MOS transistor at resetting. A first state that includes a photosensitive element that outputs an electrical signal corresponding to the amount of incident light and a transistor that is supplied with the electrical signal from the photosensitive element, and logarithmically converts the electrical signal corresponding to the amount of incident light that is linearly converted and output. In an imaging apparatus having a solid-state imaging device composed of a plurality of pixels that can be automatically switched between a second state to be output,
A bias adjusting unit that changes a potential state of the transistor immediately after reset according to a state of a luminance distribution of a subject imaged by the solid-state imaging device;
The pixel is
A photodiode in which a direct-current voltage is applied to the second electrode;
A MOS transistor connected to the first electrode of the photodiode and connected to the second electrode and outputting an electric signal from the second electrode;
Have
By the bias adjustment unit,
When the luminance range of the luminance distribution of the subject is narrow, the potential state of the MOS transistor immediately after reset is adjusted so that the potential difference between the gate electrode and the second electrode of the MOS transistor is increased. ,
When the luminance range of the luminance distribution of the subject is wide, the potential state of the MOS transistor immediately after the reset is adjusted so that the potential difference between the gate electrode and the second electrode of the MOS transistor is reduced,
  By switching the voltage applied to each of the first electrode and the gate electrode of the MOS transistor, the pixel is reset,
The image pickup apparatus, wherein the bias adjusting unit adjusts a potential state of the MOS transistor immediately after the reset by adjusting a time for switching a voltage value applied to the gate electrode of the MOS transistor at the time of reset. A first state that includes a photosensitive element that outputs an electrical signal corresponding to the amount of incident light and a transistor that is supplied with the electrical signal from the photosensitive element, and logarithmically converts the electrical signal corresponding to the amount of incident light that is linearly converted and output. In an imaging apparatus having a solid-state imaging device composed of a plurality of pixels that can be automatically switched between a second state to be output,
A bias adjusting unit that changes a potential state of the transistor immediately after reset according to a state of a luminance distribution of a subject imaged by the solid-state imaging device;
The pixel is
A photodiode in which a direct-current voltage is applied to the second electrode;
A MOS transistor connected to the first electrode of the photodiode and connected to the second electrode and outputting an electric signal from the second electrode;
Have
By the bias adjustment unit,
When the luminance range of the luminance distribution of the subject is narrow, the potential state of the MOS transistor immediately after reset is adjusted so that the potential difference between the gate electrode and the second electrode of the MOS transistor is increased. ,
When the luminance range of the luminance distribution of the subject is wide, the potential state of the MOS transistor immediately after the reset is adjusted so that the potential difference between the gate electrode and the second electrode of the MOS transistor is reduced,
By switching the voltage applied to the gate electrode and the second electrode of the MOS transistor, the pixel is reset,
The imaging apparatus, wherein the bias adjusting unit adjusts a potential value of the MOS transistor immediately after resetting by adjusting a voltage value applied to the gate electrode of the MOS transistor at resetting. A first state that includes a photosensitive element that outputs an electrical signal corresponding to the amount of incident light and a transistor that is supplied with the electrical signal from the photosensitive element, and logarithmically converts the electrical signal corresponding to the amount of incident light that is linearly converted and output. In an imaging apparatus having a solid-state imaging device composed of a plurality of pixels that can be automatically switched between a second state to be output,
A bias adjusting unit that changes a potential state of the transistor immediately after reset according to a state of a luminance distribution of a subject imaged by the solid-state imaging device;
The pixel is
A photodiode in which a direct-current voltage is applied to the second electrode;
A MOS transistor connected to the first electrode of the photodiode and connected to the second electrode and outputting an electric signal from the second electrode;
Have
By the bias adjustment unit,
When the luminance range of the luminance distribution of the subject is narrow, the potential state of the MOS transistor immediately after reset is adjusted so that the potential difference between the gate electrode and the second electrode of the MOS transistor is increased. ,
When the luminance range of the luminance distribution of the subject is wide, the potential state of the MOS transistor immediately after the reset is adjusted so that the potential difference between the gate electrode and the second electrode of the MOS transistor is reduced,
By switching the voltage applied to the gate electrode and the second electrode of the MOS transistor, the pixel is reset,
The image pickup apparatus, wherein the bias adjusting unit adjusts a potential state of the MOS transistor immediately after the reset by adjusting a time for switching a voltage value applied to the gate electrode of the MOS transistor at the time of reset.

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