JP2002300476A - Imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an imaging device, which can match a dynamic range of a subject with a dynamic range of a solid-state imaging element, without degradation. SOLUTION: When a maximum luminance and a minimum luminance of a subject are computed by an arithmetic circuit 103, based on the digital data outputted from an A/D converter 101, the luminance range of the subject is computed by the arithmetic circuit 103, and a reset bias supply circuit 104 is controlled according to the luminance range. Then, bias voltage applied to each pixel of a solid-state imaging element 100 during reset is adjusted by the reset bias supply circuit 104.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a first state in which an electric signal that changes linearly with respect to the amount of incident light is output, and a second state in which an electric signal that changes in a natural logarithm with respect to the amount of incident light is output. The present invention relates to an imaging device having a solid-state imaging device that can be switched between the two.

[0002]

2. Description of the Related Art Conventionally, the dynamic range of a solid-state imaging device that performs linear conversion on the amount of incident light is as narrow as two digits. Is not output. On the other hand, a solid-state imaging device that performs logarithmic conversion on the incident light amount has a dynamic range as wide as 5 to 6 digits. All luminance information in the distribution can be converted into an electric signal and output.

However, since the brightness range of a subject is generally about 2 to 3 digits, in the case of a solid-state imaging device which performs logarithmic conversion with a dynamic range of 5 to 6 digits,
Since the imageable area becomes wider with respect to the luminance distribution of the subject, an area without luminance data is generated in a low luminance area or a high luminance area in the imageable area. Therefore, when the image of the subject having the luminance distribution is reproduced using the electric signal from the solid-state imaging device to be logarithmically converted, the black with the minimum luminance is reproduced as dark gray, and the white with the maximum luminance is reproduced as light gray. In some cases, an image with insufficient contrast may be reproduced.

In order to solve such a problem, an electric signal output from a solid-state imaging device is converted into a digital signal, and then a luminance distribution is measured. A method has been proposed in which the value of a digital signal is converted so that the maximum value of the luminance distribution matches the maximum value of the dynamic range of the digital output so that the luminance distribution matches the dynamic range of the digital output.

[0005]

As described above, by processing the digital signal obtained by digitally converting the output from the solid-state image sensor, the luminance distribution of the subject and the output from the solid-state image sensor can be obtained by digital conversion. When the dynamic range of the digital output is matched, bit dropout occurs in the digital output, and as a result, the gradation is lowered. Therefore, the change in luminance of the reproduced image may be unsteady, and the smoothness may be lost.

In view of such a problem, the present invention increases the dynamic range of a subject without reducing gradation.
An object of the present invention is to provide an imaging device that can be adapted to a dynamic range of a solid-state imaging device.

[0007]

According to a first aspect of the present invention, there is provided an image pickup apparatus comprising: a photosensitive element for outputting an electric signal corresponding to an amount of incident light; and an electric signal from the photosensitive element. A solid-state imaging device having a plurality of pixels that has a transistor and that can automatically switch between a first state in which linear conversion is performed and output and a second state in which an electric signal corresponding to an incident light amount is logarithmically converted and output; And a bias adjustment unit that changes a potential state of the transistor immediately after reset according to a state of a luminance distribution of a subject imaged by the solid-state imaging element.

In such an image pickup apparatus, when the luminance distribution of a subject is wide, the potential state of the transistor at the time of reset is adjusted so that the transistor can operate in a sub-threshold region with low luminance. When the luminance distribution of the subject is narrow, the potential state of the transistor at the time of reset is adjusted so that the transistor can operate in a cutoff state up to high luminance.

At this time, as set forth in claim 2, at the time of resetting, by switching the value of the bias voltage applied to the transistor, the bias adjusting section adjusts the potential state of the transistor immediately after resetting. It does not matter. According to a third aspect of the present invention, the bias adjusting unit adjusts the potential state of the transistor immediately after reset by switching the length of time for applying a bias voltage to the transistor at the time of reset. No problem.

According to a fourth aspect of the present invention, in the imaging device of the first aspect, the pixel serves as the photosensitive element, and a photodiode in which a DC voltage is applied to a first electrode; The first electrode of the diode
An MOS transistor connected to the electrode and the gate electrode and outputting an electric signal from the gate electrode, wherein the bias adjustment unit controls the gate of the MOS transistor when a luminance range of the luminance distribution of the subject is narrow. The potential state of the MOS transistor immediately after reset is adjusted so that the potential difference between the electrode and the second electrode increases, and when the luminance range of the luminance distribution of the subject is wide, The potential state of the MOS transistor immediately after reset is adjusted so that the potential difference between the gate electrode and the second electrode is reduced.

In such an image pickup apparatus, the pixel is reset by switching a voltage applied to the second electrode of the MOS transistor, and the bias adjustment unit causes the bias adjustment unit to reset the M at the time of reset.
The potential state of the MOS transistor immediately after reset may be adjusted by adjusting the voltage value applied to the second electrode of the OS transistor.

At this time, assuming that the MOS transistor is an N-channel MOS transistor, when the luminance range of the subject is wide, the second of the MOS transistors at the time of resetting is used.
When the voltage value applied to the electrodes is set high and the brightness range of the subject is narrow, the second
Set the voltage value applied to the electrodes low.

Further, as described in claim 6, the MO
The pixel is reset by switching the voltage applied to the second electrode of the S transistor, and the bias adjusting unit adjusts the time for switching the voltage applied to the second electrode of the MOS transistor at the time of reset, thereby immediately after the reset. The potential state of the MOS transistor may be adjusted.

At this time, assuming that the MOS transistor is an N-channel MOS transistor, if the luminance range of the subject is wide, the second
The time for switching the voltage value applied to the electrode is set short, and when the luminance range of the subject is narrow, the time for switching the voltage value applied to the second electrode of the MOS transistor at the time of reset is set long.

Further, as set forth in claim 7, the MO
By switching the voltage applied to the gate electrode of the S transistor, the pixel is reset, and the bias adjusting unit adjusts the voltage value applied to the gate electrode of the MOS transistor at the time of reset, so that the MOS transistor immediately after reset is reset. The potential state may be adjusted.

At this time, assuming that the MOS transistor is an N-channel MOS transistor, when the luminance range of the subject is wide, the voltage value applied to the gate electrode of the MOS transistor at the time of reset is set high, and when the luminance range of the subject is narrow, The voltage value applied to the gate electrode of the MOS transistor at the time of reset is set low.

Further, as set forth in claim 8, the MO
By switching the voltage applied to the gate electrode and the second electrode of the S transistor, the pixel is reset,
The bias adjuster may adjust the voltage value applied to the gate electrode and the second electrode of the MOS transistor at the time of reset to adjust the potential state of the MOS transistor immediately after reset.

At this time, assuming that the MOS transistor is an N-channel MOS transistor, when the luminance range of the object is wide, the voltage value applied to the gate electrode and the second electrode of the MOS transistor at the time of reset is set high, and the luminance range of the object Is small, the voltage value applied to the gate electrode and the second electrode of the MOS transistor at the time of reset is set low.

According to a ninth aspect of the present invention, in the imaging device of the first aspect, the pixel serves as the photosensitive element, and a photodiode in which a DC voltage is applied to a second electrode; The second electrode of the diode
A MOS transistor connected to the electrode and outputting an electric signal from the second electrode, wherein the bias adjusting unit is configured to connect the gate electrode of the MOS transistor to a gate electrode of the MOS transistor when the luminance range of the luminance distribution of the subject is narrow. The potential state of the MOS transistor immediately after reset is adjusted so that the potential difference between the two electrodes increases, and when the luminance range of the luminance distribution of the subject is wide, the gate electrode of the MOS transistor is connected to the gate electrode of the MOS transistor. The potential state of the MOS transistor immediately after reset is adjusted so that the potential difference between the MOS transistor and the second electrode is reduced.

[0020] In such an image pickup apparatus, a tenth aspect is provided.
By switching the voltage applied to each of the first electrode and the gate electrode of the MOS transistor, the pixel is reset, and the bias adjustment unit adjusts the voltage value applied to the gate electrode of the MOS transistor at the time of reset. By adjusting the potential, the potential state of the MOS transistor immediately after the reset may be adjusted.

At this time, assuming that the MOS transistor is an N-channel MOS transistor, when the luminance range of the subject is wide, the voltage value applied to the gate electrode of the MOS transistor at the time of reset is set low, and when the luminance range of the subject is narrow, At the time of reset, the voltage value applied to the gate electrode of the MOS transistor is set high.

Further, as described in claim 11, the M
By switching the voltage applied to each of the first electrode and the gate electrode of the OS transistor, the pixel is reset, and the bias adjustment unit resets the M
By adjusting the time for switching the voltage value applied to the gate electrode of the OS transistor, the potential state of the MOS transistor immediately after resetting may be adjusted.

At this time, assuming that the MOS transistor is an N-channel MOS transistor, when the luminance range of the object is wide, the time for switching the voltage applied to the gate electrode of the MOS transistor at the time of reset is set short.
When the brightness range of the subject is narrow, the MOS
The time for switching the voltage applied to the gate electrode of the transistor is set to be long.

Further, as described in claim 12, the M
A DC voltage is applied to a first electrode and a gate electrode of the OS transistor, and a second voltage of the MOS transistor
By switching the voltage applied to the electrode, the pixel is reset, and the bias adjustment unit adjusts the voltage applied to the second electrode of the MOS transistor at the time of reset, thereby changing the potential state of the MOS transistor immediately after reset. It may be adjusted.

At this time, assuming that the MOS transistor is an N-channel MOS transistor, when the luminance range of the subject is wide, the second
When the voltage value applied to the electrode is set low and the brightness range of the subject is narrow, the second
Set a high voltage value to be applied to the electrodes.

Further, as described in claim 13, the M
By switching the voltage applied to the gate electrode and the second electrode of the OS transistor, the pixel is reset, and the bias adjustment unit adjusts the voltage applied to the gate electrode of the MOS transistor at the time of reset, thereby immediately after the reset. The potential state of the MOS transistor may be adjusted.

At this time, assuming that the MOS transistor is an N-channel MOS transistor, when the luminance range of the subject is wide, the voltage value applied to the gate electrode of the MOS transistor at the time of reset is set low, and when the luminance range of the subject is narrow, At the time of reset, the voltage value applied to the gate electrode of the MOS transistor is set high.

Also, as described in claim 14, the M
By switching the voltage applied to the gate electrode and the second electrode of the OS transistor, the pixel is reset, and the bias adjustment unit adjusts the time for switching the voltage applied to the gate electrode of the MOS transistor at the time of resetting. The MOS immediately after reset
The potential state of the transistor may be adjusted.

At this time, assuming that the MOS transistor is an N-channel MOS transistor, when the luminance range of the subject is wide, the time for switching the voltage applied to the gate electrode of the MOS transistor at the time of reset is set short.
When the brightness range of the subject is narrow, the MOS
The time for switching the voltage applied to the gate electrode of the transistor is set to be long.

[0030]

Embodiments of the present invention will be described below.

<Structural Example of Solid-State Image Sensor> First, a structural example of a solid-state image sensor provided in the image pickup apparatus of the present invention will be described. FIG. 1 schematically shows a configuration of a part of a two-dimensional MOS type solid-state imaging device according to the present invention. In the figure, G11 to Gmn indicate pixels arranged in a matrix (matrix arrangement). Reference numeral 2 denotes a vertical scanning circuit which sequentially scans rows (lines) 4-1, 4-2,..., 4-n.
Reference numeral 3 denotes a horizontal scanning circuit, which outputs an output signal line 6-1 from a pixel;
The photoelectric conversion signals derived in 6-2,..., 6-m are sequentially read in the horizontal direction for each pixel. 5 is a power supply line. .., 4-n, the output signal lines 6-1, 6-2,.
As well as other lines (eg clock line etc.)
Are also connected, but these are omitted in FIG.

The output signal lines 6-1, 6-2,.
As shown, one set of N-channel MOS transistors Q1 is provided for each m. Taking the output signal line 6-1 as an example, the gate of the MOS transistor Q1 is connected to the DC voltage line 7, and the drain is connected to the output signal line 6-1.
And the source is connected to line 8 of the DC voltage VPS '. The output signal lines 6-1, 6-2,.
The image data at the time of imaging of each pixel and the correction data at the time of reset, which are output through 6-m, are sequentially supplied to the sample and hold circuit 9.

Image data and correction data are output to the sample and hold circuit 9 for each row and sampled and held. The sampled and held image data and correction data are output to the output circuit 10 for each column, and the output circuit 10 corrects the image data based on the correction data such that noise components due to sensitivity variations are removed. You. Therefore, the output circuit 10 serially outputs the image data in which the sensitivity variation of each pixel is corrected for each pixel.

As described later, the pixels G11 to Gmn have
An N-channel MOS transistor T2 for outputting a signal based on the photocharge generated in those pixels is provided. The connection relationship between the MOS transistor T2 and the MOS transistor Q1 is as shown in FIG. Where MOS
DC voltage VPS 'connected to the source of transistor Q1
And the DC voltage VPD 'connected to the drain of the MOS transistor T2 is VPD'> VPS ', and the DC voltage VPS' is, for example, a ground voltage (ground).

In this circuit configuration, a signal is input to the gate of the upper MOS transistor T2, and a DC voltage DC is constantly applied to the gate of the lower MOS transistor Q1.
Therefore, the lower-stage MOS transistor Q1 is equivalent to a resistor or a constant current source, and the circuit of FIG. 2 is a source follower-type amplifier circuit. In this case, what is amplified and output from the MOS transistor T2 may be a current.
The configurations shown in FIGS. 1 and 2 are common to the first to sixth examples of the pixel described below.

With the configuration shown in FIG. 2, a large signal can be output. Therefore, when the pixel converts the photocurrent generated from the photosensitive element in a natural logarithmic manner to expand the dynamic range, the output signal is small as it is, but is amplified to a sufficiently large signal by the amplifier circuit. Therefore, processing in a subsequent signal processing circuit (not shown) is facilitated. Further, the MOS transistor Q1 forming the load resistance portion of the amplifier circuit is not provided in the pixel, and the output signal line 6 to which a plurality of pixels arranged in the column direction are connected is connected.
, 6-2,..., 6-m, the number of load resistances or constant current sources can be reduced, and the area occupied by the amplifier circuit on the semiconductor chip can be reduced.

<First Example of Pixel Configuration> A first example applied to each pixel of the solid-state imaging device shown in FIG. 1 will be described with reference to the drawings. FIG. 3 is a circuit diagram illustrating a configuration of a pixel provided in a solid-state imaging device used in the present example.

In FIG. 3, a pn photodiode PD
Form a photosensitive portion (photoelectric conversion portion). The anode of the photodiode PD is connected to the drain of the MOS transistor T4, and the source of the MOS transistor T4 is connected to the drain and gate of the MOS transistor T1 and the gate of the MOS transistor T2. M
The source of the OS transistor T2 is connected to the drain of the row selection MOS transistor T3. The source of the MOS transistor T3 is connected to an output signal line 6 (the output signal line 6 corresponds to 6-1 to 6-m in FIG. 1). The MOS transistors T1 to T4
Are N-channel MOS transistors each having a back gate grounded.

The DC voltage VPD is applied to the cathode of the photodiode PD and the drain of the MOS transistor T2. On the other hand, signal φVPS is applied to the source of MOS transistor T1. Also, M
The signal φS is input to the gate of the OS transistor T4,
Signal φV is input to the gate of MOS transistor T3. The signal φVPS is a binary voltage signal, and the voltage for operating the MOS transistor T1 in the sub-threshold region when the amount of incident light exceeds a predetermined value is VH.
A voltage lower than this voltage for turning on the MOS transistor T1 is VL. The operation of the pixel having such a configuration will be described below.

As shown in the timing chart of FIG.
When pulse signal φV is applied to the gate of MOS transistor T3 and the output signal is read, first, signal φS
To a low level to turn off the MOS transistor T4, thereby performing a reset operation. At this time, a negative charge flows from the source side of the MOS transistor T1, and M
The gate and drain of the OS transistor T1, the gate of the MOS transistor T2, and the MOS transistor T
The positive charges stored at the source of No. 4 recombine. Therefore, the potential is reset to a certain extent, and the potential of the region under the drain and the gate of the MOS transistor T1 decreases.

As described above, the potential of the region under the drain and the gate of the MOS transistor T1 is about to be reset to the original state. However, when the potential reaches a certain value, the speed of resetting is reduced. In particular, this tendency becomes remarkable when a bright subject suddenly becomes dark. Therefore, next, the signal φVPS given to the source of the MOS transistor T1 is set to VL. Thus, by lowering the source voltage of the MOS transistor T1,
The amount of negative charges flowing from the source of the MOS transistor T1 increases, and the positive charges stored in the gate and drain of the MOS transistor T1, the gate of the MOS transistor T2, and the anode of the photodiode PD are quickly recombined. You.

After resetting the signal φVPS to VL in this manner, by setting the signal φVPS to VH and applying a high-level pulse signal φV to the gate of the MOS transistor T3, the correction data at the time of reset is read. At this time, the reset gate voltage of the MOS transistor T1 is applied to the gate of the MOS transistor T2, and the gate voltage of the MOS transistor T1 is current-amplified by the MOS transistor T2 and is applied to the output signal line 6 via the MOS transistor T3. Is output.

The drain voltage of the MOS transistor Q1, which is determined by the resistance of the MOS transistor T2 and the MOS transistor Q1 (FIG. 2) during conduction and the current flowing through them, appears on the output signal line 6 as correction data. When the correction data is read in this way, the MOS transistor T3 is turned off, and then the signal φS is set to the high level to prepare for the next imaging operation.

When the signal φS is set to the high level to start the image pickup operation, a photocharge corresponding to the amount of incident light flows from the photodiode PD into the MOS transistor T1. Now, MO
Since the S-transistor T1 is in the cut-off state, photoelectric charges are stored in the gate of the MOS transistor T1. Therefore, the brightness of the object to be imaged is low and the photodiode P
When the amount of incident light incident on D is small, a voltage corresponding to the amount of photocharge accumulated in the gate of the MOS transistor T1 appears at the gate of the MOS transistor T1, so that the voltage is linearly proportional to the integrated value of the amount of incident light. The applied voltage appears at the gate of the MOS transistor T2.

When the brightness of the object to be imaged is high and the amount of incident light incident on the photodiode PD is large and the voltage corresponding to the amount of photocharge accumulated in the gate of the MOS transistor T1 increases, the MOS transistor T1 becomes sub-threshold. Since the operation is performed in the region, a voltage proportional to the natural logarithm of the incident light amount appears at the gate of the MOS transistor T1.

In this manner, a voltage linearly or logarithmically proportional to the amount of incident light appears at the gates of the MOS transistors T1 and T2.
By applying V to the gate of the MOS transistor T3, the gate voltage of the MOS transistor T1, which is linearly or naturally logarithmically proportional to the amount of incident light, is current-amplified by the MOS transistor T2.
3 to the output signal line 6. The drain voltage of the MOS transistor Q1, which is determined by the on-state resistance of the MOS transistor T2 and the MOS transistor Q1 and the current flowing therethrough, appears on the output signal line 6 as image data.

At this time, M when changing to logarithmic conversion operation
MOS is required to reach the gate voltage of the OS transistor T1.
The amount of photocharge flowing into the transistor T1 becomes equal in all pixels. As described above, since the amount of photocharge generated by the photodiode PD when the conversion operation in each pixel is switched to the logarithmic conversion operation is equal, the light is incident on the photodiode PD when the conversion operation in each pixel is switched to the logarithmic conversion operation. The incident light amounts are also equal. That is, in all the pixels, when the conversion operation is switched from the linear conversion operation to the logarithmic conversion operation, the brightness of the subject becomes equal, and the influence of the difference in the threshold voltage of the MOS transistor T1 on the switching operation of each pixel is affected. Can be reduced.

Further, the gate voltage of the MOS transistor T1 immediately after the reset is changed by changing the voltage value VL of the signal φVPS at the time of resetting or the time for applying the signal φVPS which becomes the voltage value VL (corresponding to the time ta in FIG. 4). Can be changed to change the potential between the gate and source of the MOS transistor T1. FIG. 5 shows the relationship between the subject luminance and the output of the solid-state image sensor when the magnitude of the voltage value VL is changed. FIG. The relationship between the object brightness and the output of the solid-state imaging device when the object is turned on is shown.

As the voltage value VL decreases, the difference in potential between the gate and the source of the MOS transistor T1 increases, so that the proportion of the luminance of the subject in which the MOS transistor T1 operates in the cutoff state increases. Therefore, as shown in FIG. 5, the lower the voltage value VL is, the larger the ratio of subject luminance to be linearly converted becomes. Therefore, it is understood that the voltage value VL should be lowered as the luminance range of the subject is narrower, and the voltage value VL should be raised as the luminance range of the subject is wider.

Further, as the time ta for giving the signal φVPS having the voltage value VL becomes longer, the gate voltage of the MOS transistor T1 becomes lower and the potential difference between the gate and the source of the MOS transistor T1 becomes larger.
The ratio of the subject luminance at which the S transistor T1 operates in the cutoff state increases. Therefore, as shown in FIG. 6, the longer the time ta during which the signal φVPS having the voltage value VL is applied, the greater the proportion of the subject luminance to be linearly converted. Therefore, the time ta for providing the signal φVPS having the voltage value VL becomes longer as the luminance range of the subject becomes narrower, and the time ta for giving the signal φVPS having the voltage value VL becomes larger as the luminance range of the subject becomes wider.
It can be seen that it is only necessary to shorten.

<Second Example of Pixel Configuration> A second example applied to each pixel of the solid-state imaging device shown in FIG. 1 will be described with reference to the drawings. FIG. 7 is a circuit diagram illustrating a configuration of a pixel provided in a solid-state imaging device used in the present example. FIG.
Elements, signal lines, and the like used for the same purpose as the pixel shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the pixel shown in FIG. 7, a MOS transistor T5 whose source is connected to a connection node between the gate and the drain of the MOS transistor T1 is added to the pixel having the configuration of the first example (FIG. 3), and T4
Is deleted. At this time, the DC voltage VPS is applied to the source of the MOS transistor T1.
Its gate and drain are connected to the anode of the photodiode PD. Then, a DC voltage RL is applied to the drain of the MOS transistor T5. And M
Signal φSW is applied to the gate of OS transistor T5. Other configurations are the same as those of the pixel in FIG. Note that M
The OS transistor T5 includes MOS transistors T1 to T
Similar to 3, the back gate is grounded by an N-channel MOS transistor.

As shown in the timing chart of FIG.
When pulse signal φV is applied to the gate of MOS transistor T3 and the output signal is read, first, signal φS
The reset operation is performed by setting W to a high level to turn on the MOS transistor T5. At this time, a DC voltage RL is applied to the gate voltage of the MOS transistor T1, and a negative charge flows from the drain of the MOS transistor T5, and the gate and drain of the MOS transistor T1, the gate of the MOS transistor T2, and the anode of the photodiode PD The positive charge stored in the is recombined. Therefore, the MOS transistor T1 is reset, and the potential of the region under the drain and the gate of the MOS transistor T1 decreases.

As described above, when resetting the signal φSW to the high level, the high-level pulse signal φ
By applying V to the gate of the MOS transistor T3, the correction data at the time of reset is read. At this time, the reset gate voltage of the MOS transistor T1 is applied to the gate of the MOS transistor T2, and the gate voltage of the MOS transistor T1 is current-amplified by the MOS transistor T2, and the MOS transistor T3
Is output to the output signal line 6 via Then, when the correction data is read, the signal φSW is set to low level and M
The OS transistor T5 is turned off to prepare for the next imaging operation.

As described above, when the operation proceeds to the imaging operation, the first
As in the example, when the luminance of the object to be imaged is low and the amount of light incident on the photodiode PD is small, a voltage corresponding to the amount of photocharge accumulated in the gate of the MOS transistor T1 appears at the gate of the MOS transistor T1. ,
The voltage that is linearly proportional to the integral of the amount of incident light is MO
It appears at the gate of S transistor T2.

When the brightness of the object to be imaged is high and the amount of light incident on the photodiode PD is large, and the voltage corresponding to the amount of photocharge accumulated in the gate of the MOS transistor T1 increases, the MOS transistor T1 becomes sub-threshold. Since the operation is performed in the region, a voltage proportional to the natural logarithm of the incident light amount appears at the gate of the MOS transistor T1.

In this way, a voltage that is linearly or natural logarithmically proportional to the amount of incident light appears at the gates of the MOS transistors T1 and T2, and the pulse signal φ
By applying V to the gate of the MOS transistor T3, the gate voltage of the MOS transistor T1, which is linearly or naturally logarithmically proportional to the amount of incident light, is current-amplified by the MOS transistor T2.
The image data is output to the output signal line 6 via 3.

By changing the voltage value of the DC voltage RL at the time of reset, the MOS
By changing the gate voltage of the transistor T1, the potential between the gate and the source of the MOS transistor T1 can be changed.

The lower the DC voltage RL, the greater the potential difference between the gate and the source of the MOS transistor T1. Therefore, the proportion of the subject luminance at which the MOS transistor T1 operates in the cutoff state increases. Therefore, the DC voltage RL may be decreased as the luminance range of the subject is narrower, and may be increased as the luminance range of the subject is wider.

<Third Example of Pixel Configuration> A third example applied to each pixel of the solid-state imaging device shown in FIG. 1 will be described with reference to the drawings. FIG. 9 is a circuit diagram illustrating a configuration of a pixel provided in a solid-state imaging device used in the present example. Note that FIG.
Elements, signal lines, and the like used for the same purpose as the pixel shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The pixel shown in FIG. 9 has a configuration in which MOS transistors T6 and T7 each having a drain connected to the source of the MOS transistor T1 are added to the pixel having the configuration of the second example (FIG. 7). At this time, the MOS transistor T6
The DC voltage VPSH is applied to the source and the signal φS1 is applied to the gate. The MOS transistor T7 has the source applied with the DC voltage VPSL and the gate supplied with the signal φS2. Other configurations are the same as those of the pixel in FIG.

The MOS transistors T6 and T7 have M
Similar to the OS transistors T1 to T3 and T5, an N-channel MOS transistor has a back gate grounded. The DC voltage VPSH is a voltage for operating the MOS transistor T1 in the subthreshold region when the amount of incident light exceeds a predetermined value, and a voltage lower than this voltage for turning on the MOS transistor T1 is VPSH.
L.

As shown in the timing chart of FIG. 10, when the pulse signal φV is applied to the gate of the MOS transistor T3 and the output signal is read, first, the signal φS1 is set to low level, and the MOS transistor T6 is turned off. At the same time, the signal φS2 is set to the high level, the MOS transistor T7 is turned on, and the DC voltage VPSL is applied to the source of the MOS transistor T1.
Then, the reset operation is performed by turning on the MOS transistor T5 by setting the signal φSW to high level.

At this time, the DC voltage RL is applied to the gate voltage of the MOS transistor T1, and negative charges flow from the drain of the MOS transistor T5, and the gate and drain of the MOS transistor T1, the gate of the MOS transistor T2, and the photodiode Positive charges stored at the anode of the PD are recombined. Therefore, MO
The S transistor T1 is reset, and the potential of the region under the drain and the gate of the MOS transistor T1 decreases.

As described above, when resetting the signal φSW to high level, the high-level pulse signal φ
By applying V to the gate of the MOS transistor T3, the correction data at the time of reset is read. Then, when the correction data is read, the signal φSW is set to low level to turn off the MOS transistor T5. Thereafter, the signal φS1 is set to low level to turn off the MOS transistor T6, the signal φS2 is set to high level to turn on the MOS transistor T7, and the DC voltage VPSH is applied to the source of the MOS transistor T1.
Prepare for the next imaging operation.

As described above, when the operation proceeds to the imaging operation, the second
As in the example, when the luminance of the object to be imaged is low and the amount of incident light incident on the photodiode PD is small, a voltage linearly proportional to the integral value of the amount of incident light appears at the gate of the MOS transistor T2. Also, when the brightness of the object to be imaged is high and the amount of incident light incident on the photodiode PD is large, and the voltage corresponding to the amount of photocharge accumulated in the gate of the MOS transistor T1 increases, the logarithm of the incident light becomes natural logarithmic. A proportional voltage appears at the gate of MOS transistor T2. By applying the pulse signal φV to the gate of the MOS transistor T3, image data that is linearly or logarithmically proportional to the amount of incident light is output.

Further, by changing the voltage values of the DC voltage RL and DC voltage VPSL at the time of reset, the gate voltage of the MOS transistor T1 immediately after reset is changed, thereby changing the potential between the gate and source of the MOS transistor T1. Can be done.

As the DC voltage RL and the DC voltage VPSL both decrease, the difference in the potential between the gate and the source of the MOS transistor T1 increases, so that the proportion of the subject luminance at which the MOS transistor T1 operates in the cut-off state increases. Therefore, the DC voltage RL and the DC voltage VPSL are both reduced as the luminance range of the subject is smaller, and the DC voltage RL and the DC voltage VPSL are larger as the luminance range of the subject is wider.
Should be raised together.

<Fourth Example of Pixel Configuration> A fourth example applied to each pixel of the solid-state imaging device shown in FIG. 1 will be described with reference to the drawings. FIG. 11 is a circuit diagram illustrating a configuration of a pixel provided in a solid-state imaging device used in the present example. Elements and signal lines used for the same purpose as the pixel shown in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the pixel shown in FIG. 11, the source of the MOS transistor T4 is connected to the cathode of the photodiode PD, and the gate of the MOS transistor T2 and the source of the MOS transistor T8 are connected to the drain of the MOS transistor T4. The DC voltage VPS is applied to the anode of the photodiode PD. And MO
The signal φVPD is applied to the drain of the S transistor T8, and the signal φVPG is applied to the gate thereof. Other configurations are the same as those of the pixel of the first embodiment (FIG. 3). The MOS transistor T8 is an N-channel MOS transistor and has a back gate grounded, similarly to the MOS transistors T2 to T4.

The signal φVPG is a binary voltage signal, which is a voltage Va for operating the MOS transistor T4 in the subthreshold region when the amount of incident light exceeds a predetermined value.
And the MOS transistor T4 having a voltage higher than this voltage.
Is a voltage Vb for initializing the source voltage. or,
The signal .phi.VPD is a binary voltage signal, the higher one being a voltage above Vb and the lower one being a voltage below Va. The operation of the pixel having such a configuration will be described below.

As shown in the timing chart of FIG. 12, when the pulse signal φV is applied to the gate of the MOS transistor T3 and the output signal is read, first, the signal φS is set to the low level, and the MOS transistor T4 is turned off.
After being set to FF, the reset operation is performed by setting the signal φVPD to low level. Immediately after the end of the imaging operation, the MOS transistor T8 has, for example, a potential state in which the potential becomes higher in the order of the source, the lower gate region, and the drain than in the source, or a potential state in which the MOS transistor T8 becomes higher in the order of the lower gate region, the source, and the drain. It is in. In any of these cases, when the signal φVPD is set to low level, M
Electric charges are injected into the region under the gate and the source of the OS transistor T8, and the drain, the region under the gate, and the source have a potential corresponding to the low level of the signal φVPD.
At this time, the voltage value of the signal φVPG is Va.

Thereafter, when the signal φVPD is returned to a high level, the drain of the MOS transistor T8 becomes a potential corresponding to the high level of the signal φVPD, and
The region under the gate and the source of the S transistor T8 have a potential corresponding to the voltage value Va of the signal φVPG. Further, from this state, by switching the voltage of the signal φVPG applied to the gate of the MOS transistor T8 from Va to Vb, the region under the gate and the source of the MOS transistor T8 have a potential corresponding to the voltage value Vb of the signal φVPG.

Then, the high-level pulse signal φV is set to M
By giving to the gate of the OS transistor T3,
The correction data at the time of reset is output. At this time, the reset source voltage of the MOS transistor T8 is applied to the gate of the MOS transistor T2, and the source voltage of the MOS transistor T8 is current-amplified by the MOS transistor T2 and is applied to the output signal line 6 via the MOS transistor T3. Is output.

By switching the voltage of signal φVPG applied to the gate of MOS transistor T8 from Vb to Va again, the region under the gate of MOS transistor T8 has a potential corresponding to the voltage Va of signal φVPG. At this time, the potential of the source of the MOS transistor T8 becomes higher than the potential of the region under the gate. By operating the signals φVPD and φVPG in this manner,
The potential state of the MOS transistor T8 is reset. After that, the signal φS is set to the high level to prepare for the next imaging operation.

When the signal φS is set to the high level to start the image pickup operation, a photocharge corresponding to the amount of incident light flows from the photodiode PD into the MOS transistor T8. Now, M
Since the gate voltage of the OS transistor T8 is lower than the source voltage, the MOS transistor T8 is in a cutoff state, and photoelectric charges are accumulated at the source of the MOS transistor T8. Therefore, when the brightness of the subject to be imaged is low and the amount of light incident on the photodiode PD is small, the MO
Since a voltage corresponding to the amount of photocharge accumulated in the source of the S transistor T8 appears at the source of the MOS transistor T8, a voltage that is linearly proportional to the integrated value of the amount of incident light appears at the source of the MOS transistor T8. At this time, since the photocharge generated in the photodiode PD is a negative photocharge, the source voltage of the MOS transistor T8 decreases as the intensity of the incident light increases.

When the brightness of the object to be imaged is high and the amount of light incident on the photodiode PD is large, the MO
Since the S-transistor T8 operates in the sub-threshold region, a voltage which is logarithmically proportional to the amount of incident light appears at the source of the MOS transistor T8.

In this manner, when a voltage linearly or logarithmically proportional to the amount of incident light appears at the gate of the MOS transistor T2, the pulse signal φV
Is applied to the gate of the MOS transistor T3, and the source voltage of the MOS transistor T8, which is linearly or natural logarithmically proportional to the amount of incident light, is
, And is output to the output signal line 6 via the MOS transistor T3. Also, the MOS transistor T2
The drain voltage of the MOS transistor Q1, which is determined by the resistance of the MOS transistor Q1 when conducting and the current flowing through the resistor, appears on the output signal line 6 as image data.
After the image data is read in this way, the above-described reset operation is performed.

At this time, M when changing to logarithmic conversion operation
MOS is required to reach the source voltage of the OS transistor T8.
The amount of photocharge flowing into the transistor T8 becomes equal in all pixels. As described above, since the amount of photocharge generated by the photodiode PD when the conversion operation in each pixel is switched to the logarithmic conversion operation is equal, the light is incident on the photodiode PD when the conversion operation in each pixel is switched to the logarithmic conversion operation. The incident light amounts are also equal. That is, in all the pixels, the brightness of the subject when the conversion operation is switched from the linear conversion operation to the logarithmic conversion operation becomes equal, and the influence of the difference in the threshold voltage of the MOS transistor T8 on the switching operation of each pixel is reduced. Can be reduced.

By changing the voltage Vb of the signal φVPG at the time of resetting or the time during which the signal φVPG giving the voltage value Vb (corresponding to time tb in FIG. 12) is changed, the source voltage of the MOS transistor T8 immediately after resetting is changed. Can be changed to change the potential between the gate and the source of the MOS transistor T8.

As the voltage value Vb increases, the potential difference between the gate and the source of the MOS transistor T8 increases, so that the proportion of the subject luminance at which the MOS transistor T8 operates in the cutoff state increases. Therefore,
It can be seen that the voltage value Vb should be increased as the luminance range of the subject becomes narrower, and the voltage value Vb should be decreased as the luminance range of the subject becomes wider.

Further, the longer the time tb during which the signal φVPG attaining the voltage value Vb is applied, the greater the potential difference between the gate and source of the MOS transistor T8.
The proportion of the subject luminance at which the MOS transistor T8 operates in the cutoff state increases. Therefore, the time tb for giving the signal φVPG that becomes the voltage value Vb becomes longer as the luminance range of the subject becomes narrower, and the voltage value Vb becomes larger as the luminance range of the subject becomes wider.
It can be seen that the time tb for giving the signal φVPG becomes as short as possible.

<Fifth Example of Pixel Configuration> A fifth example applied to each pixel of the solid-state imaging device shown in FIG. 1 will be described with reference to the drawings. FIG. 13 is a circuit diagram illustrating a configuration of a pixel provided in a solid-state imaging device used in the present example. Elements and signal lines used for the same purpose as the pixel shown in FIG. 11 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The pixel shown in FIG. 13 is different from the pixel having the configuration of the fourth example (FIG. 11) in that the source of the MOS transistor T8 and the MO
A MOS transistor T9 whose drain is connected to a connection node with the gate of the S transistor T2 is added, and the MOS transistor T4 is deleted. At this time, the DC voltage VPG is applied to the gate of the MOS transistor T8, and the cathode of the photodiode PD is connected to the source thereof. The gate of the MOS transistor T9 is supplied with the signal φSW, and the source thereof is applied with the DC voltage RL. Also MO
DC voltage VPD is applied to the drain of S transistor T8. The MOS transistor T9 is an N-channel MOS transistor and has a back gate grounded, like the MOS transistors T2, T3 and T8.

As shown in the timing chart of FIG. 14, when pulse signal φV is applied to the gate of MOS transistor T3 and the output signal is read, signal φSW
To a high level to perform a reset operation. Therefore, MO
The DC voltage RL is applied to the source of the S transistor T8, and the source voltage of the MOS transistor T8 is
Reset by L. At this time, by applying a high-level pulse signal φV to the gate of the MOS transistor T3, correction data at the time of reset is output. Then, the signal φSW is set to the low level again to turn off the MOS transistor T9 and prepare for the next imaging operation.

In this manner, when the operation proceeds to the image pickup operation, the fourth
As in the example, when the luminance of the object to be imaged is low and the amount of incident light incident on the photodiode PD is small, a voltage linearly proportional to the integral value of the amount of incident light appears at the gate of the MOS transistor T2. Also, when the brightness of the object to be imaged is high and the amount of incident light incident on the photodiode PD is large and the voltage corresponding to the amount of photocharge accumulated in the source of the MOS transistor T8 increases, the logarithm of the incident light becomes natural logarithmic. A proportional voltage appears at the gate of MOS transistor T2. By applying the pulse signal φV to the gate of the MOS transistor T3, image data that is linearly or logarithmically proportional to the amount of incident light is output.

By changing the voltage value of the DC voltage RL at the time of reset, the MOS
The potential between the gate and the source of the MOS transistor T8 can be changed by changing the source voltage of the transistor T8.

As the DC voltage RL increases, the potential difference between the gate and the source of the MOS transistor T8 increases, so that the ratio of the subject luminance at which the MOS transistor T8 operates in the cutoff state increases. Therefore, the DC voltage RL may be increased as the luminance range of the subject is narrower, and may be decreased as the luminance range of the subject is wider.

<Sixth Example of Pixel Configuration> A sixth example applied to each pixel of the solid-state imaging device shown in FIG. 1 will be described with reference to the drawings. FIG. 15 is a circuit diagram illustrating a configuration of a pixel provided in a solid-state imaging device used in the present example. Elements and signal lines used for the same purpose as the pixel shown in FIG. 11 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The pixel shown in FIG. 13 is different from the pixel having the structure of the fourth example (FIG. 11) in that the source of the MOS transistor T8 and the MO
A MOS transistor T9 having a drain connected to a connection node with the gate of the S transistor T2 is added. At this time, signal φSW is applied to the gate of MOS transistor T9, and DC voltage RL is applied to the source. The DC voltage VPD is applied to the drain of the MOS transistor T8. The MOS transistor T9 is an N-channel MOS transistor and has a back gate grounded, like the MOS transistors T2 to T4 and T8.

As shown in the timing chart of FIG. 16, when the pulse signal φV is applied to the gate of the MOS transistor T3 and the output signal is read, first, the signal φS is set to the low level, and the MOS transistor T4 is turned off.
After being set to FF, the signal φSW is set to the high level to
The reset operation is performed by turning on the S transistor T9. At this time, the voltage value of the signal φVPG is Va.

Thereafter, when the signal φSW is returned to the low level to turn off the MOS transistor T9, the region under the gate and the source of the MOS transistor T8 are changed to the signal φVPG
Is a potential corresponding to the voltage value Va of the voltage. Further, from this state, by switching the voltage of the signal φVPG applied to the gate of the MOS transistor T8 from Va to Vb, the region under the gate and the source of the MOS transistor T8 become a potential corresponding to the voltage value Vb of the signal φVPG.

Then, the high-level pulse signal φV is set to M
By giving to the gate of the OS transistor T3,
The correction data at the time of reset is output. And
Again, the signal φ applied to the gate of the MOS transistor T8
After switching the voltage of VPG from Vb to Va, the signal φS is set to the high level to prepare for the next imaging operation.

As described above, when the operation proceeds to the imaging operation, the fourth
As in the example, when the luminance of the object to be imaged is low and the amount of incident light incident on the photodiode PD is small, a voltage linearly proportional to the integral value of the amount of incident light appears at the gate of the MOS transistor T2. Also, when the brightness of the object to be imaged is high and the amount of incident light incident on the photodiode PD is large and the voltage corresponding to the amount of photocharge accumulated in the source of the MOS transistor T8 increases, the logarithm of the incident light becomes A proportional voltage appears at the gate of MOS transistor T2. By applying the pulse signal φV to the gate of the MOS transistor T3, image data that is linearly or logarithmically proportional to the amount of incident light is output.

By changing the voltage Vb of the signal φVPG at the time of resetting or the time during which the signal φVPG giving the voltage value Vb (corresponding to time tb in FIG. 16) is changed, the source voltage of the MOS transistor T8 immediately after resetting is changed. Can be changed to change the potential difference between the gate and the source of the MOS transistor T8. Therefore, as with the fourth example, the voltage value Vb is set higher as the luminance range of the subject is smaller, as in the fourth example.
The voltage value Vb may be lowered as the luminance range of the subject is wider. As for the time tb, as in the fourth example, the time tb may be set longer as the luminance range of the subject is narrower, and may be set shorter as the luminance range of the subject is wider.

<First Embodiment> A first embodiment of an image pickup apparatus having a solid-state image pickup device having pixels of the above-described examples will be described with reference to the drawings. FIG. 17 is a block diagram illustrating the internal configuration of the imaging device of the present embodiment.

The image pickup device shown in FIG. 17 includes a solid-state image pickup device 100 having the configuration of each of the above-described examples and having pixels capable of automatically switching from linear conversion operation to logarithmic conversion operation, and an output circuit 10 of the solid-state image pickup device 100. A / D converter 101 for converting image data corrected by the correction data output from FIG. 1 into digital data, and A / D converter 10
An arithmetic circuit 102 for obtaining the luminance distribution of the object from the digital data from 1; an arithmetic circuit 103 for controlling the reset bias supply circuit 104 based on the luminance distribution obtained by the arithmetic circuit 102; A reset bias supply circuit 104 for switching and supplying a bias voltage according to a control signal of the arithmetic circuit 103.

In the following, for simplicity of description, a description will be given assuming that the solid-state imaging device 100 is a solid-state imaging device having pixels having the configuration of the above-described first example (FIG. 3). Therefore, in the present embodiment, the voltage switched by the reset bias supply voltage 104 is the voltage value VL of the signal φVPS. Further, in order to measure the luminance distribution of the subject, the voltage value VL of the signal φVPS is increased once every predetermined time to enable a wide luminance range to be measured. At this time, the output from the solid-state imaging device 100 is A / A It is assumed that the data is converted into digital data by the D converter 101 and then transmitted to the arithmetic circuit 102.

In the image pickup apparatus configured as described above, the output for measuring the luminance distribution output from the solid-state image pickup element 100 every predetermined time is converted into digital data by the A / D converter 101 and transmitted to the arithmetic circuit 102. Then, the frequency of each luminance is obtained, and the luminance distribution is obtained. Then, the highest luminance and the lowest luminance are obtained from the obtained luminance distribution.

At this time, the digital data for each pixel sent from the A / D converter 101 is converted to the arithmetic circuit 101
, The digital data having the highest luminance and the digital data having the lowest luminance are obtained, and held as the highest luminance and the lowest luminance, respectively. Then, the value of the digital data of the pixel given next is compared with the values of the digital data held as the highest brightness and the lowest brightness, respectively. If the value is higher than the highest brightness, the highest brightness is used instead of the held highest brightness. If the luminance is lower than the minimum luminance, the luminance is retained as the minimum luminance instead of the retained minimum luminance. Furthermore, when the lower luminance is lower than the highest luminance and higher than the lowest luminance, the stored highest luminance and lowest luminance are
Hold as it is.

As described above, when the maximum luminance and the minimum luminance in the luminance distribution of the subject are obtained from the digital data for one field in the arithmetic circuit 102, the obtained maximum luminance and minimum luminance are sent to the arithmetic circuit 103. Is done. The arithmetic circuit 103 first obtains a luminance range of the subject by obtaining a difference between the given maximum luminance and minimum luminance. A control signal for controlling the reset bias supply circuit 104 is transmitted according to the obtained luminance range.

That is, when the arithmetic circuit 103 determines that the difference between the maximum luminance and the minimum luminance is large and the luminance range of the subject is wide, the MOS transistor T1 is switched so as to switch to the logarithmic conversion operation at a low luminance. Of the signal φVPS at the time of reset to determine the potential state of
Is sent to the reset bias supply circuit 104. Conversely, when it is determined that the difference between the maximum luminance and the minimum luminance is small and the luminance range of the subject is narrow, the MOS transistor is switched to the logarithmic conversion operation at a high luminance.
To determine the potential state of transistor T1,
A control signal for lowering the voltage value VL of the signal φVPS at the time of reset is sent to the reset bias supply circuit 104.

Therefore, if the arithmetic circuit 103 determines that the luminance range is wide, the reset bias supply circuit 104 sets the voltage value VL of the reset signal φVPS to a low value until it is determined that the luminance range is narrow. And supplied to the solid-state imaging device 100. The arithmetic circuit 1
03, it is determined that the luminance range is narrow. In the reset bias supply circuit 104, the voltage value V of the signal φVPS at the time of reset is determined until the luminance range is next determined to be wide.
L is set to a high value and supplied to the solid-state imaging device 100. The luminance range is compared with a threshold value in a plurality of stages, and the voltage value VL of the reset signal φVPS supplied from the reset bias supply circuit 104 is switched according to the threshold value range including the value. .

<Second Embodiment> A second embodiment of an image pickup apparatus having a solid-state image pickup device having pixels of the above-described examples will be described with reference to the drawings. FIG. 18 is a block diagram illustrating an internal configuration of the imaging apparatus according to the present embodiment.
Note that, in the imaging device of FIG. 18, portions used for the same purpose as the imaging device shown in FIG. 17 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The imaging device of FIG. 18 has a configuration in which a timing generator 105 is provided instead of the reset bias supply circuit 104 in the imaging device of the first embodiment (FIG. 17). This timing generator 105
Accordingly, the timing of each signal applied to each pixel of the solid-state imaging device 100 is determined. Further, the time during which the bias voltage is applied to each pixel at the time of reset in each of the above-described examples is switched by the timing generator 105. The connection relations of the other blocks 100 to 103 are the same as in the first embodiment, and the operation is the same.

In the following, for the sake of simplicity, the first
As in the embodiment, the solid-state imaging device 100 will be described as a solid-state imaging device having pixels having the configuration of the first example (FIG. 3) described above. Therefore, in this embodiment,
At the time of reset, the voltage of signal φVPS is switched to voltage value VL. Further, in order to measure the luminance distribution of the object, the voltage value VL of the signal φVPS is reset once at a predetermined time interval.
The time ta (FIG. 4) for giving a short time is given to enable a wide luminance range to be measured. At this time, the output from the solid-state imaging device 100 is converted into digital data by the A / D converter 101, and then the arithmetic circuit 102 Shall be sent.

According to the imaging apparatus having such a configuration,
As in the first embodiment, the image data output from the solid-state imaging device 100 is converted into digital data by the A / D converter 101 and applied to the arithmetic circuit 102 for one field every predetermined time. The luminance and the minimum luminance are obtained and sent to the arithmetic circuit 103. Then, the arithmetic circuit 103 obtains a luminance range of the luminance distribution of the subject from the difference between the transmitted maximum luminance and minimum luminance. The control signal corresponding to the width of the luminance range is supplied to the arithmetic circuit 103
Is given to the timing generator 105.

That is, when the arithmetic circuit 103 determines that the difference between the maximum luminance and the minimum luminance is large and the luminance range of the subject is wide, the MOS transistor T1 is switched so as to switch to the logarithmic conversion operation at a low luminance. Of the signal φVPS at the time of reset to determine the potential state of
Is sent to the timing generator 105 to shorten the time ta for applying Conversely, when it is determined that the difference between the maximum luminance and the minimum luminance is small and the luminance range of the subject is narrow, the potential state of the MOS transistor T1 is determined so that the switching to the logarithmic conversion operation is performed at a high luminance. A control signal for extending the time ta for giving the voltage value VL of the reset signal φVPS is sent to the timing generator 105.

Therefore, when the arithmetic circuit 103 determines that the luminance range is wide, the timing generator 105 sets the time ta during which the voltage value VL of the reset signal φVPS is applied until the luminance range is determined to be narrow. The voltage VL of the signal φVPS is set short so that the solid-state imaging device 1
00 is supplied. When the arithmetic circuit 103 determines that the luminance range is narrow, the timing generator 105 sets the time ta for giving the voltage value VL of the reset signal φVPS long until the luminance range is determined to be wide next. Thus, the voltage value VL of the signal φVPS is supplied to the solid-state imaging device 100. Note that, as in the first embodiment, this luminance range is compared with thresholds in a plurality of levels, and
The reset signal φVPS supplied from the timing generator 105 according to the range of the threshold value including the value
The time ta for giving the voltage value VL is switched.

Further, the signal φVPS at the time of reset provided from the timing generator 105 may be provided as a plurality of pulse signals as shown in FIG. 19 instead of one pulse signal as shown in FIG. At this time,
When the arithmetic circuit 103 determines that the luminance range is wide, the timing generator 105 resets the voltage value VL at reset until it is determined that the luminance range is narrow.
The number of occurrences of the pulse signal φVPS is set to be small and supplied to the solid-state imaging device 100. When the arithmetic circuit 103 determines that the luminance range is narrow, the timing generator 105 determines until the next determination that the luminance range is wide.
, The pulse signal φVPS of the voltage value VL at the time of reset
Are set to a large number and are supplied to the solid-state imaging device 100.

[0111]

According to the present invention, the dynamic state of the output from the solid-state image sensor can be adjusted by adjusting the potential state of the transistor provided in each pixel provided in the solid-state image sensor according to the brightness of the subject. it can.
Therefore, this is different from the case where the dynamic range is adjusted by adjusting the digital data as in the related art, and it is possible to prevent the bit drop of the digital data. Therefore, the dynamic range of the luminance distribution of the subject can be adjusted without lowering the gradation. Therefore, high-definition image data according to the luminance distribution of the subject can be obtained.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram illustrating a configuration of a solid-state imaging device.

FIG. 2 is a circuit diagram showing a part of the solid-state imaging device of FIG. 1;

FIG. 3 is a circuit diagram showing an example of a pixel configuration in the solid-state imaging device of FIG. 1;

FIG. 4 is a timing chart showing the operation of the pixel having the configuration shown in FIG. 3;

FIG. 5 is a graph showing the relationship between the luminance of a subject and the output of a solid-state imaging device.

FIG. 6 is a graph showing the relationship between the luminance of a subject and the output of a solid-state imaging device.

FIG. 7 is a circuit diagram showing an example of a pixel configuration in the solid-state imaging device of FIG. 1;

8 is a timing chart showing the operation of the pixel having the configuration shown in FIG. 7;

FIG. 9 is a circuit diagram showing an example of a pixel configuration in the solid-state imaging device of FIG. 1;

FIG. 10 is a timing chart showing the operation of the pixel having the configuration shown in FIG. 9;

FIG. 11 is a circuit diagram showing an example of a pixel configuration in the solid-state imaging device of FIG. 1;

12 is a timing chart showing the operation of the pixel having the configuration shown in FIG.

FIG. 13 is a circuit diagram showing an example of a pixel configuration in the solid-state imaging device of FIG. 1;

FIG. 14 is a timing chart showing the operation of the pixel having the configuration shown in FIG. 13;

FIG. 15 is a circuit diagram showing an example of a pixel configuration in the solid-state imaging device of FIG. 1;

16 is a timing chart showing the operation of the pixel having the configuration shown in FIG.

FIG. 17 is a block diagram illustrating an internal configuration of the imaging device according to the first embodiment.

FIG. 18 is a block diagram illustrating an internal configuration of an imaging device according to a second embodiment.

FIG. 19 is a timing chart showing the operation of the pixel having the configuration shown in FIG. 3;

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 solid-state imaging device 101 A / D converter 102 arithmetic circuit 103 arithmetic circuit 104 reset bias supply circuit 105 timing generator

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M118 AA02 AB01 BA14 CA02 DB16 DB20 FA06 FA33 FA42 FA50 5C024 CX43 GX03 GY31 GY38 HX13 HX23 HX29 HX50

Claims (14)

[Claims] An electric signal according to a first state, which has a photosensitive element for outputting an electric signal corresponding to the amount of incident light, and a transistor to which an electric signal from the photosensitive element is given, and outputs a first state which is linearly converted and output. An image pickup apparatus having a solid state image pickup device comprising a plurality of pixels which can be automatically switched between a second state and a logarithmically converted state, and the potential state of the transistor immediately after reset is imaged by the solid state image pickup element An imaging apparatus, comprising: a bias adjustment unit that changes according to a state of a luminance distribution of a subject to be performed. 2. The method according to claim 1, wherein at the time of resetting, a value of a bias voltage applied to said transistor is switched.
The imaging device according to claim 1, wherein the bias adjustment unit adjusts a potential state of the transistor immediately after reset. 3. The device according to claim 1, wherein the bias adjusting unit adjusts the potential state of the transistor immediately after reset by switching the length of time during which a bias voltage is applied to the transistor during reset. An imaging device according to claim 1. 4. The pixel, wherein the pixel serves as the photosensitive element, a photodiode having a DC voltage applied to a first electrode, and a first electrode and a gate electrode connected to a second electrode of the photodiode. And a MOS transistor that outputs an electric signal from the gate electrode. When the luminance range of the luminance distribution of the subject is narrow,
When the potential state of the MOS transistor immediately after reset is adjusted so that the potential difference between the gate electrode and the second electrode of the OS transistor becomes large, and when the luminance range of the luminance distribution of the subject is wide, The M
The imaging device according to claim 1, wherein the potential state of the MOS transistor immediately after reset is adjusted so that the potential difference between the gate electrode of the OS transistor and the second electrode is reduced. 5. The pixel is reset by switching a voltage applied to a second electrode of the MOS transistor, and the bias adjusting unit adjusts a voltage value applied to a second electrode of the MOS transistor at the time of resetting. 5. The imaging apparatus according to claim 4, wherein the potential state of the MOS transistor immediately after reset is adjusted. 6. The pixel is reset by switching a voltage applied to a second electrode of the MOS transistor, and the bias adjusting unit adjusts a time for switching a voltage value applied to the second electrode of the MOS transistor at the time of resetting. 5. The imaging apparatus according to claim 4, wherein the potential state of the MOS transistor immediately after reset is adjusted. 7. The pixel is reset by switching a voltage applied to a gate electrode of the MOS transistor, and the bias adjustment unit adjusts a voltage value applied to a gate electrode of the MOS transistor at the time of reset to reset the pixel. The imaging device according to claim 4, wherein a potential state of the MOS transistor immediately after is adjusted. 8. The pixel is reset by switching a voltage applied to a gate electrode and a second electrode of the MOS transistor, and the bias adjuster applies a voltage applied to a gate electrode and a second electrode of the MOS transistor at the time of resetting. The imaging device according to claim 4, wherein the potential state of the MOS transistor immediately after reset is adjusted by adjusting a value. 9. The photodiode, wherein the pixel serves as the photosensitive element and a DC voltage is applied to a second electrode; a second electrode is connected to a first electrode of the photodiode; And a MOS transistor that outputs an electric signal from the object. When the luminance range of the luminance distribution of the subject is narrow,
When the potential state of the MOS transistor immediately after reset is adjusted so that the potential difference between the gate electrode and the second electrode of the OS transistor becomes large, and when the luminance range of the luminance distribution of the subject is wide, The M
The imaging device according to claim 1, wherein the potential state of the MOS transistor immediately after reset is adjusted so that the potential difference between the gate electrode of the OS transistor and the second electrode is reduced. 10. The pixel is reset by switching a voltage applied to each of a first electrode and a gate electrode of the MOS transistor, and the bias adjustment unit adjusts a voltage value applied to a gate electrode of the MOS transistor at the time of reset. 10. The imaging device according to claim 9, wherein the potential state of the MOS transistor immediately after reset is adjusted. 11. The pixel is reset by switching a voltage applied to each of a first electrode and a gate electrode of the MOS transistor, and the bias adjustment unit switches a voltage value applied to a gate electrode of the MOS transistor at the time of reset. The imaging apparatus according to claim 9, wherein the potential state of the MOS transistor immediately after reset is adjusted by adjusting a time. 12. A pixel is reset by applying a DC voltage to a first electrode and a gate electrode of the MOS transistor, and by switching a voltage applied to a second electrode of the MOS transistor. 10. The imaging apparatus according to claim 9, wherein a potential value of the MOS transistor immediately after reset is adjusted by adjusting a voltage value applied to a second electrode of the MOS transistor at reset. 13. By switching a voltage applied to a gate electrode and a second electrode of the MOS transistor,
10. The pixel is reset, and the bias adjuster adjusts a potential value of the MOS transistor immediately after reset by adjusting a voltage value applied to a gate electrode of the MOS transistor at the time of reset. An imaging device according to claim 1. 14. By switching a voltage applied to a gate electrode and a second electrode of the MOS transistor,
The pixel is reset, and the bias adjustment unit adjusts a potential switching state of the MOS transistor immediately after reset by adjusting a time for switching a voltage value applied to a gate electrode of the MOS transistor at the time of reset. The imaging device according to claim 9.