KR20070021076A - Solid state imaging device, driving method for solid state imaging device, imaging apparatus, and image input apparatus - Google Patents

Abstract

In a transfer electrode to which a normally low transfer pulse is applied, a long time period in which a negative potential is applied, and an electric field is a gate insulating film ), The device reliability may be reduced. To overcome this disadvantage, the negative side potential (VL ') of normally low vertical transfer pulses (VΦ3, VΦ4) is normally-high vertically. The absolute value is set smaller than the negative potential VL of the transfer pulses VΦ1 and VΦ2. Thereby, the influence of dark current increase is suppressed, while the electric field applied to the gate insulating film is reduced.

Description

Solid state imaging device, driving method for solid state imaging device, imaging apparatus, and image input apparatus

1A to 1B are waveform diagrams illustrating a general four phase-differential vertical transfer pulse train (Vφ1 to Vφ4), respectively.

Fig. 2 is a view schematically showing the configuration of CCD and its driving circuit which can be used in the first to fourth embodiments.

3 is a cross-sectional view of an essential part taken along line AA of FIG. 2.

4A to 4D are waveform diagrams of the four-phase vertical transfer pulse trains of the first embodiment, respectively.

5A to 5D are waveform diagrams of the four-phase vertical transfer pulse trains of the second embodiment, respectively.

Fig. 6 is a diagram showing a block of the drive device including the feedback control circuit of the third embodiment together with the CCD.

7 is a block diagram illustrating an exemplary configuration of a signal processing circuit.

8A and 8B are waveform diagrams of the four-phase vertical transfer pulse trains respectively in the case where the image screen is relatively bright and relatively dark in the third embodiment.

Fig. 9 is a graph for explaining the effect of positive side potential regulation (third embodiment).

10 is a block diagram showing an example of the configuration of the image input apparatus of the fourth embodiment.

11A and 11C are circuit diagrams of a CCD output circuit, respectively.

The present invention relates to Japanese Patent Document JP 2005-236297, filed August 17, 2005, and Japanese Patent Document JP 2006-157741, filed June 6, 2006, to Japanese Patent Office. Include all content as a reference.

The present invention relates to a solid-state imaging device, a method of driving a solid-state imaging device, an imaging device, and an image input device. More specifically, the present invention relates to a charge-transfer solid-state imaging device represented by a charge coupled device (CCD) imaging device, a method of driving the solid-state imaging device, an imaging device and the image using the solid-state imaging device. It relates to an input device.

Charge-transfer solid-state imaging devices, such as charge coupled devices (CCD) solid-state imaging devices, have a " pinning action " for suppressing an increase in dark current generated in a vertical transfer register. A method called pinning operation is employed. More specifically, the image pickup device adopts a driving method for transferring a vertical transfer register using a four-phase transfer pulse train having two voltage values, respectively. Two voltage values, one voltage value is 0V as the potential of the positive side (high level side) and the other value is the negative side (low level side). As a potential, it is a negative voltage value VL (for example, refer Unexamined-Japanese-Patent No. 2004-328680 (FIG. 4 and the corresponding part of a specification)).

JP-A 2004-328680 discloses a CCD driving method for performing transfer driving of a vertical transfer register by using four-phase transfer pulse trains each having two voltage values at high and low levels, respectively. .

1A to 1D show waveform diagrams of four-phase vertical transfer pulses Vφ1 to Vφ4 as described in JP-A 2004-328680, respectively. In the figure, the case where the high level voltage is 0 [V] and the low level voltage is the negative side voltage value VL is shown.

As shown in Figs. 1A to 1D, the vertical transfer pulse trains Vφ1 to Vφ4 for driving the four-phase vertical transfer registers each have a high level (for example, 0 [V]) at a low level (for example, a negative voltage). Value VL) vertically transmitted pulses " normally high " longer than the period " normally low " It consists of transmission pulses Vφ3 and Vφ4.

A "normally-high" level means a high level during a standby time including light reception time, and a "normally-low" level means a low level during the waiting period. .

As the potential of the silicon surface serving as the vertical charge transfer channel approaches the negative side, the potential of the silicon surface decreases, and holes are more likely to accumulate thereon. For this reason, the influence of the surface level generated by the defect of the silicon surface, that is, the generation of electrons from the surface level, which is the main source of dark current, is significantly suppressed. As a result, an increase in dark current can be suppressed. This phenomenon is caused by an effect called the "pinning effect".

When a low level potential is applied to the transfer electrode while a high level potential is applied to the transfer electrode of the transfer register, a high pinning effect occurs. However, in the dislocation range in the meantime, the pinning effect decreases as the dislocation approaches the high level side and increases as the dislocation approaches the low level side.

According to the pinning effect, an inversion layer is formed on the silicon surface by applying a negative voltage to the transfer electrode while 0 V is applied to the transfer electrode of the vertical transfer register, and the surface level of the vertical transfer register is also positive. The amount of electrons, which is the main cause of the dark current generation generated from the surface level, is significantly reduced, so that the dark current can be suppressed. Therefore, the negative potential of the transfer pulse driving the vertical transfer register is very important.

In addition, Japanese Unexamined Patent Publication No. 2004-221339 discloses a technique for reducing noise caused by dark current. According to the above technique, in the vertical transfer register, the number of vertical transfer electrodes (storage gates) driven by normally-high pulses, each having a low pinning effect and a long high level period, is reduced, thereby reducing the dark current. Suppress occurrence.

Like the normally-high four-phase vertical transfer pulse trains Vφ1 to Vφ4 shown in Figs. 1A to 1D, the vertical transfer pulses Vφ1 and Vφ2 are each normally-high and each low level (side voltage). Value VL) period, which is longer than the high level (0V) period, and the vertical transmission pulses Vφ3 and Vφ4 are normally low and each has a low level period longer than the high level period.

In the transfer electrodes to which the vertical transfer pulses Vφ3 and Vφ4 are normally applied, the period in which the negative potential is applied is long, and the electric field is applied to the gate insulating film, thereby reducing the reliability of the device. There exists a possibility that efficiency may fall. The negative side potential can be reduced (near 0V) to reduce the electric field applied to the gate insulating film, but at the same time, the pinning effect also decreases, thereby causing a problem of increasing the dark current.

However, nevertheless, for example, referring to the example shown in Fig. 1, in the transfer electrode to which the vertical transfer pulses Vφ3 and Vφ4 are normally applied, the period during which the negative potential is applied is long and the gate insulating film is applied. High electric field is applied for a long time. Thus, for example, there is a concern about the deterioration of the reliability of the apparatus related to the deterioration of the quality of the insulating film. As a result, the electric field control over the transmission channel is reduced, thus reducing the transmission efficiency of the vertical transfer register. To prevent a decrease in device reliability, the negative potential can be reduced (near 0V). In this case, however, the pinning effect is reduced, so that the dark current increases noticeably.

However, on the contrary, in the normally-high vertical transmission pulses Vφ1 and Vφ2, a period during which a high level potential, for example, 0 [V], is applied is long. Therefore, if this high level can be reduced as much as possible, the pinning effect becomes stronger, so that the dark current can be reduced.

However, when the high level potential decreases, the amplitude of the vertical transfer pulse becomes small, which reduces the transfer efficiency of the vertical transfer register.

In the example of Japanese Unexamined Patent Publication No. 2004-221339, since the number of normally-horizontal driving pulses increases from 2 to 3, therefore, the number of electrodes that may decrease the reliability of the device operation while reducing the dark current. Is increased due to, for example, deterioration in the quality of the gate insulating film. Therefore, the disclosed example has a disadvantage in that the transmission efficiency is further lowered.

As such, the transfer efficiency (and signal read efficiency) of the vertical transfer register and the strength of the pinning effect for preventing the generation of the dark current are trade-off relations with each other, so that the image pickup device can be efficiently It is difficult to operate.

Under such circumstances, there is a very high demand for a technique for operating an imaging device with high transmission efficiency while suppressing generation of dark current or reducing the effect of lowering transmission efficiency.

In view of the above, it is preferable in the present invention to provide a solid state image pickup device, a method of driving such a solid state image pickup device, and an image pickup device that can improve device reliability without increasing dark current.

In order to achieve the above object, in the embodiment of the present invention, for example, a normally-high transfer pulse whose side potential period is longer than the side potential period and a normally-high transfer pulse whose side side potential period is longer than the side potential period are applied to the transfer pulse. Charge-transfer part which is transfer-driven by the drive, and the negative potential of the normally-low transfer pulse is determined to be smaller than the negative potential of the normally-high vertical transfer pulse. The configuration of the solid state image pickup device including the charge transfer section is employed.

In one of the solid-state image pickup devices configured as described above, in the driving method and the image pickup device using the image pickup device, the dark current in the vertical transfer portion mainly occurs below the transfer electrode to which a normally-high vertical transfer pulse is applied. This is due to the short duration of the negative potential and the short duration of the pinning effect in the normally-high vertical transmission pulse. Thus, the effect of dark current does not substantially occur even in the case of the negative side potential of the normally-high vertical transmission pulse in which the amount of generation of dark current is very small in relation to the absolute value of the normal-high vertical transmission pulse being slightly reduced. However, on the other hand, while a high electric field is applied to the gate oxide film, the electric field is applied to it through the transfer electrode to which the normal transfer pulse is normally applied. Therefore, a decrease in the absolute value of the negative potential of the normally-vertical vertical transfer pulse leads to a decrease in the electric field applied to the gate insulating film.

In another embodiment of the present invention, the driving apparatus of the solid state imaging device transmits signal charges generated in response to light reception in the charge transfer unit. The driving device includes a transfer pulse supply circuit for generating a first transfer pulse and a second transfer pulse, and supplying the generated first transfer pulse and the second transfer pulse to a charge transfer unit of the solid state image pickup device. The transfer pulse is a pulse having a positive potential during a waiting period including the reception of signal charges, and a negative potential during a charge transfer, and the second transfer pulse is a negative potential during a waiting period. At this time, a pulse having a positive potential is obtained, and the negative potential is smaller than the negative potential of the first transmission pulse.

Suitably, in the present embodiment, the transfer pulse supply circuit intermittently makes the negative potential of the second transfer pulse smaller than the negative potential of the first transfer pulse.

According to the above configuration, in the transfer pulse supply circuit, the second transfer pulse whose potential (standby level) in the waiting period is the negative side potential is generated so that the potential thereof is smaller than the negative potential of the first transfer pulse. The second transfer pulse and the first transfer pulse are supplied from the transfer pulse supply circuit to the solid-state image pickup device, thereby transferring the signal charges.

In the second transmission pulse having the negative potential in the waiting period, the period in which the pinning effect acts is long. On the other hand, in the first transmission pulse, a period in which the pinning effect is low is long. Therefore, if the negative potential of the second transmission pulse is changed so that the absolute value of the potential becomes small, the degree of reduction of the pinning effect is smaller than that of the case of changing in the first transmission pulse.

However, the pinning effect is intensified by the change of the negative potential, and the effect lasts for some time. In the case where the negative potential of the second transmission pulse is intermittently changed, the pinning effect does not change as compared with the case where the negative potential of the second transmission pulse is not changed intermittently, while the driving capability is increased.

A drive device for a solid-state imaging device according to another embodiment of the present invention transfers signal charges generated in response to light reception in a charge transfer section, converts the signal charges into an image signal, and outputs the image signal. . The driving apparatus may supply the first transfer pulse and the second transfer pulse to the solid state image pickup device as driving pulses of the charge transfer unit, respectively, and receive at least one standby level of the first transfer pulse and the second transfer pulse from the solid state image pickup device. And a feedback control circuit capable of changing in relation to the received image signal, wherein the first transfer pulse has a positive potential during a waiting period including a light receiving time during which signal charges occur and a pulse having a negative side potential during a charge transfer time. The second transfer pulse is the pulse having the negative potential during the waiting period and the positive potential during the charge transfer time.

Suitably, in the present embodiment, the feedback control circuit includes a transfer pulse supply circuit for supplying the first transfer pulse and the second transfer pulse to the solid state image pickup device, inputting an image signal from the solid state image pickup device, and amplifying the image signal. And a control circuit for detecting the brightness of the image picked up by the solid-state imaging device in relation to the image signal and supplying a gain corresponding to the detected brightness to the variable gain amplifier so that the gain can be changed. The transmission pulse supply circuit inputs a gain from the control circuit and changes the standby level according to the input gain.

According to the above arrangement, since the image signal from the solid-state image pickup device contains the brightness information of the image pickup screen, the brightness can be detected, whereby the transfer pulse supply circuit supplies the gain obtained in the gain control performed in response to the detected brightness. As a result, the atmospheric level can be changed. In this case, the pinning effect can be enhanced or maintained, and at the same time, the effect of the lowering of the driving capability can be minimized by reducing the driving capability only when the influence is meaningless.

An image input device according to another embodiment of the present invention includes a solid state image pickup device for transmitting signal charges generated in response to light reception, a drive circuit of a solid state image pickup device, and an image pickup surface of a solid state image pickup device in a charge transfer unit. An optical system for guiding image light from a subject. The driving circuit includes a transfer pulse supply circuit for generating a first transfer pulse and a second transfer pulse, and supplying the generated first transfer pulse and the second transfer pulse to the charge transfer unit of the solid state image pickup device. The first transfer pulse has the positive potential during the standby period including the reception of the signal charges, and the negative potential pulse during the charge transfer. The second transfer pulse is the negative potential during the standby period. It becomes a pulse having a positive potential, and the negative potential is smaller in absolute value than the negative potential of the first transfer pulse.

According to another aspect of the present invention, there is provided an image input apparatus according to another embodiment of the present invention, comprising: a solid state image pickup device for transmitting signal charges generated in response to light reception in a charge transfer section; A driving circuit, an optical system for guiding image light from a subject to an image pickup surface of a solid state image pickup device, and a signal varying according to the amount of signal charge of the solid state image pickup device can be output. It includes a means. The driving circuit can supply the first transfer pulse and the second transfer pulse to the solid state image pickup device as driving pulses of the charge transfer unit, respectively, and at least one standby level of the first transfer pulse and the second transfer pulse is used for signal charge. And a transfer pulse supply circuit capable of varying with respect to a signal that changes in response to a quantity, wherein the first transfer pulse has a positive potential during a waiting period including a light receiving time where signal charges occur. It becomes the pulse of the negative potential, and the second transfer pulse is the negative potential during the waiting period, and the pulse having the positive potential during charge transfer.

A method for driving a solid state image pickup device according to the embodiment of the present invention is to drive a solid state image pickup device that transfers signal charges generated in response to light reception in a charge transfer section. The driving method includes a first step of generating a first transfer pulse and a second transfer pulse, wherein the first transfer pulse has charge transfer with a positive potential during a waiting period including a light receiving time at which signal charge is generated. Is a pulse having a negative side potential, the second transfer pulse has a negative side potential during the waiting period, and the negative side potential is smaller than an absolute value of the negative side potential of the first transfer pulse, and And a second step of performing driving by supplying the second transfer pulse to the charge transfer section of the solid state image pickup device.

In the method of driving a solid state image pickup device, a signal charge generated in response to light reception is transmitted in a charge transfer section, the signal charge is converted into an image signal, and the image signal is output to drive the solid state image pickup device. The driving method includes a first step of generating a first transfer pulse and a second transfer pulse, wherein the first transfer pulse has a positive potential during a standby period including a light receiving time at which signal charge is generated. Is the pulse having the negative potential, and the second transfer pulse is the pulse having the negative potential during the standby period and the positive potential during the charge transfer, and the generated first transfer pulse and the second transfer pulse are converted into the solid state image pickup device. A second step of performing driving by supplying to the charge transfer section of the first transmission circuit; and generating and supplying the first transfer pulse and the second transfer pulse, in connection with the image signal received from the solid state image pickup device, And changing a standby level of at least one of the transmission pulses.

EMBODIMENT OF THE INVENTION Hereinafter, the Example of this invention is described in detail.

FIG. 2 is a diagram showing the configuration of a charge-transfer solid state imaging device, for example, a CCD solid state imaging device employed in the present invention.

The CCD shown in FIG. 2 includes an imaging section 11 and a peripheral section 10, which includes, for example, an output circuit, input and output terminals, and a bus.

Referring to FIG. 2, the imaging unit 11 includes a plurality of light receiver sections (pixels) 12 and a plurality of vertical transfer registers 14 (vertical transfer units). section)). The light receiver 12 is two-dimensionally arranged in a matrix form on the semiconductor substrate 10, and converts incident light into a single charge corresponding to the amount of incident light. The vertical transfer registers 14 are arranged in units of columns of the matrix arrangement of the light receiving unit 12, and transmit signal charges photoelectrically converted by the light receiving unit 12, respectively, and read out gate sections. It reads from the light receiving part 12 through 13. In this case, each signal is transmitted in the vertical direction (up-down direction in the figure) in units of columns.

A channel stop region 29 is disposed between the vertical transfer register 14 and a pixel column adjacent to the light receiving unit 12. The channel stop region 29 prevents entrainment of charges of other pixels in the transmission signal. Although not specifically shown, the channel stop region 29 is also arranged in the vertical direction of each light receiving portion 12, thereby preventing accompanying pixel signals.

A horizontal transfer register 15 (horizontal transfer section) is provided on one of the upper and lower sides of the imaging unit 11. The horizontal transfer register 15 sequentially transfers sent signal charges that have been shifted from the plurality of vertical transfer registers 14 along the horizontal direction (right-left direction in the figure). An output section 16 is provided at the end portion of the transfer destination side of the horizontal transfer register.

The output unit 16 is configured of, for example, a floating diffusion amplifier, converts signal charges sequentially transmitted by the horizontal transfer register 15 into a signal voltage, and converts the voltage into an output terminal ( It outputs as an image signal S1 to the outside of the CCD 1 via an output terminal 17. As shown in FIG.

A TG circuit 18 (TG), a vertical driver 19 and a horizontal driver 20 are provided outside the semiconductor substrate 10. The TG circuit 18, for example, for driving the vertical transfer register 14 and the horizontal transfer register 15 in accordance with the vertical synchronizing signal VD, the horizontal synchronizing signal HD and the master clock McKK, Generate various timing signals. More specifically, the TG circuit 18 is, for example, a four-phase vertical transfer pulse train VΦ1 to VΦ4 for transfer drive of the vertical transfer register 14 and two for transfer drive of the horizontal transfer register 15. Generate phase horizontal transmission pulses HΦ1 and HΦ2.

More specifically, the vertical driver 19 generates four-phase vertical transfer pulse trains VΦ1 to VΦ4 as driving pulses for the vertical transfer register 14, for example.

The horizontal driver 20 generates, for example, two-phase horizontal transfer pulses HΦ1 and HΦ2 as drive pulses to the horizontal transfer register 15.

The driver circuit 2 generates drive pulses for the vertical transfer register 14 and the horizontal transfer register 15 according to various signals from the TG circuit 18.

More specifically, the drive circuit 2 includes a vertical driver 19 for generating a drive pulse for the vertical transfer register 14 and a horizontal driver 20 for generating a drive pulse for the horizontal transfer register 15. do. Among these drivers, the vertical driver 19 corresponds to an example of the transmission pulse supply circuit of the present invention.

The four-phase vertical transfer pulse trains VΦ1 to VΦ4 are terminals 21-1 to 21-4 electrically coupled to corresponding transfer electrodes (not shown) of the vertical transfer register 14 through the vertical driver 19, respectively. Is supplied. Although not shown in the figure, the four-phase vertical transfer pulse trains VΦ1 to VΦ4 are imaged to prevent propagation delays caused by parasitic capacitance and resistance of the wires transmitting pulses, for example. It is supplied to each transfer electrode of the vertical transfer register 14 from both left and right sides of the unit 11. The two-phase horizontal transfer pulses HΦ1 and HΦ2 are terminals 22-1 and 22- of the horizontal transfer register 15 electrically coupled with the corresponding transfer electrodes of the horizontal transfer register 15 through the horizontal driver 20. 2) is supplied.

The four-phase vertical transfer pulse trains VΦ1 to VΦ4 are terminals 21-1 to 21- electrically coupled to corresponding transfer electrodes (not shown) of the vertical transfer register 14 through the vertical driver 19, respectively. 4) is supplied.

Suitably, the four-phase vertical transfer pulse trains VΦ1 to VΦ4 are vertically transmitted from both left and right sides of the imaging unit 11, for example, to prevent propagation delays caused by resistance and parasitic capacitance of the wires transmitting the pulses. It is supplied to each transfer electrode of the register 14.

The two-phase horizontal transfer pulses (HΦ1 and HΦ2) are horizontal drivers through terminals 22-1 and 22-2 of the horizontal transfer register 15 electrically coupled with the corresponding transfer electrodes of the horizontal transfer register 15. It is supplied from 20.

In the present invention, as described below, the electric potential of the four-phase vertical transfer pulse trains VΦ1 to VΦ4 used for transfer driving of the vertical transfer register is set.

3 is a cross-sectional view of the relevant part taken along line A-A in FIG.

Referring to FIG. 3, for example, a p-type well region 22 serving as an overflow area (OFB) impurity region is formed on the n-type semiconductor substrate 21. In addition, various impurity regions constituting the light receiving portion 12, the read gate portion 13, and the vertical transfer register 14 are formed on the p-type semiconductor layer 23.

More specifically, the light receiving part 12 includes a photodiode which forms a pn junction from the p-type semiconductor layer 23 and the n-type impurity region 24 formed in the p-type semiconductor layer 23. Include. The light receiving portion 12 further includes a hole storage region 25 composed of a p-type impurity region in a surface side portion in the n-type impurity region 24.

The vertical transfer register 14 includes a transfer channel 26 composed of n-type impurity regions formed in the surface layer protion of the p-type semiconductor layer 23, and a substrate surface on the transfer channel 26. and a polysilicon transfer electrode 28 formed on the substrate surface. A channel stop region 29 composed of a high concentration p-type impurity region is formed along the transmission channel 26.

The read gate part 13 divides a part of the transfer electrode 28 of the vertical transfer register 14 into a gate electrode and uses a gate insulating layer under the gate electrode, the gate electrode, and the p-type semiconductor layer 23. It has a metal-insulator-semiconductor (MIS) structure composed of a film (27). The gate insulating film 27 is composed of a single layer or a multilayer insulating film, for example, an oxide-nitride-oxide (ONO) structure.

The light shield film 31 is formed of aluminum or tungsten, for example, and covers each vertical transfer register 14 except for the light receiving portion 12 through an interlayer insulation film 30. It is formed in such a way that.

The setting of the potentials of the four-phase vertical transfer pulse trains VΦ1 to VΦ4, which are features of the present invention, will be described with reference to the first and second embodiments.

(First embodiment)

4A to 4D are waveform diagrams of the four-phase vertical transfer pulse train according to the first embodiment, respectively. Referring to the drawings, the four-phase vertical transfer pulse trains VΦ1 to VΦ4 are normally normalized each having a period of positive side potential (0 V in this embodiment) longer than the period of negative side potential (negative voltage value VL in this embodiment). A high transmission pulse (normally-high vertical transmission pulses VΦ1 and VΦ2 in this embodiment) and a normally-low transmission pulse having a period of negative side potential longer than the period of the positive potential (vertical transmission pulse VΦ3 in this embodiment, respectively). And VΦ4).

(First embodiment)

4A to 4D are waveform diagrams showing vertical transfer pulse trains of four phases according to the present embodiment. As shown in the figure, the vertical transfer pulse trains Vφ1 to Vφ4 of four phases have a normally-longer duration (0 V in this example) than the period of the negative potential (NV in this example). A high transfer pulse train (in this example, the vertical transfer pulse trains Vφ1 and Vφ2) and a transfer pulse train to a normally-long period where the period of the negative potential is longer than the period of the positive potential (in this example, the vertical transfer pulse trains Vφ3 and Vφ4). Doing.

In the first embodiment, the negative side potential VL 'of the vertically-transfer pulses Vφ3 and Vφ4 to the normally-higher is made an absolute value than the negative side potential VL of the vertically-transfer pulses Vφ1 and Vφ2 of the normally-high. It is characterized by small setting (potential VL 'approaches 0V). As an example, the negative side potential VL 'of the vertical transfer pulses Vφ3 and Vφ4 is set to be smaller than the negative side voltage VL of the vertical transfer pulses Vφ1 and Vφ2. Do it.

The negative potential VL 'of the vertical transfer pulses Vφ3 and Vφ4 is a vertical transfer pulse having an amplitude of "0 [V] -VL" which is in the vertical driver 19 and is supplied from the TG circuit 18, for example. For example, it can set easily by dividing by a resistance dividing circuit. According to this, there is no need to provide a separate power supply for the negative potential VL '. In the case employed in this configuration, the resistance voltage divider circuit in the vertical driver 19 has the function of a potential setting means as described in the further claims of the present invention.

However, the potential setting means is not limited to the resistance voltage divider circuit in the vertical driver 19. For example, a resistive voltage divider circuit is provided on the semiconductor substrate 10 and has a "0 [V]-VL" amplitude in accordance with a vertical transfer pulse of "0 [V]-VL" amplitude supplied from the vertical driver 19. It is also possible to generate the vertical transfer pulses Vφ3 and Vφ4.

Therefore, the negative side potential VL 'of the vertically-transfer pulses Vφ3 and Vφ4 to the normally-lower is set to be smaller than the negative side potential VL of the vertically-transfer pulses Vφ1 and Vφ2 of the normally-high, The vertical transfer register 14 is driven to transfer by the four-phase vertical transfer pulse trains Vφ1 to Vφ4 including the vertical transfer pulses Vφ3 and Vφ4. As a result, the following effects can be obtained.

In particular, the dark current in the vertical transfer register 14 mainly occurs in the portion under the transfer electrode to which the normally-high vertical transfer pulses Vφ1 and Vφ2 are applied. This is because in the normally-high vertical transfer pulses Vφ1 and Vφ2, the period of the negative side potential is short and the period of the pinning effect is short. Therefore, even if the negative side potential VL 'of the vertical transfer pulses Vφ3 and Vφ4 to the normally-lower generation of the dark current is much smaller than the normal-high vertical transfer pulses Vφ1 and Vφ2, the absolute value may be reduced to some extent as an absolute value. However, there is little effect on the increase of dark current.

On the other hand, the electric field is strongly hung on the gate oxide film 37 (see FIG. 3), and the electric field is applied through the transfer electrodes to which the vertical transfer pulses Vφ3 and Vφ4 are normally applied. Therefore, a decrease in the absolute value of the negative potential VL 'of the vertically transmitted pulses Vφ3 and Vφ4 to the normally-lead leads to a decrease in the electric field applied to the gate oxide film 37.

As a result, the negative side potential VL 'of the vertically transmitted pulses Vφ3 and Vφ4 to the normally-lower is set to be smaller than the negative side potential VL of the vertically transmitted pulses Vφ1 and Vφ2 of the normally-high. Therefore, in order to reduce the electric field applied to the gate oxide film 37 while suppressing the influence of the increase in the dark current, the dark current is not increased, thus improving the reliability of the device and thus transferring the vertical transfer register 14. The efficiency can be improved.

Although it is typically shown in FIGS. 4A-4D, the period in which there is no waveform change in the period T0 before and after that is called "waiting time".

The standby time includes at least a light receiving and reading period. In the light receiving period, the signal charges generated by the light receiving portion 12 are accumulated; The accumulated signal charges are discharged to the vertical transfer register 14 via the read gate portion 13.

In the structure shown in FIG. 3, since the transfer electrode 28 also serves as the gate electrode of the read gate portion 13, vertical transfer and light reception cannot be performed at the same time.

Therefore, the vertical transfer pulses Vφ1 and Vφ2 shown in Figs. 4A and 4B have the standby level at the positive potential, and the vertical transfer pulses Vφ3 and Vφ4 shown in Figs. 4C and 4D have the standby levels set as the negative potential, respectively. It is.

The vertical transfer pulses Vφ1 and Vφ2 correspond to the "first transfer pulse" of the present invention, and the vertical transfer pulses Vφ3 and Vφ4 correspond to examples of the "second transfer pulse" of the present invention.

Therefore, the feature of the present invention is that the negative potential VL 'of the normally-low vertical transfer pulses Vφ3 and Vφ4 (second transmission pulse) is the normally-high vertical transfer pulses Vφ1 and Vφ2 (first transmission). Pulse) is set smaller than the absolute potential VL.

As an example, the negative side potential VL 'of the vertical transfer pulses Vφ3 and Vφ4 is set to be smaller than the negative side voltage VL of the vertical transfer pulses Vφ1 and Vφ2. Do it.

The negative potential VL 'of the vertical transfer pulses Vφ3 and Vφ4 is in the vertical driver 19 and is a vertical transfer pulse of " 0 [V]-VL " amplitude supplied from the TG circuit 18, for example. The voltage can be easily set by dividing by a resistance voltage dividing circuit. According to this, there is no need to provide a separate power supply for the negative potential VL '.

However, the potential setting means is not limited to the resistance voltage divider circuit in the vertical driver 19. For example, a resistive voltage divider circuit is provided on the semiconductor substrate 21 (see FIG. 3), and "0 [V" in accordance with the vertical transfer pulse of the "0 [V]-VL" amplitude supplied from the vertical driver 19. It is also possible to generate vertical transfer pulses Vφ3 and Vφ4 with] −VL ″ amplitude.

Therefore, the negative side potential VL 'of the vertically-transfer pulses Vφ3 and Vφ4 to the normally-lower is set to be smaller than the negative side potential VL of the vertically-transfer pulses Vφ1 and Vφ2 of the normally-high, The vertical transfer register 14 is driven to transfer by the four-phase vertical transfer pulse trains Vφ1 to Vφ4 including the vertical transfer pulses Vφ3 and Vφ4. As a result, the following effects can be obtained.

The dark current in the vertical transfer register 14 mainly occurs at a portion below the transfer electrode to which normally-high vertical transfer pulses Vφ1 and Vφ2 are applied. This is because in the normally-high vertical transfer pulses Vφ1 and Vφ2, the period of the negative side potential is short and the period of the pinning effect is short. Therefore, even if the negative side potential VL 'of the vertical transfer pulses Vφ3 and Vφ4 to the normally-lower generation of the dark current is much smaller than the normal-high vertical transfer pulses Vφ1 and Vφ2, the absolute value may be reduced to some extent as an absolute value. However, there is little effect on the increase of dark current.

On the other hand, the electric field is strongly hung on the gate oxide film 37 (see FIG. 3), and the electric field is applied through the transfer electrodes to which the vertical transfer pulses Vφ3 and Vφ4 are normally applied. Therefore, a decrease in the absolute value of the negative potential VL 'of the vertically transmitted pulses Vφ3 and Vφ4 to the normally-lead leads to a decrease in the electric field applied to the gate oxide film 37.

As a result, the negative side potential VL 'of the vertically transmitted pulses Vφ3 and Vφ4 to the normally-lower is set to be smaller than the negative side potential VL of the vertically transmitted pulses Vφ1 and Vφ2 of the normally-high. Therefore, in order to reduce the electric field applied to the gate oxide film 37 while suppressing the influence of the increase in the dark current, the dark current is not increased, thus improving the reliability of the device and thus transferring the vertical transfer register 14. The efficiency can be improved.

By setting the potential of the four-phase vertical transfer pulse trains Vφ1 to Vφ4, the features of the present invention are described below.

4A to 4D are waveform diagrams showing a vertical transfer pulse train of four phases according to the first embodiment.

As shown in the figure, the vertical transfer pulse trains Vφ1 to Vφ4 of four phases have a normal-high period in which the period of the positive side potential (0 V in this example) is longer than the period of the negative side potential (NV voltage value VL in this example). The transfer pulse train (in this example, the vertical transfer pulse trains Vφ1 and Vφ2) and the transfer pulse train (normally, the vertical transfer pulse trains Vφ3 and Vφ4) to the longer distance than the period of the positive potential are included.

The vertical transfer pulses Vφ1 and Vφ2 are horizontally transferred from the vertical transfer register 14 by repeating the waveform change shown in the period T1 during the vertical transfer driving the vertical transfer register 14 of FIG. 2. The signal charge is transferred to the side of the register 15.

(Second embodiment)

In the present embodiment (second embodiment), the level change of the transmission pulse is intermittently implemented. 2 and 3 are also commonly applied to this embodiment.

5A to 5D are waveform diagrams showing vertical transfer pulse trains Vφ1 to Vφ4 of four phases according to the second embodiment.

As shown in the figure, the vertical transfer pulse trains Vφ1 to Vφ4 of the four phases have a longer period of positive potential (0 V in this example) than the period of negative potential (negative voltage value VL) as in the case of the first embodiment. The normally-high vertical transfer pulses Vφ1 and Vφ2 and the negative side potential include the normal-normal vertical transfer pulses Vφ3 and Vφ4 longer than the positive potential period.

In the second embodiment, the negative side potential VL 'of the normal-to-normal vertical transfer pulses Vφ3 and Vφ4 is made an absolute value than the negative side potential VL of the normal-high vertical transfer pulses Vφ1 and Vφ2. Make it small intermittently (potential (VL ') approaches 0V). As an example, only the voltage value of about 5% of the corresponding potential VL is lower than the negative potential VL of the vertical transfer pulses Vφ1 and Vφ2, and the negative potential VL 'of the vertical transfer pulses Vφ3 and Vφ4 is intermittently smaller. do.

However, in the present embodiment, the negative potential VL 'of the vertically transmitted pulses Vφ3 and Vφ4 (the second transmission pulses) to the normally-separated values is set to the vertically transmitted pulses Vφ1 and Vφ2 of the normally-high (first). It is made intermittently smaller than the negative potential VL of the transmission pulse) (potential VL 'approaches 0V).

That is, as in the first embodiment, the negative side potential VL 'of the vertically transmitted pulses Vφ3 and Vφ4 to the normally-normally is always the negative side potential VL of the vertically transmitted pulses Vφ1 and Vφ2 of the normally-high. Instead of making it smaller than the absolute value, it is made intermittently small and the negative potential VL in the remaining period.

As an example, only the voltage value of about 5% of the corresponding potential VL than the negative potential VL of the vertical transfer pulses Vφ1 and Vφ2 intermittently causes the negative potential VL 'of the vertical transfer pulses Vφ3 and Vφ4. Make it small.

The approach according to the second embodiment is effective as in the first embodiment, and the negative side potential VL 'of the normally-vertically vertical transfer pulses Vφ3 and Vφ4 is dark-high vertical transfer pulses Vφ1, Since all the time is set to an absolute value smaller than the negative potential VL of Vφ2), it causes an increase in the dark current.

That is, the difference from the first embodiment, the negative side potential VL 'of the normally-low vertical transfer pulses Vφ3 and Vφ4 is the absolute value than the negative side potential VL of the normally-high vertical transfer pulses Vφ1 and Vφ2. It is not always small. However, in this embodiment, the negative potential VL 'is intermittently set smaller than the negative potential VL of the vertical transfer pulses Vφ1 and Vφ2, and is set to the negative potential VL in the remaining period. That is, the negative potential VL 'of the normally-low vertical pulses Vφ3 and Vφ4 is set intermittently large at an absolute value, whereby the interface level can be eliminated to prevent an increase in the dark current.

The pinning effect is intensified by the change to the negative potential, and the effect remains for a while. Therefore, in the case where the negative potential of the second transmission pulse is intermittently changed, the effect of pinning does not change as compared with the case where it is not, but the driving ability is increased.

For the above reasons, the pulse control method of the present embodiment can maintain the effect of making it difficult to generate electrons from the interface level by using the pinning effect as compared with the first embodiment.

At the same time, the negative side potential VL 'of the vertically transmitted pulses Vφ3 and Vφ4 to the normally-lower is made intermittently smaller than the negative side potential VL of the vertically transmitted pulses Vφ1 and Vφ2 of the normally-higher. The time required for the electric field to be strongly applied to the gate oxide film 37 is shorter than that of the conventional example in which the vertical transfer pulses Vφ3 and Vφ4 to the normally-normally are always negative side potential VL. The deterioration of the transmission efficiency is reduced.

Therefore, the embodiment is described by exemplifying the case of four-phase driving of the vertical transfer register 14 by using four-phase vertical transfer pulse trains Vφ1 to Vφ4. However, the present invention is not limited to the application of four-phase drive and can be generally applied widely to other multiphase drive systems, such as three-phase and six-phase drive systems.

Moreover, in the embodiment, the driving method is described with reference to the example in the case of the vertical transfer register 14 provided as the driven-object charge transfer portion of the present invention. However, the driving method is a normally-high transfer pulse in which the horizontal transfer register 15 has a duration of the positive potential longer than the period of the negative potential and a normally-low with a period of the negative potential longer than the period of the positive potential. It can be applied to the horizontal transfer register 15 in a configuration that is transfer-driven by a multiphase transfer pulse, including the transfer pulse.

(Application example)

The CCD solid state image pickup device according to the above embodiment is suitable for use as any one image pickup device of an image pickup device, such as a digital camera and a video camera.

In the case of this example, the imaging device relates to a camera system (such as a digital camera or a video camera) including a camera module (used in an electronic device such as a mobile phone) or a camera module. The camera module includes a solid-state imaging device prepared as an imaging device, an optical system for imaging image light of a subject on an imaging surface (light receiving surface) of the solid-state imaging device, and a signal processing circuit of the solid-state imaging device.

10 is a block diagram showing an example of the configuration of an image input device according to the present invention. Referring to FIG. 10, the imaging device of this example is configured to include an optical system including, for example, a lens 6, an imaging device 1, a signal processing circuit 4, and a device driving circuit 2. .

An optical system including a lens 6 picks up image light coming from a subject on an image pickup surface of the image pickup device 1. By being driven by the device driving circuit 2, the image pickup device 1 is an image captured on an image capture plane through the lens 6 in an electronic signal, for example, in units of fields and pixels. Output is performed in units of an image signal corresponding to one frame obtained by switching of light. The CCD solid-state imaging device corresponding to the embodiment is used as the imaging device 1.

The signal processing circuit 4 includes, for example, a correlated double sampling (CDS) circuit and an automatic gain control (AGC) circuit, and the processing is performed on an image signal output from the imaging element 1, for example. The CDS circuit eliminates the fixed pattern noise included in the image signal, and the AGC circuit performs the stabilization (gain adjustment) of the signal level.

For example, as shown in FIG. 2, the device driving circuit 2 is configured to include a TG circuit 18, a vertical driver 19, and a horizontal driver 20. Thereby, the imaging element 1 is driven by using the four-phase vertical transfer pulse trains Vφ1 to Vφ4 according to the first or second embodiment. That is, between the four-phase vertical transfer pulse trains Vφ1 to Vφ4 according to the first embodiment, the negative potential VL 'of the normally-transformed vertical transfer pulses Vφ3 and Vφ4 is the normally-high vertical transfer pulse Vφ1. , The negative side is set smaller than the negative potential VL of the Vφ2, and between the four-phase vertical transfer pulse trains Vφ1 to Vφ4 according to the second embodiment, the negative side of the normal transfer pulses Vφ3 and Vφ4. The potential VL 'is set intermittently smaller than the negative potential VL of the normally-high vertical transfer pulses Vφ1 and Vφ2.

As described above, in imaging devices such as digital cameras and video cameras, since the CCD solid-state image pickup device according to the embodiment is mounted as the image pickup device, device reliability can be improved without increasing the dark current in the CCD solid-state image pickup device. , High quality images can be obtained.

10 is a block diagram showing an example of the configuration of an image input device according to the present invention.

In the drawings, components and signals common to those in FIGS. 6 and 7 are assigned the same reference numerals, and descriptions thereof will be omitted.

The image input device 50 shown in FIG. 10 is, for example, an optical system including a lens 6, an aperture 7 and an aperture driving means 8, an imaging element (e.g., CCD 1), and driving. It is comprised so that the circuit 2, the signal processing circuit 4, and the control circuit 5 may be included.

The optical system uses the diaphragm 7 to limit the area of image light from the subject, and uses the lens 6 to concentrate the light on the lens 6, whereby an imaging element (e.g., CCD ( An image is formed on the imaging surface of 1)). By being driven by the drive circuit 2, the imaging device receives an image pickup signal S1 of one frame that can be obtained by converting image light captured on the imaging surface through the lens 6 into an electric signal in units of pixels, for example. For example, output in units of fields.

At this time, the aperture 7 is connected to the aperture driving means 8. The aperture driving means 8 inputs the iris control signal S45 from the automatic iris control (AIC) circuit 45 in the signal processing circuit 4 and controls the aperture amount of the aperture 7. It is a mechanical driving means.

In the present embodiment, this iris control signal S45 is input to the drive circuit 2 via the control circuit 5, whereby it is a "signal which changes depending on the amount of signal charge and the brightness of an image". The iris control signal S45 is input to the drive circuit 2. And the adjustment of the positive potential according to the first and second embodiments is performed. Although not shown, the positive potential can be adjusted based on the gains according to the first and second embodiments.

Therefore, in the image input device 50, an optical system, a CCD 1 as an imaging device, a drive circuit 2 and a signal processing circuit 4 and a control circuit 5 required for feedback control are mounted. As a result, a high-quality captured image can be obtained because the reliability or the transfer efficiency of the device can be improved without increasing the dark current.

(Third Embodiment)

In the above two embodiments, the presence or absence of a level change is controlled according to the difference of the standby level of a transmission pulse.

However, in the third embodiment, the presence or absence of the change of the level of the transfer pulse is controlled by using the feedback based on the imaging signal S1 output from the CCD 1 of FIG.

FIG. 6 is a diagram showing a block of a driving apparatus including a feedback control circuit together with the CCD 1.

The drive device shown in the figure includes a drive circuit 2, a TG circuit 18, a signal processing circuit 4 and a control circuit 5 in a feedback control circuit 20 surrounded by broken lines.

Among these, the driving circuit 2 and the TG circuit 18 have the same basic functions and operations as those in the first embodiment (Fig. 2 and its description). The CCD 1 is also the same as in the first embodiment.

7 is a block diagram illustrating an exemplary configuration of the signal processing circuit 4.

The signal processing circuit 4 shown in the figure includes a CDS circuit 41 (correlated double sampling circuit), an AGC circuit 42 (automatic gain control circuit) including a variable gain amplifier, and a gamma correction circuit 43 (" [gamma]). "," Synchronous output circuit 44 (represented by "Sync"), and AIC circuit 45 (automatic iris control circuit).

The CDS circuit 41 inputs the imaging signal S1 from the CCD 1 and effectively removes the induced noise, particularly the reset noise, included in the imaging signal S1.

The AGC circuit 42 inputs the gain control signal S5 from the control circuit 5 of FIG. 6 and adjusts the gain of the internal variable gain amplifier. Thereby, the gain adjustment of the imaging signal S41 input to the AGC circuit 42 from the CDS circuit 41 is performed.

The control circuit 5 of FIG. 6 enables the input of the imaging signal S41 from the CDS circuit 41, and detects the brightness of the screen (the imaging screen) indicated by the imaging signal.

Although not specifically shown, the control circuit 5 can be configured to include a memory for storing image pickup signals in units of frames, a circuit for averaging (or integrating), a CPU, and the like. With this configuration, the control circuit 5 obtains the brightness of the captured screen, calculates the gain of the AGC circuit 42 suitable for this brightness, and uses the gain information as the gain control signal S5 as the gain control signal S5. ) In the present embodiment, the gain control signal S5 and the control circuit 5 correspond to examples of " signal changing in accordance with the amount of signal charge " and " means for outputting signal ", respectively.

The gamma correction circuit 43 is, for example, a circuit that performs luminance correction for fitting an input signal to a device or the like connected to an output.

The synchronous output circuit 44 is a circuit for inputting the synchronous signal SYNC and sending the output signal S44 to a circuit or an integrated circuit located at a later stage in synchronization with this signal. In some cases, the synchronous output circuit 44 may have a function of signal amplification.

The AIC circuit 45 is a circuit for automatically performing iris adjustment. For this reason, the AIC circuit 45 may have a function of detecting the brightness of the captured screen. However, in this example, since the control circuit 5 has a function of detecting the brightness, the brightness information therefrom is obtained, and the iris control signal S45 is generated and output based on the brightness information.

The gamma correction circuit 43, the synchronous output circuit 44 and the AIC circuit 45, and the CDS circuit 41 described above are not essential configurations.

Next, using the waveform diagrams of FIGS. 8A and 8B, level adjustment corresponding to the brightness of the captured screen will be described.

This adjustment is performed by the vertical driver 19 of FIG. This level adjustment is made for normally-high transfer pulses, that is, for vertical transfer pulses Vφ1 and Vφ2 at the standby potentials.

8A and 8B represent a vertical transmission pulse Vφ1. Although not particularly shown, the vertical transfer pulse Vφ2 is similarly controlled.

8A shows the waveform of the vertical transfer pulse Vφ1 when the imaging screen is relatively bright, and FIG. 8B shows the waveform of the vertical transfer pulse Vφ1 when the imaging screen is relatively dark.

When the imaging screen is relatively bright, the gain is set relatively small in the gain control signal S5. On the other hand, when the imaging screen is relatively dark, on the contrary, the gain is set large in the gain control signal S5. By performing the automatic gain control in this manner, the AGC circuit 42 can limit the amount of signals that can be handled by the circuit connected to the rear stage or the video display unit, or make the noise inconspicuous.

When the gain is relatively small (the image screen is bright), the amount of signal charge generated in the CCD 1 is relatively large, so that the signal-to-noise ratio (S / N ratio) does not decrease even if there is a dark current. Therefore, as shown in Fig. 8A, the positive potential (0 [V] in this example) at the standby level is maintained as it is. As a result, since the amount of charge handled in the vertical transfer is not reduced, when the amount of signal charge is large, the transfer efficiency is not reduced. That is, it is possible to prevent the generation of untransferred residual charges during transfer.

On the other hand, when the gain is relatively large (the image screen is dark), the amount of signal charge is relatively small. For this reason, even if the waveheight value is reduced, for example, untransferred residual charges do not occur, so that efficient transmission is possible. Therefore, as shown in FIG. 8B, the control which slightly lowers the positive potential from 0 [V] is performed.

For this amount of reduction, an optimal value exists depending on the average amount of signal charge (brightness of the screen) and the amount of dark current increase. In this example, the negative potential is lowered from 0 [V] to -1 [V]. In addition, the fall amount (level change amount) is arbitrary, and when the gain value is adjusted according to the threshold value by changing the threshold value for detecting the brightness of the image, the amount of level change amount is obtained for each gain or gain width. You can change it. For example, it is possible to adjust from 0 [V] to -0.5 [V], -1 [V], -1.5 [V] or -2 [V].

8A and 8B, the side potential (in this example, the side potential VL = -7.5 [V]) is the same.

However, it is also possible to perform a combination of the first and second embodiments in which the level of the negative potential is changed.

Next, with reference to FIG. 9, the effect of positive side electric potential adjustment is demonstrated.

9 is a graph showing the positive potential VH dependence of the degree of white noise (arbitrary unit: (a.u.)) on the display screen.

The degree of white noise classifies the voltage change which becomes white noise (white noise point) when inputting a constant video signal on an actual display screen by order, the number of white noise points in each rank, and the total rank thereof. Managed by water.

In this graph, three broken lines corresponding to three CCDs are shown.

As can be seen from this graph, the white noise point is reduced by setting the positive potential VH from 0 [V] to -1 [V].

Therefore, according to the present embodiment, when the signal amplification gain that does not affect the vertical transmission is large, the positive potential VH of the first transmission pulse (vertical transmission pulses Vφ1 and Vφ2) is changed so that the crest value becomes smaller. . As a result, the pinning effect can be enhanced and the dark current can be reduced without lowering the transfer efficiency.

For this reason, the S / N ratio at the time of imaging a dark screen can be improved. In addition, at this time, since the peak value of a transfer charge can be lowered, power consumption is reduced by that much.

Fourth Embodiment

The CCD driving apparatus according to the above embodiment is very suitable as an IC for driving the imaging element in an image input apparatus such as a digital camera or a video camera.

In the case of this example, the image input device refers to a camera module such as a digital camera or a video camera including a camera module (used on an electronic device such as a mobile phone) or a camera module. The camera module includes a solid-state imaging device as an imaging device, an optical system for picking up image light of a subject on an imaging surface (light receiving surface) of the solid-state imaging device, and a signal processing circuit of the solid-state imaging device. 10 is a block diagram showing an example of the configuration of an image input device according to the present invention. As shown in FIG. 6, components and signals common to those in FIGS. 6 and 7 are denoted by the same reference numerals, and description thereof is omitted.

The image input device 50 shown in FIG. 10 includes an optical system including a lens 6, an aperture 7, and an aperture driving means 8, an imaging device (e.g., a CCD 1), and a driving circuit 2 ), The signal processing circuit 4, the control circuit 5, and the like.

The optical system restricts the area of the image light from the subject by the aperture 7 and uses the lens 6 to concentrate on the lens 6, whereby the imaging element (for example, the CCD 1) is used. An image is formed on the imaging surface. Driven by the element driving circuit 2, the imaging element (for example, the CCD 1) is one that can be obtained by converting the image light imaged on the imaging surface by the lens 6 into an electric signal in units of pixels. The image pickup signal S1 of the frame of? Is output, for example, in units of fields.

At this time, the aperture driving means 8 is connected to the aperture 7. The aperture driving means 8 is mechanical driving means for inputting the iris control signal S45 from the AIC circuit 45 in the signal processing circuit 4 to control the opening amount of the aperture 7.

In the present embodiment, this iris control signal S45 is input to the drive circuit 2 via the control circuit 5, whereby it is a "signal which changes depending on the amount of signal charge and the brightness of an image". The iris control signal S45 is input to the drive circuit 2. Then, the positive potential is adjusted according to the fourth embodiment.

Although not shown, the positive potential can be adjusted based on the gain of the third embodiment.

Therefore, in the image input device 50, an optical system, a CCD 1 as an imaging device, a drive circuit 2, and a signal processing circuit 4 and a control circuit 5 necessary for feedback control are mounted. As a result, a high-quality captured image can be obtained because the reliability or transmission efficiency of the device can be improved without increasing the dark current.

Finally, based on the gain of the third embodiment and the iris control of the present embodiment, the power consumption of the " output circuit " is reduced, whereby a method of reducing noise and a configuration therefor will be described.

The "output circuit" is, for example, a circuit formed in the peripheral portion 10 of the CCD 1 (which may be a CMOS sensor in this example) in FIG. 2.

In addition to the dark current generated by the CCD 1 itself, the noise that generates the white noise is also increased by heat generation, that is, thermal noise, in the circuit portion (in particular, the output circuit) due to the increase in power consumption. Therefore, it is important to suppress not only the dark current but also this thermal noise. In particular, when the exposure time is extended to several hundred milliseconds [msec], such as when photographing a night scene, noise reduction of the output circuit becomes essential.

In addition, in order to optimize the output circuit according to a large data rate, it is necessary to increase the frequency characteristic of the output circuit to a higher range. However, an output circuit driven at a high frequency by inputting a high frequency signal is likely to generate thermal noise due to an increase in power consumption. That is, the S / N ratio of the circuit itself falls. In addition, heat generation to the output circuit is transmitted to the entire image pickup device, and the dark current also increases by that amount.

Therefore, in this example, by limiting the current consumption of the output circuit, high frequency noise components are suppressed together with the generated thermal noise due to the heat generation, and also dark current is hardly generated.

There are two methods of driving a CCD: an operation mode of two methods, a moving image pick-up mode with a high data rate and a still image pick-up mode with a low data rate.

In particular, a CCD used in a digital camera (DSC) includes a mode for photographing still images that are recorded and stored, and a monitoring mode for displaying a moving image on a monitor screen for focusing and framing still images. It is required. In addition, a video capturing mode exists in a camera capable of capturing video.

On-chip output circuits are optimally designed for high data rate video modes that require maximum performance. Since the monitoring mode is also a kind of moving picture mode, a higher data rate is required than the still image pick-up mode.

However, when shooting still images, the data rate can be slower than that of a moving picture, and the output circuit optimized for the moving picture pick-up mode becomes over-specified, accompanied by useless power consumption and heat generation, and this. The decrease in S / N ratio is called.

Hereinafter, a method and a configuration therefor for eliminating unnecessary power consumption and accompanying unnecessary dynamic range expansion and thereby suppressing heat generation to improve the S / N ratio will be described.

This description describes the conversion of the circuit configuration in the monitoring mode assuming the DSC and the still image pick-up mode. In the following description, the "monitoring mode" may be replaced with the "movie imaging mode".

The configuration of the CCD is the same as shown in Figs. 2 and 3, and portions other than the CCD can be applied to Figs.

The mode switching is performed by the control circuit 5 of FIG. 6, and the mode switching signal S5m can be supplied from the control circuit 5 to the output circuit of the CCD 1, as indicated by the dotted line.

The control circuit 5 sets a monitoring mode, for example, by supplying a power supply or the like. Then, the focusing ends, and for example, the camera enters the still image capturing mode at the moment when the aim is hit.

11A to 11C each show a structural example of the output circuit.

This output circuit is composed of two stage source follower circuits. Specifically, the output circuit includes two NMOS transistors, that is, a signal-input NMOS transistor Q1 and a signal-output transistor Q2. The input signal Sin is input to the signal input NMOS transistor Q1 through its gate, and the drain thereof is connected to the supply line of the power supply voltage Vdd. In the signal output NMOS transistor Q2, the gate is connected to the source of the signal input NMOS transistor Q1, the drain is connected to the supply line of the power supply voltage Vdd, and the output signal Sout is outputted from the source.

In the configuration of FIGS. 11A and 11B, a load transistor Q3 formed of an NMOS transistor is connected between the source of the signal input NMOS transistor Q1 and the ground voltage GND. In addition, a load transistor Q4 formed of an NMOS transistor and a resistor R (may be a variable resistor) are connected between the source of the signal output NMOS transistor Q2 and the ground voltage GND. The switch is connected in parallel with the resistor R. The load transistors Q3 and Q4 work as a resistor determined by the bias voltage. Thus, the change in bias voltage VGG makes the transistor to work as a variable resistor.

In the configuration of Fig. 11B, the switch described above is formed by the bipolar transistor Q5. In FIG. 11A, the type of this switch is not limited by showing by "SW" which means a general switch.

In either case, the switch SW or the bipolar transistor Q5 is controlled by the mode switching signal S5m given from the control circuit 5 of FIG. 6, for example.

Specifically, in the monitoring mode in which the gain is not increased, the switch SW or the bipolar transistor Q5 is turned on; In the still image pick-up mode in which the gain is increased, the switch SW or the bipolar transistor Q5 is turned off.

In monitoring mode, the picture quality may be reduced because the image is viewed on a small monitor screen, and the gain does not increase.

Therefore, since the frequency response of the output circuit does not have to be high, the current flowing through the resistor is bypassed to suppress heat generation. At this time, the current flowing in the signal input NMOS transistor Q1 and the load transistor Q4 is offset from the optimum value, and the output current is also reduced. However, in the still image pick-up mode, since the image is recorded, the image quality cannot be degraded, so that the gain is increased. Therefore, the frequency response of the output circuit also needs to be set to the highest performance. For this reason, a resistor is put in a circuit and sets the bias condition optimized by the bias voltage VGG. As a result, the current flows to the resistor R, and heat is generated, thereby increasing the power consumption of the circuit.

By this operation, particularly unnecessary heat generation and power consumption can be reduced, whereby the S / N ratio can be improved.

In the output circuit shown in Fig. 11C, the resistor R is omitted, and instead, the capacitor C and the bipolar transistor Q6 are connected between the output node and the ground voltage GND. Bipolar transistor Q6 is controlled by mode switching signal S5m, like bipolar transistor Q5 in FIG. 11B.

The bipolar transistor Q6 is turned on in the monitoring mode, but turned off in the still image pick-up mode.

Thus, in the monitoring mode, the frequency responsiveness of the output signal Sout to the input signal Sin is reduced, and the noise is lowered by the band limit. However, power consumption, heat generation amount, and the like for charging and discharging the capacitor C do not change.

By adding the above control to the fourth to fourth embodiments, there is an advantage that the S / N ratio can be further improved.

Further, the first to fourth embodiments have been described taking the case of four-phase driving in which the vertical transfer register 14 is driven by the four-phase vertical transfer pulses Vφ1 to Vφ4. However, the present invention is not limited to the application of four-phase drive, but can be applied to a general multiphase drive system such as three-phase drive, six-phase drive, or the like.

Further, in the embodiment, the driving method has taken the vertical transfer register 14 as an example of the charge transfer unit to be driven of the present invention. However, the horizontal transfer register may be formed by a multi-phase transfer pulse including a normally-high transfer pulse whose duration of the positive potential is longer than the period of the negative potential and the transfer pulse to normally-long period of the negative potential. In the case of applying the configuration for transfer driving 15), it is also applicable to the horizontal transfer register 15.

It is a matter of course that various changes, combinations, partial combinations and substitutions may be made by those skilled in the art within the scope of the appended claims or equivalents thereof by design requirements and other elements.

According to embodiments of the present invention, the influence of dark current increase is suppressed in such a manner that the negative potential of the normally-low vertical transfer pulse is smaller than the negative potential of the normally-high vertical transfer pulse, The applied electric field can be reduced. Therefore, device reliability can be improved without increasing dark current.

In addition, according to embodiments of the present invention, the imaging device can be operated at a high transmission efficiency at the same time the generation of dark current is suppressed or the effect of lowering the transmission efficiency is reduced.

Claims (21)

In a solid state imaging device, Normally high transfer pulses with a period of positive side potential longer than the period of negative side potential and normally with periods of negative side potential longer than the period of negative side potential A charge transfer section transfer-driven by a normally-low transfer pulse, And a potential setting means for setting the negative side potential of the normally-low transmission pulse to have an absolute value smaller than the negative side potential of the normally-high vertical transfer pulse. device. The method of claim 1, And the potential setting means sets the negative side potential of the normally-transfer pulse to be smaller than the negative side potential of the normally-high vertical transfer pulse. device. Charge transfer section that is transfer-driven by a normally-high transfer pulse having a period of the positive potential longer than the period of the negative potential and a normally-low transfer pulse having a period of the negative potential longer than the period of the negative potential In the driving method of the solid-state imaging device comprising a), And the driving method is configured to render the negative potential of the normally-low transfer pulse smaller than the negative potential of the normally-high vertical transfer pulse. . The method of claim 3, And the negative side potential of the normally-low transfer pulse is intermittently rendered to have an absolute value smaller than the negative side potential of the normally-high vertical transfer pulse. In an imaging apparatus, Solid-state imaging device, An optical system for guiding imaging light from a subject on an imaging surface of the solid state imaging device, The solid state imaging device, A charge transfer section which is transfer-driven by a normally-high transfer pulse having a period of the positive potential longer than the period of the negative potential and a normally-low transfer pulse having a period of the negative potential longer than the period of the negative potential; And potential setting means for setting the negative potential of the normally-low transmission pulse to have an absolute value smaller than the negative potential of the normally-high vertical transmission pulse. Device. The method of claim 5, And the potential setting means is configured to intermittently set the negative potential of the normally-low transfer pulse to be smaller than the negative potential of the normally-high vertical transfer pulse. In the method of driving a solid-state image pickup device for transmitting the signal charge (signal charge) generated by the light reception in the charge transfer unit, And a transfer pulse supply circuit for generating a first transfer pulse and a second transfer pulse and supplying the generated first transfer pulse and the second transfer pulse to the charge transfer unit of the solid state image pickup device. , The first transfer pulse is a pulse having a positive potential and a negative potential during charge transfer during a standby time including when light reception occurs where the signal charge is generated, The second transfer pulse is a pulse having a negative side potential during the waiting period and a positive side potential during the charge transfer, and the negative side potential is configured to have an absolute value smaller than the negative side potential of the first transfer pulse. A method of driving a solid state imaging device. The method of claim 7, wherein And the transfer pulse supply circuit is configured to intermittently make the negative potential of the second transfer pulse smaller than the negative potential of the first transfer pulse. A method of driving a solid state image pickup device for transmitting signal charges generated by light reception in a charge transfer unit, converting the signal charges into an image signal, and outputting the image signal, The first transfer pulse and the second transfer pulse may be supplied to the solid state image pickup device as driving pulses of the charge transfer unit, and the standby level of at least one of the first transfer pulse and the second transfer pulse may be supplied. And a feedback control circuit capable of changing according to the image signal received from the solid state image pickup device, The first transfer pulse is a pulse having a positive side potential and a negative side potential during charge transfer during a waiting period including when receiving the signal charges. And the second transfer pulse is configured to be a pulse having a negative side potential during the waiting period and a positive side potential during the charge transfer. The method of claim 9, And the feedback control circuit is configured to intermittently change the absolute value of the negative potential of the second transfer pulse when the standby level of the second transfer pulse changes. The method of claim 9, The feedback control circuit, A transfer pulse supply circuit for supplying said first transfer pulse and said second transfer pulse to said solid state image pickup device; A variable gain amplifier for inputting the image signal from the solid state image pickup device and amplifying the image signal; A control for detecting a brightness of an imaging screen obtained by the solid state imaging device according to the image signal and supplying a gain corresponding to the detected brightness to the variable gain amplifier so that the gain can be changed Configured to include circuits, And said transmission pulse supply circuit is configured to input said gain from said control circuit and to change said standby level in accordance with said input gain. In the image input apparatus, A solid-state image pickup device for transmitting signal charges generated by light reception in the charge transfer unit; A driving circuit of the solid state image pickup device; An optical system for guiding image light from a subject on an imaging surface of the solid state imaging device, The drive circuit,  And a transfer pulse supply circuit for generating a first transfer pulse and a second transfer pulse and supplying the generated first transfer pulse and the second transfer pulse to the charge transfer unit of the solid state image pickup device. The pulse is a pulse having a positive potential and a negative potential during charge transfer during the standby period including the time of receiving light when the signal charge is generated, and the second transfer pulse has a negative potential during the standby period. And a negative voltage having a positive potential, wherein the negative potential is configured to have an absolute value smaller than the negative potential of the first transmission pulse. The method of claim 12, And the transfer pulse supply circuit intermittently reduces the negative potential of the second transfer pulse so that the absolute value is smaller than the negative potential of the first transfer pulse. In the image input device, A solid-state image pickup device for transmitting signal charges generated by light reception in the charge transfer unit; A driving circuit of the solid state image pickup device; An optical system for guiding the imaging light from the subject on the imaging surface of the solid state imaging device; Means for outputting a signal that changes in accordance with the amount of signal charge of the solid state image pickup device, The drive circuit, A first transfer pulse and a second transfer pulse may be supplied to the solid state image pickup device as driving pulses of the charge transfer unit, and the standby level of at least one of the first transfer pulse and the second transfer pulse may be applied to the amount of the signal charge. And a transmission pulse supply circuit capable of changing according to the signal correspondingly changing, wherein the first transmission pulse has a positive potential during a waiting period including a light receiving time when the signal charge is generated and a negative side during charge transfer. And the second transfer pulse is configured to be a pulse having a negative potential during the waiting period and a positive potential during charge transfer. The method of claim 14, And the transfer pulse supply circuit is configured to intermittently change the absolute value of the negative potential of the second transfer pulse when the standby level of the second transfer pulse changes. The method of claim 14, The transmission pulse supply circuit, A variable gain amplifier for inputting the image signal from the solid state image pickup device and amplifying the image signal; And a control circuit for detecting the brightness of an image picked up by the solid state image pickup device according to the image signal and supplying a gain corresponding to the detected brightness to the variable gain amplifier so that the gain can be changed. And the transmission pulse supply circuit is configured to change the standby level in accordance with the gain received from the control circuit. The method of claim 14, The optical system comprises a variable diaphragm, The drive circuit, A circuit for detecting the brightness of the captured screen obtained by the solid-state imaging device in accordance with an image signal; An iris control circuit for controlling the aperture amount of the variable aperture according to the brightness of the image pickup screen obtained by the solid state image pickup device; And a transmission pulse supply circuit for changing the standby level in accordance with the aperture received from the iris control circuit. In the method of driving a solid-state image pickup device for transmitting a signal charge generated in accordance with the light reception in the charge transfer unit, Generating a first transfer pulse and a second transfer pulse, wherein the first transfer pulse is a pulse having a positive side potential and a negative side potential during charge transfer during a waiting period including a light receiving time when the signal charge is generated; The second transfer pulse has a negative potential during the waiting period, the negative potential is a first step having an absolute value smaller than the negative potential of the first transmission pulse, And a second step of performing driving by supplying the generated first transfer pulse and the second transfer pulse to the charge transfer section of the solid state image pickup device. The method of claim 18, And wherein in the first step, the negative potential of the second transfer pulse is intermittently made smaller in absolute value than the negative potential of the first transfer pulse. A method of driving a solid-state image pickup device for transmitting signal charges generated by light reception in a charge transfer section, converting the signal charges into an image signal, and outputting the image signal, Generating a first transfer pulse and a second transfer pulse, wherein the first transfer pulse is a pulse having a positive side potential and a negative side potential during charge transfer during a waiting period including a light receiving time when the signal charge is generated; A first transfer pulse having a negative potential during the waiting period and a pulse having a positive potential during the charge transfer; A second step of performing driving by supplying the generated first transfer pulse and second transfer pulse to the charge transfer section of the solid state image pickup device; A third step of generating and supplying the first transfer pulse and the second transfer pulse, while varying the standby level of at least one of the first transfer pulse and the second transfer pulse in accordance with the image signal received from the solid state image pickup device; A method of driving a solid-state image pickup device comprising a. The method of claim 20, And in the third step, the absolute value of the negative potential corresponding to the standby level of the second transfer pulse is changed intermittently in the standby period.

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