JP2009260701A - Imaging device and method of controlling solid-state imaging element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging element of low power consumption suitable for operation in a high-frequency band. <P>SOLUTION: An imaging device 1 has the solid-state imaging element 10 including an output amplifier 17. The output amplifier 17 has a current control means which has an amplifier circuit 37 which includes a drive transistor Tr5 (hereinafter Tr5) and a load transistor Tr7 (hereinafter Tr7) serving as a current supply means for the Tr5, and controls an amount of current supplied to the Tr5 by applying a dedicated control signal for controlling an operation state of the Tr7 to the gate of the Tr7. The control signal includes a first signal for making the Tr7 operates so that the amount of current supplied to the Tr5 has a desired value, and a second signal for making the Tr7 operate so that the amount of current supplied to the Tr5 is smaller than the desired value. The current control means applies the first signal to the gate of the Tr7 in a signal output period wherein the output amplifier 17 is made to output a signal in the operation period of the solid-state imaging element 10, and the second signal to the gate of the Tr7 in other periods. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device having a charge transfer unit that transfers charges generated in a photoelectric conversion element and an output unit that outputs a signal corresponding to the charge transferred through the charge transfer unit.

  The CCD (Charge Coupled Device) type solid-state imaging device transfers a plurality of vertical charge transfer units for transferring charges read from photoelectric conversion elements arranged in a two-dimensional matrix in a vertical direction, and transfers from the vertical charge transfer unit. A horizontal charge transfer unit that transfers the charge for one line in the horizontal direction, and an output amplifier that converts the charge transferred by the horizontal charge transfer unit into a voltage signal and outputs the voltage signal.

  In general, an output amplifier includes a floating diffusion (hereinafter referred to as FD) unit that accumulates charges transferred from a horizontal charge transfer unit, and a multi-stage connected source follower circuit that outputs a signal corresponding to a potential change in the FD unit. It consists of and. Each source follower circuit includes an enhancement type drive transistor and a depletion type load transistor.

  2. Description of the Related Art In recent years, with an increase in shooting speed in an imaging device, current consumption has increased, and due to this increase in current consumption, the amount of heat generated by the imaging device has increased. The solid-state imaging device is formed on a silicon substrate, and it is known that dark current increases as the temperature rises. In recent years, higher sensitivity has been developed, and the influence on image quality due to an increase in dark current has become a problem. As a method for preventing an increase in current consumption, methods described in Patent Documents 1 and 2 have been proposed.

  Patent Document 1 discloses a method of suppressing a current flowing through an output amplifier by controlling a load transistor of each source follower circuit of an output amplifier of a solid-state imaging device with a vertical transfer pulse during an exposure period. Further, there is a description (paragraph 0074) that the pulse for controlling the current of the load transistor may be realized not by the vertical transfer pulse but by a pulse dedicated to current control.

  In Patent Document 2, a current control transistor is provided in series with a load transistor of a source follower circuit at the final stage of an output amplifier of a solid-state image sensor, and the current control transistor is controlled by a vertical transfer pulse, thereby providing an output amplifier. A method for suppressing flowing current is disclosed.

JP 2006-157945 A JP 2002-335449 A

  In the method described in Patent Document 1, since the vertical transfer pulse is used for current control, the period during which the source current of the load transistor is not suppressed in the horizontal blanking period and the signal charge sweeping period in the operation period of the solid-state imaging device. Will occur. For this reason, it cannot be said that current consumption is sufficiently suppressed. In paragraph 0074 of Patent Document 1, there is a description that the pulse for performing the current control of the load transistor may be realized not by the vertical transfer pulse φV2 but by a pulse dedicated to current control. There is no specific description of what kind of pulses are. It is possible to determine that the same pulse as the vertical transfer pulse φV2 is separately generated and used, but in this case, it is consumed in the horizontal blanking period and the signal charge sweeping period. The current cannot be sufficiently suppressed.

  In the method described in Patent Document 2, since the current control transistor is provided in series with the load transistor, the output impedance of the output amplifier becomes high and is not suitable for operation in a high frequency band. Further, since the current control is performed by the vertical transfer pulse, the consumption current cannot be sufficiently suppressed as described above.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a low power consumption solid-state imaging device suitable for operation in a high frequency band.

  A solid-state imaging device according to the present invention includes a solid-state imaging device including a charge transfer unit that transfers charges generated by a photoelectric conversion element, and an output unit that outputs a signal corresponding to the charges transferred through the charge transfer unit. In the imaging apparatus, the output unit includes an amplifying circuit including a driving transistor to which a signal corresponding to the charge is input, and a first load transistor that forms a current supply unit for the driving transistor, Current control means for controlling the amount of current supplied to the drive transistor by applying a dedicated control signal for controlling the operating state of the first load transistor to the control terminal of the first load transistor; The control signal includes a first signal for controlling the first load transistor such that an amount of current supplied to the drive transistor becomes a desired value, and the drive transistor. And a second signal for controlling the first load transistor so that the amount of current supplied to the transistor is less than the desired value, and the current control means includes an operation period of the solid-state imaging device. In the signal output period in which a signal corresponding to the charge is output from the output unit, the first signal is applied to the control terminal of the first load transistor, and in a period other than the signal output period, A second signal is applied to the control terminal of the first load transistor.

  With this configuration, since the amount of current supplied to the drive transistor is controlled by a dedicated control signal, the amount of current supplied to the drive transistor can be suppressed in all periods other than the signal output period. Dark current can be reduced by reducing power consumption and suppressing heat generation.

  In the solid-state imaging device of the present invention, the current control unit generates a timing signal for driving the solid-state imaging device or processing a signal output from the solid-state imaging device, and the timing A signal generation unit configured to generate the first signal and the second signal from a signal, and to input one of them to a control terminal of the first load transistor according to an operation period of the solid-state imaging device; Has been.

  With this configuration, the amount of current supplied to the drive transistor can be controlled based on a timing signal from an existing timing generator (specifically, a pre-blanking signal (PBLK) used in AFE), so that a control signal is generated. The cost can be reduced as compared with the case where another signal source is provided.

  In the solid-state imaging device of the present invention, the amplification circuit includes a second load transistor that is connected in parallel to the first load transistor and forms current supply means for the drive transistor, and the second load transistor The transistor is always on during the operation of the solid-state imaging device, and the second signal is a signal for turning off the first load transistor.

  With this configuration, since the second load transistor is always on, until the amount of current supplied to the drive transistor reaches the required amount when the first load transistor returns from the off state to the on state. Can be shortened. For example, when driving is repeated such that a horizontal blanking period is provided after the signal output period and then a signal output period is provided again, the amount of current supplied to the drive transistor when switching from the horizontal blanking period to the signal output period Can be restored at high speed, the first load transistor can be turned off until the end of the horizontal blanking period, and the power consumption can be further reduced.

  In the solid-state imaging device of the present invention, the amount of current flowing through the first load transistor when the first signal is input to the control terminal is greater than the amount of current flowing through the on-state of the second load transistor. .

  With this configuration, the signal output period is smaller than when the amount of current flowing through the first load transistor when the first signal is input to the control terminal is less than the amount of current flowing when the second load transistor is on. During this period, the amount of current supplied to the drive transistor can be reduced, and power consumption can be further reduced.

  According to the present invention, it is possible to provide a low power consumption solid-state imaging device suitable for operation in a high frequency band.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram illustrating a schematic configuration of an imaging apparatus according to an embodiment of the present invention.
The imaging apparatus 1 shown in FIG. 1 includes a CCD solid-state imaging device 10, an analog front end (AFE) circuit 20, and a central control unit (MPU) 30.

  The AFE circuit 20 includes a CDS 38 that performs gain control and correlated double sampling processing on the imaging signal output from the solid-state imaging device 10, and an amplifier (VGA) 39 that amplifies the luminance component output from the CDS 38 to a desired gain. And an analog-to-digital converter (ADC) 21 that converts an analog signal output from the amplifier 39 into a digital signal, and a drive unit that drives the solid-state imaging device 10.

  In response to an instruction from the MPU 30, the driving unit drives the solid-state imaging device 10 and processes a signal output from the solid-state imaging device 10 (for example, for supplying to the driver circuit 23. A timing generator (TG) 22 that generates signals and signals to be supplied to the CDS 38, VGA 39, and ADC 21), and a driver circuit 23 that converts the timing signal received from the TG 22 into a required voltage pulse signal.

  In the illustrated example, the driver circuit 23 includes three driver circuits 23a, 23b, and 23c. The driver circuit 23a generates a line memory drive pulse φLM, the driver circuit 23b generates horizontal transfer pulses φH1 and φH2, and the driver circuit 23c generates a read pulse and a vertical transfer pulse φV system, and the generated pulses are solid-state imaged. Supply to the element 10. The TG 22 inputs a dedicated timing signal (specifically, an existing timing signal such as a pre-blanking (PBLK) signal used in the AFE circuit 20) for controlling the output amplifier of the solid-state imaging device 10 to the solid-state imaging device 10. To do.

FIG. 2 is a schematic plan view showing a schematic configuration of the solid-state imaging device 10 shown in FIG.
The solid-state imaging device 10 corresponds to a large number of photoelectric conversion elements (photodiodes (PDs)) 12 arranged in a two-dimensional array (in the illustrated example, a square lattice) on the surface of the semiconductor substrate 11 and each photodiode row. A plurality of vertical charge transfer paths 13 that are formed on the side and transfer signal charges accumulated in the photodiodes 12 of the corresponding photodiode array in the vertical direction, and the photodiodes 12 and the vertical charge transfer paths 13. And a read gate 14 provided between the two. In the example shown in the drawing, four vertical transfer electrodes provided on the vertical charge transfer path 13 are provided per one photodiode, and the vertical charge transfer path 13 performs vertical transfer of signal charges to each of the four electrodes. The vertical transfer pulses φV1, φV2, φV3, and φV4 are applied (in the case of four-phase driving).

  Further, the solid-state imaging device 10 includes a horizontal charge transfer path 15 provided at the lower side of the semiconductor substrate 11, a floating diffusion section (FD section) 16 and an output amplifier 17 provided at the output section of the horizontal charge transfer path 15. With.

  Two horizontal transfer electrodes are provided for each vertical charge transfer path on the horizontal charge transfer path 15, and a horizontal transfer pulse for performing horizontal transfer of signal charges through the horizontal charge transfer path 15 to each of the two sheets. φH1 and φH2 are respectively applied (in the case of two-phase driving).

  Further, the solid-state imaging device 10 receives and temporarily accumulates signal charges transferred by the vertical charge transfer paths 13 at the boundary between the end portions of the vertical charge transfer paths 13 and the horizontal charge transfer paths 15, A buffer line memory 18 that is driven independently of the driving of the vertical charge transfer path 13 is provided. This line memory 18 may be omitted.

  Although the terms “vertical” and “horizontal” have been described here, this only means “one direction” along the light receiving surface of the solid-state imaging device 10 and “a direction substantially orthogonal to the one direction”. . The arrangement of the photodiodes 12 is a square lattice. However, the arrangement is not limited to this, and various known arrangements can be applied. Various known methods can be applied to the driving method of the vertical charge transfer path and the horizontal charge transfer path.

  In the imaging apparatus 1 having such a structure, each photodiode 12 accumulates signal charges corresponding to the amount of incident light from the subject, and when the readout pulse is applied from the driver circuit 23, the signal charges are passed through the readout gate 14. Is read from the photodiode 12 to the adjacent vertical charge transfer path 13.

  When the vertical transfer pulses φV 1 to φV 4 are applied to the vertical charge transfer path 13, the signal charge is transferred in the direction of the horizontal charge transfer path 15 (vertical direction) and transferred to the end of each vertical charge transfer path 13. The signal charge for one horizontal line is transferred to the line memory 18 and temporarily stored.

  When the drive pulse φLM is applied to the line memory 18, the signal charge on the line memory 18 is transferred to the horizontal charge transfer path 15. By controlling the line memory 18, pixel addition of signal charges in the horizontal direction can be performed.

  When the horizontal transfer pulses φH 1 and φH 2 are applied to the horizontal charge transfer path 15, signal charges are transferred along the horizontal charge transfer path 15 in the direction of the FD portion 16 (horizontal direction). The pulse φH2 is an inverted pulse with respect to the pulse φH1, and the signal charge stored in the potential packet formed under one horizontal transfer electrode is adjacent when the pulses φH1 and φH2 are inverted. It is transferred into a potential packet formed under the horizontal transfer electrode. In other words, the horizontal transfer for one stage is performed, and when the pulses φH1 and φH2 are inverted next, the horizontal transfer for the next stage is performed.

  When the signal charge is transferred in the horizontal direction and an imaging signal corresponding to the amount of signal charge that has entered the FD unit 16 is output from the output amplifier 17, the signal charge in the FD unit 16 is discarded. The operation in which the next signal charge enters the FD section 16 is repeated until the signal charge on the horizontal charge transfer path 15 disappears (a period in which this operation is repeated is referred to as a horizontal transfer period). A horizontal blanking period is provided before the next horizontal transfer period starts.

FIG. 3 is a circuit diagram showing a schematic configuration of the output amplifier of the solid-state imaging device shown in FIG.
The output amplifier 17 shown in FIG. 3 detects a potential change in the FD unit 16 of the solid-state image sensor 10 and outputs three imaging circuits (source follower circuits 35, 36, and 37) connected in multiple stages for outputting an image signal corresponding thereto. ).

  The first-stage source follower circuit 35 includes an enhancement type drive transistor Tr1 and a depletion type load transistor Tr2 that forms a current supply means for the drive transistor Tr1. The drive transistor Tr1 has a gate connected to the FD unit 16, a source connected to the drain of the load transistor Tr2, and a drain connected to a power supply VCC + of about + 15V, for example. The load transistor Tr2 is always in an on state (a state in which a current flows) during the operation of the solid-state imaging device 10 because the gate and the source of the load transistor Tr2 are grounded.

  The second-stage source follower circuit 36 includes an enhancement type drive transistor Tr3 and a depletion type load transistor Tr4 that forms a current supply means for the drive transistor Tr3. The gate of the drive transistor Tr3 is connected between the source of the drive transistor Tr1 and the drain of the load transistor Tr2, the source is connected to the drain of the load transistor Tr4, and the drain is connected to the power supply VCC +. The load transistor Tr4 has a gate and a source that are grounded, so that the load transistor Tr4 is always in an on state (a state in which a current flows) while the solid-state imaging device 10 is in operation.

  The third-stage source follower circuit 37 includes an enhancement type drive transistor Tr5, and a depletion type load transistor Tr6 and a depletion type load transistor Tr7 connected in parallel to form a current supply means for the drive transistor Tr5. Composed. The drive transistor Tr5 has a gate connected between the source of the drive transistor Tr3 and the drain of the load transistor Tr4, a source connected to the drains of the load transistors Tr6 and Tr7, and a drain connected to the power supply VCC +.

  The load transistor Tr6 has a gate and a source grounded, so that the load transistor Tr6 is always in an on state (a state in which a current flows) during the operation of the solid-state imaging device 10. The drain of the load transistor Tr7 is connected between the source of the driving transistor Tr5 and the drain of the load transistor Tr6, the source is grounded, and the control terminal 39 is connected to the gate via the level conversion circuit 38. The operation state of the load transistor Tr7 is controlled by a control signal applied to the gate from the level conversion circuit 38.

  An output terminal OS is connected to the source of the drive transistor Tr5, and an imaging signal is output from the output terminal OS.

  The control terminal 39 is a terminal for directly inputting a timing signal from the TG 22.

  The level conversion circuit 38 includes enhancement type transistors Tr8 to Tr10, resistors R1 to R5, and capacitors C1 and C2.

The transistor Tr9 has its gate connected to the control terminal 39, its drain connected to the source of the transistor Tr8, and its source connected to a power supply VCC− of about −8 V, for example, via a resistor R2.

  The transistor Tr8 has its drain connected to the power supply VCC +, its source connected to the drain of the transistor Tr9, and its gate connected between the resistor R3 and the resistor R4 connected in series between the power supply VCC + and the ground line. Has been.

  The transistor Tr10 has a gate connected to the source of the transistor Tr9 via a resistor R5, a source connected to the gate of the load transistor Tr7, and a drain connected to the source of the load transistor Tr7.

  A power supply VCC− is connected between the gate of the transistor Tr10 and the resistor R5 via a capacitor C1. A capacitor C2 and a resistor R1 are connected in parallel between the gate of the load transistor Tr7 and the power supply VCC−.

  The level conversion circuit 38 and the TG 22 configured as described above apply a dedicated control signal for controlling the operation state of the load transistor Tr7 to the gate terminal which is the control terminal of the load transistor Tr7, thereby changing the operation state of the load transistor Tr7. By controlling, it functions as current control means for controlling the amount of current supplied to the drive transistor Tr5.

  As this control signal, the first signal for controlling the load transistor Tr7 so that the amount of current supplied to the drive transistor Tr5 becomes a desired value (for example, 5 mA) necessary for the output of the imaging signal, and the drive transistor And a second signal for controlling the load transistor Tr7 so that the amount of current supplied to Tr5 is less than the desired value (for example, 0.1 mA).

  The level conversion circuit 38 generates the first signal and the second signal from the dedicated timing signal supplied from the TG 22 and corresponds to the signal charge generated in the photodiode 12 during the operation period of the solid-state imaging device 10. In the signal output period (corresponding to the horizontal transfer period) in which the imaging signal is output from the output amplifier 17, the first signal is applied to the gate terminal of the load transistor Tr7, and in the period other than the signal output period, the second signal is applied. By applying the voltage to the gate terminal of the load transistor Tr7, the amount of current supplied to the drive transistor Tr5 is controlled.

  For example, when the timing signal input to the control terminal 39 becomes high level, the load transistor Tr7 is turned on, and the characteristics of each transistor are determined so that a current of 4.9 mA is supplied to the drive transistor Tr5. deep. As a result, when the timing signal is at a high level, the first signal is applied to the gate of the load transistor Tr7, and the drive transistor Tr5 has a current of 0.1 mA that is constantly supplied from the load transistor Tr6. In addition, a total current of 5.0 mA is supplied.

  On the other hand, when the timing signal input to the control terminal 39 becomes low level, the characteristics of each transistor are determined so that the load transistor Tr7 is turned off (high resistance state in which almost no current flows). Thus, when the timing signal is at a high level, the second signal for turning off the load transistor Tr7 is applied to the gate of the load transistor Tr7, and the load transistor Tr6 is applied to the drive transistor Tr5. Only a current of 0.1 mA supplied from is supplied.

  Since the load transistor Tr7 is a depletion type, it cannot be turned off unless the signal (voltage) applied to the gate terminal is a sufficiently large negative signal. Since the timing signal generated by the TG 22 does not generate a signal that can turn off the load transistor Tr7, the level conversion circuit 39 converts the level of the timing signal to turn off the load transistor Tr7. Is possible.

  In the output amplifier 17, in order to effectively reduce power consumption, the amount of current that always flows through the load transistor Tr6 is equal to the current that flows through the load transistor Tr7 when the first signal is applied to the gate of the load transistor Tr7. The sizes of the load transistors Tr6 and Tr7 are determined so as to be sufficiently smaller than the amount. Of course, even if the amount of current that always flows through the load transistor Tr6 is larger than the amount of current that flows through the load transistor Tr7 when the first signal is applied to the gate of the load transistor Tr7, it is possible to reduce power consumption somewhat. .

Details of the operation of the output amplifier 17 shown in FIG. 3 will be described below.
In the signal output period (horizontal transfer period), a high-level timing signal (referred to as input Hi voltage) is input to the control terminal 39. During the period when the input Hi voltage is input, if the bias state of the transistor Tr9 is Vds (drain-source voltage)> Vgs (gate-source voltage), the source voltage of the transistor Tr9 (= the gate of the transistor Tr10). Voltage) becomes “input Hi voltage −Vgs (for transistor Tr9)”, and the gate potential of the load transistor Tr7 is “GND (ground potential) −Vds (for transistor Tr10)” (= first signal). Become. Since the load transistor Tr7 is a depletion type, the load transistor Tr7 is in an operating state and becomes a bias condition that allows normal output. That is, the drive transistor Tr5 is supplied with a total current of the current supplied from the load transistor Tr6 and the current supplied from the load transistor Tr7, and can output an imaging signal corresponding to the signal charge. It becomes a state.

  During a period other than the signal output period (horizontal transfer period) in the operation period of the solid-state imaging device 10, a low-level timing signal (referred to as input Lo voltage) is input to the control terminal 39. During the period when the input Lo voltage is input, the source voltage of the transistor Tr9 (= the gate voltage of the transistor Tr10) becomes “input Lo voltage−Vgs (of the transistor Tr9)”, and the gate potential of the load transistor Tr7 is "Input Lo voltage -Vgs (for transistor Tr9) -Vgs (for transistor Tr10)" (= second signal). The sizes of the transistors Tr9 and Tr10 are set so that “input Lo voltage−Vgs (for transistor Tr9) −Vgs (for transistor Tr10)” <“threshold of load transistor Tr7”. As a result, the load transistor Tr7 is turned off (a high resistance state in which no current flows). Therefore, only the current supplied from the load transistor Tr6 is supplied to the drive transistor Tr5, and the power consumption in the output amplifier 17 is greatly suppressed during periods other than the signal output period.

  The resistors R3 and R4 and the transistor Tr8 are effective for suppressing the current flowing to the power supply VCC− via the resistor R2 when the timing signal input to the control terminal 39 is at a high level. This is not necessary if the value is sufficiently large and the gate breakdown voltage of the transistor Tr10 is increased.

  The capacitor C1 and the resistor R5 function as a low-pass filter that reduces the influence of noise from the control terminal 39. The resistor R1 is a resistor for suppressing the current flowing through the transistor Tr10, and at the same time forms a low-pass filter in combination with the capacitor C2, thereby reducing the swing of the gate of the load transistor Tr7.

  As described above, since the imaging device of the present embodiment controls the gate of the load transistor Tr7 not by the vertical transfer pulse but by a dedicated control signal independent of this, the operation period of the solid-state imaging device 10 In the signal output period, the load transistor Tr7 is turned on so that a current necessary for outputting the imaging signal is supplied to the drive transistor Tr5. In other periods, the load transistor Tr7 is turned off and the load transistor Tr6 is turned off. Only a small amount of current can be supplied to the drive transistor Tr5. For this reason, it is possible to significantly increase the time for suppressing the amount of current supplied from the load transistor Tr7 as compared with the conventional case where the load transistor is controlled by the vertical transfer pulse. Therefore, the power consumption can be further reduced, and the dynamic range can be secured more broadly by suppressing the heat generation of the imaging device, suppressing the generation of dark current, and improving the S / N characteristics.

  In Patent Documents 1 and 2, it is necessary to set one of the vertical transfer pulses to an active level during the signal output period. In order to set the active level to a low level, a p-channel transistor is required, which increases the number of manufacturing steps and increases costs. In addition, when the active level is set to the high level, the dark current increases in the charge transfer path, which is not preferable. According to the imaging apparatus of this embodiment, since the load transistor Tr7 is controlled by a dedicated control signal independent of the vertical transfer pulse, the above-described cost increase and dark current increase can be prevented, and low power consumption can be achieved. Become.

  In addition, since the imaging apparatus according to the present embodiment controls the load transistor Tr7 using a control signal independent of the vertical transfer pulse, it is necessary to change the design of the vertical transfer pulse in order to control the load transistor Tr7. And can be easily applied to an existing imaging apparatus. Further, this control signal can be generated by converting the level of the timing signal from the TG 22 (for example, an existing timing signal such as a pre-blanking signal used in AFE), so that a control signal having a negative voltage level is generated. The manufacturing cost can be reduced as compared with the case where another signal source is provided.

  In the imaging apparatus of the present embodiment, only the load transistor Tr6 or the load transistor Tr7 is interposed between the output terminal OS of the output amplifier 17 and the ground line. An output impedance equivalent to that of a typical output amplifier can be maintained, and operation in a high frequency band can be supported.

  In the imaging apparatus of the present embodiment, the load transistor of the source follower circuit 37 is configured by a load transistor Tr6 and a load transistor Tr7 connected in parallel. Since the load transistor Tr6 is always on, when the load transistor Tr7 returns from the off state to the on state, the time until the amount of current supplied to the drive transistor Tr5 reaches the required amount can be shortened. it can. Specifically, when switching from the horizontal blanking period to the signal output period, the amount of current supplied to the drive transistor Tr5 can be restored at high speed, so that the load transistor Tr7 is turned off until the end of the horizontal blanking period. Thus, power consumption can be further reduced.

  Further, in the imaging device of the present embodiment, the amount of current that flows when the load transistor Tr6 is on is less than the amount of current that flows through the load transistor Tr7 when the first signal is applied to the gate of the load transistor Tr7. As described above, the sizes of the load transistors Tr6 and Tr7 are determined. For this reason, when the first signal is applied to the gate of the load transistor Tr7, the amount of current flowing through the load transistor Tr7 is smaller than the amount of current flowing when the load transistor Tr6 is on. The amount of current supplied to the drive transistor Tr5 during the period can be reduced, and the power consumption can be further reduced.

  Hereinafter, modifications of the imaging device according to the present embodiment will be listed.

(1) The load transistor Tr6 of the source follower circuit 37 may be omitted.
In this case, since the current supplied to the drive transistor Tr5 is substantially zero during periods other than the signal output period, the effect of reducing power consumption is high.

(2) The load transistor Tr7 may not be turned off when the second signal is applied to the gate.
The load transistor Tr7 is designed not to be completely turned off when the second signal is applied to the gate, but to suppress the current more than when the first signal is applied to the gate. You can keep it. Even in this case, in the signal output period and other periods, the amount of current supplied to the drive transistor Tr5 is reduced in the signal output period, so that an effect of reducing power consumption can be obtained.

  (3) The configuration of the output amplifier 17 is not limited to a three-stage source follower circuit, and may be a one-stage, two-stage, or four or more stages, for example.

  (4) The transistor used for the source follower circuit is not limited to a MOS transistor, and may be a structure using a junction FET or a bipolar transistor.

(5) The configuration of the load transistor of the source follower circuit 37 may be applied to other source follower circuits.
For example, a depletion type load transistor may be provided in parallel with each of the load transistor Tr2, the load transistor Tr4, or both, and this load transistor may be controlled by a control signal in the same manner as the load transistor Tr7. By doing in this way, in the period other than the signal output period, the amount of current supplied to the drive transistors Tr1 and Tr3 can also be suppressed, so that power consumption can be further reduced. In the case of source follower circuits connected in multiple stages, the power consumption in the source follower circuit in the final stage is the most dominant, and as shown in FIG. 3, the load transistor of the source follower circuit 37 in the final stage is controlled. Only by this, the effect of reducing power consumption can be sufficiently obtained.

  (6) A circuit independent of the TG 22 that generates the first signal and the second signal and applies them to the gate of the load transistor Tr7 may be provided.

1 is a block diagram showing a schematic configuration of an imaging apparatus that is an embodiment of the present invention. 1 is a schematic plan view showing a schematic configuration of the solid-state imaging device shown in FIG. 2 is a circuit diagram showing a schematic configuration of an output amplifier of the solid-state imaging device shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Imaging device 10 Solid-state image sensor 17 Output amplifier Tr5 Drive transistor Tr7 Load transistor

Claims (5)

An image pickup apparatus having a solid-state image pickup device including a charge transfer unit that transfers charges generated by a photoelectric conversion element and an output unit that outputs a signal corresponding to the charge transferred through the charge transfer unit,
The output unit includes an amplifying circuit including a driving transistor to which a signal corresponding to the electric charge is input, and a first load transistor that forms current supply means for the driving transistor;
Current control means for controlling the amount of current supplied to the drive transistor by applying a dedicated control signal for controlling the operating state of the first load transistor to the control terminal of the first load transistor;
The control signal includes a first signal for controlling the first load transistor so that a current amount supplied to the drive transistor becomes a desired value, and a current amount supplied to the drive transistor A second signal for controlling the first load transistor to be less than a desired value;
The current control unit is configured to output the first signal to a control terminal of the first load transistor in a signal output period in which a signal corresponding to the charge is output from the output unit in an operation period of the solid-state imaging device. An imaging apparatus that applies and applies the second signal to a control terminal of the first load transistor in a period other than the signal output period. The imaging apparatus according to claim 1,
The current control means generates a timing signal for driving the solid-state imaging device or processing a signal output from the solid-state imaging device, the first signal from the timing signal, and An image pickup apparatus comprising: a signal generation unit configured to generate the second signal and input one of the signals to a control terminal of the first load transistor according to an operation period of the solid-state image sensor. The imaging apparatus according to claim 1 or 2,
The amplifier circuit includes a second load transistor connected in parallel to the first load transistor and serving as a current supply means to the drive transistor;
The second load transistor is always on during the operation of the solid-state imaging device,
The imaging apparatus, wherein the second signal is a signal for turning off the first load transistor. The imaging apparatus according to claim 3,
An imaging apparatus in which an amount of current flowing through the first load transistor when the first signal is input to the control terminal is greater than an amount of current flowing when the second load transistor is on. A charge transfer unit configured to transfer a charge generated in the photoelectric conversion element; and an output unit configured to output a signal corresponding to the charge transferred through the charge transfer unit, wherein the output unit is a signal corresponding to the charge. A solid-state imaging device control method comprising an amplifier circuit including a drive transistor to which is input and a load transistor that forms current supply means for the drive transistor,
A current control step for controlling the amount of current supplied to the drive transistor by applying a dedicated control signal for controlling the operating state of the first load transistor to the control terminal of the first load transistor;
The control signal includes a first signal for operating the first load transistor so that a current amount supplied to the drive transistor becomes a desired value, and a current amount supplied to the drive transistor A second signal for operating the first load transistor to be lower than a desired value,
In the current control step, in the signal output period in which a signal corresponding to the charge is output from the output unit in the operation period of the solid-state imaging device, the first signal is supplied to the control terminal of the first load transistor. A solid-state imaging device control method that applies and applies the second signal to a control terminal of the first load transistor during a period other than the signal output period.

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