JP4048415B2 - Solid-state imaging device and driving method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a MOS sensor type solid-state imaging device provided with a photoelectric conversion element and a readout circuit for each pixel constituting an imaging region portion, and a driving method thereof.
[0002]
[Prior art]
FIG. 10 is a circuit diagram illustrating a configuration example of a main part in a MOS sensor type solid-state imaging device.
A large number of pixels 10 are arranged in a two-dimensional array in the imaging region, and each pixel is provided with a photodiode PD as a photoelectric conversion element and four MOS transistors Tr1 to Tr4 constituting a readout circuit thereof. It has been.
The photodiode PD generates a signal charge corresponding to the amount of received light, and the transfer transistor (transfer gate means) Tr1 transfers the signal charge of the photodiode PD to the floating diffusion (FD) section based on the transfer pulse. To do.
The reset transistor (reset means) Tr2 periodically resets the voltage of the FD section to the power supply voltage Vdd based on the reset pulse.
The amplifying transistor (amplifying means) Tr3 has an FD portion connected to its gate, and outputs an output signal corresponding to the voltage fluctuation of the FD portion.
The selection transistor Tr4 outputs the output signal of the amplification transistor Tr3 to the vertical signal line (output signal line) 12 based on a selection pulse for selecting a pixel row.
[0003]
The vertical signal line 12 is provided for each pixel column, and one end thereof is connected to a load transistor Tr5 as a constant current source outside the imaging region. The other end of the vertical signal line 12 is connected to a signal processing circuit provided for each pixel column outside the imaging region.
This signal processing circuit is provided at the next stage of the imaging region and performs various kinds of signal processing on the pixel signal. This signal processing circuit includes a CDS (Correlated Double Sampling) circuit as shown in FIG. ing.
In this CDS circuit, a CDS (Correlated Double Sampling) circuit is a circuit that inputs two signals in time series and outputs a signal proportional to the difference between them. Specifically, transistors Tr6, Tr7, Tr8, capacitors Cs, Cr, and a differential amplifier 14 are included.
[0004]
Then, the transistor Tr6 is turned on by the timing signal SHS when the signal charge of the photodiode PD is accumulated in the FD portion, whereby the output signal is held by the capacitor Cs and the timing at the time when the FD portion is reset. By turning on the transistor Tr7 by the signal SHR, the output signal is held by the capacitor Cr. Then, the levels held in the two capacitors Cs and Cr are compared by the differential amplifier 14 to obtain a difference between the two, and the difference value is output to the horizontal signal line 16 via the transistor Tr8.
[0005]
FIG. 11 is a timing chart showing a conventional operation example in the solid-state imaging device having such a configuration, and FIG. 12 is a potential diagram showing signal charge transitions during the operation shown in FIG. Note that the numbers indicating the timing in FIGS. 11 and 12 correspond to each other.
First, during timing 0, photoelectrons are accumulated in the photodiode PD. When the selection transistor Tr4 is turned on at timing 1, the amplification transistor Tr3 of the pixel is connected to the vertical signal line 12.
Then, a constant current determined by the load transistor Tr5 flows from Vdd (power supply voltage terminal) through a path of the amplification transistor Tr3 → the vertical signal line 12 → the load transistor Tr5.
Since the amplification transistor Tr3 and the load transistor Tr5 form a source follower, a gate voltage of the amplification transistor Tr3, that is, a voltage corresponding to the voltage of the FD portion appears on the vertical signal line 12. This continues for as long as the selection transistor Tr4 is turned on.
[0006]
Next, the FD section is reset by a reset pulse at timing 2. The potential at timing 3 immediately after this is as shown in (3) of FIG. As shown in the figure, photoelectrons have accumulated in the photodiode PD at this time, and the FD portion is in a state immediately after reset.
In order to make the following description easy to understand, it is assumed that the voltage of the FD section is substantially equal to Vdd.
At timing 3, since a voltage (reset level) corresponding to the potential of the FD portion appears on the vertical signal line 12, by inputting an SHR pulse, this is sampled and held in the capacitor Cr of the CDS circuit.
[0007]
Next, the photoelectrons of the photodiode PD are transferred to the FD portion with a pulse of timing 4. The potential at the timing 5 immediately after this is as shown in (5) of FIG. As shown in the figure, the potential of the FD portion is shifted to the minus side by the amount of photoelectrons.
Since a voltage (signal level) corresponding to the potential of the FD portion appears on the vertical signal line 12, when an SHS pulse is input, it is sampled and held in the capacitor Cs of the CDS circuit.
The differential amplifier 14 of the CDS circuit outputs a voltage proportional to the difference between the signal level held in the capacitors Cs and Cr and the reset level as described above.
Next, at timing 6, the selection transistor Tr4 is turned off to disconnect the amplification transistor Tr3 from the vertical signal line 12.
Thereafter, the output of the differential amplifier 14 of the CDS circuit is read out to the horizontal signal line 16 under the control of the transistor Tr8 from the H selection means (horizontal scanner circuit).
[0008]
[Problems to be solved by the invention]
However, the conventional techniques as described above have the following problems.
(1) Low voltage is difficult. That is, since the FD section can actually be reset only at a voltage lower than Vdd, the signal follower amplitude must be taken from the reset voltage, and the source follower must be stably operated. Considering the amplitude, the source follower operating voltage, and their margins, the peripheral circuit can be reduced in voltage, but the pixel operating voltage regulates the power supply voltage and cannot be reduced.
[0009]
(2) Since the capacity of the photodiode cannot be increased, the dynamic range is narrow. That is, when the capacity of the photodiode is increased, unless the capacity of the FD portion is increased, the photoelectrons of the photodiode cannot be received by the FD portion, and electrons remain in the photodiode. However, increasing the capacity of the FD portion reduces the efficiency of converting charges into voltage, which causes a decrease in sensitivity. Also, the pixel area is increased. Accordingly, the capacity of the photodiode cannot be increased, and it is difficult to expand the dynamic range.
[0010]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a solid-state imaging device and a driving method thereof capable of expanding a dynamic range and reducing a voltage.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, the present invention comprises a semiconductor substrate provided with an imaging region unit composed of a plurality of pixels and a peripheral circuit unit that controls the imaging region unit, and each pixel of the imaging region unit receives light. A photoelectric conversion element for generating a signal charge according to the amount, a transfer gate means for transferring the signal charge generated by the photoelectric conversion element to a floating diffusion part, and an electric signal according to the voltage of the floating diffusion part. In a solid-state imaging device configured to include amplification means for outputting to an output signal line, and reset means for resetting the voltage of the floating diffusion section, The peripheral circuit unit includes a signal level when the signal charge generated by the photoelectric conversion element is transferred to the floating diffusion unit by the transfer gate unit, and a signal level when the floating diffusion unit is reset by the reset unit. Each having the transfer gate means turned on, and a signal processing circuit for outputting a signal corresponding to the difference value, An electrical signal output to the output signal line in a state where the transfer gate means is turned on is captured by a signal processing circuit provided in the peripheral circuit section, and an imaging signal is generated from the captured signal.
[0012]
Further, the present invention is configured by providing a semiconductor substrate with an imaging region unit composed of a plurality of pixels and a peripheral circuit unit for controlling the imaging region unit, and each pixel of the imaging region unit corresponds to the amount of received light A photoelectric conversion element that generates a signal charge, transfer gate means that transfers the signal charge generated by the photoelectric conversion element to a floating diffusion unit, and an electrical signal corresponding to the voltage of the floating diffusion unit to an output signal line In a driving method of a solid-state imaging device configured to include an amplifying unit that outputs and a reset unit that resets a voltage of the floating diffusion unit, The peripheral circuit unit includes a signal level when the signal charge generated by the photoelectric conversion element is transferred to the floating diffusion unit by the transfer gate unit, and a signal level when the floating diffusion unit is reset by the reset unit. Each having the transfer gate means turned on, and a signal processing circuit for outputting a signal corresponding to the difference value, An electrical signal output to the output signal line in a state where the transfer gate means is turned on is captured by a signal processing circuit provided in the peripheral circuit section, and an imaging signal is generated from the captured signal.
[0013]
In the solid-state imaging device and the driving method thereof according to the present invention, an electrical signal output to the output signal line in a state where the transfer gate means is turned on is captured by a signal processing circuit provided in the peripheral circuit unit, and an imaging signal is obtained from the captured signal. Was generated.
Therefore, the voltage of the floating diffusion part can be increased by using the capacitive coupling between the transfer gate means and the floating diffusion part, and the voltage in the pixel can be reduced accordingly.
Further, since the floating diffusion part, the channel of the transfer gate means, and the photoelectric conversion element can be used as a signal charge receiving tray, the number of handling electrons can be increased and the dynamic range can be expanded.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a solid-state imaging device and a driving method thereof according to the present invention will be described below.
The present embodiment provides a method for driving a CMOS sensor type solid-state imaging device with a low voltage and a wide dynamic range. When a pixel signal of a CMOS sensor is read, the transfer gate means of each pixel is turned on. By reading the voltage of the output signal line of the pixel signal as it is, the voltage is reduced by the amount of capacitive coupling, and the amount of charge handled is increased to solve the shortage of saturation and expand the dynamic range. It is a thing.
[0015]
FIG. 1 is a schematic plan view showing an example of the entire configuration of a MOS sensor type solid-state imaging device according to the present embodiment.
This solid-state imaging device includes an imaging pixel unit 112 formed on a semiconductor chip 110, a V selection unit 114, an H selection unit 116, a timing generator (TG) 118, a CDS unit 120, a constant current unit 122, a horizontal signal line 124, An output unit 126 and the like are included.
[0016]
The imaging pixel unit 112 constitutes the above-described imaging region, and a large number of pixels are arranged in a two-dimensional matrix, and each pixel has a photodiode PD, FD as shown in FIG. , A transfer transistor Tr1, a reset transistor Tr2, an amplification transistor Tr3, a selection transistor Tr4, and the like. In the following description, the reference numerals shown in FIG.
In addition, each pixel of the imaging pixel unit 112 is sequentially selected in units of horizontal lines (pixel rows) in the vertical direction by the V selection unit 114, and the MOS transistor of each pixel is controlled by various pulse signals from the timing generator 118. Thus, each pixel signal is read out to the CDS unit 120 for each pixel column through the vertical signal line.
[0017]
The CDS unit 120 is provided with the above-described CDS circuit shown in FIG. 10 for each pixel column of the imaging pixel unit 112, and performs CDS processing on the pixel signal read from each pixel column of the imaging pixel unit 112. And the pixel signal is output to the output unit 126 via the horizontal signal line 124.
The output unit 126 is provided with circuits that perform processing such as automatic gain conversion (AGC), analog / digital (A / D) conversion, and amplification on the pixel signal from the CDS circuit.
The H selection means 116 selects the pixel signal output from the CDS unit 120 in the horizontal direction and outputs it to the horizontal signal line 124.
[0018]
The constant current unit 122 supplies a constant current source for each pixel column to the imaging pixel unit 112 as described above.
The timing generator 118 also supplies various timing signals to each part other than each pixel of the imaging pixel part 112 described above.
The output unit 126 outputs a digital signal sent from the horizontal signal line 124 to an external terminal of the semiconductor chip 110.
Such a configuration itself is basically the same as the conventional one, and the present invention is characterized by a driving method described below.
[0019]
FIG. 2 is a timing chart showing a first operation example (first example) in the solid-state imaging device according to the present embodiment. FIG. 3 shows signal charges during the operation of the first example shown in FIG. It is a potential diagram which shows the transition of. Note that the numbers indicating the timing in FIGS. 2 and 3 correspond to each other.
In this example, during the period in which the selection transistor Tr4 is on at the timings 2 to 6 in FIG. 2, the voltage corresponding to the potential of the FD portion is output to the vertical signal line as in the conventional example.
However, in FIG. 2, the FD section is reset by a reset pulse (first reset pulse) at timing 2. Further, with the transfer gate Tr1 turned on at timing 3, an SHS pulse is input to the transistor Tr6 of the CDS circuit, and the voltage (signal level) of the vertical signal line 12 is taken into the capacitor Cs of the CDS circuit. Here, the photoelectrons of the photodiode PD are transferred to the FD portion, and the potential is in the state shown in (3) of FIG.
[0020]
The difference here is that
(1) Since a high-level gate signal is input to the transfer gate Tr1, the voltage under the channel of the transfer gate Tr1 is also high.
(2) Although photoelectrons exist in the FD portion, photoelectrons are accumulated from a voltage higher than the reset voltage (here, approximately Vdd) due to capacitive coupling between the transfer gate Tr1 and the FD portion.
That is.
In the present example, the latter is particularly important. As a result, the driving voltage of the pixel can be lowered. The capacitive coupling between the transfer gate Tr1 and the FD portion is about 0.5V with respect to the power supply voltage of 2.5V, and plays an important role in lowering the voltage.
[0021]
Next, returning to FIG. 2 and continuing the explanation, after the transfer pulse is lowered after the timing 3 described above, the FD section is reset by the second reset pulse at the timing 4, and the transfer pulse is raised again. At timing 5, an SHR pulse is input to the transistor Tr7, and the voltage (reset level) of the vertical signal line 12 is input to the capacitor Cr of the CDS circuit.
The potential at this point is as shown in (5) of FIG.
Here, due to the capacitive coupling between the transfer gate Tr1 and the FD portion, the FD portion has a voltage higher than the reset voltage (approximately Vdd). This amount contributes to lowering the voltage as described above.
Thereafter, the differential amplifier 14 of the CDS circuit outputs a signal proportional to the difference between the signal level and the reset level, and then the transfer gate Tr1 and the selection gate Tr4 are closed to complete the pixel operation.
[0022]
Note that in the imaging pixel unit 112, the pixels 10 are arranged in a matrix, and all the pixels for one row are simultaneously driven by this scanning, and the pixel signals for one row are simultaneously applied to the CDS unit in which the CDS circuits are arranged. Read and hold. Thereafter, the photoelectron accumulation period starts.
Then, although omitted in FIG. 2, the H selection means 116 is operated during this period, and the output of the CDS circuit is sequentially guided to the horizontal signal line 116 and output.
Thereafter, when the next row is selected by the V selection means 114 and the same operation is performed, the signal of the next row is read out. The signals of all rows can be read out by sequentially scanning with the V selection means 114.
In this manner, a solid-state imaging device with a low voltage and a wide dynamic range can be realized.
[0023]
Next, a second operation example (second embodiment) will be described.
The second embodiment is intended to cope with the case where the potential well of the photodiode PD is deep or the capacitance is large so that photoelectrons cannot be received by the FD portion.
FIG. 4 is a timing chart showing the operation in the second embodiment, and FIG. 5 is a potential diagram showing signal charge transition during the operation of the second embodiment shown in FIG. Note that the numbers indicating the timing in FIGS. 4 and 5 correspond to each other. First, after the selection transistor Tr4 is turned on, a reset pulse (first reset pulse) is input, and then the transfer gate Tr1 is turned on. At timing 3, the voltage (signal level) of the vertical signal line 12 is set to the capacitor Cs by the SHS pulse. This is the same as the first embodiment.
At this time, if the photoelectrons cannot be received by the FD portion, the photoelectrons exist up to the channel of the transfer gate Tr1 and the photodiode PD as shown in (3) of FIG. Since the signal is output in this state, the signal of all photoelectrons can be read, unlike the case where the photodiode PD and the FD portion are separated by turning off the conventional transfer gate Tr1.
[0024]
FIG. 6 is an explanatory diagram showing the relationship between the amount of received light and the amount of output signal in the photodiode.
As shown in the figure, when the light amount is small, the photoelectrons can be received by the FD unit, so that the gradient of the light amount-output curve is relatively large.
Further, when the amount of light increases, the light is received by the channels of the FD portion and the transfer gate Tr1, so that the inclination becomes gentle. When the amount of light further increases, photoelectrons remain in the photodiode PD, so that the inclination becomes gentler.
As described above, even when the photoelectrons cannot be received by the FD portion, it is possible to increase the number of photoelectrons handled by increasing the sensitivity in a dark place and decreasing the sensitivity in a bright place.
Next, when the reset gate Tr2 is also turned on (activated), both the FD portion and the photodiode PD are reset. In particular, the FD section is reset to a voltage of approximately Vdd. Then, when the transfer gate Tr1 is turned off at timing 4, the voltage of the FD portion tends to decrease due to capacitive coupling. However, since the reset gate Tr2 is turned on (activated), the potential of the FD portion is still kept at approximately Vdd. It is. This order is different from the first embodiment shown in FIG. 2, and if the order is reversed, the photoelectrons remaining in the photodiode PD are not reset.
[0025]
Then, when the reset gate Tr2 is turned off (inactivated) and then the transfer gate Tr1 is turned on, the timing 5 returns to the same state as in the first embodiment. The voltage (reset level) of the vertical signal line 12 at this time is taken into the capacitor Cr by the SHR pulse and processed, and the transfer gate Tr1 and the selection transistor Tr4 are turned off as in the first embodiment.
Thus, even when the photodiode PD has a large number of saturated electrons and cannot be received by the FD portion, the sensitivity is high in a dark place, the sensitivity is lowered in a bright place, and an output with a large number of handled photoelectrons is possible. It is also clear that the effect of lowering the voltage using capacitive coupling between the transfer gate Tr1 and the FD portion is the same as that of the first embodiment.
Of course, there is no problem even if this operation is performed when the photodiode PD has a small number of saturated photoelectrons and can be received by the FD portion.
[0026]
Next, a third operation example (third embodiment) will be described.
The third embodiment provides a driving method capable of further expanding the dynamic range.
FIG. 7 is a timing chart showing the operation in the third embodiment. Further, the potential diagram in the third embodiment is the same as that in FIG. 5 and will be described with reference to FIG. Note that the numbers indicating the timing in FIGS. 7 and 5 correspond to each other.
The third embodiment is different from the operation of the second embodiment in that there is no reset pulse immediately after the selection transistor Tr4 shown in FIG. 4 is turned on.
When the amount of light is large, electrons overflow from the photodiode PD to the FD portion during the photoelectron accumulation period at timing 0, and photoelectrons accumulate in the FD portion. At timing 3, the photodiode is not reset. The photoelectrons transferred from the PD are added (see FIG. 5).
[0027]
The subsequent operation is the same as in the second embodiment. Therefore, in the third embodiment, while maintaining the same effect as in the second embodiment, the amount of charge handled increases not to the saturation amount of the photodiode PD but to the sum of the saturation amount of the photodiode PD and the saturation amount of the FD portion. .
However, this third embodiment is disadvantageous in terms of noise because dark charges (noise components generated regardless of light) accumulated in the FD section during the period of timing 0 are read together. .
Therefore, it is preferable to appropriately select and employ the driving method of the second embodiment capable of reducing noise and the driving method of the third embodiment capable of expanding the dynamic range according to the use of the solid-state imaging device. .
[0028]
Next, a fourth operation example (fourth embodiment) will be described.
The fourth embodiment provides a driving method that saves operating time while expanding the dynamic range.
FIG. 8 is a timing chart showing the operation in the fourth embodiment, and FIG. 9 is a potential diagram showing signal charge transitions during the operation of the fourth embodiment shown in FIG. Note that the numbers indicating the timing in FIGS. 8 and 9 correspond to each other.
In the fourth embodiment, there is no reset pulse immediately after the selection transistor Tr4 is turned on, as in the third embodiment.
Next, the transfer gate Tr1 is turned on at timing 2, and an SHS pulse is input at timing 3 to take in the signal level to the capacitor Cs. Then, reset is performed at timing 4 and an SHR pulse is input at timing 5 to capture the reset level into the capacitor Cr.
In this case, the potentials of timing 3 and timing 5 are as shown in (3) and (5) of FIG.
[0029]
Also, when resetting the FD portion, the transfer gate Tr1 is turned on, so that the reset voltage of the FD portion at timing 5 has no increase effect due to the coupling capacitance so far, and in this case, is approximately Vdd. .
At timing 3, photoelectrons are transferred to the FD section, but photoelectrons accumulate from the voltage as shown in FIG. 5 (3). Therefore, there is no effect of lowering the voltage.
However, the amount of charge handled is the sum of the saturation amount of the photodiode PD and the saturation amount of the FD portion, and the dynamic range is widened as in the third embodiment, and the effect of widening the dynamic range can be obtained.
In the fourth embodiment, since the drive pulse is simple, it is effective when it is desired to save the operation time.
[0030]
As described above, the four examples of the present embodiment have been described, but any of them can be provided with an electronic shutter function.
Further, although the pixel transistor is an NMOS, it is the same even if the voltage polarity is changed by using it as a PMOS.
In addition, the photoelectric conversion element may not be a photodiode, and may be, for example, a photogate.
Further, the driving method can be variously modified within a range that does not change the gist of the present invention, for example, a case where the number of reset pulses is one in the above-described example is executed with a plurality of pulses.
[0031]
In the above example, the voltage is output from the pixel to the vertical signal line. However, the output signal line may be a horizontal wiring, and the output signal may be a current signal.
In addition, the pixel structure is not limited to the one having four transistors as described above.
Further, although the CDS circuit is taken as an example of the signal processing circuit at the next stage, for example, an A / D converter having a CDS effect may be used, or a circuit that simply holds the reset level and the signal level. For the CDS, it is also possible to adopt a configuration in which the CDS is arranged in the subsequent stage. Thus, the present invention can be implemented in various configurations.
[0032]
【The invention's effect】
As described above, according to the solid-state imaging device of the present invention, the electrical signal output to the output signal line with the transfer gate means turned on is captured by the signal processing circuit provided in the peripheral circuit section, and the captured signal Since the imaging signal is generated from the voltage, the voltage of the floating diffusion portion can be increased by using the capacitive coupling between the transfer gate means and the floating diffusion portion, and the voltage in the pixel can be reduced accordingly. .
Further, since the floating diffusion part, the channel of the transfer gate means, and the photoelectric conversion element can be used as a signal charge receiving tray, the number of handling electrons can be increased and the dynamic range can be expanded.
[0033]
Similarly, according to the driving method of the solid-state imaging device of the present invention, the electric signal output to the output signal line with the transfer gate means turned on is captured by the signal processing circuit provided in the peripheral circuit section and captured. Since the imaging signal is generated from the signal, the voltage of the floating diffusion portion can be increased by using the capacitive coupling between the transfer gate means and the floating diffusion portion, and the voltage in the pixel can be reduced accordingly. Can do.
Further, since the floating diffusion part, the channel of the transfer gate means, and the photoelectric conversion element can be used as a signal charge receiving tray, the number of handling electrons can be increased and the dynamic range can be expanded.
[Brief description of the drawings]
FIG. 1 is a schematic plan view showing an overall configuration example of a MOS sensor type solid-state imaging device according to an embodiment of the present invention.
FIG. 2 is a timing chart showing an operation in the first embodiment of the present invention.
3 is a potential diagram showing signal charge transitions during the operation of the first embodiment shown in FIG. 2; FIG.
FIG. 4 is a timing chart showing an operation in the second embodiment of the present invention.
FIG. 5 is a potential diagram showing signal charge transition during operation of the second embodiment shown in FIG. 4;
FIG. 6 is an explanatory diagram showing the relationship between the amount of light received by the photodiode and the amount of output signal in the second to fourth embodiments of the present invention.
FIG. 7 is a timing chart showing an operation in the third embodiment of the present invention.
FIG. 8 is a timing chart showing an operation in the fourth embodiment of the present invention.
FIG. 9 is a potential diagram showing signal charge transition during operation of the fourth embodiment shown in FIG. 8;
FIG. 10 is a circuit diagram illustrating a configuration example of an output main part in a conventional MOS sensor type solid-state imaging device;
11 is a timing chart illustrating an operation example of the solid-state imaging device illustrated in FIG. 10;
12 is a potential diagram showing signal charge transition during the operation shown in FIG. 11; FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 110 ... Semiconductor chip, 112 ... Imaging pixel part, 114 ... V selection means, 116 ... H selection means, 118 ... Timing generator (TG), 120 ... CDS part, 122 ... Constant current part, 124 ... horizontal signal line, 126 ... output section.

Claims (10)

A semiconductor substrate is provided with an imaging region unit composed of a plurality of pixels, and a peripheral circuit unit that controls the imaging region unit,
Each pixel in the imaging region section has a photoelectric conversion element that generates a signal charge corresponding to the amount of received light, a transfer gate means that transfers the signal charge generated by the photoelectric conversion element to a floating diffusion section, and the floating diffusion In a solid-state imaging device configured to include an amplifying unit that outputs an electric signal corresponding to the voltage of the fusion unit to an output signal line, and a reset unit that resets the voltage of the floating diffusion unit.
The peripheral circuit unit includes a signal level when the signal charge generated by the photoelectric conversion element is transferred to the floating diffusion unit by the transfer gate unit, and a signal level when the floating diffusion unit is reset by the reset unit. Each having the transfer gate means turned on, and a signal processing circuit for outputting a signal corresponding to the difference value,
An electrical signal output to the output signal line in a state where the transfer gate unit is turned on is captured by a signal processing circuit provided in the peripheral circuit unit, and an imaging signal is generated from the captured signal.
A solid-state imaging device.   After the first reset pulse is input to the reset means, the transfer gate means is turned on. In this state, the electric signal output to the output signal line is taken into the signal processing circuit, and then the transfer gate means is turned off. 2. The method according to claim 1, wherein after the second reset pulse is input to the reset means, the transfer gate means is turned on, and an electric signal output to the output signal line in that state is taken into the signal processing circuit. Solid-state imaging device. After the first reset pulse is input to the reset means, the transfer gate means is turned on, and in this state, the electric signal output to the output signal line is taken into the signal processing circuit, and then the reset means is activated, and the transfer gate 2. The device according to claim 1, wherein after the means is turned off and then the reset means is deactivated, the transfer gate means is turned on, and the electric signal output to the output signal line in that state is taken into the signal processing circuit. The solid-state imaging device according to 1 . After deactivating the reset means, the transfer gate means is turned on. In this state, the electric signal output to the output signal line is taken into the signal processing circuit, then the reset means is activated, and the transfer gate means is turned off. , then after inactivation of the reset means to turn on the transfer gate means, according to claim 1, wherein the solid, characterized in that capturing the electric signal output to the output signal line in that state to the signal processing circuit Imaging device. The transfer gate means is turned on, and the electric signal output to the output signal line in that state is taken into the signal processing circuit, then the reset pulse is input to the reset means, and the electric signal output to the output signal line in that state is output. the solid-state imaging device according to claim 1, wherein the capturing signal to the signal processing circuit. A semiconductor substrate is provided with an imaging region unit composed of a plurality of pixels, and a peripheral circuit unit that controls the imaging region unit,
Each pixel in the imaging region section has a photoelectric conversion element that generates a signal charge corresponding to the amount of received light, a transfer gate means that transfers the signal charge generated by the photoelectric conversion element to a floating diffusion section, and the floating diffusion In a driving method of a solid-state imaging device configured to include an amplifying unit that outputs an electric signal corresponding to the voltage of the fusion unit to an output signal line, and a reset unit that resets the voltage of the floating diffusion unit.
The peripheral circuit unit includes a signal level when the signal charge generated by the photoelectric conversion element is transferred to the floating diffusion unit by the transfer gate unit, and a signal level when the floating diffusion unit is reset by the reset unit. Each having the transfer gate means turned on, and a signal processing circuit for outputting a signal corresponding to the difference value,
An electrical signal output to the output signal line in a state where the transfer gate unit is turned on is captured by a signal processing circuit provided in the peripheral circuit unit, and an imaging signal is generated from the captured signal.
A method for driving a solid-state imaging device. After the first reset pulse is input to the reset means, the transfer gate means is turned on. In this state, the electrical signal output to the output signal line is taken into the signal processing circuit, and then the transfer gate means is turned off. to, after entering the second reset pulse to the reset means, and turns on the transfer gate means, according to claim 6, wherein the capturing the electric signal output to the output signal line in that state to the signal processing circuit Driving method for a solid-state imaging device. After the first reset pulse is input to the reset means, the transfer gate means is turned on, and in this state, the electric signal output to the output signal line is taken into the signal processing circuit, and then the reset means is activated, and the transfer gate 2. The device according to claim 1, wherein after the means is turned off and then the reset means is deactivated, the transfer gate means is turned on, and the electric signal output to the output signal line in that state is taken into the signal processing circuit. 6. A driving method of a solid-state imaging device according to 6 . After deactivating the reset means, the transfer gate means is turned on. In this state, the electric signal output to the output signal line is taken into the signal processing circuit, then the reset means is activated, and the transfer gate means is turned off. 7. The solid-state signal processing circuit according to claim 6 , wherein after the reset means is deactivated, the transfer gate means is turned on, and an electric signal output to the output signal line in that state is taken into the signal processing circuit. Driving method of imaging apparatus. The transfer gate means is turned on, and the electric signal output to the output signal line in that state is taken into the signal processing circuit, then the reset pulse is input to the reset means, and the electric signal output to the output signal line in that state is output. The method for driving a solid-state imaging device according to claim 6 , wherein a signal is taken into the signal processing circuit.

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