JP2007214791A - Imaging element, imaging apparatus, and driving method of imaging element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an imaging element having such constitution that respective pixels can be simplified in constitution and a readout time of signal charges can be shortened. <P>SOLUTION: The imaging element has a plurality of pixels (1) arranged in two dimensions, and also has a plurality of selection lines (18) for selecting respective rows and a plurality of output lines (7) for reading signal charges out of the pixels connected to respective columns. Then each of the pixels comprises a photodiode (2), a MOS transistor (3) for amplification which amplifies a potential of a control electrode and outputs a corresponding signal to an output line, a MOS transistor (5) for resetting which resets the gate electrode of the MOS transistor for amplification to a reset potential, a MOS transistor (4) for transfer which turns on and off transfer of electric charges accumulated in the photodiode to the gate electrode, and a capacitor provided between the gate electrode and selection line. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an imaging device, an imaging device using the imaging device, and a driving method of the imaging device, and more particularly to an imaging device, an imaging device, and a driving method configured with a CMOS sensor.

  Conventionally, as a solid-state imaging device, a CCD is often used because of its good SN ratio.

  On the other hand, so-called amplification type solid-state imaging devices have also been developed which have advantages such as ease of use and low power consumption. The amplification type solid-state imaging device is of a type that guides signal charges accumulated in a light receiving pixel to a control electrode of a transistor provided in a pixel portion, and outputs an amplified signal from a main electrode. Among these types, there are a SIT type image sensor using SIT as an amplifying transistor (for example, see Non-Patent Document 1) and a BASIS using a bipolar transistor (for example, see Non-Patent Document 2). In addition, there are CMD using a JFET whose control electrode is depleted (for example, see Non-Patent Document 3), CMOS sensor using a MOS transistor (for example, see Non-Patent Document 4), and the like. In particular, the CMOS sensor is well matched with the CMOS process, and the peripheral CMOS circuit can be made on-chip.

  The problem common to the amplification type solid-state imaging device is that fixed pattern noise (FPN) is added to the signal of the image sensor because the output offset of the amplification transistor provided in each pixel is different for each pixel. In order to eliminate this FPN, various signal readout circuits have been devised conventionally.

  In addition, the CMOS sensor has a drawback in that it is difficult to reduce the area of the pixel because a large number of MOS transistors are required to configure one pixel. In view of this drawback, a proposal has been made to eliminate the selection MOS transistor in the pixel for selecting a row for reading the potential of the gate electrode portion of the amplification MOS transistor to the vertical output line (for example, see Patent Document 1). reference).

  In the CMOS sensor described in Patent Document 1, since there is no selection MOS transistor in the pixel, the area per pixel can be reduced as compared with a CMOS sensor including a selection MOS transistor, and the same as in the conventional case. A signal with a high S / N ratio can be output.

A. Yusa, J. et al. Nishizawa et al., “SIT image sensor: Design consideration and characteristics,” IEEE trans. Vol. ED-33, pp.735-742, June 1986 N. Tanaka et al., “A 310K pixel bipolar imager (BASIS),” IEEE Trans. Electron Devices, vol.35, pp. 646-652, May 1990 Nakamura et al. “Gate Storage MOS Phototransistor Image Sensor”, Television Society Journal, 41, 11, pp.1075-1082 Nov., 1987 S.K.Mendis, S.E.Kemeny and E.R.Fossum, “A 128 × 128 CMOS active image sensor for highly integrated imaging systems,” in IEDM Tech. Dig., 1993, pp. 583-586 JP-A-11-112018

  However, in the configuration described in Patent Document 1, since there is no selection MOS transistor, when the signal transfer of all the pixels is performed at once, the signal potentials of the gate electrode portions of the amplification MOS transistors in all the rows are vertical. It will be read to the output line. Therefore, in order to read the charge signal for each row, the gate electrode portion must be reset for each row immediately before the charge is transferred to the gate electrode portion of the amplifying transistor. In the configuration described in Patent Document 1, both the supply of the reset potential of the gate electrode portion and the reading of the charge signal are performed using the vertical output line. Therefore, compared to a configuration having a selection MOS transistor that requires only one reset of all pixels, it takes time to change the potential of the vertical output line and time to reset the gate electrode portion for each row. It takes a long time to read the signal charge.

  In addition, in the case of moving image shooting, the time for outputting pixel signals for one screen or one field is determined by the standard. Therefore, when taking a moving image with a CMOS sensor without a selection MOS transistor of Patent Document 1, the horizontal scanning time has to be shortened by the amount of signal readout time. That is, the horizontal scanning frequency must be increased. However, the higher the horizontal scanning frequency is, the higher the noise component is on the sensor signal, leading to a reduction in the S / N ratio of the sensor signal.

  Furthermore, when an image is to be taken by electronic shutter control using a CMOS sensor without the selection MOS transistor described in Patent Document 1, rolling electronic shutter control is performed. This is because it is not possible to read out charge signals to the gates of the amplifying MOS transistors all at once and select a specific row, so that it is necessary to read out the charge from the photoelectric conversion unit one row at a time. Therefore, it is necessary to reset the photoelectric conversion unit before the necessary exposure time from the timing of reading each row. In this case, in addition to the reset operation of the gate of the amplification MOS transistor of the signal readout row pixel, it is necessary to perform the operation of resetting the pixel of another row in time series. Therefore, there is a problem that the time required for reading each row becomes longer than that of a CMOS sensor having a selection MOS transistor. In the rolling shutter control, the longer the time for reading, the more the shooting timing shifts at the top and bottom of the screen, so that when the subject is moving, the image becomes distorted.

  The present invention has been made in view of the above problems, and in the imaging device, an imaging device having a configuration capable of simplifying the configuration of each pixel and shortening the signal charge readout time, and the imaging device. It is an object of the present invention to provide an imaging device used and a method for controlling the imaging device.

  In order to achieve the above object, an image pickup device according to the present invention in which a plurality of pixels are arranged two-dimensionally includes a plurality of selection lines for selecting each row and a plurality of readout signals for pixels connected to each column. Output line, each pixel performs photoelectric conversion and accumulates the generated charge, and amplifies the potential of the control electrode and outputs a corresponding signal to the output line A transistor, a reset switch for resetting the control electrode of the amplifying transistor to a reset potential, and provided between the photoelectric converting means and the amplifying transistor, of the charge signal accumulated in the photoelectric converting means, A transfer switch for turning on and off transfer to the control electrode of the amplifying transistor; and a capacitor provided between the control electrode of the amplifying transistor and the selection line.

  An image pickup apparatus according to the present invention includes the image pickup device described above, an image processing unit that processes a charge signal obtained by the image pickup device to acquire image data, and an image data processed by the image processing unit. Storage means for storing.

  Further, in the driving method of the present invention for the imaging element described above, a reset step of resetting the control electrodes of the amplification transistors of the plurality of pixels to the reset potential via the reset switch;

  A selection step of displacing the potential of the selection line of the readout row;

  A charge signal transfer step of turning on the transfer switch of the read row while the potential of the selection line is displaced, and after the transfer step, while the potential of the selection line is displaced, And a reading step of reading out the signal of the output line.

  According to the present invention, in the imaging device, the configuration of each pixel is simplified, and the imaging device having a configuration capable of shortening the signal charge readout time, the imaging device using the imaging device, and the imaging An element control method can be provided.

  The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings.

<First Embodiment>
FIG. 1 is a circuit diagram showing a configuration of a CMOS sensor according to the first embodiment of the present invention. As for the components of the CMOS sensor according to the first embodiment, the MOS transistor is assumed to be N-type, and is turned on when the gate is High (H) and non-conductive when it is Low (L). The conduction state (off) is established. The photodiode is configured to store signal electrons in an N-type semiconductor region formed in a P-type semiconductor.

  In FIG. 1, 1 is a unit pixel, and only 4 × 4 pixels are shown for easy understanding of the figure. However, in general, a general CMOS sensor used for a digital camera or the like has a very large number of pixels. Have pixels. Reference numeral 2 denotes a photodiode (PD) that receives light and accumulates signal charges. Reference numeral 3 denotes a signal charge amplification MOS transistor (hereinafter referred to as “amplification MOS”). Reference numeral 4 denotes a transfer MOS transistor (hereinafter referred to as “transfer MOS”) for transferring the signal charge accumulated in the PD 2 to the gate electrode portion of the amplification MOS 3. Reference numeral 5 denotes a reset MOS transistor (hereinafter referred to as “reset MOS”) for resetting the gate electrode potential of the amplification MOS 3. Reference numeral 6 denotes a power supply potential supply line, and the drain electrode of the amplification MOS 3 is connected to the power supply potential supply line 6. 44 is a so-called floating diffusion part (FD) in which the transfer MOS 4, the drain of the reset MOS 5, and the gate of the amplification MOS 3 are connected, and signal charges are transferred from the transfer MOS 4. Reference numeral 45 denotes a capacitor having an FD 44 and an FD potential control line 18 described later as electrodes.

  7 is a pixel output line, 8 is a switching MOS transistor (hereinafter referred to as “switch MOS”) for supplying a reset potential Vres through the output line 7, and the reset potential Vres is supplied from a terminal 43. Further, a pulse φ42 described later with reference to FIG. 2 is supplied to the gate electrode of the switch MOS8 from the pulse supply terminal 42 via the control line 12.

  Reference numeral 9 denotes a constant current supply MOS transistor for supplying a constant current to the output line 7 (hereinafter referred to as “constant current supply MOS”). The constant current supply MOS 9 operates with the amplification MOS 3 as a source follower so that a potential having a certain voltage difference from the gate potential of the amplification MOS 3 appears on the output line 7. Further, a signal φ41 having a predetermined potential as described later with reference to FIG. 2 is applied to the gate electrode of the constant current supply MOS 9 so as to perform a saturation region operation such that the constant current supply MOS 9 becomes a constant current supply source. Is supplied from the potential supply terminal 41 via the constant potential supply line 13.

  10 is a transfer control line for controlling the gate potential of the transfer MOS 4, and 11 is a reset control line for controlling the gate potential of the reset MOS 5.

  Reference numeral 14 denotes a transfer pulse input terminal for supplying the transfer pulse φTX to the transfer control line 10, and reference numeral 16 denotes a reset pulse input terminal for supplying the reset pulse φRES to the reset control line 11. A vertical scanning circuit 17 outputs selection pulses (φV1 to φV4) for sequentially selecting and scanning the rows of pixels arranged in a matrix. Reference numeral 18 denotes an output line of the vertical scanning circuit 17, which is an FD potential control line.

  Reference numeral 19 denotes a switch MOS transistor (hereinafter referred to as “switch MOS”) for guiding the transfer pulse φTX from the pulse supply terminal 14 to the control line 10. The gate of the switch MOS 19 is connected to the FD potential control line 18, and which row of pixels is driven is determined by vertical scanning pulses φV 1 to φV 4 on the FD potential control line 18.

  Reference numeral 22 denotes a readout circuit that reads out signal charges from the pixels. In the readout circuit 22, reference numeral 23 denotes a capacitor for holding the reset signal output of the pixel (hereinafter referred to as “noise capacitor”), and 24 denotes a capacitor for holding the signal charge output of the pixel accumulated by the PD 2 (hereinafter referred to as “noise capacity”). Called "signal capacity"). Reference numeral 25 denotes a switching MOS transistor (hereinafter referred to as “noise readout MOS”) for turning on / off the conduction between the pixel output line 7 and the noise capacitor 23. Reference numeral 26 denotes a switching MOS transistor (hereinafter referred to as “signal readout MOS”) for turning on / off the conduction between the pixel output line 7 and the signal capacitor 24.

  Reference numeral 27 denotes a noise output line through which a reset signal output held in the noise capacitor 23 is guided. Reference numeral 28 denotes a signal output line through which a signal charge output held in the signal capacitor 24 is guided. 29 is a switching MOS transistor for turning on / off the conduction between the noise capacitor 23 and the noise output line 27, and 30 is a switching MOS transistor for turning on / off the conduction between the signal capacitor 24 and the signal output line 28.

  Reference numeral 31 denotes a noise output line reset MOS transistor for resetting the potential of the noise output line 27, and reference numeral 32 denotes a signal output line reset MOS transistor for resetting the potential of the signal output line 28. Reference numeral 33 denotes a reset potential supply terminal for supplying a reset potential to the source electrodes of the reset MOS transistors 31 and 32.

  Reference numeral 34 denotes a horizontal scanning circuit that outputs horizontal scanning pulses φH1 to φH4 for sequentially selecting and scanning the noise capacitors 23 and the signal capacitors 24 provided for each column of pixels arranged in a matrix, and reference numeral 35 denotes an output line of the horizontal scanning circuit 34. is there. The output line 35 of the horizontal scanning circuit 34 is connected to switching MOS transistors 29 and 30.

  Reference numeral 36 denotes a pulse input terminal for applying a pulse φCRES to the gate electrodes of the reset MOS transistors 31 and 32. Reference numerals 37 and 38 denote pulse supply terminals for applying pulses φCN and φCS to the gate electrodes of the noise readout MOS 25 and the signal readout MOS 26, respectively. A differential amplifier 39 amplifies and outputs a difference voltage between the potential of the noise output line 27 and the potential of the signal output line 28, and 40 is an output terminal of the differential amplifier 39.

  Next, the operation of the CMOS sensor having the above configuration will be described with reference to the timing chart of FIG. FIG. 2 shows a timing chart when the PD2 in the fourth row is reset simultaneously with the reading of the signal charges in the first row.

  First, in a state where high is applied to the terminal 42 and the output line 7 is reset by the reset potential Vres, the reset pulse φRES is changed from the low level (L) to the high level (H) (t1), so that all pixels Are reset to the reset potential Vres at once. At this time, the capacitor 45 is charged up to the reset potential Vres. Next, when the reset pulse φRES is returned to L and the vertical scanning circuit 17 sets the vertical scanning pulse φV1 to H (t2), the first row is selected. By this operation, the potential of the FD 44 in the first row is raised to the potential of Vres + (H−L) by capacitive coupling by the capacitor 45, and becomes higher than the potential of the FD 44 in other rows. By making this FD potential difference, that is, the gate potential difference of the amplification MOS 3, only the amplification MOS 3 of the selected row pixel becomes conductive, and the FD 44 of the pixel of the selected row is output.

For example, when the potential of the FD 44 in the selected row is 4V, the potential of the FD 44 in the non-selected row is 3V, and the threshold Vth of the amplification MOS 3 is 0.7V, the source follower operation of the selected row pixel
Pixel output line (source of amplification MOS 3) potential = 4V-Vth = 3.3V

It becomes. Therefore, in the amplification MOS 3 in the non-selected row, Vgs = 3V−3.3V = −0.3V <0.7V (Vth), and thereby, the amplification MOS 3 of the pixel in the non-selected row becomes non-conductive.
Note that the potential difference (HL) raised by capacitive coupling of the capacitor 45 is set as follows. First, since the switch MOS 10 is turned on when H of φV1 to φV4 is applied to the gate of the switch MOS10, the maximum potential of the transfer control line 10 is H-Vth1 (threshold of the switch MOS10). Since the maximum potential of the transfer control line 10 is applied to the gate of the transfer MOS 4, assuming that the threshold of the transfer MOS 4 is Vth2, the minimum value (the value of the brightest pixel, Vh) that the FD 44 can take is Vres− (H−Vth1). -Vth2). Further, since the maximum value (value of the darkest pixel, Vd) that can be taken by the FD 44 is Vres, the potential difference (Vd−Vh) = Vres− (Vres−H + Vth1 + Vth2) = H−. Vth1-Vth2. Therefore, if (HL) is set to H-Vth1-Vth2 or more, only the amplification MOS 3 in the selected row can be turned on.

  Although the potential difference (H−L) is ideally Vd−Vh, there is actually a variation in the threshold value Vth of the amplification MOS 3 of each pixel 1, and generally, the current of the MOS transistor is almost completely turned off. It is necessary that Vgs <Vth−0.4V. Therefore, it is preferable that Vd−Vh + α and α≈0.6V. Of course, it goes without saying that α is not limited to this value.

  Next, the pulse φ42 is set to L to turn off the switch MOS8, and the potential of the pulse φ41 is set to a potential at which the constant current supply MOS9 can supply a constant current (t3). As a result, the potential of the FD 44 is read out to the output line 7. In this state, φCN is set to H and the noise readout MOS 25 is turned on, whereby the reset output (noise signal) of the pixels in the first row is accumulated in the noise capacitor 23 (t4).

  Next, the transfer pulse φTX is set to H, and φV4 for selecting a row for resetting PD2 other than the first row (here, the fourth row) is set to H (t5). Here, the switch MOS 19 in the first row and the fourth row in which φV1 is H are simultaneously turned on, and only the transfer MOSs 4 in the first row and the fourth row are turned on. Accordingly, the signal charge is transferred from the PD 2 to the FD 44 only in the first row and the fourth row.

  At this time, the potential of the FD 44 in the fourth row is a potential obtained by adding the charge Vpd transferred from the PD 2 to the potential raised to Vres + (H−L) by the capacitive coupling of the capacitor 45.

  Then, simultaneously with the transfer pulse φTX being returned to L, φV4 is also returned to L (t6). Along with this, the potential of the FD 44 in the fourth row decreases through the capacitor 45, so that the potential of the FD 44 becomes Vres + (HL) + Vpd− (HL) = Vres + Vpd. As described above, since PD2 of the first embodiment of the present invention stores electrons, Vres + Vpd is at a potential lower than Vres, so that amplification MOS 3 is turned off and the fourth row is a non-selected row. Thus, after the charge transfer is completed, only the potential corresponding to the signal charge in the first row appears on the pixel output line 7 and the PD2 of the pixel in the fourth row is reset.

  In this state, φCS is set to H to turn on the signal readout MOS 26 (t6), whereby the signal charge output of the first row is accumulated in the signal capacitor 24. When reading of the signal charge output of the first row is finished in this way, φV1 for selecting the first row is set to L (t7).

  Next, by sequentially turning on the vertical scanning pulses φH1 to φH4 (t8 to t11), the noise signal and the charge signal accumulated in the noise capacitor 23 and the signal capacitor 24 are sequentially converted into the noise output line 27 and the signal output line 28, respectively. Is output. Then, the difference is taken by 39 and a signal corresponding to the optical signal from which the noise has been removed is output from the terminal 40.

  Thereafter, the reset of the (n + 1) th row (the first row in the example of FIG. 1) is reset simultaneously with the signal readout of the second row, and the (n + 2) th row (FIG. 1) simultaneously with the signal readout of the third row. In the example of FIG. 5, the signal is read out and the PD2 in another row is sequentially reset, as in the second row).

  As described above, according to the first embodiment, the reset operation of the photodiode in any row can be performed in parallel with the signal read operation in another row, and the selected row and the non-selected row are selected. It is not necessary to reset the FD of the row at different timings. Accordingly, it is possible to shorten the time required for pixel reading.

  According to the first embodiment, since one capacitor for raising the FD potential is added to the pixel configuration of Patent Document 1, it is disadvantageous for pixel reduction. Compared with a pixel configuration with a mark, the pixel configuration is simplified.

<Second Embodiment>
FIG. 3 is a circuit diagram showing the configuration of the CMOS sensor according to the second embodiment of the present invention. Components common to those in FIG. 3 is different in that the gate electrode and the source of the reset MOS 5 in each pixel in FIG. 1 are connected to a power source, and the reset control line 11, the reset pulse input terminal 16, the switch MOS 8 and the control line 12 in FIG. .

  The drive pulse for driving the CMOS sensor having the configuration of FIG. 3 is obtained by eliminating the FD potential reset pulse φRES and the control pulse φ42 of the switch MOS8 in the drive pulse timing of the first embodiment shown in FIG. Is the same.

  When the threshold voltage of the reset MOS 5 is Vth and the power supply voltage is VDD, the potential of the FD 44 is reset to (VDD−Vth) at the normal time when the output of the vertical scanning circuit 17 is L. When the potential of FD44 is equal to or higher than (VDD-Vth), the drain current does not flow through the reset MOS. Therefore, the FD potential does not rise above (VDD-Vth).

  In this state, when any of the output lines 18 of the vertical scanning circuit 17 becomes H in order to select a certain row, the potential of the FD 44 of the selected row pixel is raised by (HL), and the pixel output of the selected row is output. Appears in the pixel output line 17 in the same manner as in the first embodiment. In addition, since the FD 44 of the selected row pixel is raised to a potential of (VDD−Vth) or higher, the reset MOS 5 of the selected row pixel remains in the off state.

  When the pixel output is completed and the output of the vertical scanning circuit 17 becomes L, the FD potential of the pixel is now swung down through the capacitor 45, and the potential of the FD 44 is temporarily set by the amount of the signal charge of PD2 transferred to the FD 44. It drops below (VDD-Vth). In this state, a drain current flows through the reset MOS 5, and the FD potential returns to (VDD-Vth) within a very short time.

  As described above, according to the second embodiment of the present invention, the reset control line 11 of the reset MOS 5 is unnecessary in addition to the same effects as those of the first embodiment. The configuration becomes simpler. Furthermore, the reset pulse φRES of the FD 44 required in the first embodiment is not necessary, and the operation time is further shortened.

<Third Embodiment>
FIG. 4 is a circuit diagram showing a configuration of a CMOS sensor according to the third embodiment of the present invention. Components common to those in FIG. FIG. 4 is different from the configuration shown in FIG. 1 in that the pixel reset MOS 5 is replaced with a junction transistor (JFET) 46 and its control electrode is a P-type semiconductor common to the fixed potential electrode of the photodiode 2. Accordingly, the reset control line 11, the reset pulse input terminal 16, the switch MOS 8 and the control line 12 shown in FIG.

  The JFET 46 is a general normally-on type, and when the pinch-off voltage is Vp, the threshold voltage value is −Vp. Assuming that the P-type semiconductor that is the control electrode of the JFET 46 is grounded and set to 0V, the potential of the FD 44 is normally reset to 0 − (− Vp), that is, Vp. This situation is the same as in the second embodiment described above. The driving of the CMOS sensor of FIG. 4 other than the JFET 46 is the same as the driving of the second embodiment.

  Thus, according to the third embodiment of the present invention, the gate electrode necessary for the MOS transistor is not necessary in the junction transistor for FD reset. Therefore, the configuration of the pixel is simpler than that of the second embodiment, and the configuration of the pixel is simpler than that of the configuration with the reset MOS transistor, and the pixel can be reduced. Further, in the point of driving the sensor including the rolling reset operation, the FD reset pulse is unnecessary as in the second embodiment, and the PD2 is reset simultaneously with the signal charge transfer in the signal readout row. be able to. Therefore, the driving time of the sensor can be shortened compared with the conventional example.

  In the first to third embodiments, the components of the CMOS sensor are configured such that the MOS transistor is N-type and the photodiode is configured to store signal electrons in an N-type semiconductor region formed in a P-type semiconductor. Explained that there is. However, the present invention is not limited to this. This is a system in which a MOS transistor is a P-type MOS transistor which is turned on when its gate is (L), and a signal hole is accumulated in a P-type semiconductor region formed in an N-type semiconductor. Obviously, the invention can also be constructed.

  In the first to third embodiments, the case where the rolling shutter control is realized has been described. However, the present invention is not limited to this. When the CMOS sensor of the present invention is applied to a camera having a mechanical shutter, the photodiodes of all the pixels are reset all at once, then the shutter is closed after a predetermined exposure time, and the signal charges accumulated in the photodiodes are stored for each row. The operation is such that it is read out. In this case, when the signal charge of the PD in one row is read to the FD, the PD2 in another row is not reset. Even in this case, it is not necessary to reset the FD immediately before reading the signal charges in each row, so that the reading time can be shortened.

<Fourth Embodiment>
Next, a digital still camera using the amplification type solid-state imaging device described in the first to third embodiments will be described with reference to FIG.

  In FIG. 3, 401 is a barrier that serves as a lens protect and a main switch, 402 is a lens that forms an optical image of a subject on the amplification type solid-state imaging device 404, and 403 is a diaphragm for variably controlling the amount of light passing through the lens 402. It is. Reference numeral 404 denotes an amplification type solid-state imaging device for taking in the subject optical image formed by the lens 402 as an image signal, and has the configuration described in any of the first to third embodiments.

  Reference numeral 405 denotes an imaging signal processing circuit including a variable gain amplifier that amplifies an image signal output from the imaging device 404, a gain correction circuit that corrects a gain value, and the like. An A / D converter 406 performs analog-digital conversion of the image signal processed by the imaging signal processing circuit 405, and 407 performs various corrections on the image data output from the A / D converter 406 and compresses the data. A signal processing unit. Reference numeral 408 denotes a timing generation unit that outputs various timing signals to the imaging device 404, the imaging signal processing circuit 405, the A / D converter 406, and the signal processing unit 407. Reference numeral 409 denotes an overall control / arithmetic unit for controlling various calculations and the entire digital still camera, and 410 denotes a memory unit for temporarily storing image data.

  Reference numeral 411 denotes a recording medium control interface unit for recording or reading on the recording medium, 412 denotes a detachable recording medium such as a semiconductor memory for recording or reading image data, and 413 denotes a communication with an external computer or the like. It is an interface part.

  Next, the operation at the time of shooting in the digital still camera having the above configuration will be described.

  When the barrier 401 is opened, the main power supply is turned on, then the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 406 is turned on.

  Thereafter, in order to control the exposure amount, the overall control / arithmetic unit 409 opens the aperture 403, and the signal output from the imaging device 404 is converted by the A / D converter 406 and then input to the signal processing unit 407. Is done. The overall control / calculation unit 409 performs photometry based on the data that has been subjected to predetermined signal processing by the signal processing unit 407, determines brightness based on the result, and calculates exposure. The diaphragm 403 is controlled in accordance with the obtained exposure.

  Next, based on the signal output from the imaging device 404, the overall control / calculation unit 409 extracts the high frequency component and calculates the distance to the subject. Thereafter, the lens is driven to determine whether or not it is in focus. When it is determined that the lens is not in focus, the lens is driven again to perform distance measurement. Then, after the in-focus state is confirmed, the main exposure is started.

  When the exposure is completed, the image signal output from the imaging device 404 is A / D converted by the A / D converter 406, passes through the signal processing unit 407, and is written in the memory unit 410 by the overall control / calculation unit 409.

  Thereafter, the data stored in the memory unit 410 is recorded on a removable recording medium 412 such as a semiconductor memory through the recording medium control I / F unit 411 under the control of the overall control / arithmetic unit 409.

  Further, the image may be processed by directly inputting to a computer or the like through the external I / F unit 413.

<Fifth Embodiment>
Next, a digital video camera using the amplification type solid-state imaging device described in the first to third embodiments will be described with reference to FIG.

  In FIG. 4, reference numeral 501 denotes a photographing lens, which includes a focus lens 501A for performing focus adjustment, a zoom lens 501B for performing a zoom operation, and an imaging lens 501C. Reference numeral 502 denotes an aperture, and reference numeral 503 denotes an amplification type solid-state imaging device that photoelectrically converts an object image formed on the imaging surface by the photographing lens 501 and converts it into an electrical image signal. The configuration described in the embodiment is provided. Reference numeral 504 denotes a sample-and-hold circuit (S / H circuit) that samples and holds the imaging signal output from the imaging device 503 and further amplifies the signal level, and outputs a video signal.

  A process circuit 505 performs predetermined processing such as gamma correction, color separation, and blanking processing on the video signal output from the S / H circuit 504, and outputs a luminance signal Y and a chroma signal C. The chroma signal C output from the process circuit S / H5 is subjected to white balance and color balance correction by the color signal correction circuit 21, and is output as color difference signals RY and BY.

  Also, the luminance signal Y output from the process circuit 505 and the color difference signals RY and BY output from the color signal correction circuit 21 are modulated by an encoder circuit (ENC circuit) 24, and are used as standard television signals. Is output. Then, it is supplied to a monitor EVF such as a video recorder (not shown) or an electronic viewfinder.

  Reference numeral 506 denotes an iris control circuit which controls the iris driving circuit 507 based on the video signal supplied from the S / H circuit 504 so that the level of the video signal becomes a constant value of a predetermined level. The ig meter is automatically controlled to control the opening amount.

  Reference numerals 513 and 514 denote different band-limited band pass filters (BPFs) for extracting high-frequency components necessary for performing focus detection from the video signal output from the S / H circuit 504. Signals output from the first bandpass filter 513 (BPF1) and the second bandpass filter 514 (BPF2) are gated by the gate circuit 515 and the focus gate frame signal, respectively, and the peak value is detected by the peak detection circuit 516. Is detected and held. Further, the peak value is input to the logic control circuit 517. This signal is called a focus voltage, and the focus is adjusted by this focus voltage.

  Reference numeral 518 denotes a focus encoder that detects the moving position of the focus lens 501A, 519 denotes a zoom encoder that detects the focal length of the zoom lens 501B, and 520 denotes an iris encoder that detects the opening amount of the diaphragm 502. The detection values of these encoders are supplied to a logic control circuit 517 that performs system control.

  The logic control circuit 517 performs focus detection on the subject based on a video signal corresponding to the set focus detection area, and performs focus adjustment. That is, the peak value information of the high frequency component supplied from each of the bandpass filters 513 and 514 is taken in, and the focus motor 510 is moved to the focus driving circuit 509 to drive the focus lens 501A to the position where the peak value of the high frequency component is maximized. Control signals such as a rotation direction, a rotation speed, and rotation / stop are supplied and controlled.

It is a circuit diagram which shows the structure of the CMOS sensor of the 1st Embodiment of this invention. It is a timing chart which shows the drive pulse timing explaining the sensor operation | movement in the 1st thru | or 3rd embodiment of this invention. It is a circuit diagram which shows the structure of the CMOS sensor of the 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the CMOS sensor of the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the digital still camera in the 4th Embodiment of this invention. It is a block diagram which shows the structure of the digital video camera in the 5th Embodiment of this invention.

Explanation of symbols

  1: pixel, 2: photodiode (PD), 3: signal charge amplification MOS transistor, 4: signal transfer MOS transistor, 5: reset MOS transistor, 6: power supply potential supply line, 7: pixel output line, 8 : MOS transistor for switch, 9: MOS transistor for constant current supply, 10: Transfer control line, 11: Reset control line, 12: Control line, 13: Constant potential supply line, 14: Transfer pulse input terminal, 16: Reset pulse Input terminal, 17: vertical scanning circuit, 18: FD potential control line, 19: switching MOS transistor, 22: readout circuit, 23: noise capacity, 24: signal capacity, 25, 26: switching MOS transistor, 27: noise Output line 28: Signal output line 29: Switch MOS transistor 30: Switch MOS transistor 3 : MOS transistor for resetting noise output line, 32: MOS transistor for resetting signal output line, 33: Reset potential supply terminal, 34: Horizontal scanning circuit, 35: Output line, 36, 37, 38: Pulse input terminal, 39: Difference Dynamic amplifier, 40: output terminal, 41: potential supply terminal, 42: pulse supply terminal, 43: terminal, 44: floating diffusion part (FD), 45: capacitance, 46: JFET

Claims (11)

An imaging device in which a plurality of pixels are two-dimensionally arranged, and includes a plurality of selection lines for selecting each row, and a plurality of output lines for reading out charge signals of pixels connected to each column, Pixel is
Photoelectric conversion means for performing photoelectric conversion and accumulating the generated charges;
An amplifying transistor that amplifies the potential of the control electrode and outputs a corresponding signal to the output line;
A reset switch for resetting the control electrode of the amplifying transistor to a reset potential;
A transfer switch provided between the photoelectric conversion means and the amplifying transistor, for turning on / off the transfer of the charge signal accumulated in the photoelectric conversion means to the control electrode of the amplifying transistor;
An image pickup device comprising: a capacitor provided between a control electrode of the amplification transistor and the selection line. Supply means for supplying a reset potential to the output line;
A constant current source for driving the output line at a constant current when reading the signal charge;
The reset switch is connected to the output line, and at least the control electrode of the amplifying transistor is reset by the reset switch, the supply means is used, and the signal charge is read by using the constant current source. The imaging device according to claim 1, wherein the imaging device is driven.   The image pickup device according to claim 1, wherein the reset switch includes a MOS transistor, and drives the control electrode and the drain electrode at the same potential.   The imaging device according to claim 1, wherein the reset switch includes a junction transistor.   When the charge signal of the photoelectric conversion means is read out, the potential of the selection line for selecting a reading row is changed with the reset switch turned off, whereby the control electrode of the amplifying transistor is controlled via the capacitor. 5. The image pickup device according to claim 1, wherein the electric potential is displaced by the electric potential displacement of the selection line.   The imaging device according to claim 5, wherein a transfer switch of the readout row is turned on while the potential of the selection line is displaced. A holding capacitor for holding the signal of the vertical line;
The image sensor according to claim 6, wherein after the transfer switch of the readout row is turned off, the signal of the vertical line is read out to the storage capacitor while the potential of the selection line is displaced.   While the transfer switch of the readout row is turned on, the potential of the selection line of the row to reset the photoelectric conversion means is displaced, and the transfer switch of the row to be reset is turned on and the selection of the row to be reset is performed. 8. The image pickup device according to claim 7, wherein the signal of the vertical line is read out to the storage capacitor after the line potential is returned to the potential before displacement and the transfer switch of the row to be reset is turned off. The image sensor according to any one of claims 1 to 8,
Image processing means for processing the charge signal obtained by the image sensor to obtain image data;
An image pickup apparatus comprising: storage means for storing image data processed by the image processing means. A plurality of pixels are two-dimensionally arranged, an imaging device having a plurality of selection lines for selecting each row and a plurality of output lines for reading signal charges of the pixels connected to each column, A photoelectric conversion means for performing photoelectric conversion and accumulating the generated charge, an amplifying transistor for amplifying a charge signal of the control electrode and outputting a corresponding signal to the output line, and a control electrode of the amplifying transistor A reset switch for resetting the signal to a reset potential, and transferring the charge signal accumulated in the photoelectric conversion means to the control electrode of the amplification transistor provided between the photoelectric conversion means and the amplification transistor And a transfer switch that turns on and off, a control electrode of the amplification transistor, and a capacitor provided between the selection lines,
Resetting the control electrodes of the amplifying transistors of the plurality of pixels to the reset potential via the reset switch;
A selection step of displacing the potential of the selection line of the readout row;
A charge signal transfer step of turning on the transfer switch of the read row while displacing the potential of the selection line;
And a reading step of reading out the signal of the output line while displacing the potential of the selection line after the transfer step. While the transfer switch of the readout row is turned on in the transfer step, the potential of the selection line of the row for resetting the photoelectric conversion means is displaced, and the reset row selection for turning on the transfer switch of the row to be reset The driving method according to claim 10, wherein the step and the reading step are performed after a transfer switch of the reading row is turned off.

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