JP4537271B2 - Imaging apparatus and imaging system - Google Patents

Description

  The present invention relates to an imaging device that captures a subject image.

  In recent years, the cell size of a photoelectric conversion unit using a miniaturization process has been energetically reduced for high resolution. On the other hand, an amplification type solid-state imaging device capable of amplifying and outputting an electric signal has attracted attention because the output of the electric signal converted by the photoelectric conversion unit is lowered. Such amplification type solid-state imaging devices include solid-state imaging devices such as MOS type, AMI, CMD, and bipolar type image sensors.

  Among these, the MOS type solid-state imaging device accumulates light carriers generated by the photodiode in the gate electrode of the MOS transistor, and amplifies the potential change of the gate to the output unit according to the drive timing from the scanning circuit. Output. In recent years, a CMOS solid-state imaging device that is realized by a CMOS process, including the photoelectric conversion portion and its peripheral circuit portion, has attracted particular attention among MOS solid-state imaging devices.

FIG. 10 is an internal configuration diagram of a conventional solid-state imaging device. The solid-state imaging device shown in FIG. 10 has a photodiode 1 that converts an incident optical signal into an electric signal, a transfer switch 2 that transfers signal charges from the photodiode 1 to a floating diffusion region 11, and amplifies the transferred signal. A source follower (amplification transistor 10, constant current source 7) and constant voltage source 5, and a selection switch 6 for reading out a signal accumulated in the floating diffusion 11 to the vertical signal line 13; , and a reset switch 3 and the reset voltage source 4 for resetting the floating diffusion region 11 to a potential V _PR.

  Further, the solid-state imaging device shown in FIG. 10 includes a vertical scanning circuit 14 that outputs a control signal for switching on / off of each switch to each gate of the transfer switch 2, the reset switch 3, and the selection switch 6; Transfer gates 15a and 15b for removing fixed pattern noise caused by on / off switching and a signal storage unit 16 for storing a signal input when the transfer gates 15a and 15b are turned on are provided.

  Note that FIG. 10 illustrates the arrangement of four pixels, but the number of pixels is not particularly limited, and the pixel arrangement may be one-dimensional or two-dimensional. There may be.

  FIG. 11 is a diagram showing waveforms of control signals output from the vertical scanning circuit 6 shown in FIG. FIG. 10 shows a selection signal ΦSEL input to the gate of the selection switch 6, a reset signal ΦRES input to the gate of the reset switch 3, a transfer gate signal ΦTX input to the gate of the transfer switch 2, and a transfer gate. The noise signal readout signal ΦTN and the transfer signal ΦTS input to the gates 15a and 15b are shown. The gate of each switch is turned on when the pulse wave of each signal is at a high level, and the gate of each switch is turned off when the pulse wave of each signal is at a low level.

Next, the operation of the solid-state imaging device shown in FIG. 10 will be described with reference to FIG. First, a low level signal is input from the vertical scanning circuit 6 to each gate of the selection switch 6 and the transfer switch 2, and a high level signal is input to the gate of the reset switch 3. At this time, incident light is photoelectrically converted by the photodiode 1 and the obtained charges are accumulated. Also, the floating diffusion region 11, and the reset potential _{V PR.}

  Subsequently, the transfer gate signal ΦTX is set to a high level, and the charge accumulated in the photodiode 1 is transferred to the floating diffusion region 11 via the transfer switch 2. When the transfer gate signal ΦTX is set to a low level, the photodiode 1 accumulates charges.

  Next, immediately after the selection signal ΦSEL is set to the high level and the reset Φ signal is switched to the low level, the noise signal readout signal ΦTN is set to the high level, and the noise in the solid-state imaging device is transferred to the vertical signal line 13 and the transfer gate 15b. Through the signal storage unit 16. Then, after the noise signal read signal ΦTN is switched to the low level, the selection signal ΦSEL is set to the low level and the transfer gate signal ΦTX is set to the high level. The transferred charge is transferred to the floating diffusion region 11 by the transfer gate signal ΦTX.

  When the transfer gate signal TX is set to the low level, the transfer of charges from the photodiode 1 to the floating diffusion region 11 is finished, and the photodiode 1 starts to accumulate charges again. Since the charge accumulated in the photodiode 1 before the transfer gate signal TX is set to the low level is transferred to the floating diffusion region 11, the photodiode 1 is depleted and almost reset. It becomes a state.

  Thereafter, when the selection signal ΦSEL is set to the high level and the transfer signal ΦTS is set to the high level immediately thereafter, the amplified signal amplified by the source follower 10 based on the charge transferred to the floating diffusion region 11 is transferred to the vertical signal line 13. The signal is input to the signal storage unit 16 through the gate 15a.

  The signal accumulation unit 16 outputs the input signal input through the transfer gate 15b and the input signal input through the transfer gate 15a after being timed so as to be differentiated by a differential circuit (not shown). To the output. In the output unit, the fixed pattern noise generated when the transfer switch 2 is switched on / off is removed by subtracting the two input signals.

  However, in the conventional technique, since the constant current source is connected to the vertical signal line 13, the potential of the vertical signal line approaches 0V while charges are accumulated in the photodiode. As a result, the potential of the vertical signal line becomes relatively low, and a minute leak current may flow from the vertical signal line toward the photodiode.

  At that time, charge flows into the photodiode from the vertical signal line. Therefore, when charges are transferred from the photodiode to the floating diffusion region, charges based on the leakage current are superimposed on the charges converted from the incident light, and the amplified signal amplified based on these charges is also a vertical signal. Read to line.

  As described above, in the read amplified signal, the charge generated by the potential difference between the photodiode and the vertical signal line may be further added to the charge actually obtained by photoelectric conversion. In some cases, an image obtained based on the amplified signal may deteriorate.

  Therefore, the present invention prevents the leakage current from flowing from the vertical signal line to the photoelectric conversion unit while accumulating charges in the photoelectric conversion unit such as a photodiode so that the read signal has less noise. The task is to do.

  In order to solve the above-described problems, the present invention provides a photoelectric conversion unit including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, and the first An image pickup apparatus having a plurality of pixels including a conductive semiconductor region and a transistor having a second conductive type source / drain region arranged to form a PN junction, wherein at least one of the source / drain regions Is connected to a constant current source, and while the electric charge is accumulated in the photoelectric conversion unit, the first semiconductor region and the constant current source of the second conductivity type source / drain region are connected. An imaging device is provided in which a reverse bias is applied to a PN junction constituted by the other.

  As described above, the image pickup apparatus of the present invention can reduce the leakage of leakage current to the photoelectric conversion unit while accumulating electrical signals generated by photoelectric conversion in the photoelectric conversion unit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an equivalent circuit diagram of the solid-state imaging device according to the first embodiment of the present invention. The solid-state imaging device shown in FIG. 1 transfers a photodiode 1 serving as a photoelectric conversion unit that converts an incident optical signal into an electric signal, and a signal charge from the photodiode 1 to a floating diffusion region 11 that is a storage region. A transfer switch 2, a source follower (amplification transistor 10, constant current source) and a constant voltage source 5 that amplify and output the transferred signal are provided.

The solid-state imaging device 1 includes a selection switch 6 charges accumulated selects photodiode 1 to be transferred, a reset switch 3 and the reset voltage source 4 for resetting the floating diffusion region 11 to a potential V _PR Transfer gates 15a and 15b for removing fixed pattern noise caused by switching on / off of the transfer switch 2, and a signal storage unit 16 for storing signals input when the transfer gates 15a and 15b are turned on It has.

  Here, the photodiode 1, the transfer switch 2, the reset switch 3, the selection switch 6, and the amplification transistor 10 constitute a pixel.

In the present embodiment, for example, when the accumulation of charges in the photodiode 1 is started by grounding the anode side of the photodiode 1 to the GND and connecting the cathode side to the transfer switch 2, The reverse bias photovoltage V _{REV is set} to about 1V.

FIG. 2 is a schematic cross-sectional view showing a connection state of each part of the solid-state imaging device shown in FIG. In FIG. 2, a is a photodiode 1, b is a gate of a transfer switch 2 that transfers charges from the photodiode 1, c is a floating diffusion region 11 that is a transfer destination of charges, d is a gate of a reset switch 3, and e is a reset. The power supply 4 and the constant voltage source 5, f is the gate of the selection switch 6, g is the source of the amplification transistor 10, h is the gate of the amplification transistor 10, and i is a diffusion region (output unit) connected to the vertical signal line 13. ing. Note that an n-type conductivity type (n ⁺ layer) photodiode a to diffusion region i are formed in a p-type well.

  FIG. 3 is a timing chart for operating the solid-state imaging device shown in FIG. In FIG. 3, the selection signal ΦSEL input to the gate of the selection switch 6, the reset signal ΦRES input to the gate of the reset switch 3, the transfer gate signal ΦTX input to the gate of the transfer switch 2, and each transfer A noise signal readout signal ΦTN and a transfer signal ΦTS input to the gates of the gates 15a and 15b are shown.

  In this embodiment, the gate of each switch is turned on when the pulse wave of each signal is at a high level, and the gate of each switch is turned off when the pulse wave of each signal is at a low level.

  Next, the operation of the solid-state imaging device shown in FIG. 1 will be described with reference to FIG. First, when the transfer gate signal ΦTX input to the gate of the transfer switch 2 is set to the low level while the reset signal ΦRES input to the gate of the reset switch 3 is set to the high level, the photodiode 1 Accumulation of electric charge obtained by photoelectric conversion is started.

At this time, by setting the selection signal ΦSEL applied to the gate of the selection switch 6 to the high level, the diffusion region (i in FIG. 2 ) becomes a predetermined potential, and the p-type well (p-substrat) and the diffusion region ( A reverse bias is applied during i) in FIG. Further, the potential on the vertical signal line 13 side is set higher than the potential of the photodiode 1. Thus, no leakage current flows from the vertical signal line 13 side to the photodiode 1.

  Next, after setting the reset signal ΦRES applied to the gate of the reset switch 3 to the low level, the noise signal readout signal ΦTN is set to the high level, and the fixed pattern noise signal generated by the amplification transistor 10 is converted into the vertical signal line 13, The signal is input to the signal storage unit 16 via the transfer gate 15b.

  Then, after the noise signal readout signal ΦTN is set to the low level and then the transfer gate signal ΦTX is set to the high level, the charge accumulation at the photodiode 1 is completed and the accumulated charge is transferred to the floating diffusion region 11. The

  Then, the transfer gate signal TX is set to a low level, and the transfer of charges from the photodiode 1 to the floating diffusion region 11 is completed.

  Further, since the selection signal ΦSEL is at a high level, an amplified signal obtained by being amplified by the source follower 10 based on the charge transferred to the floating diffusion region 11 is read out to the vertical signal line 13. Subsequently, when the transfer signal ΦTS is set to the high level, the signal read out to the vertical signal line 13 is input to the signal storage unit 16 through the transfer gate 15a.

  In the signal storage unit 16, the input signal input through the transfer gate 15b and the input signal input through the transfer gate 15a are output to the output unit at a timing such that the difference is made by a difference circuit (not shown). The In the output unit, the fixed pattern noise generated when the transfer switch 2 is switched on / off is removed by subtracting the two input signals. Then, the selection signal ΦSEL is set to the low level, and the reading operation is finished.

During the period in which charges are accumulated in the photodiode 1, the signals input to the gate of the selection switch 6 and the gate of the reset switch 3 are each at a high level, so that the potential of the reset power supply 4 is V _PR and the force follower 10 Assuming that V _GS is between the gate and the source, the voltage Vout on the vertical signal line 13 side is
Vout = V _PR −V _GS
It can be expressed as.

In this embodiment, when V _PR = 3.5 V and V _GS = 1.5 V, for example, a reverse bias of 2 V is provided between the diffusion region (i in FIG. 2) and the p-well (p-sublate in FIG. 2). A voltage is applied, and the relationship between the potential of the photoelectric conversion unit and the potential on the vertical signal line side is
V _REV <Vout
Are in a relationship.

  FIG. 8 is a diagram showing the potential with respect to signal charges in the photodiode a, p-type well and diffusion region i of FIG. FIG. 8 also shows the potential of the conventional diffusion region i for comparison. As described above, since the potential of the output part i is lower than the potential of the photodiode a while the charge is accumulated in the photodiode 1, the charge in the diffusion region i is photoelectrically transmitted through the p-type well. Since the current does not flow to the conversion part a side, no leakage current flows from the output part i to the photodiode a while charges are accumulated in the photodiode 1.

  That is, the potential of the diffusion region connected to the vertical signal line 13 is set higher than the potential of the cathode of the photodiode 1. As a result, it is possible to eliminate the flow of charge from the output section to the photodiode 1. Therefore, when the charge accumulated in the photodiode 1 is read out, the charge has less noise, so a high-quality image can be obtained.

  Here, in the above-described embodiment, the potential of the diffusion region i is set higher than the potential a of the photodiode. However, regardless of the relationship between the potential of the photodiode a and the potential of the diffusion region i, p It may be only by applying a reverse bias between the well (p-substrate) and the diffusion region i.

(Embodiment 2)
FIG. 4 is an equivalent circuit diagram of the solid-state imaging device according to the second embodiment of the present invention. As shown in FIG. 4, the solid-state imaging device of the present embodiment has a first switch 8 connected in series to the vertical signal line 13. In the present embodiment, by providing the first switch 8, when charge is accumulated in the photodiode 1, current is not flown between the source and drain of the source follower 10, thereby suppressing power consumption. ing. In FIG. 4, the same parts as those in FIG.

  FIG. 5 is a timing chart for operating the solid-state imaging device shown in FIG. FIG. 5 also shows a signal ΦIOFF input to the gate of the switch 8 in addition to the selection signal ΦSEL, the reset signal ΦRES, and the transfer gate signal ΦTX.

  In the present embodiment, the reset signal ΦRES is at a low level and the signal ΦIOFF is at a high level. Further, the charge accumulated in the photodiode 1 is transferred to the floating diffusion region 11 by setting the transfer gate signal ΦTX to the high level and the low level, and then the reset signal ΦRES is set to the high level and the signal ΦIOFF Is at a low level.

  That is, the switching of the high level / low level of the signal ΦIOFF is performed at the same timing as the low level / high level of the reset signal ΦRES. Thus, in the present embodiment, as described above, when charge is accumulated in the photodiode 1, current is not allowed to flow between the source and drain of the source follower 10 to reduce power consumption.

  In the first and second embodiments, while the photo diode 1 is accumulating the electrical signal generated by the photoelectric conversion, the driving for controlling the pulse to turn off the transfer switch and turn on the reset switch and the selection switch is performed. The circuit (108 in FIG. 9) corresponds to the potential control means.

  In the first and second embodiments, the selection switch 6 may be connected between the amplification transistor 10 and the vertical signal line 10.

(Embodiment 3)
FIG. 6 is an equivalent circuit diagram of the solid-state imaging device according to the third embodiment of the present invention. As shown in FIG. 6, the solid-state imaging device of the present embodiment has a second potential for setting the potential of the vertical signal line 13 to V _VR that is higher than the potential of the photodiode 1 that accumulates charges. A switch 9 and a constant voltage source V _VR 12 are provided. In the present embodiment, by providing the second switch 9 and the constant voltage source V _VR 12, the potential of the vertical signal line 13 is made higher than the potential of the photodiode 1 regardless of the selection switch 6 or the like. In FIG. 6, the same parts as those in FIG. 4 are denoted by the same reference numerals.

  FIG. 7 is a timing chart for operating the solid-state imaging device shown in FIG. FIG. 7 also shows a signal ΦVR input to the gate of the second switch 9 in addition to the selection signal ΦSEL, the reset signal ΦRES transfer gate signal ΦTX, and the signal ΦIOFF.

  The operation of the solid-state imaging device shown in FIG. 6 will be described with reference to FIG. First, when the transfer gate signal ΦTX input to the gate of the transfer switch 2 is set to the low level while the reset signal ΦRES input to the gate of the reset switch 3 is set to the high level, the photodiode 1 Accumulation of electric charge obtained by photoelectric conversion is started.

  At this time, both the selection signals ΦSEL applied to the gates of the selection switches 6 are set to the high level so that the potential on the vertical signal line 13 side is higher than the potential of the photodiode 1. Thus, no leakage current flows from the vertical signal line 13 side to the photodiode 1.

  As in the second embodiment, the signal ΦIOFF switches between the high level and the low level at the same timing as the low level / high level of the reset signal ΦRES. Further, the signal ΦVR switches between the high level and the low level at the same timing as the high level / low level of the reset signal ΦRES.

  Next, after the reset signal ΦRES applied to the gate of the reset switch 3 is set to a low level, that is, the signal ΦIOFF is set to a high level and the signal ΦVR is set to a low level, the selection signal ΦSEL is switched to a high level. Then, the noise read signal ΦTN is set to the high level, and the fixed pattern noise generated by the switching of the high level and the low level of the transfer switch 2 is input to the signal storage unit 16 via the vertical signal line 13 and the transfer gate 15b.

  After that, when the noise read signal ΦTN is set to the low level and then the transfer gate signal ΦTX is set to the high level, the charge accumulation in the photodiode 1 is completed and the accumulated charge is transferred to the floating diffusion region 11.

  Then, the transfer gate signal TX is set to the low level, the transfer of charges from the photodiode 1 to the floating diffusion region 11 is terminated, and charges are accumulated in the photodiode 1 again. The charge accumulated in the photodiode 1 until the transfer gate signal TX is set to the low level is transferred to the floating diffusion region 11 to be depleted and almost reset. Become.

  Further, since the selection signal ΦSEL is at a high level, an amplified signal obtained by being amplified by the source follower 10 based on the charge transferred to the floating diffusion region 11 is read out to the vertical signal line 13. Subsequently, when the transfer signal ΦTS is set to the high level, the signal read out to the vertical signal line 13 is input to the signal storage unit 16 through the transfer gate 15a.

  The signal accumulation unit 16 outputs the input signal input through the transfer gate 15b and the input signal input through the transfer gate 15a after being timed so as to be differentiated by a differential circuit (not shown). To the output. In the output unit, the fixed pattern noise generated when the transfer switch 2 is switched on / off is removed by subtracting the two input signals. Then, the selection signal ΦSEL is set to the low level, and the reading operation is finished.

In the present embodiment, since the signal ΦVR is at a high level when charges are accumulated in the photodiode 1, the vertical signal line 13 can be set to a higher potential than the photodiode 1 by the constant voltage source V _VR 12. it can. Therefore, it is possible to prevent leakage current from flowing from the vertical signal line 13 side to the photodiode 1 without setting the selection signal ΦSEL to the high level as in the first embodiment. When the charge is read, the charge has less noise and a high-quality image can be obtained.

  Here, in the third embodiment, as in the first and second embodiments, only a reverse bias is applied between the p-well j and the diffusion region i regardless of the potential a of the photodiode and the potential of the diffusion region i. It may be.

  In the third embodiment, the second switch 9, the constant current source 12, and the photodiode 1 are turned on while the electrical signal generated by the photoelectric conversion is accumulated. A drive circuit (108 in FIG. 9) that controls to output a pulse corresponds to the potential control means.

  In the third embodiment, the photodiode 1, the transfer switch 2, the reset switch 3, the selection switch 6, and the amplification transistor 10 constitute one pixel. For example, the photodiode 1 and the transfer switch 2 are used as one pixel. Other pixel configurations such as configuring pixels may be used.

(Embodiment 4)
Based on FIG. 9, the imaging system using the solid-state imaging device described in the first to third embodiments described above will be described.

  In the figure, 101 is a barrier that serves as a lens switch and a main switch, 102 is a lens that forms an optical image of a subject on the solid-state image sensor 104, 103 is a stop for changing the amount of light passing through the lens 102, and 104 is a lens. A solid-state image sensor for capturing the subject imaged in 102 as an image signal, 105 is a gain variable amplifier for amplifying an image signal output from the solid-state image sensor 104, and a gain correction circuit for correcting the gain value The image signal processing circuit 106 includes an A / D converter 106 that performs analog-to-digital conversion of an image signal output from the solid-state image sensor 104, and 107 performs various types of image data output from the A / D converter 106. A signal processing unit 108 that performs correction and compresses data, a solid-state imaging device 104, an imaging signal processing circuit 105, and A / A drive circuit that outputs various timing signals to the converter 106 and the signal processing unit 107, 109 is an overall control / arithmetic unit that controls various calculations and the entire imaging apparatus, and 110 is a memory unit for temporarily storing image data , 111 is an interface unit for recording or reading on a recording medium, 112 is a removable recording medium such as a semiconductor memory for recording or reading image data, and 113 is an interface unit for communicating with an external computer or the like It is.

  Next, the operation of the image pickup apparatus at the time of shooting in the above configuration will be described.

  When the barrier 101 is opened, the main power supply is turned on, the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 106 is turned on. Then, in order to control the exposure amount, the overall control / arithmetic unit 109 opens the aperture 103, and the signal output from the solid-state image sensor 104 is converted by the A / D converter 106 and then sent to the signal processing unit 107. Entered.

  Based on this data, exposure calculation is performed by the overall control / calculation unit 109.

  The brightness is determined based on the result of the photometry, and the overall control / calculation unit 9 controls the aperture according to the result.

  Next, based on the signal output from the solid-state image sensor 104, the high-frequency component is extracted and the distance to the subject is calculated by the overall control / calculation unit 109. Thereafter, the lens is driven to determine whether or not it is in focus. When it is determined that the lens is not in focus, the lens is driven again to perform distance measurement.

  Then, after the in-focus state is confirmed, the main exposure starts.

  When the exposure is completed, the image signal output from the solid-state image sensor 104 is A / D converted by the A / D converter 106, passes through the signal processing unit 7, and is written in the memory unit by the overall control / calculation unit 109.

  Thereafter, the data stored in the memory unit 110 is recorded on a removable recording medium 112 such as a semiconductor memory through the recording medium control I / F unit under the control of the overall control / arithmetic unit 109. Further, the image may be processed by directly inputting to a computer or the like through the external I / F unit 113.

It is an equivalent circuit schematic of the solid-state image sensor of Embodiment 1 of the present invention. It is a schematic cross section which shows the connection state of each part of the solid-state image sensor shown in FIG. It is a timing chart which shows the operation | movement of FIG. It is the equivalent circuit schematic of the solid-state image sensor of Embodiment 2 of this invention. 6 is a timing chart showing the operation of FIG. It is an equivalent circuit schematic of the solid-state image sensor of Embodiment 3 of the present invention. 7 is a timing chart showing the operation of FIG. 6. It is the figure which showed the potential with respect to the signal charge in the photodiode of FIG. It is a figure showing the imaging device using the solid-state image sensor of Embodiment 1-3. It is an equivalent circuit schematic of the solid-state image sensor of a prior art. It is a timing chart which shows the operation | movement of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Photodiode 2 Transfer switch 3 Reset switch 4 Reset voltage source 5 Constant voltage source 6 Selection switch 7 Constant current source 8 1st switch 9 2nd switch 10 Source follower 11 Floating diffusion area 12 Constant voltage source _VVR

Claims (4)

A photoelectric conversion unit configured to include a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type;
An imaging apparatus having a plurality of pixels including a transistor having a second conductivity type source / drain region arranged to form a PN junction with the first conductivity type semiconductor region,
At least one of the source / drain regions is connected to a constant current source, and while the electric charge is accumulated in the photoelectric conversion unit, the first semiconductor region and the source / drain region of the second conductivity type An imaging apparatus, wherein a reverse bias is applied to a PN junction formed by one of the constant current sources connected to the PN junction.   The imaging device according to claim 1, wherein the transistor is an amplification transistor that amplifies a signal charge from the photoelectric conversion unit.   The imaging device according to claim 1, wherein the transistor is a selection transistor for selecting a specific pixel from the plurality of pixels. The imaging device according to any one of claims 1 to 3,
A lens for imaging light on the pixel;
An analog / digital conversion circuit for converting a signal from the pixel into a digital signal;
A signal processing circuit for performing signal processing of a signal from the analog-digital conversion circuit;
An imaging system comprising:

Images