JP3474700B2 - Solid-state imaging device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a solid-state image pickup device using an amplification type MOS sensor.

[0002]

2. Description of the Related Art In recent years, a solid-state image pickup device using an amplification type MOS sensor has been proposed as one of solid-state image pickup devices. This solid-state imaging device amplifies the signal detected by the photodiode for each cell with a transistor,
It has the characteristic of high sensitivity.

FIG. 20 is a circuit diagram showing a conventional example of this type of solid-state image pickup device. Photodiode 1-1-
Amplification transistors 2-1-1, 2-1-2, ..., 2-2- for amplifying signals of 1, 1-1-2, ..., 1-2-2
2, vertical selection transistors 3-1-1, 3-1-2, ..., 3-2-2 for selecting a line for reading a signal, reset transistors 4-1-1, 4 for resetting a signal charge
About 2 × 2 unit cells each including -1-2, ..., 4-2-2 are two-dimensionally arranged. Actually, more unit cells are arranged.

The horizontal address lines 6-1 and 6-2 wired in the horizontal direction from the vertical shift register 5 are connected to the gates of the vertical selection transistors to determine the lines from which signals are read. The reset lines 7-1 and 7-2 are connected to the gate of the reset transistor. The source of the amplification transistor is connected to the vertical signal lines 8-1 and 8-2, and the load transistors 9-1 and 9-2 are provided at one end thereof. The other ends of the vertical signal lines 8-1 and 8-2 are 1
1 line (1 row) via the signal capturing transistors 10-1 and 10-2 that captures signals for 1 line (1 row)
Minute signal storage capacitors 11-1 and 11- for storing minute signals
2 as shown in the drawing, and is connected to the horizontal signal line 50 via the horizontal selection transistors 12-1 and 12-2 selected by the selection pulse supplied from the horizontal shift register 13.

FIG. 21 is a timing diagram of pulse signals for driving this device. When the address pulse 101 which makes the horizontal address line 6-1 high level is applied, only the selection transistors 3-1-1 and 3-1-2 of this line are turned on, and the amplification transistors 2-1-1 and 2-1-1 of this row −
A source follower circuit is composed of 1-2 and the load transistors 9-1 and 9-2, and the gate voltage of the amplification transistor,
That is, a voltage substantially equal to the voltage of the photodiode appears on the vertical signal lines 8-1 and 8-2. At this time, the signal capture pulse 103 is applied to the common gate 49 of the signal capture transistors 10-1 and 10-2, and the amplified signal storage capacitor 1
The amplified signal charges of the product of the voltage appearing on the vertical signal line and its capacitance are stored in 1-1 and 11-2.

After the signals are stored in the amplified signal storage capacitors 11-1 and 11-2, the reset transistors 4-1-1 and
Applying the signal reset pulse 102-1 to 4-1-2,
The signal charges accumulated in the photodiodes 1-1-1, 1-1-2 are reset.

Next, horizontal selection pulses 104-1 and 104-2 are sequentially applied from the horizontal shift register 13 to the horizontal selection transistors 12-1 and 12-2, and the output signal 105- for one row is output from the horizontal signal line 50. 1, 105-2 are sequentially taken out.

By continuing this operation sequentially for the next line and the next line, all two-dimensional signals can be read.

However, this type of solid-state image pickup device has the following problems. One is 9 in FIG.
This means that the current is constantly flowing through the source follower circuit using -1, 9-2 as load transistors, resulting in high power consumption. Considering application to a television camera, since the number of cells in the horizontal direction is at least 600 or more, even if the current flowing through one cell is small, the total current becomes very large. Since the response in the source follower is determined by the current amount of the constant current source, it is necessary to increase the current in order to speed up the response, which increases power consumption.

The current of the source follower is the vertical signal line 8-
1, 8-2 capacity and amplified signal storage capacity 10-1, 10-
It is used to drive 2 but a normal sensor requires a current of at least 50 microamps to fully drive the vertical signal line and the amplified signal storage capacitance of about 1 pF. Therefore, a total current of at least 30 milliamperes is required, and if the power supply voltage is 3.3V, at least 100 milliwatts of power will be consumed. In the future, considering the application of a video camera, since it is desired to reduce the total sensor to 100 milliwatts or less, the power consumption of 100 milliwatts only with the imaging device is not an acceptable value.

The other is that the source follower operation causes a voltage drop in the load transistor / amplification transistor, which narrows the range in which a signal can be handled. When a current of 100 microamperes is passed, the source-gate channel voltage is about 0.
6V and a gate-channel / drain voltage of about 0.6V are required. Since these voltages are required for the load transistor and the amplification transistor respectively, 3.3-2 ×
There is only an operating range of (0.6 + 0.6) = 0.9V. This state is shown in FIG. 22 using a potential diagram. Manufacturing variation of threshold voltage of each transistor is ± 0.2V
Then, the operable range becomes only 0.1V.

If there is a manufacturing variation of the threshold voltage of ± 0.2V with respect to the source-gate channel voltage of 0.6V of the load transistor, the current of the source follower circuit becomes 4V.
It cannot be used as a product design because it fluctuates about twice. In order to suppress this variation, in practice, the gate width / gate length ratio (W / L ratio) of the load transistor is made small (0.5 or less, 0.2 or less) to reduce the influence of this variation. This further increases the source-gate channel voltage of the load transistor and reduces the operating range.

[0013]

As described above, conventionally, in the amplification type solid-state imaging device, there has been a problem that the power consumption becomes large when the response of the source follower is fast.

Further, since current always flows through the source follower circuit formed by the amplification transistor and the load transistor of the unit cell, power consumption is large. Further, when the source follower operation is performed, there is a voltage drop between the load transistor and the amplification transistor, which causes a problem that the operating range is narrowed.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a solid-state image pickup device capable of quick response of a source follower without increasing power consumption. is there.

Another object of the present invention is an amplification type MOS.
An object of the present invention is to provide a solid-state imaging device that can reduce the power consumption and expand the operating range in a configuration using a sensor.

[0017]

[Means for Solving the Problems]

(Structure) In order to solve the above problems, the present invention employs the following structures.

That is, according to the present invention (claim 1), a photodiode for photoelectric conversion on a semiconductor substrate, an amplification transistor for inputting the output of the photodiode to a gate,
An image pickup region formed by arranging unit cells including reset transistors for resetting the photodiodes in a two-dimensional matrix, a vertical selection unit for selecting a read row of the image pickup region, and a column direction for reading the output of the amplification transistor are arranged. Load transistors provided at the ends of multiple vertical signal lines
When amplified signal accumulation signals vertical signal lines provided for each column
In a solid-state image pickup device comprising a signal acquisition transistor for reading out to a capacitance and forming a source follower or emitter follower amplifier by coupling a load transistor and an amplification transistor, signal reading by the vertical selection means
It is characterized in that a potential control transistor for temporarily controlling the potential of the vertical signal line to be lowered within the period is provided.

According to the present invention (claim 4), a photodiode for photoelectric conversion on a semiconductor substrate, an amplification transistor for inputting the output of the photodiode to a gate,
An image pickup region formed by arranging unit cells including reset transistors for resetting the photodiodes in a two-dimensional matrix, a vertical selection unit for selecting a read row of the image pickup region, and a column direction for reading the output of the amplification transistor are arranged. Load transistors provided at the ends of multiple vertical signal lines
When amplified signal accumulation signals vertical signal lines provided for each column
And a signal acquisition transistor for reading out the capacity, in the solid-state imaging device which constitutes a source follower or an emitter follower amplifier by combining the amplification transistor and the load transistor, in the signal readout period by the vertical selection means, a gate of said load transistor To the tran
It is characterized in that a second voltage lower than the first voltage is applied after the first voltage for completely turning on the transistor is applied.

The present invention (claim 5) provides a semiconductor substrate.
The photodiode for photoelectric conversion, this photodiode
Amplifying transistor that inputs the output of iodine to the gate,
Reset transistor that resets the photodiode
Image area formed by arranging unit cells containing
And a vertical selection means for selecting the readout row of this imaging region
And arranged in the column direction to read the output of the amplification transistor.
Load transistors provided at the ends of multiple vertical signal lines
And the signal of the vertical signal line is stored in each column
It is equipped with a signal acquisition transistor for reading the capacitance and
Load transistor and amplification transistor are combined and source
Solids that make up a follower or emitter follower amplifier
In the image pickup device, an electric signal that controls the potential of the vertical signal line is used.
Position control transistor is provided, and the signal by the vertical selection means is provided.
Signal reading period, the potential control transistor gate
The first voltage between the ground potential Vss and the power supply potential Vdd.
After applying the voltage, a second voltage is applied to the gate of the load transistor.
A second voltage between the voltage of 1 and the ground potential Vss is applied.
Characterized in that that.

Further, the present invention (claim 6 ) provides a photodiode for photoelectric conversion on a semiconductor substrate, and the photodiode.
Amplifying transistor that inputs the output of iodine to the gate,
Reset transistor that resets the photodiode
Image area formed by arranging unit cells containing
And a vertical selection means for selecting the readout row of this imaging region
And arranged in the column direction to read the output of the amplification transistor.
Load transistors provided at the ends of multiple vertical signal lines
And the signal of the vertical signal line is stored in each column
It is equipped with a signal acquisition transistor for reading the capacitance and
Load transistor and amplification transistor are combined and source
Solids that make up a follower or emitter follower amplifier
In the image pickup device, signal reading by the vertical selection means
The ground potential is applied to the gate of the load transistor within
By applying an intermediate voltage between Vss and the power supply potential Vdd,
Except during the signal readout period, the gate voltage of the load transistor is
The pressure is set to be lower than the intermediate voltage .

(Operation) According to the present invention, the voltage control transistor controls the operating point of the amplification transistor (lowers the potential of the signal line connected to the source).
The response of the amplification transistor can be increased. In this case, the potential of the signal line is lowered only during the reading period by the vertical selection means, so that the increase in current consumption is small. Therefore, the power consumption can be reduced as compared with the conventional one while realizing the quick response of the source follower.

The above-mentioned problem is that a relatively large current for driving the vertical signal line flows through the source follower circuit which is composed of the load transistor and the amplification transistor.

There are two ways to solve this problem. One is a method in which a current is passed through the load transistor when the signal of the photodiode is taken out to the vertical signal line, and a current is not passed or a small current is passed when the signal is not taken out to the vertical signal line. Although this method solves the problem of power consumption, it does not solve the problem of signal handling range.

To solve the two problems of power consumption and signal handling range at the same time, the following measures should be taken.

The problem is solved by making the load transistor a vertical signal line reset transistor capable of injecting charges into the vertical signal line and resetting its potential. The gate width / gate length ratio (W / L ratio) of the load transistor used in the amplification type image pickup device is generally set to be small in order to stabilize a small current flowing. As described above, at about 50 microamperes, W / L = 0.2 or less is designed in consideration of manufacturing variations as described above.

On the other hand, since the vertical signal line reset transistor wants to reset the vertical signal line capacitance of about 1 pF to the source voltage as fast as possible (preferably within 50 nanoseconds or less), W
If the / L ratio can be 1 or more, design with 3 or more. In order to reduce the variation in the threshold voltage of the load transistor, W
The design is the reverse of reducing the / L ratio.

The high level voltage of the pulse is applied to the gate of the vertical signal line reset transistor during the period in which the amplification transistor corresponding to the vertical selection line is activated during the period for reading the signal of the cell corresponding to one vertical selection line. Are driven in a divided manner into a vertical signal line drive period when a low voltage is applied and a signal voltage detection period when a low level is applied. Basically, a signal is taken out when a low level is applied to the vertical signal line reset transistor, that is, when almost no current flows in the amplification transistor, so that two problems of power consumption and signal handling range can be solved.

[0029]

DETAILED DESCRIPTION OF THE INVENTION The details of the present invention will be described below with reference to the illustrated embodiments.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a circuit configuration diagram showing a solid-state imaging device according to the embodiment. Photodiode 1 (1-1-1, 1-1-2,
~, 1-3-3) amplifying transistor 2 (2-1-1, 1-2-2, ~, 2-3-3) for amplifying the detection signal, and vertical selection transistor 3 for selecting a line for reading the signal.
(3-1-1, 3-1-2, ..., 3-3-3), reset transistor 4 for resetting signal charges (4-1-
1, 4-1-2, ..., 4-3-3) are arranged in a two-dimensional matrix. Although 3 × 3 cells are arranged in the figure, more unit cells are actually arranged.

Horizontal address lines 6 (6-1, 6-2, 6-) are wired in the horizontal direction from the vertical shift register 5.
3) is connected to the gate of the vertical selection transistor 3 and determines a line for reading a signal. Similarly, the reset line 7 wired in the horizontal direction from the vertical shift register 5
(7-1, 7-2, 7-3) is connected to the gate of the reset transistor 4. The source of the amplification transistor 2 is a vertical signal line 8 (8-1, 8-) arranged in the column direction.
2, 8-3), and a load transistor 14 (14-1, 14-2, 14-3) is provided at one end thereof.

At the other end of the vertical signal line 8, a sample hold transistor 10 (10-1, 10-2, 10-) is provided.
3), sample and hold capacitors 11 (11-1, 11-
2, 11-3) is connected to the noise elimination circuit. Then, this noise elimination circuit includes horizontal selection transistors 12 (12-1, 12-2, 12-3) driven by the selection pulse supplied from the horizontal shift register 14.
It is connected to the horizontal signal line 50 via.

The structure up to this point is the same as the conventional one, but in this embodiment, a potential control transistor is additionally provided. That is, in the vertical signal line connected to the source of the amplification transistor 2, along with the load transistor 14 of the constant current source that constitutes the amplification transistor 2 and the source follower amplifier, the potential control transistor 40 (40-1, 40-1 that controls the potential of this signal line). 40-2, 40-3) are connected. Here, a high level voltage is applied to the gate of the potential control transistor 40, and an intermediate level voltage is applied to the load transistor 14.

FIG. 2 shows a potential diagram of the source follower.
As can be seen from FIG. 2A, when the start state of the potential of the vertical signal line connected to the source of the amplification transistor 2 is higher than the end state, the response of the source follower amplifier is such that electrons flow from the load transistor 14 and the potential of the signal line. It will be the time until it is lowered to the final state. Therefore, the response time depends on the current amount of the load transistor 14. However, when the starting state of the potential of the signal line is lower than the ending state as shown in FIG. 2B, the electrons accumulated in the signal line flow through the amplification transistor 2. This transient current is greater than the current provided by the load transistor 14, so
The response of the amplifier can be made faster than in (a).

In the case of (a), it is necessary to increase the current of the load transistor 14 which constantly flows in order to speed up the response. Therefore, power consumption naturally increases. However, in the case of (b), the current caused by the electrons flowing from the signal line to the amplification transistor 2 in the initial stage is an excessive current until the potential of the signal line is settled to the final state, so the power consumption by the excessive current is small. Therefore, in (b), a faster response of the amplifier can be obtained with lower power consumption than in (a).

From the above, the potential of the signal line is controlled by the means for controlling the potential of the vertical signal line to drive the source follower amplifier in the potential relationship as shown in FIG. Is obtained.

In order to obtain a fast response of the amplifier as described above, it is desirable that the W / L ratio of the potential control transistor is set larger than the W / L ratio of the amplification transistor. The reason is that the time required to turn on the potential control transistor and set the potential of the signal line to the start state is shorter than the time required for the signal line to change from the start state to the end state by the current flowing through the amplification transistor. This is because it is necessary to make the response of the amplifier depend on the time from the start state to the end state of the signal line. Further, when the vertical signal line is set to the starting state, the potential control transistor is turned on and the potential of the signal line is reset to the source potential of the potential control transistor. As described above, in order to control the potential of the signal line, it is necessary for the potential control transistor to flow a current more easily than for the amplification transistor. Therefore, the W / L ratio of the potential control transistor is set to be higher than that of the amplification transistor. Also needs to be larger.

FIG. 3 is a timing chart showing a driving method at the time of reading a signal in this embodiment. As shown in FIG. 3A, after the potential control transistor 40 is turned on in the signal read period in which the vertical selection transistor 3 is turned on, the load transistor 14 is turned on and the potential control transistor 40 is turned off in the signal read period. To do. Also,
As shown in FIG. 3B, the load transistor 14 is always turned on during the signal reading period, and the potential control transistor 40 is turned on and then turned off.

By such driving, the signal can be read with the potential distribution shown in FIG. 2B, and low power consumption and fast response can be realized.

The fast response of the source follower amplifier is obtained by temporally controlling the potentials of the source and gate of the load transistor 14. That is, FIG.
As shown in (c), the source potential of the load transistor 14 is set to a potential lower than that in the final state of the signal line. In that state, the gate is made sufficiently high to completely turn on the load transistor 14. Then, the potential of the signal line becomes substantially equal to the source of the load transistor 14. After that, the potential of the gate is lowered so that a desired current can be obtained. As a result, the amplifier operates in the potential relationship shown in FIG. 2B, so that the response becomes faster. In this case, the potential control transistor 40 can be omitted.

In the embodiment, the source follower is composed of the amplifying transistor and the load transistor using the MOS transistor, but the emitter follower may be composed of the bipolar transistor.

(Second Embodiment) A second embodiment of the present invention will be described. When a current is passed through the load transistor when the signal of the photodiode is taken out to the vertical signal line, and a current is not passed or a small current is taken when the signal is not taken out, as shown in FIG.
The gate electrodes 51 of 1 and 14-2 are independently taken out, and are driven according to the timing chart shown in FIG. During the period 201 in which the signal of the photodiode is taken out from the vertical signal line to the amplified signal storage capacitor, the load transistor 14-
The load transistor activation pulse 106 is applied to the common gate electrodes 51 of 1 and 14-2, and a current is passed through the load transistors. In the other period 202, the gate voltage of the load transistor is reduced and the current thereof is reduced.

By doing so, the power consumption can be reduced. However, this method solves the problem of power consumption,
The problem of signal coverage cannot be solved.

FIG. 6 shows an embodiment in which the two problems of power consumption and signal handling range are solved. Vertical signal line reset transistors 15-1 and 15-2 different in W / L from the conventional load transistor are connected to the vertical signal line.
The reason why the vertical signal line reset transistor is provided on the horizontal signal line 50 side of the vertical signal line is that there is an advantage that the vertical signal line is reliably reset when the resistance of the vertical signal line is high. There is also a method of providing vertical signal line reset transistors above and below the vertical signal line in order to further quickly reset the vertical signal line having high resistance. The load transistor of the source follower circuit has no advantage provided at the upper and lower ends.

FIG. 7 shows an operation timing chart in the apparatus of FIG.

Vertical signal line reset transistor 15-
Charge injection pulse 1 to common gate electrode 52 of 1, 15-2
07 is applied. At this time, the vertical signal lines 8-1, 8-2
Electric charges are injected from the common source 53 of the vertical signal line reset transistor to the preset signal and are almost preset to the source potential. When the charge injection pulse is turned off, a part of the injected charge is discharged through the amplification transistor of the addressed row, the potential of the vertical signal line changes, and the potential of the vertical signal line almost matches the gate potential of the amplification transistor. .

This state is shown in FIG. 8 (b). That is, the signal of the gate voltage of the amplification transistor, which receives the signal voltage of the photodiode, is transmitted to the vertical signal line. The phase relationship between the charge injection pulse 107 and the signal acquisition pulse 103 is important for accurately transmitting a voltage equivalent to this voltage to the amplified signal storage capacitor. Charge injection pulse 107
Since the voltage corresponding to the signal charge appears on the vertical signal line after the power is turned off, finally the amplified signal storage capacitors 11-1 and 11
The trailing edge of the signal acquisition pulse 103 that determines the −2 potential is later than the trailing edge of the charge injection pulse 107 in time.

This is completely different from the load transistor pulse driving described with reference to FIGS. In the case of load transistor pulse driving, when the load transistor activation pulse is ON, the source follower circuit that constitutes the amplification transistor operates, so at this time, the signal is on the vertical signal line,
This is because it is necessary to turn off the signal capture pulse 103 while the load transistor activation pulse is on.

Regarding the leading edge of the signal capture pulse 103, the signal capture pulse is turned off and the potential of the vertical signal line becomes almost equal to the gate potential of the amplification transistor, that is, after the amplification transistor is in the weak inversion state. When the pulse is applied, the charge accumulated in the vertical signal line is divided by the ratio of the capacitance of the vertical signal line and the capacitance of the amplified signal storage capacitor, so that the voltage of the amplified signal storage capacitor becomes smaller than the signal voltage that should originally appear. Therefore, the leading edge of the signal acquisition pulse 103 must precede the trailing edge of the charge injection pulse 107 in time.

More specifically, the period A in FIG. 8A immediately after the charge injection pulse 107 is turned off is shown in FIG.
As indicated by A in (b), since the current in the strong inversion region still flows in the amplification transistor and has the capacity drive capacity, even if there is the leading edge 108 of the signal acquisition pulse 103 in this period, the amplification signal The original signal can be stored in the storage capacitor.

In this operation, it is easy to understand that the power consumption is small because the period for supplying the current to the vertical signal line reset transistor is short.

The fact that the signal handling range is widened by the vertical signal line resetting operation will be described with reference to the drawings. 9 (a) to 9 (c) are potential diagrams of a circuit composed of a cell amplification transistor and a vertical signal line reset transistor.

When the charge injection pulse is applied, as shown in FIG.
As shown in (a), the potential of the vertical signal line becomes almost the source potential of the vertical signal line reset transistor. In order to quickly reach this state, the vertical signal line reset transistor has a large W / L ratio as described above. Immediately after the charge injection pulse is turned off, a part of the charges injected into the vertical signal line flows into the amplification transistor as shown in FIG. 9B, and then the vertical signal line as shown in FIG. 9C. Becomes almost the same as the potential of the gate of the amplification transistor.

The state of FIG. 9C is a potential diagram when the signal is actually taken into the amplified signal storage capacitor. As can be seen from this figure, almost no current flows in the amplification transistor or the vertical signal line reset transistor.
It can be seen that there is no voltage drop there and the signal handling range is 2.7 V, which is very wide when the power supply voltage is 3.3 V.

W / L of vertical signal line reset transistor
It is desirable that the ratio be larger than the W / L ratio of the amplification transistor. The reason is that in order to reset the vertical signal line to the source potential of the vertical signal line reset transistor, it is necessary to make it easier for the reset transistor to pass the current than the amplification transistor. Further, it is necessary to shorten the time required from the reset of the potential of the vertical signal line to the potential of the gate of the amplification transistor. Therefore, the W / L ratio of the reset transistor is made larger than the W / L ratio of the amplification transistor. There is a need.

(Third Embodiment) In the amplification type solid-state image pickup device described above, since variations in the threshold voltage of the amplification transistors 2-1-1 to 2-2-2 are superimposed on the signal, the image pickup is performed. to become spatially fixed fixed pattern noise when playing images, providing a noise canceller for suppressing the noise portion of the amplified signal storage capacitance and the signal input transistor of FIG. As the noise canceller, a correlated double sampling type that takes the difference between the signal and noise in the voltage domain and a slice type that takes the difference in the charge domain will be taken up here, but the noise canceller is not limited to this type.

FIG. 10 is a circuit diagram using a correlated double sampling type and a vertical signal line reset transistor, and FIG. 14 is a circuit diagram using a slice type and a vertical signal line reset transistor.

The configuration and principle of the noise canceller will be briefly described. In the correlated double sampling type, as shown in FIG. 10, the vertical signal lines 8-1, 8-2 are connected to the clamp capacitors 16-1,
16-2, clamp transistors 17-1, 17-2,
Sample hold transistors 18-1 and 18-2 and hold capacitors 19-1 and 19-2 are provided.

FIG. 11 is an operation timing chart of the sensor of FIG. When the address pulse 101 is applied from the horizontal address line 6-1, the vertical selection transistor 3-1-
1, 3-1-2 turn on, amplification transistor 2-1
1, 1-2-2 is activated. Here, the charge injection pulse 107 is applied to the common gate 52 of the vertical signal line reset transistor to inject charges into the vertical signal line and then turned off.

Part of the injected charge is discharged through the gate channel of the activated amplification transistor, and the vertical signal line 8
A signal voltage corresponding to the voltage of the photodiode appears at -1 and 8-2. At this time, the clamp pulse 109 is applied to the common gate 55 of the clamp transistor to turn on the clamp transistors 17-1 and 17-2, and the voltage on the clamp transistor side of the clamp capacitors 16-1 and 16-2 is applied to the common source of the clamp transistor. It is fixed to the voltage of 54 and then turned off.

Next, the signal reset pulse 102-1 is applied from the reset line 7-1 to the reset transistors 4-1-1 and 4-1-1.
It is applied to 4-1-2 to discharge the signal charge of the photodiode, and the noise detection charge injection pulse 124 is applied to the common gate 52 of the vertical signal line reset transistor to inject charges into the vertical signal line and then turn off. . Then, a noise voltage appears on the vertical signal lines 8-1 and 8-2 due to the threshold variation of the amplification transistor.

At this time, the clamp capacitors 16-1, 16-
The voltage on the clamp transistor side of No. 2 is the common source 54 of the clamp transistor, which is the noise-free signal voltage obtained by subtracting the noise voltage from the voltage change of the vertical signal line.
It appears superimposed on the voltage of. The common source voltage also has no noise.

A sample-hold pulse 110 is applied to the common gate 56 of the sample-hold transistor, and this noise-free signal voltage is applied to the sample-hold transistor 1.
8-1, 18-2 via the hold capacitors 19-1, 19
-Tell it to 2.

Then, the horizontal selection transistor 12-
Signals without noise are read out sequentially through 1 and 12-2.

The trailing edges of the clamp pulse 109 and the sample hold pulse 110, which are important pulses in this type of noise canceller, are in the period after the charge injection pulse 107 and the noise detection charge injection pulse 124 are turned off. The reason is as described above in the description of FIG.

The leading edge of the clamp pulse 109 is the same as that described in FIG.
Either before the trailing edge or immediately after the trailing edge, the amplifying transistors of the addressed row are in the strong inversion state. The same is required for the leading edge of the sample-hold pulse 110 and the trailing edge of the noise detection charge injection pulse 124.

FIG. 12 is an improved version of FIG. 11, in which the address pulse is divided into two parts according to the detection of signal and noise. FIG. 13 shows a dummy address pulse 115-1 (115-
2), a dummy charge injection pulse 125 and a dummy clamp pulse 117 are added. As described above, these methods ensure that the cell states at the two trailing edge times of the important clamp pulse 109 and sample hold pulse 110 that determine the noise and signal capture are in the same conditions as much as possible.

On the other hand, the structure and principle of another noise canceller, a slice type noise canceller, will be briefly described. As shown in FIG. 14, the vertical signal lines 8-1,
The gates of the slice transistors 20-1 and 20-2 are connected to 8-2. Slice capacitors 21-1 and 21-2 and slice source reset transistors 22-1 and 22-2 are connected to the sources of the slice transistors. The drain has slice charge storage capacitors 24-1 and 24-2.
4-2 and slice drain reset transistor 23-
1, 23-2 are connected.

FIG. 15 is an operation timing chart of the sensor of FIG. When the address pulse 101 is applied from the horizontal address line 6-1, the vertical selection transistor 3-1-
1, 3-1-2 turn on, amplification transistor 2-1
1, 1-2-2 is activated. Charge injection pulse 1 here
07 is a common gate 5 of the vertical signal line reset transistor
2 is applied to inject charges into the vertical signal line and then turned off.

Part of the injected charge is discharged through the gate channel of the activated amplification transistor, and the vertical signal line 8
A signal voltage corresponding to the voltage of the photodiode appears at -1 and 8-2. At this time, the slice source reset pulse 118 is applied to the common gate 58 of the slice source reset transistors 22-1 and 22-2, and the common terminal 57 of the slice capacitors 21-1 and 21-2 in which sufficient charges have been injected in advance. Then, the first slice pulse 119 is applied, and excess charge is discharged to the drain of the slice transistor through the gate channels of the slice transistors 20-1 and 20-2. The extra charge is applied to the common gate 61 of the slice drain reset transistors 23-1 and 23-2 by applying the slice charge reset pulse 121 to the slice drain reset transistor 23.
-1, 23-2 are discharged to the common drain 60.

Next, the signal reset pulse 102-1 is applied from the reset line 7-1 to the reset transistors 4-1-1 and 4-1-1.
It is applied to 4-1-2 to discharge the signal charge of the photodiode, and the noise detection charge injection pulse 124 is applied to the common gate 52 of the vertical signal line reset transistor to inject charges into the vertical signal line and then turn off. . Then, a noise voltage appears on the vertical signal lines 8-1 and 8-2 due to the threshold variation of the amplification transistor.

At this time, the slice capacities 21-1, 21-
When the second slice pulse 120 is applied to the second common terminal 57, the change amount of the voltage of the vertical signal lines 8-1 and 8-2 connected to the gates of the slice transistors 20-1 and 20-2, that is, the signal is changed. The amplified signal charges obtained by multiplying the slice-capacitance by the noise-free signal voltage having no noise component are transferred to the slice charge storage capacitors 24-1, 24-2.

Then, the horizontal selection transistor 12-
1, 12-2 are sequentially turned on to read out a signal without noise.

The important pulses in this type of noise canceller are the first slice pulse 119 for presetting the charge of the slice capacitance and the second slice pulse for transferring the charge proportional to the difference between the signal and noise to the drain of the slice transistor. is there. The trailing edges of these pulses are during the period when the load transistor activation pulse 106 that activates the load transistor is applied. The first noise suppression pulse described in the claims corresponds to the first slice pulse, and the second noise suppression pulse corresponds to the second slice pulse.

The leading edge of the first slice pulse 119 is not limited to the charge injection pulse 107 unlike the clamp pulse of the correlated double sampling type noise canceller.
The reason is that the vertical signal lines 8-1 and 8-2 are connected to the gates of the slice transistors 20-1 and 20-2, and it is not necessary to supply the charges that become amplified signals from the vertical signal lines. That is, after the charge injection pulse 107 is turned off,
First, the slice pulse 119 may be applied. Second slice pulse 120 and charge injection pulse 12 for noise detection
The same applies to the relationship of 4.

FIG. 16 is an improved version of FIG. The address pulse is divided into two. FIG. 17 shows a further improvement. A dummy address pulse 115-1 (115-2) is generated before the first address pulse. Similarly, a dummy charge injection pulse 125 is generated before the charge injection pulse 107. Address pulse 1 to dummy
15-1 (115-2) -Dummy charge injection pulse 12
5, a dummy slice pulse 122 is generated before the first slice pulse 119. It is also possible to generate the dummy slice charge reset pulse 123 before the slice charge reset pulse 121.

[0077]

As described in detail above, according to the present invention, the operating point of the amplifying transistor is controlled by the voltage control transistor, so that the power consumption is not increased.
The response of the source follower can be made faster.

In addition, the current is passed through the load transistor only during the period in which the signal of the photodiode is amplified and transmitted to the vertical signal line and the amplified signal storage capacitor, and otherwise the amount of the flowing current is reduced to reduce power consumption. Can be lowered.

Further, the vertical signal line reset transistor resets the vertical signal line in a short time, and the final signal is taken in when no current flows through the vertical signal line reset transistor. Both can be improved.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a solid-state imaging device according to a first embodiment.

FIG. 2 is a potential diagram of a source follower according to the first embodiment.

FIG. 3 is a drive timing chart at the time of reading a signal in the first embodiment.

FIG. 4 is a circuit configuration diagram showing an amplification type solid-state imaging device in which a load transistor is pulse-driven.

5 is an operation timing chart in pulse driving of the load transistor of FIG.

FIG. 6 is a circuit configuration diagram showing an amplification type solid-state imaging device which performs pulse driving of a load transistor and reset driving of a vertical signal line.

7 is an operation timing chart in the reset drive of FIG.

FIG. 8 is a diagram illustrating a phase relationship between a charge injection pulse and a signal acquisition pulse.

FIG. 9 is a diagram for explaining that the signal handling range is wide in the vertical signal line reset drive.

FIG. 10 is a circuit configuration diagram showing an amplification type solid-state imaging device using a correlated double sampling type noise canceller and a vertical signal line reset transistor.

FIG. 11 is a driving timing chart of FIG. 10, in which one address pulse is used for reading a signal and noise.

FIG. 12 is a driving timing chart of FIG. 10 in which separate address pulses are used for reading a signal and noise.

13 is a drive timing chart of FIG. 10 using a dummy address pulse, a dummy charge injection pulse, and a dummy clamp pulse.

FIG. 14 is a circuit configuration diagram showing an amplification type solid-state imaging device using a slice type noise canceller and a vertical signal line reset transistor.

FIG. 15 is a drive timing chart of FIG. 14, in which one address pulse is used for reading a signal and noise.

16 is a driving timing chart of FIG. 14, in which different address pulses are used for reading a signal and noise.

FIG. 17 is a driving timing chart of FIG. 14, in which a dummy address pulse, a dummy charge injection pulse, a dummy slice pulse, and a dummy slice charge reset pulse are used.

FIG. 18 is a circuit configuration diagram showing an amplification type solid-state imaging device using a correlated double sampling type noise canceller and a vertical signal line reset transistor in a cell having a charge transfer transistor.

FIG. 19 is a circuit configuration diagram showing an amplification type solid-state imaging device using a slice type noise canceller and a vertical signal line reset transistor in a cell having a charge transfer transistor.

FIG. 20 is a circuit configuration diagram showing an example of a conventional amplification type solid-state imaging device.

21 is an operation timing chart of the solid-state imaging device of FIG. 51.

FIG. 22 is a diagram illustrating that a signal handling range of a circuit including an amplification transistor and a load transistor is narrow.

[Explanation of symbols]

1-1-1, 1-1-2, ..., 1-3-3 ... Photodiode 2-1-1, 2-1-2, ..., 2-3-3 ... Amplifying transistor 3-1-1 3-1-2, ..., 3-3-3 ... Vertical selection transistors 4-1-1, 4-1-2, ..., 4-3-3 ... Reset transistor 5 ... Vertical shift registers 6-1, 6- 2, 6-3 ... Horizontal address lines 7-1, 7-2, 7-3 ... Reset lines 8-1, 8-2, 8-3 ... Vertical signal lines 9-1, 9-2, 9-3 ... Load transistors 10-1, 10-2, 10-3 ... Signal acquisition transistors 11-1, 11-2, 11-3 ... Amplified signal storage capacitors 12-1, 12-2, 12-3 ... Horizontal selection transistor 13 ... Horizontal shift registers 14-1, 14-2, 14-3 ... Load transistors 15-1, 15-2 ... Vertical signal line reset transition 16-1, 16-2 ... Clamp capacitors 17-1, 17-2 ... Clamp transistors 18-1, 18-2 ... Sample and hold transistors 19-1, 19-2 ... Hold capacitors 20-1, 20-2 ... Slice transistors 21-1, 21-2 ... Slice capacitors 22-1, 22-2 ... Slice source reset transistors 23-1, 23-2 ... Slice drain reset transistors 24-1, 24-2 ... Slice charge storage capacitors 49 ... Common gate 50 of signal acquisition transistor ... Horizontal signal line 51 ... Common gate electrode 52 of pulse-driven load transistor ... Common gate electrode 53 of vertical signal line reset transistor ... Common source of vertical signal line reset transistor 54 ... Common source of clamp transistor 55 ... Common gate 5 of clamp transistor ... common gate 57 of sample hold transistor ... common terminal 58 of slice capacitance ... common gate 60 of slice source reset transistor ... common drain 61 of slice drain reset transistor ... common gates 101-1 and 101-2 of slice drain reset transistor ... address Pulses 102-1 and 102-2 ... Signal reset pulse 103 ... Signal acquisition pulse 104-1, 104-2 ... Horizontal selection pulse 105-1, 105-2 ... Output signal 106 ... Load transistor activation pulse 107 ... Charge injection pulse 108 ... Leading edge 109 of signal acquisition pulse 103 ... Clamp pulse 110 ... Sample and hold pulses 111-1, 111-2 ... First address pulses 112-1, 112-2 ... Second address pulse 117 ... Dummy clamp Pulse 118 ... Slice source reset pulse 119 ... First slice pulse 120 ... Second slice pulse 121 ... Slice charge reset pulse 122 ... Dummy slice pulse 123 ... Dummy slice charge reset pulse 124 ... Noise detection charge injection pulse 125 ... dummy charge injection pulse 201 ... period 202 for extracting detection signal to vertical signal line / amplified signal storage capacitor ... period other than period 201

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 5/30-5/335 H01L 27/146

Claims (6)

(57) [Claims] 1. Unit cells including a photodiode for photoelectric conversion, an amplification transistor for inputting the output of the photodiode to a gate, and a reset transistor for resetting the photodiode are arranged in a two-dimensional matrix on a semiconductor substrate. an imaging region formed of a vertical selection means for selecting a read row of the imaging area, a load transistor provided in a plurality of end of vertical signal lines disposed in a column direction to read the output of the amplifying transistor, vertical signal lines Signal for each column
And a signal acquisition preparative <br/> transistor for reading the amplified signal storage capacitor provided in the solid-state imaging device which constitutes a source follower or an emitter follower amplifier by combining the amplification transistor and the load transistor, by the vertical selection means A solid-state imaging device comprising a potential control transistor for temporarily controlling the potential of the vertical signal line to be low during a signal reading period . 2. The load control transistor is turned on after the potential control transistor is turned on within the signal read period by the vertical selection means, and the potential control transistor is turned off within the read period. 1. The solid-state imaging device according to 1. 3. The solid-state image pickup device according to claim 1, wherein the load transistor is kept in an ON state during a signal reading period by the vertical selection means, and the potential control transistor is turned on and then turned off. 4. A unit cell including a photodiode for photoelectric conversion, an amplification transistor for inputting the output of the photodiode to a gate, and a reset transistor for resetting the photodiode is arranged in a matrix two-dimensional form on a semiconductor substrate. an imaging region formed of a vertical selection means for selecting a read row of the imaging area, a load transistor provided in a plurality of end of vertical signal lines disposed in a column direction to read the output of the amplifying transistor, vertical signal lines Signal for each column
In the solid-state imaging device, which comprises a signal fetching transistor for reading to an amplified signal storage capacitor provided, and which constitutes a source follower or emitter follower amplifier by coupling a load transistor and an amplifying transistor, Fully turn on the load transistor gate during the signal readout period
After applying the first voltage to the first voltage
A solid-state imaging device characterized by applying a second voltage lower than the above . 5. A unit cell including a photodiode for photoelectric conversion, an amplification transistor for inputting the output of the photodiode to a gate, and a reset transistor for resetting the photodiode is arranged in a two-dimensional matrix on a semiconductor substrate. an imaging region formed of a vertical selection means for selecting a read row of the imaging area, a load transistor provided in a plurality of end of vertical signal lines disposed in a column direction to read the output of the amplifying transistor, vertical signal lines Signal for each column
In the solid-state imaging device, which includes a signal capture transistor for reading the provided amplified signal storage capacitor and which combines a load transistor and an amplification transistor to form a source follower or emitter follower amplifier , Potential control transistor that controls the potential
And a ground potential Vs is applied to the gate of the potential control transistor during a signal read period by the vertical selection means.
s and the power supply potential Vdd, and then the first voltage and ground are applied to the gate of the load transistor.
A solid-state imaging device, wherein a second voltage between the potential Vss and the potential Vss is applied. 6. A unit cell including a photodiode for photoelectric conversion, an amplification transistor for inputting the output of the photodiode to a gate, and a reset transistor for resetting the photodiode is arranged in a matrix two-dimensional array on a semiconductor substrate. an imaging region formed of a vertical selection means for selecting a read row of the imaging area, a load transistor provided in a plurality of end of vertical signal lines disposed in a column direction to read the output of the amplifying transistor, vertical signal lines Signal for each column
In a solid-state imaging device that includes a signal acquisition transistor that reads out to the provided amplification signal storage capacitor and that constitutes a source follower or emitter follower amplifier by coupling a load transistor and an amplification transistor, in a signal readout period by the vertical selection unit. , The ground potential Vss and the power supply potential V at the gate of the load transistor
Applying an intermediate voltage between dd and
Is the gate voltage of the load transistor above the intermediate voltage.
A solid-state imaging device characterized by being made even lower .