JP2012054952A - Semiconductor device and driving method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device for increasing a range where a signal amplification value is large and an input/output relation operates linearly while preventing the extension of a signal writing period, and a driving method of the semiconductor device.SOLUTION: A semiconductor device including an amplification transistor 101 and a bias transistor 102 performs pre-discharge by the provision of a discharge transistor 108. Alternatively, a semiconductor device including the amplification transistor 101 and the bias transistor 102 performs pre-discharge by making the potential of a bias-side power source line 104 connected to the bias transistor 102 closer to the potential of an amplification side power source line 103 connected to the amplification transistor.

Description

The present invention relates to a semiconductor device and a driving method thereof. More specifically, the present invention relates to a MOS sensor device having an image sensor function and a driving method thereof.

In recent years, information devices such as personal computers have become widespread, and there is an increasing demand for reading various information into a personal computer as electronic information. For this reason, a digital still camera is attracting much attention as an alternative to the conventional silver salt camera, and a scanner as a means for reading what is printed on paper or the like.

In the digital still camera, an area sensor in which pixels are arranged two-dimensionally is used. In scanners and copiers, line sensors in which pixels are arranged one-dimensionally are used. When reading a two-dimensional image using a line sensor, the signal is read while moving the line sensor.

In these image reading devices, CCD type sensors are mainly used as image sensors. In a CCD sensor, photoelectric conversion is performed by a photodiode of each pixel, and the signal is read out using a CCD. However, in recent years, a single MOS-type sensor made using a single crystal silicon substrate has been developed with the advantage of being able to incorporate peripheral circuits, being able to be integrated into one chip, being suitable for real-time signal processing, and having low power consumption. Shows signs of widespread use. At the research level, MOS type sensors created using TFTs on glass substrates have also been developed. In the MOS sensor, photoelectric conversion is performed by a photodiode of each pixel, and a signal of each pixel is read using a switch formed by a MOS transistor.

Various types of pixel configurations for MOS sensors have been developed. They are,
It can be roughly classified into two types: passive sensors and active sensors.
A passive sensor is a sensor in which no signal amplification element is mounted on each pixel, and an active sensor is a sensor in which a signal amplification element is mounted on each pixel.
An active sensor has a merit that it is more resistant to noise than a passive sensor because a signal is amplified in each pixel.

FIG. 2 shows a circuit example of a pixel in the passive sensor. The pixel 10005 includes a switching transistor 10001 and a photodiode 10004. The photodiode 10004 is connected to the power supply reference line 10006 and the source terminal of the switching transistor 10001. A gate signal line 10002 is connected to the gate terminal of the switching transistor 10001, and a signal output line 10003 is connected to the drain terminal. In the photodiode 10004, photoelectric conversion is performed. That is, a charge is generated according to incident light, and the charge is accumulated there. Then, the gate signal line 10003 is controlled to turn on the switching transistor 10001, and the charge of the photodiode 10004 is read out through the signal output line 10003.

There are various types of pixel configurations of the active sensor. IEDM95: p17: CMOS Im
age Sensors, Electronic Camera On a Chip, or IEDM97: p201: CMOS Image Senso
rs-Recent Advances and Device Scaling Considerations
It introduces the pixel configuration and operation of the photogate type. ISSCC97: p180: A 1/4 Inch 330
k Square Pixel Progressive Scan CMOS Active Pixel Image Sensor classifies pixel configurations in terms of pixel selection methods. That is, the case where a transistor is used as the element to be selected or the case where a capacitor is used is described. As described above, there are various types of transistors constituting one pixel. JIEC Seminar: CMOS Camera Development Outlook: Heisei
On February 20, 2010, we introduced a wide range of CMOS-type sensors, including a logarithmic conversion type that outputs a logarithmic signal of light intensity by connecting the gate electrode and drain electrode of a reset transistor. Also said.

As shown in FIG. 3, the pixel configuration of the active sensor most often adopted is a type in which one pixel 308 is constituted by three N-channel transistors and one photodiode. The P-channel side terminal of the photodiode 304 is connected to the power supply reference line 312, and the N-channel side terminal is connected to the gate terminal of the amplifying transistor 306. Amplifying transistor 306
The drain terminal and the source terminal are connected to the power supply line 309 and the drain terminal of the switching transistor 301. A gate signal line 302 is connected to the gate terminal of the switching transistor 301, and a signal output line 303 is connected to the source terminal. Reset transistor 307
The gate terminal is connected to the reset signal line 306. The source terminal and the drain terminal of the reset transistor 307 are connected to the power supply line 309 and the gate terminal of the amplification transistor 306.

In the case of an area sensor, not only one pixel 308 but many pixels are connected to one signal output line 303. However, only one biasing transistor 311 is arranged for one signal output line 303. A bias signal line 310 is connected to the gate terminal of the bias transistor. The source terminal and the drain terminal of the bias transistor are connected to the signal output line 303 and the bias power supply line 313.

  Next, a basic operation of the pixel 308 will be described.

First, the reset transistor 307 is turned on. Since the P-channel terminal of the photodiode 304 is connected to the power supply reference line 312 and the N-channel terminal is electrically connected to the power supply line 309, a reverse bias voltage is applied to the photodiode 304. Hereinafter, an operation in which the potential of the N-channel side terminal of the photodiode 304 is charged to the potential of the power supply line 309 is referred to as reset. Thereafter, the reset transistor 307 is turned off. Then, when light is irradiated to the photodiode 304, electric charge is generated by photoelectric conversion. Therefore, as time passes, the potential of the N-channel side terminal of the photodiode 304 that has been charged to the potential of the power supply line 309 gradually decreases due to charges generated by light. After a certain period of time has elapsed, the switching transistor 301 is turned on. Then, the signal output line passes through the amplifying transistor 306.
A signal is output to 303.

However, when a signal is output, a potential is applied to the bias signal line 310,
A current flows through the biasing transistor 311. Therefore, the amplifying transistor 306 and the biasing transistor 311 operate as a so-called source follower circuit.

FIG. 4 shows an example of the most basic source follower circuit. FIG. 4 shows the case where an N-channel transistor is used. A source follower circuit can also be configured using a P-channel transistor. A power supply potential Vdd is applied to the amplification side power supply line 403.
A reference potential 0 V is applied to the bias side power supply line 404. The drain terminal of the amplifying transistor 401 is connected to the amplifying side power supply line 403, and the source terminal is connected to the drain terminal of the biasing transistor 402. The source terminal of the bias transistor 402 is connected to the bias side power line 404. A bias potential Vb is applied to the gate terminal of the bias transistor 402. Therefore, the bias current Ib flows through the bias transistor 402. The bias transistor 402 basically operates as a constant current source. The gate terminal of the amplifying transistor 401 becomes the input terminal 406. Therefore, the input potential Vin is applied to the gate terminal of the amplifying transistor 401. The source terminal of the amplifying transistor 401 becomes the output terminal 407. Therefore, the potential of the source terminal of the amplifying transistor 401 becomes the output potential Vout. The input / output relationship of the source follower circuit at this time is Vout = Vin−Vb.

When FIG. 3 and FIG. 4 are compared, the amplifying transistor 306 corresponds to the amplifying transistor 401. The bias transistor 311 corresponds to the bias transistor 402. Since the switching transistor 301 is assumed to be in a conductive state, it can be considered that it is omitted in FIG. The potential of the N-channel side terminal of the photodiode 304 is the input potential V
This corresponds to in (the gate potential of the amplifying transistor 401, that is, the potential of the input terminal 406). The potential of the signal output line 303 corresponds to the output potential Vout (the source potential of the amplifying transistor 401, that is, the potential of the output terminal 407).

Therefore, in FIG. 3, the potential of the N-channel side terminal of the photodiode 304 is Vpd, the potential of the bias signal line 310, that is, the bias potential is Vb, the potential of the signal output line 303 is Vout, and the power supply reference line 312 When the potential of the bias side power supply line 313 is 0 V, Vout = Vpd−Vb. Therefore, when the potential Vpd of the N-channel side terminal of the photodiode 304 changes, Vout also changes, so that the change in Vpd can be output as a signal and the light intensity can be read.

The basic operation of the source follower circuit is as described above. However, since it is necessary to explain the operation of the present invention, the operation principle of the source follower circuit will be described in detail next. In the description here, for simplicity, the amplifying transistor and the biasing transistor are
Assume that the characteristics are the same. Also, the current characteristics are ideal, that is, the source
It is assumed that even if the drain-to-drain voltage changes, the current value in the saturation region does not change.

First, as shown in FIG. 4, the bias potential is applied to the gate terminal of the bias transistor 402.
Vb has been added. When the biasing transistor 402 operates in the saturation region, it is assumed that a current Ib flows as shown in FIG. On the other hand, since both transistors are connected in series, the same amount of current should flow through the amplifying transistor 401 and the biasing transistor 402 in a steady state. Therefore, when the current Ib flows through the biasing transistor 402, the current Ib also flows through the amplifying transistor 401. Amplifying transistor 401 has current Ib
In order to flow, the gate-source voltage Vgs of the amplifying transistor 401 is equal to the bias potential Vb.
It is necessary to be equal to

Therefore, the output potential Vout in the source follower circuit is obtained. The output potential Vout is lower than the input potential Vin by the gate-source voltage Vgs of the amplifying transistor 401. Therefore, Vout = Vin−Vgs. Here, since the gate-source voltage Vgs of the amplifying transistor 401 is equal to the bias potential Vb, Vout = Vin−Vb. However, this formula is
As shown in FIG. 5, when the biasing transistor 402 operates in the saturation region (this is Vin
This is only true if Bias transistor 402 with small Vin
When operating in the linear region, the equation of Vout = Vin−Vb does not hold as shown in FIG. When the biasing transistor 402 operates in the linear region, Vout = Vin−Vb ′. Here, Vb ′ is a gate-source voltage in the amplifying transistor 401 at that time. If the current flowing when the biasing transistor 402 operates in the linear region is Ib ′, then Ib ′ <Ib. Therefore, Vb ′ <Vb. That is, as Vin and Ib ′ become smaller, Vb ′ also becomes smaller. As a result, as shown in FIG. 7, the input / output relationship (the relationship between Vin and Vout) becomes nonlinear.

  From the above, the following can be understood.

First, in order to increase the amplitude value of the output potential Vout in the source follower circuit, it is better to decrease the bias potential Vb. Since Vout = Vin-Vb, Vout can be increased if Vb is small. However, the bias transistor 402 needs to be in a conductive state. Therefore, the bias potential Vb must be larger than the threshold voltage of the biasing transistor 402.

On the other hand, when the bias potential Vb is large, the bias transistor 402 is easily operated in the linear region when the input potential Vin is small. As a result, the input / output relationship of the source follower circuit tends to be nonlinear. Considering this point, the bias potential Vb should be small.

So far, the operation in the steady state in the source follower circuit has been described. Next, the operation in the transient state in the source follower circuit will be described. As circuit configuration,
It is assumed that a load is added to the circuit of 4. That is, as shown in FIG. 8, a case where a load capacitor 805 is connected between an output terminal, that is, a source terminal of the amplifying transistor 801, and a load capacitor power supply line 806 is considered. Therefore, the potential of the load capacitor 805 is the output potential V of the source follower circuit.
Same as out.

First, a case where the output potential Vout is small in the initial state, that is, a case where Vout <Vin−Vb is considered. FIG. 8A shows a circuit diagram, and FIG. 8B shows a timing chart. In that case, the gate-source voltage Vgs of the amplifying transistor 801 is larger than the gate-source voltage Vgs of the biasing transistor 802. Therefore, a large current flows through the amplifying transistor 801. Therefore, the load capacity 805 is charged quickly, and the output potential Vout increases.
The gate-source voltage Vgs of the amplifying transistor 801 becomes smaller. Finally, when the gate-source voltage Vgs of the amplifying transistor 801 becomes equal to the bias potential Vb, a steady state is reached. The output potential at that time is Vout = Vin−Vgs = Vin−Vb. As described above, when Vout <Vin−Vb, in the transient state, the gate-source voltage Vgs of the amplifying transistor 801 is initially large, so that a large current flows through the amplifying transistor 801 to the load capacitor 805. Therefore, the signal writing time to the load capacitor 805 can be short.

On the other hand, the case where the output potential Vout is large in the initial state, that is, the case where Vout> Vin−Vb is considered. FIG. 9A shows a circuit diagram, and FIG. 9B shows a timing chart.
In that case, since the gate-source voltage Vgs of the amplifying transistor 901 is a small value, the amplifying transistor 901 is in a non-conductive state. The charge accumulated in the load capacitor 905 flows through the bias transistor 902 and is discharged. At that time, the bias transistor 9
Since the gate-source voltage of 02 is the bias potential Vb, the bias transistor 902
The current flowing through is Ib. Then, the output potential Vout gradually decreases, and the gate-source voltage Vgs of the amplifying transistor 901 increases. Finally, the amplification transistor 901
When the gate-source voltage Vgs becomes equal to Vb, a steady state is reached. In steady state, Vout
Is a constant value, and no current flows through the load capacitor 905. The current Ib continues to flow through the two transistors of the source follower circuit.

From the above, it can be seen that the discharge time of the load capacitor 905 when Vout> Vin−Vb, that is, the signal writing time is determined by the current Ib flowing through the biasing transistor 902. The current Ib is determined by the magnitude of the bias potential Vb.
Therefore, in order to increase the current Ib and shorten the signal writing time to the load capacitor 905,
It is necessary to increase the bias potential Vb.

Next, a signal timing chart in the pixel 309 is shown in FIG. First, the reset transistor 307 is turned on by controlling the reset signal line 305.
Then, the potential of the N-channel side terminal of the photodiode 304 is charged to the potential Vdd of the power supply line 309. That is, the pixel is reset. Then, the reset transistor 307 is turned off by controlling the reset signal line 305. Thereafter, when the photodiode 304 is irradiated with light, a charge corresponding to the light intensity is generated. Therefore, the charge charged by the reset operation is gradually discharged. That is, photodiode 304
The potential of the N-channel side terminal of the terminal is lowered. When dark light is irradiated, since the amount of discharge is small, the potential of the N-channel side terminal of the photodiode 304 does not drop so much.
At a certain point, the switching transistor 301 is turned on, and the potential of the N-channel side terminal of the photodiode 304 is read as a signal. This signal is proportional to the light intensity. Then, the reset transistor 307 is turned on again to reset the photodiode 304, and the same operation is repeated.

Next, a transistor in the pixel 309 is described. The polarities are often all N-channel types. In rare cases, the reset transistor may be a P-channel type (JIEC Seminar: CMOS Camera Development Outlook: February 20, 1998: p9, see Fig. 11). As for the arrangement of the amplifying transistor and the selecting transistor, both transistors are N-channel type, and as shown in FIG. 3, the power line 309 and the amplifying transistor 306 are connected, and the amplifying transistor 306 and the switching transistor are connected. In many cases, 301 is connected, and the switch transistor 301 and the signal output line 303 are connected. In rare cases, both transistors use N-channel type,
In some cases, the power supply line 309 and the switching transistor 301 are connected, the switching transistor 301 and the amplification transistor 306 are connected, and the amplification transistor 306 and the signal output line 303 are connected (ISSCC97: p180: A 1 / 4 Inch 330k Square Pixel Progressive Scan CMOS Activ
e Pixel Image Sensor).

Next, a sensor unit that performs photoelectric conversion and the like will be described. Usually, light is converted into electricity using a PN photodiode. In addition, there are PIN type diodes, avalanche type diodes, npn buried type diodes, Schottky type diodes and the like. In addition, there are photoconductors for X-rays and infrared sensors. This is described in the basics of solid-state imaging devices-the mechanism of electronic eyes: Takao Ando and Hirohito Tsuji: Japan Science and Technology Publishing.

Next, the application products of the sensor will be described. In addition to ordinary digital still cameras and scanners, they are also used for X-ray cameras. In that case, there are a case where a photoconductor that directly converts X-rays into an electric signal is used, and a case where the light is read after being converted into light by a fluorescent material or a scintillator. Euro Display 99: p203: X-ray Detectors based o
n Amorphous Silicon Active Matrix describes a case where X-rays are converted to light by a scintillator and then the light is read. IEDM 98: p21: amorphous silicon tft x-ra
y image sensors read using amorphous silicon, AM-LCD99: p45: re
The al-time imaging flat panal x-ray detector has been reported for reading using a photoconductor.

First, items required for the source follower circuit 405 will be considered. What is most necessary is to obtain as large a value as possible as the amplitude of the output potential Vout, that is, a value comparable to the amplitude of the input potential Vin. If the amplitude of the output potential Vout is large, a signal having a large number of gradations can be obtained. As a result, the image quality of the image read from the image sensor is improved. Also, the input / output relationship must be linear. In other words, the input potential Vin in the source follower circuit
It is important that the relationship between the output potential Vout is linear and the operating range is wide. That is, it is important that the relationship of Vout = Vin−Vb is maintained even when the input potential Vin becomes small, that is, that the biasing transistor 402 operates in the saturation region. In addition, the time required for writing the output signal Vout to the load capacitor is short. If the signal writing time is long,
Operation becomes slow.

Therefore, consider a method for satisfying the requirements for the source follower circuit described above.

First, in order to increase the amplitude of the output potential Vout, since Vout = Vin−Vb, the bias potential V
b should be small. In addition, the bias potential Vb may be reduced when the operation region where the input / output relationship is linear is widened. Because when the bias potential Vb is small, the output potential Vo
This is because even if ut becomes small, the biasing transistor 402 easily operates in the saturation region. However, when the bias potential Vb is small, the writing time of the output signal becomes long.

That is, the amplitude of the output potential and the signal writing time are in a trade-off relationship. It is impossible to shorten the writing time of the output potential while increasing the amplitude value of the output potential. In addition, it is impossible to increase the operation region where the input / output relationship is linear while increasing the amplitude value of the output potential.

  The object of the present invention is to solve the problems of the prior art.

In the present invention, in a source follower circuit using N-channel transistors, the output potential (potential of load capacitance) is once lowered before outputting a signal therefrom (source follower circuit using P-channel transistors). In this case, increase the output potential). Hereinafter, lowering the output potential of the source follower circuit (load capacitance potential) once (in the case of using a P-channel transistor) is referred to as pre-discharge, and the pre-discharge period is pre-discharged. This is called a discharge period. In the present invention, an actual signal is output after the pre-discharge.

Conventionally, in a source follower circuit using an N-channel transistor, when Vout> Vin−Vb in the initial state, the charge of the load capacitance is discharged through the bias transistor. However, in the present invention, the potential of the load capacitance is once lowered to a state of Vout <Vin−Vb. This operation is pre-discharge. Thereafter, an actual signal is output. When outputting an actual signal, Vout <Vin−Vb is already satisfied, so that the signal is output to the load capacitor through the amplifying transistor. Therefore, the signal writing time does not become long.

A potential value that is as low as possible, that is, a potential slightly higher than the threshold voltage of the bias transistor, is added to the gate potential of the bias transistor when an actual signal is output, that is, the bias potential Vb. Because the input / output relationship Vout of the source follower circuit
Considering = Vin−Vb, in order to increase the output potential Vout, the bias potential Vb should be as low as possible. However, the biasing transistor needs to be in a conductive state. That is, the bias transistor needs to operate in the saturation region. Therefore, the gate potential of the bias transistor when the actual signal is output,
That is, the bias potential Vb is set slightly higher than the threshold voltage of the biasing transistor. Actually, the potential is set slightly higher than the maximum threshold voltage value of all the bias transistors in the circuit.

Thus, the bias potential Vb is reduced, so that even if the current amount of the biasing transistor is reduced, the charge of the load capacitance is not discharged through the biasing transistor. There is no end. In addition, since the bias potential Vb is small, the operation region where the input / output relationship is linear is wide. As a result, it is possible to simultaneously increase the amplitude of the output potential and widen the operation region in which the input / output relationship is linear while preventing the signal writing time from becoming long. The configuration of the present invention is shown below.

The present invention is a semiconductor device having an amplifying transistor, a bias transistor, an amplifying side power line, a bias side power line, a bias signal line, a discharging transistor, and a discharging power line according to the above configuration, and the amplifying transistor The drain terminal of the amplifying transistor is connected to the amplifying side power line, the source terminal of the biasing transistor is connected to the biasing side power line, and the source terminal of the amplifying transistor is connected to the drain terminal of the biasing transistor. And the gate terminal of the biasing transistor is connected to the bias signal line, the gate terminal of the amplifying transistor is an input terminal, and the source terminal of the amplifying transistor is an output terminal. One of the output terminal and the discharge power supply line is the discharge terminal. The source terminal of the use transistors, one semiconductor device, characterized in that connected to the drain terminal of said discharge transistor is provided.

The present invention is a semiconductor device having an amplifying transistor, a biasing transistor, an amplifying power supply line, a biasing power supply line, and a bias signal line according to the above configuration, wherein the drain terminal of the amplifying transistor is the amplifying power supply line A source terminal of the bias transistor is connected to the bias-side power line, a source terminal of the amplifier transistor is connected to a drain terminal of the bias transistor, and the bias transistor Is connected to the bias signal line, the gate terminal of the amplifying transistor is an input terminal, the source terminal of the amplifying transistor is an output terminal, and the bias-side power line Signal generation that operates to bring the potential closer to that of the power supply line on the amplification side Wherein a the location is connected to the bias signal line is provided.

According to the present invention, there is provided a semiconductor device characterized in that one terminal of a load capacitor is connected to the output terminal and the other terminal of the load capacitor is connected to a power supply line for a load capacitor. Provided.

According to the present invention, there is provided a semiconductor device characterized in that the discharge power line and the bias-side power line are connected by the above-described configuration.

According to the present invention, there is provided a semiconductor device characterized in that at least two of the discharge power supply line, the load capacity power supply line, or the bias side power supply line are connected.

According to the present invention, there is provided a semiconductor device characterized in that the load capacity power supply line is connected to the amplification power supply line.

According to the present invention, there is provided a semiconductor device characterized by having at least one selection switch for controlling a current flowing from the amplification side power supply line or the bias side power supply line to the load capacitance or the output terminal. Provided.

According to the present invention, there is provided a semiconductor device having at least one selection switch for controlling a current flowing from the amplification side power supply line or the bias side power supply line to the output terminal.

According to the present invention, there is provided a semiconductor device characterized in that the selection switch includes at least one of an N-channel transistor or a P-channel transistor.

According to the present invention, the absolute value of the gate-source voltage of the biasing transistor is equal to the minimum value of the absolute value of the gate-source voltage necessary for bringing the biasing transistor into a conductive state. A semiconductor device is provided.

According to the present invention, there is provided a semiconductor device characterized in that a photoelectric conversion element is connected to the input terminal.

According to the present invention, there is provided a semiconductor device characterized in that a signal generated by a photoelectric conversion element is input to the input terminal by the above configuration.

According to the present invention, there is provided a semiconductor device characterized in that the photoelectric conversion element is an X-ray sensor or an infrared sensor.

According to the present invention, there is provided a semiconductor device characterized in that the photoelectric conversion element is any one of a photodiode, a Schottky diode, an avalanche diode, or a photoconductor.

According to the present invention, there is provided a semiconductor device characterized in that the photodiode is any one of a PN type, a PIN type, and an NPN buried type.

According to the present invention, there is provided a semiconductor device having a reset transistor, the source terminal or the drain terminal of the reset transistor being connected to the photoelectric conversion element.

According to the present invention, in the case where a plurality of the bias transistors are provided, the absolute value of the gate-source voltage of the plurality of bias transistors is necessary for making all of the plurality of bias transistors conductive. A semiconductor device is provided that is equal to the minimum absolute value of the gate-source voltage.

According to the present invention, there is provided a semiconductor device characterized in that the amplifying transistor, the biasing transistor, and the discharging transistor are transistors having the same polarity.

The present invention has an amplification transistor, a bias transistor, an amplification side power supply line, a bias side power supply line, and a bias signal line, and the drain terminal of the amplification transistor is connected to the amplification side power supply line. A source terminal of the bias transistor is connected to the bias-side power supply line, a source terminal of the amplifier transistor is connected to a drain terminal of the bias transistor, and a gate terminal of the bias transistor is In the method for driving a semiconductor device, which is connected to the bias signal line, the gate terminal of the amplification transistor is an input terminal, and the source terminal of the amplification transistor is an output terminal, pre-discharge is performed. After that, there is provided a method for driving a semiconductor device, characterized by outputting a signal. Provided.

The present invention has an amplification transistor, a bias transistor, an amplification side power supply line, a bias side power supply line, and a bias signal line, and the drain terminal of the amplification transistor is connected to the amplification side power supply line. A source terminal of the bias transistor is connected to the bias-side power supply line, a source terminal of the amplifier transistor is connected to a drain terminal of the bias transistor, and a gate terminal of the bias transistor is In the method of driving a semiconductor device, which is connected to the bias signal line, the gate terminal of the amplification transistor is an input terminal, and the source terminal of the amplification transistor is an output terminal, the bias-side power supply By preliminarily bringing the potential of the line close to the potential of the amplification power After the electrodeposition, the driving method of a semiconductor device and outputs a signal.

The present invention has an amplification transistor, a bias transistor, an amplification side power supply line, a bias side power supply line, a bias signal line, a discharge transistor, and a discharge power supply line, and the drain terminal of the amplification transistor is configured as described above. Connected to the amplification side power supply line, the source terminal of the bias transistor is connected to the bias side power supply line, and the source terminal of the amplification transistor is connected to the drain terminal of the bias transistor. The gate terminal of the bias transistor is connected to the bias signal line, the gate terminal of the amplification transistor is an input terminal, the source terminal of the amplification transistor is an output terminal, One of the output terminal and the discharge power supply line is the source of the discharge transistor. In the method for driving a semiconductor device, one of which is connected to the drain terminal of the discharge transistor, the pre-discharge is performed by bringing the discharge transistor into a conductive state, and then a signal is output. A method for driving a semiconductor device is provided.

According to the present invention, there is provided a method for driving a semiconductor device, characterized in that the potential of the discharge power supply line takes a value between the potential of the bias signal line and the potential of the bias side power supply line.

According to the present invention, in the semiconductor device according to the above structure, one terminal of a load capacitor is connected to the output terminal, and the other terminal of the load capacitor is connected to a load capacitor power line. A driving method is provided.

According to the present invention, there is provided a method for driving a semiconductor device, characterized in that the discharge power supply line and the bias power supply line are connected by the above configuration.

According to the present invention, there is provided a driving method of a semiconductor device characterized in that at least two of the discharge power supply line, the load capacity power supply line, and the bias side power supply line are connected.

According to the present invention, there is provided a method for driving a semiconductor device, characterized in that the load capacitor power supply line is connected to the amplification power supply line.

According to the present invention, there is provided a semiconductor device characterized by having at least one selection switch for controlling a current flowing from the amplification side power supply line or the bias side power supply line to the load capacitance or the output terminal. A driving method is provided.

According to the present invention, there is provided a driving method of a semiconductor device having at least one selection switch for controlling a current flowing from the amplification power supply line or the bias power supply line to the output terminal. The

According to the present invention, there is provided a method for driving a semiconductor device, wherein the selection switch has at least one of an N-channel transistor or a P-channel transistor.

According to the present invention, the absolute value of the gate-source voltage of the biasing transistor is equal to the minimum value of the absolute value of the gate-source voltage necessary for bringing the biasing transistor into a conductive state. A featured method for driving a semiconductor device is provided.

According to the present invention, there is provided a method for driving a semiconductor device, characterized in that a photoelectric conversion element is connected to the input terminal.

According to the present invention, there is provided a method for driving a semiconductor device, characterized in that a signal generated by a photoelectric conversion element is input to the input terminal.

According to the present invention, there is provided a method for driving a semiconductor device, characterized in that the photoelectric conversion element is an X-ray sensor or an infrared sensor.

According to the present invention, there is provided a method for driving a semiconductor device, characterized in that the photoelectric conversion element is any one of a photodiode, a Schottky diode, an avalanche diode, or a photoconductor.

According to the present invention, there is provided a method for driving a semiconductor device, characterized in that the photodiode is any one of a PN type, a PIN type, and an NPN buried type.

According to the present invention, there is provided a method for driving a semiconductor device, characterized in that it has a resetting transistor, and the resetting transistor resets the photoelectric conversion element.

According to the present invention, in the case where a plurality of the bias transistors are provided, the absolute value of the gate-source voltage of the plurality of bias transistors is necessary for making all of the plurality of bias transistors conductive. There is provided a method for driving a semiconductor device, characterized by being equal to a minimum absolute value of a gate-source voltage.

According to the present invention, there is provided a method for driving a semiconductor device, characterized in that the amplifying transistor, the biasing transistor, and the discharging transistor are transistors having the same polarity.

The present invention can increase the amplitude of the output potential while avoiding an increase in the writing time of the output potential of the source follower circuit. At the same time, the operation region in which the input / output relationship of the source follower circuit is linear can be widened. Therefore, a sensor with high image quality is realized.

Circuit diagram and timing chart of source follower circuit of the present invention Circuit diagram of a conventional passive sensor pixel Conventional active sensor pixel circuit diagram Circuit diagram of conventional source follower circuit Current characteristics of source follower circuit Current characteristics of source follower circuit Input / output characteristics of source follower circuit Source follower circuit schematic and timing chart Source follower circuit schematic and timing chart Timing chart with active sensor Circuit diagram and timing chart of source follower circuit of the present invention Circuit diagram and timing chart of source follower circuit of the present invention Circuit diagram and timing chart of source follower circuit of the present invention Circuit diagram and timing chart of source follower circuit of the present invention Circuit diagram and timing chart of source follower circuit of the present invention Circuit diagram and timing chart of source follower circuit of the present invention Circuit diagram and timing chart of source follower circuit of the present invention Circuit diagram and timing chart of source follower circuit of the present invention Circuit diagram and timing chart of source follower circuit of the present invention Block diagram of area sensor of the present invention Circuit diagram of pixel of active sensor of the present invention Circuit diagram of pixel of active sensor of the present invention Circuit diagram of signal processing circuit of the present invention Circuit diagram of final output amplification circuit of the present invention Circuit diagram of final output amplification circuit of the present invention Timing chart of area sensor of the present invention Timing chart of area sensor of the present invention Timing chart of area sensor of the present invention Circuit diagram of signal processing circuit of the present invention The figure which shows the preparation process of the image sensor of this invention The figure which shows the preparation process of the image sensor of this invention The figure which shows the preparation process of the image sensor of this invention The figure which shows the preparation process of the image sensor of this invention Diagram of an electronic device using the image sensor of the present invention Diagram of an electronic device using the image sensor of the present invention Diagram of an electronic device using the image sensor of the present invention Diagram of an electronic device using the image sensor of the present invention

[Embodiment 1] A typical embodiment of the present invention will be described below.
FIG. 11 shows an example of a pre-discharge implementation method. FIG. 11A shows a circuit diagram, and FIG. 11B shows a signal timing chart. In FIG. 11, pre-discharge is performed by disposing a dedicated discharge transistor 1108. FIG. 11 shows an example in which a source follower circuit is configured using N-channel transistors.

The potential of the gate terminal (input terminal 1105) of the amplifying transistor 1101 becomes the input potential Vin,
This corresponds to the potential of the N channel side terminal of the photodiode. Amplifying transistor 11
The drain terminal of 01 is connected to the amplification side power supply line 1103, and the source terminal is connected to the drain terminal of the biasing transistor 1102. The source terminal of the amplifying transistor 1101 is an output terminal 1107, and the potential thereof becomes the output potential Vout. A bias potential Vb is applied to the gate terminal of the bias transistor 1102. The source terminal of the bias transistor 1102 is connected to the bias side power supply line 1104. The source terminal and the drain terminal of the discharging transistor 1108 are connected to the output terminal 1107 of the source follower circuit (the source terminal of the amplifying transistor 1101) and the discharging power supply line 1109.

As shown in FIG. 11B, when the discharge transistor 1108 becomes conductive, the potential of the output terminal 1107 becomes the potential of the discharge power supply line 1109, and pre-discharge is performed. During the pre-discharge period, since the gate potential of the discharging transistor 1108 is large, a large current can be passed through the discharging transistor 1108. As a result, the output potential Vout can be rapidly lowered, and the pre-discharge period can be shortened. In the case of this method, the bias potential Vb may remain the same as before, or may be increased during the pre-discharge period.

After pre-discharge, an actual signal is output. In that case, because it is in the state of Vout <Vin-Vb,
A large current flows through the amplifying transistor 1101 because its gate-source voltage is large. As a result, the signal writing time can be shortened.

Considering the input / output relationship Vout = Vin−Vb, the bias potential Vb when outputting the output potential Vout is preferably as low as possible in order to increase the output potential Vout.
However, the biasing transistor 1202 must be in a conductive state.
That is, the bias transistor 1202 needs to be able to operate in the saturation region and have a value that allows constant current to flow. Therefore, the optimum value of the absolute value of the bias signal potential (the voltage between the gate and the source of the bias transistor) outside the pre-discharge period is a potential slightly larger than the absolute value of the threshold voltage of the bias transistor 1202. is there.

In addition, when the bias potential Vb is low, the bias transistor 1102 easily operates in the saturation region, so that the operation region in which the input / output relationship is linear can be widened.

As a result, it is possible to simultaneously increase the amplitude of the output potential and widen the operation region in which the input / output relationship is linear while preventing the signal writing time from becoming long.

The polarity of the discharging transistor 1108 is the same as that of the amplifying transistor 1101 and the biasing transistor 1102, that is, in FIG. 11, the N-channel type is preferable.
This is because the discharge power supply line 1109 is at a low potential, so that when the discharge transistor 1108 is turned on, the N-channel type can increase the gate-source voltage. If the discharging transistor 1108 has a polarity different from that of the amplifying transistor 1101 and the biasing transistor 1102, that is, in the case of the P channel type in FIG. 11, the gate terminal of the discharging transistor 1108 has a very low potential, that is, It is necessary to apply a potential lower than that of the bias side power supply line 1104. From the above, it is desirable that the polarity of the discharging transistor 1108 be the same as that of the amplifying transistor 1101 and the biasing transistor 1102.

In FIG. 11, a plurality of discharge transistors 1108N may be used.
Both polarity transistors may be used.

Next, the potential of the discharge power supply line 1109 will be described. The pre-discharge is to make a state of Vout <Vin−Vb. Therefore, the potential of the discharge power supply line 1109 needs to be low. Although it may be lower than the bias side power supply line 1104, the potential operating range of the output terminal 1107 is between the potential of the amplification side power supply line 1103 and the potential of the bias side power supply line 1104. Therefore, even if the potential of the discharge power supply line 1109 is lower than the potential of the bias side power supply line 1104, there is no improvement effect. Discharge power line 11
When the potential of 09 is higher than the potential of the bias side power supply line 1104, the bias signal line 11
If the potential is higher than 06, Vout <Vin-Vb may not be achieved. Therefore, the potential of the discharge power supply line 1109 is equal to or higher than the potential of the bias-side power supply line 1104 and the bias signal line
The potential needs to be 1106 or less. Normally, the same potential as that of the bias-side power supply line 1104 may be set. Therefore, the discharge power line 1109 and the bias side power line 1104 may be connected.

Actually, when the circuit of FIG. 11 is used, in many cases, a load capacitor is connected to the output terminal 1107 and a signal is stored there. A circuit diagram when a load capacitor is connected to the circuit shown in FIG.
Shown in 1. One terminal of the load capacitor 110 is connected to the output terminal 107, and the other terminal is connected to the load capacitor power line 111. The potential value of the load capacitor power supply line 111 may be an arbitrary value. Usually, the same value as that of the bias-side power supply line 104 is often set. Therefore, the load capacity power supply line 111 and the bias side power supply line 104 may be connected. The load capacity power supply line 111 and the amplification power supply line 103 may be connected. From the above, any two or more of the load capacity power supply line 111, the bias power supply line 104, and the discharge power supply line 109 may be connected to each other. 3
FIGS. 12A and 12B show a circuit diagram and a timing chart when the book is connected.

So far, the case where a source follower circuit is configured using N-channel transistors has been described. However, it is also possible to configure a source follower circuit using the P channel type. Therefore, the figure when the P channel type is used is shown below.
FIG. 13 shows the case where the P channel type is used for FIG. FIG. 14 shows the case where the P channel type is used for FIG. FIG. 15 shows the case where the P channel type is used for FIG. When a source follower circuit is configured using N-channel transistors, the potential of the amplification side power supply line 1103 is higher than the potential of the bias side power supply line 1104. However, when a source follower circuit is configured using a P-channel transistor, the potential of the amplification side power supply line 1303 is lower than the potential of the bias side power supply line 1304.

There are cases where a plurality of source follower circuits are arranged and output terminals are connected to each other.
At that time, a signal needs to be output only from one source follower circuit. Therefore, a switch may be arranged to stop the current flow. FIGS. 16A and 16B show a circuit diagram and a timing chart when the transfer transistor 1612 is arranged between the output terminal 1607 and the load capacitor 1610 in the circuit of FIG. FIG. 17 shows a circuit diagram and a timing chart when a switching transistor 1713 is arranged between the output terminal 1707 and the amplifying transistor 1701 in the circuit of FIG. In FIG. 16 or FIG. 17, the amplifying transistor,
And at least one element of a biasing transistor and a selection switch,
A unit pixel may be configured.

Note that the switch may be either an N-channel type or a P-channel type in order to stop the current flow. A plurality of switches may be used. The connection method may also be serial or parallel.

[Embodiment 2] Next, FIG. 18 shows an embodiment in which pre-discharge is performed by a method different from Embodiment 1. FIG. FIG. 18A shows a circuit diagram, and FIG. 18B shows a signal timing chart. In FIG.
Pre-discharge is performed by increasing the bias potential Vb. FIG. 18 shows an example in which a source follower circuit is configured using N-channel transistors.

The potential of the gate terminal of the amplifying transistor 1801 becomes the input potential Vin, which corresponds to the potential of the N-channel side terminal of the photodiode. The drain terminal of the amplifying transistor 1801 is connected to the amplifying side power supply line 1803, and the source terminal is connected to the drain terminal of the biasing transistor 1802. The source terminal of the amplification transistor 1801 is the output terminal 1807,
The potential there becomes the output potential Vout. A bias potential Vb is applied to the gate terminal of the bias transistor 1802. The source terminal of the bias transistor 1802 is connected to the bias side power supply line 1804.

During the pre-discharge period, the bias potential Vb is increased. As a result, the potential of the output terminal 1807 becomes the potential of the bias side power supply line 1804, and pre-discharge is executed. During the pre-discharge period, since the gate potential of the bias transistor 1802, that is, the bias potential Vb is large, a large current can flow through the bias transistor 1802. As a result, the output potential Vout is
It can be rapidly lowered and the pre-discharge period can be short.

After pre-discharge, an actual signal is output. In that case, because it is in the state of Vout <Vin-Vb,
A large current flows through the amplifying transistor 1801 because its gate-source potential is large. As a result, the signal writing time can be shortened.

Considering the input / output relationship Vout = Vin−Vb, the bias potential Vb when the actual output potential Vout is output should be as low as possible in order to increase the output potential Vout. However, the biasing transistor 1802 must be in a conductive state. That is, the bias transistor 1802 needs to be able to operate in the saturation region and have a value that allows constant current to flow. Therefore, the optimum value of the absolute value of the bias signal potential (the voltage between the gate and the source of the biasing transistor) outside the pre-discharge period is slightly higher than the absolute value of the threshold voltage of the biasing transistor 1802. is there.

Further, when the bias potential Vb is low, the bias transistor 1802 easily operates in the saturation region, so that the operation region in which the input / output relationship is linear can be widened.

As a result, it is possible to simultaneously increase the amplitude of the output potential and widen the operation region in which the input / output relationship is linear while preventing the signal writing time from becoming long.

The potential value of the bias potential Vb at the time of pre-discharge is preferably as high as possible in order to perform discharge. Therefore, it is appropriate to increase it to the highest potential in the circuit, for example, the amplification power supply line 1803.

In the prior art, a constant potential is applied to the bias signal line 1806. In the present embodiment, the bias potential Vb changes during pre-discharge. Therefore, a signal generator is connected to the bias signal line 1806 in order to change the bias potential Vb.

So far, the case where a source follower circuit is configured using N-channel transistors has been described. However, it is also possible to configure a source follower circuit using the P channel type. Accordingly, FIG. 19 shows a diagram in the case of using the P channel type.
As in the first embodiment, the potential of the amplification side power supply line and the potential of the bias side power supply line are the same when the source follower circuit is configured using N-channel transistors and when the source follower circuit is configured using P-channel transistors. The magnitude relationship with is different.

In the present embodiment as well, it is possible to dispose a load capacitor and a selection switch as in the first embodiment.

Next, an embodiment will be described in which pre-discharge is performed using a discharge transistor in an area sensor in which a driving circuit is mounted in the periphery and pixels are two-dimensionally arranged. An overall circuit diagram is shown in FIG. First, there is a pixel arrangement unit 2005 in which pixels are arranged two-dimensionally.
Drive circuits for driving the gate signal line and the reset signal line of each pixel are arranged on the left and right sides of the pixel array unit 2005. In FIG. 20, the gate signal line drive circuit 2006 is on the left side.
A reset signal line drive circuit 2007 is arranged on the right side. A signal processing circuit or the like is disposed above the pixel array unit 2005. In FIG. 20, a bias circuit 2003 is arranged on the pixel array unit 2005. The bias circuit 2003 is paired with the amplifying transistor of each pixel to form a source follower circuit. A sample hold & signal processing circuit 2002 is arranged on the bias circuit 2003. Here, a circuit for temporarily storing the signal, performing analog / digital conversion, and reducing noise is arranged. A signal output line drive circuit 2001 is arranged on the sample hold & signal processing circuit 2002. The signal output line drive circuit 2001 outputs a signal for sequentially outputting the temporarily stored signals. A final output amplification circuit 2004 is arranged before a signal is output to the outside. Here is a sample hold & signal processing circuit 2002
And the signal output line drive circuit 2001 amplify the sequentially output signals before going out. Therefore, it is not necessary when the signal is not amplified, but in reality, it is often arranged.

Next, a circuit diagram of each part is shown. First, as an example, a circuit diagram of an i-th row and j-th column pixel unit circuit 2008 from the two-dimensionally arranged pixel array unit 2005 is shown in FIG. In FIG. 21, a P-channel reset transistor 2107, a P-channel switch transistor 2101, an N-channel amplification transistor 2106, and a photoelectric conversion element (here, the most representative photodiode 2104)
It is composed of In the photodiode 2104, the P channel side terminal is connected to the power supply reference line 2112, and the N channel side terminal is connected to the gate terminal of the amplification transistor 2106. An i-th row reset signal line 2105 is connected to a gate terminal of the reset transistor 2107, and a source terminal and a drain terminal are connected to a j-th column power line 2109 and a gate terminal of the amplification transistor 2106. The switching transistor 2101 has a gate terminal connected to the i-th gate signal line 2102, and a source terminal and a drain terminal connected to the j-th column power line 2109 and the amplifying transistor 2106. The source terminal and drain terminal of the amplifying transistor 2106 are connected to the j-th column signal output line 2103 and the switching transistor 2101. The i-th gate signal line 2102 and the i-th reset signal line 2105 extend in the horizontal direction as usual.

When corresponding to the wiring in the source follower circuit, the j-th column power line 2109 corresponds to the amplification-side power line 1103, the power reference line 2112 corresponds to the bias-side power line 1104, and the output terminal 1107 corresponds to the j-th column signal. This corresponds to the output line 2103.

In FIG. 21, the reset transistor 2107 is a P-channel type. However, the reset transistor may be an N-channel type. However, in the N-channel type, the gate-source voltage cannot be increased during the reset operation. Therefore, the reset transistor operates in the saturation region, and the photodiode 2104 cannot be charged sufficiently. Therefore, the reset transistor operates with an N-channel type, but a P-channel type is more desirable.

For the switching transistor 2101, the i-th row power line 2109 and the amplifying transistor 2106
It is desirable to use a P-channel type. However, since the N-channel type operates as in the conventional case, the N-channel type may be used, or the n-th channel type signal output line 2103 and the amplifying transistor 2106 may be disposed. However, since it is difficult to output a signal correctly, the switching transistor 2101 is arranged between the i-th power line 2109 and the amplifying transistor 2106,
In addition, it is desirable to use the P channel type.

As the amplifying transistor 2106, an N-channel type is used in FIG.
However, it is also possible to use a P channel type. However, in that case, in order to operate as a source follower circuit in combination with the bias transistor, it is necessary to change the circuit connection method. That is, simply changing the polarity of the amplifying transistor 2106 in the circuit diagram of FIG.

Thus, FIG. 22 shows an example of a circuit configuration when a P-channel type amplifying transistor is used. The difference from FIG. 21 is that the polarity of the amplifying transistor 2206 is a P-channel type, the direction of the photodiode is reversed, and the power supply line and the power supply reference line are interchanged. When the P-channel type is used for the amplifying transistor, it is necessary to use the P-channel type for the bias transistor. This is because the biasing transistor needs to be operated as a constant current source. Therefore, in FIG. 22, a biasing transistor 2211 is also described for reference. 22 includes an N-channel reset transistor 2207, an N-channel switch transistor 2201, a P-channel amplification transistor 2206, a photoelectric conversion element (here, the most representative photo). Diode 2204). The photodiode 2204 has an N channel side terminal connected to the power supply line 2209 and a P channel side terminal connected to the gate terminal of the amplification transistor 2206. An i-th row reset signal line 2205 is connected to the gate terminal of the reset transistor 2207, and a source terminal and a drain terminal are connected to the j-th column power supply reference line 2212 and the gate terminal of the amplification transistor 226.
The switching transistor 2201 has a gate terminal connected to the i-th gate signal line 2202, and a source terminal and a drain terminal connected to the j-th column power supply reference line 2212 and the amplifying transistor 2206. The source terminal and drain terminal of the amplifying transistor 2206 are connected to the j-th column signal output line 2203 and the switching transistor 2201. A bias signal line 2210 is connected to a gate terminal of the bias transistor 2211, and a source terminal and a drain terminal are connected to a j-th column signal output line 2203 and a power supply line 2209.

When corresponding to the wiring in the source follower circuit, the power supply line 2212 in the j-th column is
03, the power line 2209 corresponds to the bias side power line 1804, and the output terminal 1807 corresponds to the j-th column signal output line 2203.

In FIG. 22, the reset transistor 2207 is an N-channel type. However, the reset transistor may be a P-channel type. However, in the case of the P channel type, the gate-source voltage cannot be increased during the reset operation. Therefore, the reset transistor operates in the saturation region, and the photodiode 2204 cannot be charged sufficiently. Therefore, the reset transistor operates with a P-channel type, but is preferably an N-channel type.

In FIG. 22, the switching transistor 2201 is preferably disposed between the j-th column power supply reference line 2212 and the amplifying transistor 2206, and is preferably an N-channel type. However, since the P-channel type also operates, the P-channel type may be used, or it may be arranged between the j-th column signal output line 2203 and the amplifying transistor 2206. However, since it is difficult to output a signal correctly, it is desirable that the switching transistor 2201 be disposed between the j-th column power supply reference line 2209 and the amplifying transistor 2206 and to use an N-channel type.

Thus, as can be seen by comparing FIG. 21 and FIG. 22, when the polarity of the amplifying transistor is different, the optimum transistor configuration is also different.

Next, FIG. 23 shows a circuit diagram of the j-th column peripheral circuit 2009 as a circuit for one column from the bias circuit 2003 and the sample hold & signal processing circuit 2002. A bias transistor 2311 is arranged in the bias circuit 2003. The polarity is the same as the polarity of the amplifying transistor of each pixel. Therefore, when the amplifying transistor of the pixel is an N channel type, the bias transistor is also an N channel type. In FIG. 23, the biasing bias transistor 2311 is an N-channel type. A bias signal line 2310 is connected to the gate terminal of the bias transistor 2311, and the source terminal and the drain terminal are connected to the j-th column signal output line 2303.
And the power supply reference line 2312 (when the bias transistor is a P-channel type,
Use a power line instead of a power line.) The biasing transistor 2311 is paired with the amplifying transistor of each pixel and operates as a source follower circuit. A transfer signal line 2314 is connected to the gate terminal of the transfer transistor 2313, and the source terminal and the drain terminal are
The j-th column signal output line 2303 and the load capacitor 2315 are connected. The transfer transistor is operated when the potential of the signal output line 2303 is transferred to the load capacitor 2315. Therefore, a P-channel transfer transistor may be added and connected in parallel with the N-channel transfer transistor 2314. The load capacitor 2315 is connected to the transfer transistor 2313 and the power supply reference line 2312.
The role of the load capacitor 2315 is to temporarily store a signal output from the signal output line 2303. The gate terminal of the discharge transistor 2316 is connected to the pre-discharge signal line 2317, and the source terminal and the drain terminal are connected to the load capacitor 2315 and the power supply reference line 2312. Before the discharge transistor 2316 inputs the potential of the signal output line 2303 to the load capacitor 2315, the load capacitor
It operates to discharge the charge accumulated in 2315.

An analog / digital signal conversion circuit, a noise reduction circuit, or the like can be arranged.

A final selection transistor 2319 is connected between the load capacitor 2315 and the final output line 2320. The source terminal and the drain terminal of the final selection transistor 2319 are connected to the load capacitor 2315 and the final output line 2320, and the gate terminal is connected to the j-th column final selection line 2318. The final selection line is scanned sequentially from the first column. When the j-th column final selection line 2318 is selected and the final selection transistor 2319 is turned on, the potential of the load capacitor 2315 and the potential of the final output line 2320 become equal. As a result, the signal accumulated in the load capacitor 2315 can be output to the final output line 2320. However, if charges are accumulated in the final output line 2320 before a signal is output to the final output line 2320, the electric potential when the signal is output to the final output line 2320 is affected by the charge. Therefore, before outputting a signal to the final output line 2320, the potential of the final output line 2320 must be initialized to a certain potential value. In FIG. 23, the final output line 2320 and the power supply reference line
A final reset transistor 2322 is arranged between the transistors 2312. The j-th column final reset line 2321 is connected to the gate terminal of the final reset transistor 2322. Then, before selecting the j-th column final selection line 2318, the j-th column final reset line 2321 is selected, and the potential of the final output line 2320 is initialized to the potential of the power supply reference line 2312. Thereafter, the j-th column final selection line 2318 is selected, and the signal accumulated in the load capacitor 2315 is output to the final output line 2320.

The signal output to the final output line 2320 may be taken out as it is. However,
Since the signal is weak, the signal is often amplified before being taken out. FIG. 24 shows a circuit of the final circuit 2010 as a circuit for that purpose. There are various circuits such as operational amplifiers for amplifying signals. Any circuit may be used as long as it is a circuit that amplifies a signal. Here, a source follower circuit is shown as the simplest circuit configuration. FIG. 24 shows an N channel type case. An input to the final output amplification circuit 2004 is a final output line 2402. Signals are output to the final output line 2402 in order from the first column. The signal is amplified by the final output amplification circuit 2004 and output to the outside. The final output line 2402 is connected to the gate terminal of the amplification transistor 2404 for final output amplification. The drain terminal of the amplifying transistor 2404 for final output amplification is connected to the power supply line 2406, and the source terminal is an output terminal. The gate terminal of the bias transistor 2403 for final output amplification is connected to the bias signal line 2405 for final output amplification. The source terminal and the drain terminal are connected to the power supply reference line 2407 and the source terminal of the amplification transistor 2404 for final output amplification.

FIG. 25 shows a circuit diagram in the case of using a source follower circuit in the case of the P channel type. Figure 24
The difference is that the power supply line and the power supply reference line are reversed. The final output line 2502 is connected to the gate terminal of the amplification transistor 2504 for final output amplification. The drain terminal of the amplification transistor 2504 for final output amplification is connected to the power supply reference line 2507, and the source terminal is an output terminal. The gate terminal of the final output amplification bias transistor 2503 is connected to the final output amplification bias signal line 2505. The source terminal and the drain terminal are connected to the power supply line 2506 and the source terminal of the amplification transistor 2504 for final output amplification. The potential of the bias signal line 2505 for final output amplification is the bias signal line 2405 for final output amplification when the N-channel type is used.
And the value is different.

In FIGS. 24 and 25, the source follower circuit is composed of only one stage. However, it may be composed of a plurality of stages. For example, in the case of two stages, the first stage output terminal may be connected to the second stage input terminal. In each stage, either an N channel type or a P channel type may be used.

The gate signal line reset signal line drive circuit 2006, the power supply line drive circuit 2007, and the signal output line drive circuit AZ01 are circuits that simply output a pulse signal. Therefore, it can be implemented using a known technique.

Next, a timing chart of signals will be described. First, FIG. 26 shows a timing chart in the circuit of FIG. The reset signal line is scanned sequentially from the first row. For example, the (i-1) -th row is selected, the i-th row is then selected, and then the (i + 1) -th row is selected. A period until the same row is selected again corresponds to a frame period. Similarly, the gate signal lines are scanned sequentially from the first row. However, the timing to start scanning the gate signal line is later than the timing to start scanning the reset signal line. For example, when focusing on the pixel in the i-th row, the i-th row reset signal line is selected, and then the i-th gate signal line is selected. When the i-th gate signal line is selected, a signal is output from the i-th row pixel.
The period from when the pixel is reset to when a signal is output is the accumulation time. During the accumulation time, charges generated by light are accumulated in the photodiode.
In each row, the reset timing and the signal output timing are different. Therefore, the accumulation time is the same for all rows of pixels, but the accumulation time is different.

Next, FIG. 27 shows a timing chart of signals in FIG. Since this is a repetitive operation, consider the case where the i-th gate signal line is selected as an example. First, after the gate signal line 2102 in the i-th row is selected, the pre-discharge signal line 2317 is selected, and the discharging transistor 2316 is turned on. Thereafter, the transfer signal line 2314 is selected. Then, the signal of each column is output to the load capacitance 2315 of each column from the pixel in the i-th row.

After the signals of all the pixels in the i-th row are accumulated in the load capacitors 2315 of each column, the signals of each column are sequentially output to the final output line 2320. During the period from when the transfer signal line 2314 is not selected until the gate signal line is selected, the signal output line drive circuit 2001 scans all columns. First, the final reset line in the first column is selected, the final reset transistor 2322 is turned on, and the final output line 2320 is initialized to the potential of the power supply reference line 2312. Then, the last selection line 23 in the first column
18 is selected, the final selection transistor 2319 is turned on, and the signal of the load capacitance 2315 in the first column is output to the final output line 2320. Next, the final reset line in the second column is selected, the final reset transistor 2322 is turned on, and the final output line 2320 is initialized to the potential of the power supply reference line 2312. Thereafter, the final selection line 2318 in the second column is selected, the final selection transistor 2319 is turned on, and the signal of the load capacitance 2315 in the second column is output to the final output line 2320. Thereafter, the same operation is repeated. Also in the j-th column, the final reset line in the j-th column is selected, the final reset transistor 2322 is turned on, and the final output line 2320 is initialized to the potential of the power supply reference line 2312.
Thereafter, the final selection line 2318 in the j-th column is selected, the final selection transistor 2319 is turned on, and the signal of the load capacitor 2315 in the j-th column is output to the final output line 2320. Next, the final reset line in the (j + 1) th column is selected, the final reset transistor 2322 is turned on, and the final output line 2320 is initialized to the potential of the power supply reference line 2312. Thereafter, the final selection line 2318 in the (j + 1) th column is selected, the final selection transistor 2319 is turned on, and the signal of the load capacitor 2315 in the (j + 1) th column is output to the final output line 2320. Thereafter, the same operation is repeated, and the signals of all the columns are sequentially output to the final output line. Meanwhile, the bias signal line 2310 remains constant. Final output line 23
The signal output to 20 is amplified by the final output amplification circuit 2004 and output to the outside.

Next, the (i + 1) th row gate signal line is selected. Then, the operation is performed in the same manner as when the i-th gate signal line is selected. Further, the gate signal line in the next row is selected, and the same operation is repeated.

Here, the potential of the bias signal line 2310 will be described. In FIG. 23, a plurality of bias transistors 2311 are arranged. Therefore, even if the threshold voltage of the biasing transistor 2311 varies, all the biasing transistors 2311 need to be in a conductive state.
Therefore, the absolute value of the gate-source voltage of the bias transistor needs to be equal to the minimum value of the absolute value of the gate-source voltage necessary for making all the bias transistors conductive.

For sensor units that perform photoelectric conversion, in addition to ordinary PN type photodiodes, PIN type diodes, avalanche type diodes, npn buried type diodes, Schottky type diodes, X-ray photoconductors, infrared rays For example, a sensor may be used. Also,
After converting X-rays into light using a fluorescent material or scintillator, the light may be read.

As described above, the photoelectric conversion element is often connected to the input terminal of the source follower circuit. However, a switch may be interposed between them as in the photogate type. Or you may input the signal after processing so that it may become the logarithm value of light intensity like a logarithmic conversion type | mold to an input terminal.

In the present embodiment, the area sensor in which the pixels are two-dimensionally described has been described, but a line sensor in which the pixels are one-dimensionally arranged can also be realized.

Next, an embodiment in which pre-discharge is performed by controlling a bias signal line in an area sensor in which a driving circuit is mounted in the periphery and pixels are two-dimensionally arranged will be described. The difference from the first embodiment is a part of the circuit diagram (FIG. 23) and a part of the signal timing chart (FIG. 27).
Only. Therefore, FIG. 29 is shown as a diagram corresponding to FIG. As a figure corresponding to FIG.
FIG. 28 is shown.

FIG. 29 is a diagram in which the discharge transistor 2316 and the pre-discharge signal line 2317 are omitted from FIG.

Next, FIG. 28 shows a timing chart of signals in FIG. Since this is a repetitive operation, consider the case where the i-th gate signal line is selected as an example. First, after the gate signal line 2102 in the i-th row is selected, the potential of the bias signal line 2910 and the potential of the transfer transistor 2913 are increased, and pre-discharge is executed. Thereafter, the potential of the bias signal line 2910 is restored.
Then, the signal of each column is output to the load capacitor 2915 of each column from the pixel in the i-th row. Then, after the signals of all the pixels in the i-th row are accumulated in the load capacitors 2915 of each column, the signals of each column are sequentially output to the final output line 2920.

In this embodiment, the bias potential Vb changes during pre-discharge. Therefore, a signal generator may be connected to the bias signal line 2910 in order to change the bias potential Vb.

About the production method when producing the sensor of the present invention on glass using TFT,
This will be described with reference to FIGS.

First, as shown in FIG. 30A, a base film 201 is formed to a thickness of 300 nm over a glass substrate 200. In this embodiment, a silicon nitride oxide film is stacked and used as the base film 201. At this time, the nitrogen concentration in contact with the glass substrate 200 is preferably set to 10 to 25 wt%. In addition, it is effective to provide the base film 201 with a heat dissipation effect, and a DLC (diamond-like carbon) film may be provided.

Next, an amorphous silicon film (not shown) having a thickness of 50 nm is formed on the base film 201 by a known film formation method. Note that the semiconductor film is not limited to an amorphous silicon film, and any semiconductor film including an amorphous structure (including a microcrystalline semiconductor film) may be used. Further, a compound semiconductor film including an amorphous structure such as an amorphous silicon germanium film may be used. The film thickness may be 20 to 100 nm.

Then, the amorphous silicon film is crystallized by a known technique to form a crystalline silicon film (also referred to as a polycrystalline silicon film or a polysilicon film) 202. Known crystallization methods include a thermal crystallization method using an electric furnace, a laser annealing crystallization method using laser light, and a lamp annealing crystallization method using infrared light. In this embodiment, crystallization is performed using excimer laser light using XeCl gas.

In this embodiment, a pulse oscillation type excimer laser beam processed into a linear shape is used. However, a rectangular shape, a continuous oscillation type argon laser beam, or a continuous oscillation type excimer laser beam may be used. .

In this embodiment, a crystalline silicon film is used as an active layer of a TFT, but an amorphous silicon film can also be used.

Note that it is effective to form the active layer of the resetting transistor that needs to reduce the off current from an amorphous silicon film and the active layer of the amplifying transistor from a crystalline silicon film. Since the amorphous silicon film has low carrier mobility, it is difficult for an electric current to flow and an off current is difficult to flow. That is,
Advantages of both an amorphous silicon film that hardly allows current to flow and a crystalline silicon film that easily allows current to flow can be utilized.

Next, as shown in FIG. 30B, a protective film 2 made of a silicon oxide film is formed on the crystalline silicon film 202.
03 is formed to a thickness of 130 nm. This thickness is 100-200 nm (preferably 130
It may be selected in the range of ˜170 nm. Any other film may be used as long as it is an insulating film containing silicon.
This protective film 203 is provided to prevent the crystalline silicon film from being directly exposed to plasma when impurities are added, and to enable fine concentration control.

Then, resist masks 204a, 204b, and 204c are formed thereon, and the protective film 20
Impurity element imparting n-type via 3 (hereinafter referred to as n-type impurity element)
Add. As the n-type impurity element, typically, an element belonging to Group 15 of the periodic table,
Typically, phosphorus or arsenic can be used. In this embodiment, phosphine (PH
₃ ) Using a plasma doping method in which plasma is excited without mass separation, phosphorus is 1 × 10 ¹
Add at a concentration of ⁸ atoms / cm ³ . Of course, an ion implantation method for performing mass separation may be used.

In the n-type impurity regions (b) 205a and 205b formed by this step, an n-type impurity element is 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ (typically 5 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³
) Adjust the dose so that it is included at the concentration of

Next, as shown in FIG. 30C, the protective film 203 and the resist masks 204a and 204b
, 204c are removed, and the added n-type impurity element is activated. As the activation means, a known technique may be used. In this embodiment, activation is performed by irradiation with excimer laser light (laser annealing). Of course, the pulse oscillation type or the continuous oscillation type may be used, and it is not necessary to limit to the excimer laser beam. However, since the purpose is to activate the added impurity element, it is preferable to irradiate with energy that does not melt the crystalline silicon film. Note that laser light may be irradiated with the protective film 203 attached.

When the impurity element is activated by the laser beam, activation by heat treatment (furnace annealing) may be used in combination. When activation by heat treatment is performed, heat treatment at about 450 to 550 ° C. may be performed in consideration of the heat resistance of the substrate.

By this step, the end portions of n-type impurity regions (b) 205a and 205b, that is, the boundary portions (junctions) with regions not added with the n-type impurity element existing around n-type impurity regions (b) 205a and 205b. Part) becomes clear. This is because when the TFT is completed later, the LD
This means that the D region and the channel formation region can form a very good junction.

Next, as shown in FIG. 30D, unnecessary portions of the crystalline silicon film are removed, and island-shaped semiconductor films (hereinafter referred to as active layers) 206 to 210 are formed.

Next, as shown in FIG. 31A, the gate insulating film 211 is covered with the active layers 206 to 210.
Form. The gate insulating film 211 is 10 to 200 nm, preferably 50 to 150.
An insulating film containing silicon with a thickness of nm may be used. This may be a single layer structure or a laminated structure.
In this embodiment, a silicon nitride oxide film having a thickness of 110 nm is used.

Next, a conductive film having a thickness of 200 to 400 nm is formed and patterned to form gate electrodes 212 to
216 is formed. In this embodiment, the gate electrode and the wiring for electrical connection (hereinafter referred to as gate wiring) electrically connected to the gate electrode are formed of the same material. Of course, the gate electrode and the gate wiring may be formed of different materials. Specifically, a material having a lower resistance than the gate electrode may be used as the gate wiring. This is because a material that can be finely processed is used for the gate electrode, and a material that has a low wiring resistance is used for the gate wiring even though it cannot be finely processed. With such a structure, the wiring resistance of the gate wiring can be extremely reduced, so that a sensor portion having a large area can be formed. That is, the above pixel structure is extremely effective in realizing an area sensor having a sensor portion with a screen size of 10 inches or more (or 30 inches or more) diagonally.

The gate electrode may be formed of a single-layer conductive film, but it is preferable to form a stacked film of two layers or three layers as necessary. Any known conductive film can be used as a material for the gate electrodes 212 to 216.

Typically, a film made of an element selected from aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), silicon (Si), or the above Element nitride films (typically tantalum nitride films, tungsten nitride films,
Titanium nitride film) or an alloy film combining the above elements (typically Mo—W alloy, Mo
-Ta alloy), or a silicide film of the element (typically a tungsten silicide film,
Titanium silicide film) can be used. Of course, it may be used as a single layer or may be laminated.

In this embodiment, a stacked film including a tungsten nitride (WN) film having a thickness of 30 nm and a tungsten (W) film having a thickness of 370 nm is used. This may be formed by sputtering. Further, when an inert gas such as Xe or Ne is added as a sputtering gas, peeling of the film due to stress can be prevented.

At this time, the gate electrodes 213 and 216 are n-type impurity regions (b) 205a and 2a, respectively.
It is formed so as to overlap a part of 05b with the gate insulating film 211 interposed therebetween. This overlapped portion later becomes an LDD region overlapping with the gate electrode.

Next, as shown in FIG. 31B, an n-type impurity element (phosphorus in this embodiment) is added in a self-aligning manner using the gate electrodes 212 to 216 as masks. The n-type impurity regions (c) 217 to 224 thus formed have 1/2 to 1/1 of the n-type impurity regions (b) 205a and 205b.
Adjust so that phosphorus is added at a concentration of 0 (typically 1/3 to 1/4). Specifically, a concentration of 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ (typically 3 × 10 ^{17 to} 3 × 10 ¹⁸ atoms / cm ³ ) is preferable.

Next, as shown in FIG. 31C, resist masks 225a to 225c are formed so as to cover the gate electrodes 212, 214, and 215, and an n-type impurity element (phosphorus in this embodiment) is added to form a high concentration. N-type impurity regions (a) 226 to 233 containing phosphorus are formed. Again, the ion doping method using phosphine (PH ₃ ) is used, and the phosphorus concentration in this region is 1 × 10 ²⁰ to
It is adjusted to 1 × 10 ²¹ atoms / cm ³ (typically 2 × 10 ^{20 to} 5 × 10 ²¹ atoms / cm ³ ).

By this step, the source region or drain region of the n-channel TFT is formed. In the n-channel TFT, the n-type impurity region 217 formed in the step of FIG.
218, 222 and 223 are left. This remaining region becomes an LDD region.

Next, as shown in FIG. 31D, the resist masks 225a to 225c are removed, and new resist masks 234a and 234b are formed. Then, a p-type impurity element (boron in this embodiment) is added to form p-type impurity regions 235 and 236 containing boron at a high concentration.
Here, 3 × 10 ^{20 to} 3 × 10 ²¹ atom is formed by ion doping using diborane (B ₂ H ₆ ).
Boron is added so as to have a concentration of s / cm ³ (typically 5 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ ).

Note that phosphorus is already added to the impurity regions 235 and 236 at a concentration of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ , but the boron added here is added at a concentration at least three times higher than that. Is done. Therefore, the n-type impurity region formed in advance is completely inverted to the p-type and functions as a p-type impurity region.

Next, after removing the resist masks 234a and 234b, the n-type or p-type impurity elements added at the respective concentrations are activated. As activation means, furnace annealing method,
Laser annealing or lamp annealing can be used. In this embodiment, heat treatment is performed in an electric furnace in a nitrogen atmosphere at 550 ° C. for 4 hours.

At this time, it is important to eliminate oxygen in the atmosphere as much as possible. This is because the presence of even a small amount of oxygen oxidizes the exposed surface of the gate electrode, leading to an increase in resistance. Therefore, the oxygen concentration in the treatment atmosphere in the activation step is 1 ppm or less, preferably 0.
It is desirable to set it to 1 ppm or less.

Next, as shown in FIG. 32A, a first interlayer insulating film 237 is formed. As the first interlayer insulating film 237, an insulating film containing silicon may be used as a single layer, or a laminated film combined therewith may be used. The film thickness may be 400 nm to 1.5 μm. In this embodiment, 200
A silicon oxide film having a thickness of 800 nm is stacked on a silicon nitride oxide film having a thickness of nm.

Further, a hydrogenation treatment is performed by performing a heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen. This step is a step in which the dangling bonds of the semiconductor film are terminated with hydrogen by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Note that the hydrogenation treatment may be performed while the first interlayer insulating film 237 is formed. That is, 200
After forming a silicon nitride oxide film having a thickness of nm, hydrogenation is performed as described above, and then the remaining 8
A silicon oxide film having a thickness of 00 nm may be formed.

Next, contact holes are formed in the gate insulating film 211 and the first interlayer insulating film 237, and source wirings 238 to 242 and drain wirings 243 to 247 are formed. In this embodiment, this electrode is made of a Ti film of 100 nm, an aluminum film containing Ti of 300 nm, T
A laminated film having a three-layer structure in which an i film of 150 nm is continuously formed by sputtering is used. Of course, other conductive films may be used.

Next, a first passivation film 248 is formed with a thickness of 50 to 500 nm (typically 200 to 300 nm). In this embodiment, the first passivation film 248 is 300 nm.
A thick silicon nitride oxide film is used. This may be replaced by a silicon nitride film. Note that it is effective to perform plasma treatment using a gas containing hydrogen such as H ₂ or NH ₃ prior to formation of the silicon nitride oxide film. Hydrogen excited by this pretreatment is supplied to the first interlayer insulating film 237 and heat treatment is performed, whereby the film quality of the first passivation film 248 is improved. At the same time, hydrogen added to the first interlayer insulating film 237 diffuses to the lower layer side, so that the active layer can be effectively hydrogenated.

Next, as shown in FIG. 32B, a second interlayer insulating film 249 made of an organic resin is formed.
As the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used. In particular, since the second interlayer insulating film 249 has a strong meaning of planarization,
Acrylic having excellent flatness is preferred. In this embodiment, the acrylic film is formed with a film thickness that can sufficiently flatten the step formed by the TFT. The thickness is preferably 1 to 5 μm (more preferably 2 to 4 μm).

Next, the drain wiring 245 is formed on the second interlayer insulating film 249 and the first passivation film 248.
Is formed, and a cathode electrode 250 of the photodiode is formed so as to be in contact with the drain wiring 245. In this embodiment, an aluminum film formed by sputtering is used as the cathode electrode 250, but other metals such as titanium, tantalum, tungsten, and copper can be used.
Alternatively, a laminated film made of titanium, aluminum, or titanium may be used.

Next, an amorphous silicon film containing hydrogen is formed over the entire surface of the substrate and then patterned to form a photoelectric conversion layer 251. Next, a transparent conductive film is formed on the entire surface of the substrate. In this embodiment, ITO having a thickness of 200 nm is formed as a transparent conductive film by a sputtering method. The transparent conductive film is patterned to form the anode electrode 252. (Fig. 32 (C))

Next, as shown in FIG. 33A, a third interlayer insulating film 253 is formed. Third interlayer insulating film 2
By using a resin such as polyimide, polyamide, polyimide amide, or acrylic as 53, a flat surface can be obtained. In this example, a polyimide film having a thickness of 0.7 μm was formed on the entire surface of the substrate as the third interlayer insulating film 253.

Next, a contact hole reaching the anode electrode 252 is formed in the third interlayer insulating film 253, and a sensor wiring 254 is formed. In this embodiment, an aluminum alloy film (an aluminum film containing 1 wt% titanium) is formed to a thickness of 300 nm.

  Thus, a sensor substrate having a structure as shown in FIG. 33B is completed.

270 is an amplifying TFT, 271 is a switching TFT, 272 is a resetting TFT, 27
3 is a bias TFT, and 274 is a discharge TFT.

In this embodiment, the amplification TFT 270 and the bias TFT 273 are n-channel TFTs.
LDD regions 281-2 on both the source region side and the drain region side, respectively.
84. The LDD regions 281 to 284 do not overlap with the gate electrodes 212 and 215 with the gate insulating film 211 interposed therebetween. With the above configuration, the amplification TFT 270 and the bias TFT 273 can reduce hot carrier injection as much as possible.

In this embodiment, the switching TFT 271 and the discharging TFT 274 are n-channel T
The FT has LDD regions 283 and 286 only on the drain region side. The LDD regions 283 and 286 overlap with the gate electrodes 213 and 216 with the gate insulating film 211 interposed therebetween.

The reason why the LDD regions 283 and 286 are formed only on the drain region side is to reduce hot carrier injection and not to reduce the operation speed. Further, the switch 271 and the discharge TFT 274 do not need to worry about the off-current value so much, and it is better to focus on the operation speed than that. Therefore, the LDD regions 283 and 286 are completely formed in the gate electrode 2.
13 and 216, and it is desirable to reduce the resistance component as much as possible. That is, it is better to eliminate the so-called offset.
In particular, when the source signal line drive circuit or the gate signal line drive circuit is driven at 15 V to 20 V, the above-described configuration of the discharge TFT 274 of this embodiment is effective for reducing hot carrier injection and not reducing the operation speed. It is.

In this embodiment, the reset TFT 272 is a p-channel TFT and does not have an LDD region. In the p-channel TFT, since deterioration due to hot carrier injection is hardly noticed, it is not particularly necessary to provide an LDD region. Of course, like n-channel TFT, LD
It is also possible to provide a D region and take measures against hot carriers. Reset TFT
272 may be an n-channel TFT.

Further, a connector (flexible printed circuit: FPC) for connecting a terminal routed from an element or circuit formed on the substrate and an external signal terminal is attached to complete the product.

Note that in this embodiment, a sensor is manufactured using a TFT or a photodiode on glass, but a sensor can be manufactured using a transistor on a single crystal silicon substrate.

A sensor formed by implementing the present invention can be used in various electronic devices. Examples of such an electronic device of the present invention include a scanner, a digital still camera, an X-ray camera, a portable information terminal (mobile computer, mobile phone, portable game machine), a notebook personal computer, a game device, a video phone, and the like. Can be mentioned.

FIG. 34A shows a scanner, which includes a reading area 3402, a sensor portion 3401, a reading start switch 3403, and the like. The present invention can be used for the sensor portion 3401.

FIG. 34B shows a digital still camera, which includes a finder 3405, a sensor portion 3404, a shutter button 3406, and the like. The present invention can be used for the sensor portion 3404.

FIG. 35 shows an X-ray camera, which includes an X-ray generator 3501, a sensor unit 3503, and a signal processing computer 35.
Including 04. A measurement object 3502 enters between the X-ray generator 3501 and the sensor unit 3503, and an X-ray photograph is taken. The present invention can be used for the sensor portion 3503.

FIG. 36 shows a personal computer, which includes a main body 3601, a housing 3602, a display device 3603, a keyboard 3604, a sensor portion 3605, and the like. The present invention relates to a display device 3603 and a sensor unit 360.
5 can be used.

Here, FIG. 37 shows a mobile phone, which includes a main body 3701, an audio output unit 3702, an audio input unit 3703, a display device 3704, operation switches 3705, an antenna 3706, and a sensor unit 3707. The present invention can be used for the sensor portion 3707.

101 Amplifying transistor
102 Bias transistor
103 Amplified power line
104 Bias side power line
105 Input terminal
106 Bias signal line
107 Output terminal
108 Discharge transistor
109 Discharge power line
110 Load capacity
111 Power line for load capacity

Claims (43)

A semiconductor device having an amplifying transistor, a biasing transistor, an amplifying side power line, a bias side power line, a bias signal line, a discharging transistor, and a discharging power line,
The drain terminal of the amplification transistor is connected to the amplification-side power line,
A source terminal of the bias transistor is connected to the bias-side power line;
A source terminal of the amplifying transistor is connected to a drain terminal of the biasing transistor;
A gate terminal of the bias transistor is connected to the bias signal line;
The gate terminal of the amplifying transistor is an input terminal,
The source terminal of the amplifying transistor is an output terminal,
One of the output terminal and the discharge power supply line is connected to the source terminal of the discharge transistor, and the other is connected to the drain terminal of the discharge transistor. A semiconductor device having an amplifying transistor, a biasing transistor, an amplifying side power line, a bias side power line, and a bias signal line,
The drain terminal of the amplification transistor is connected to the amplification-side power line,
A source terminal of the bias transistor is connected to the bias-side power line;
A source terminal of the amplifying transistor is connected to a drain terminal of the biasing transistor;
A gate terminal of the bias transistor is connected to the bias signal line;
The gate terminal of the amplifying transistor is an input terminal,
The source terminal of the amplifying transistor is an output terminal,
A semiconductor device, characterized in that a signal generator that operates so as to bring the potential of the bias side power supply line closer to the potential of the amplification side power supply line is connected to the bias signal line. In claim 1 or claim 2,
One terminal of the load capacity is connected to the output terminal,
A semiconductor device, wherein the other terminal of the load capacitor is connected to a load capacitor power line. In any one of Claim 1 or Claim 3,
A semiconductor device, wherein the discharge power supply line and the bias side power supply line are connected. In claim 3,
A semiconductor device, wherein at least two of the discharge power supply line, the load capacity power supply line, and the bias side power supply line are connected. In any one of Claim 3 or Claim 5,
The semiconductor device, wherein the load capacitor power line is connected to the amplification side power line. In any one of Claims 3 thru | or 6,
A semiconductor device comprising at least one selection switch for controlling a current flowing from the amplification side power supply line or the bias side power supply line to the load capacitor or the output terminal. In any one of Claim 1 thru | or Claim 7,
A semiconductor device having at least one selection switch for controlling a current flowing from the amplification side power supply line or the bias side power supply line to the output terminal. In claim 7 or claim 8,
The semiconductor device, wherein the selection switch includes at least one of an N-channel transistor or a P-channel transistor. In any one of Claims 1 thru | or 9,
A semiconductor device, wherein an absolute value of a gate-source voltage of the biasing transistor is equal to a minimum value of an absolute value of a gate-source voltage necessary for making the biasing transistor conductive. In any one of Claims 1 to 10,
A semiconductor device, wherein a photoelectric conversion element is connected to the input terminal. In any one of Claims 1 to 10,
A semiconductor device, wherein a signal generated by a photoelectric conversion element is input to the input terminal. In claim 11 or claim 12,
The semiconductor device, wherein the photoelectric conversion element is an X-ray sensor or an infrared sensor. In claim 11 or claim 12,
The semiconductor device, wherein the photoelectric conversion element is any one of a photodiode, a Schottky diode, an avalanche diode, or a photoconductor. In claim 14,
The semiconductor device is characterized in that the photodiode is one of a PN type, a PIN type, and an NPN buried type. In any one of Claims 11 thru | or 15,
It has a reset transistor,
A semiconductor device, wherein a source terminal or a drain terminal of the reset transistor is connected to the photoelectric conversion element. In any one of Claims 1 thru | or 16,
When there are a plurality of the bias transistors, the absolute values of the gate-source voltages of the plurality of bias transistors are the absolute values of the gate-source voltages necessary for making all of the plurality of bias transistors conductive. A semiconductor device characterized by being equal to a minimum value. In claim 1, or any one of claims 3 to 17,
The semiconductor device, wherein the amplifying transistor, the biasing transistor, and the discharging transistor are transistors having the same polarity. An amplification transistor, a bias transistor, an amplification power line, a bias power line, and a bias signal line;
The drain terminal of the amplification transistor is connected to the amplification-side power line,
A source terminal of the bias transistor is connected to the bias-side power line;
A source terminal of the amplifying transistor is connected to a drain terminal of the biasing transistor;
A gate terminal of the bias transistor is connected to the bias signal line;
The gate terminal of the amplifying transistor is an input terminal,
In the method for driving a semiconductor device in which the source terminal of the amplifying transistor is an output terminal,
A method for driving a semiconductor device, comprising: outputting a signal after performing pre-discharge. An amplification transistor, a bias transistor, an amplification power line, a bias power line, and a bias signal line;
The drain terminal of the amplification transistor is connected to the amplification-side power line,
A source terminal of the bias transistor is connected to the bias-side power line;
A source terminal of the amplifying transistor is connected to a drain terminal of the biasing transistor;
A gate terminal of the bias transistor is connected to the bias signal line;
The gate terminal of the amplifying transistor is an input terminal,
In the method for driving a semiconductor device in which the source terminal of the amplifying transistor is an output terminal,
A method for driving a semiconductor device, comprising: performing pre-discharge by bringing the potential of the bias side power supply line close to the potential of the amplification side power supply line and then outputting a signal. An amplification transistor, a bias transistor, an amplification side power line, a bias side power line, a bias signal line, a discharge transistor, and a discharge power line;
The drain terminal of the amplification transistor is connected to the amplification-side power line,
A source terminal of the bias transistor is connected to the bias-side power line;
A source terminal of the amplifying transistor is connected to a drain terminal of the biasing transistor;
A gate terminal of the bias transistor is connected to the bias signal line;
The gate terminal of the amplifying transistor is an input terminal,
The source terminal of the amplifying transistor is an output terminal,
In the method of driving a semiconductor device, one of the output terminal and the discharge power supply line is connected to a source terminal of the discharge transistor and one is connected to a drain terminal of the discharge transistor.
A method for driving a semiconductor device comprising: outputting a signal after performing pre-discharge by bringing the discharging transistor into a conductive state. In claim 21,
A driving method of a semiconductor device, wherein the potential of the discharge power supply line takes a value between the potential of the bias signal line and the potential of the bias side power supply line. In any one of Claim 19 thru | or Claim 22,
One terminal of the load capacity is connected to the output terminal,
A method for driving a semiconductor device, wherein the other terminal of the load capacitor is connected to a load capacitor power line. In any one of Claim 21 or Claim 22,
A method for driving a semiconductor device, comprising: connecting the discharge power line and the bias power line. In claim 23,
A method for driving a semiconductor device, comprising connecting at least two of the discharge power line, the load capacity power line, or the bias side power line. In any one of Claim 23 or Claim 25,
A method for driving a semiconductor device, wherein the load capacitor power line is connected to the amplification-side power line. In any one of claims 23 to 26,
A method for driving a semiconductor device, comprising: at least one selection switch for controlling a current flowing from the amplification-side power supply line or the bias-side power supply line to the load capacitance or the output terminal. In any one of Claim 19 thru | or Claim 26,
A method for driving a semiconductor device, comprising: at least one selection switch for controlling a current flowing from the amplification side power supply line or the bias side power supply line to the output terminal. In claim 27 or claim 28,
The method for driving a semiconductor device, wherein the selection switch includes at least one of an N-channel transistor and a P-channel transistor. 30.In any one of claims 19 to 29,
Driving a semiconductor device, characterized in that the absolute value of the gate-source voltage of the bias transistor is equal to the minimum value of the absolute value of the gate-source voltage necessary for making the bias transistor conductive. Method. A device according to any one of claims 19 to 30.
A method for driving a semiconductor device, wherein a photoelectric conversion element is connected to the input terminal. A device according to any one of claims 19 to 30.
A method for driving a semiconductor device, wherein a signal generated by a photoelectric conversion element is input to the input terminal. In claim 31 or claim 32,
The method for driving a semiconductor device, wherein the photoelectric conversion element is an X-ray sensor or an infrared sensor. In claim 31 or claim 32,
The method for driving a semiconductor device, wherein the photoelectric conversion element is any one of a photodiode, a Schottky diode, an avalanche diode, or a photoconductor. In claim 34,
The method of driving a semiconductor device, wherein the photodiode is one of a PN type, a PIN type, and an NPN buried type. 36. In any one of claims 31 to 35,
It has a reset transistor,
A method for driving a semiconductor device, wherein the resetting transistor resets the photoelectric conversion element. In any one of claims 19 to 36,
When there are a plurality of the bias transistors, the absolute values of the gate-source voltages of the plurality of bias transistors are the absolute values of the gate-source voltages necessary for making all of the plurality of bias transistors conductive. A method for driving a semiconductor device, characterized by being equal to a minimum value. In any one of claims 21 to 37,
A method for driving a semiconductor device, wherein the amplifying transistor, the biasing transistor, and the discharging transistor are transistors having the same polarity.   A scanner using the semiconductor device according to any one of claims 1 to 18.   A digital still camera using the semiconductor device according to any one of claims 1 to 18.   An X-ray camera using the semiconductor device according to any one of claims 1 to 18.   A portable information terminal using the semiconductor device according to any one of claims 1 to 18.   A computer using the semiconductor device according to any one of claims 1 to 18.

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