JP2001308306A - Semiconductor device and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that can reduce the influence of current leaking from a transistor for resetting to a photoelectric conversion element, and the driving method of the semiconductor device. SOLUTION: In this semiconductor device and its driving method, the semiconductor device has the transistor for resetting, the photoelectric conversion element, and reset- and diode-side power lines, and the potential of the reset-side power line is brought closer to that of the diode-side power line when the transistor for resetting does not conduct electricity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device and a driving method thereof. More specifically, the present invention relates to a MOS sensor device having an image sensor function and a driving method thereof.

[0002]

2. Description of the Related Art In recent years, information devices such as personal computers have become widespread, and demands for reading various information as electronic information into personal computers and the like have increased. For this reason, digital still cameras have attracted much attention as alternatives to conventional silver halide cameras, and scanners as means for reading objects printed on paper or the like.

In a digital still camera, an area sensor in which pixels are two-dimensionally arranged is used. Scanners, copiers, and the like use a line sensor in which pixels are arranged one-dimensionally. When reading a two-dimensional image using a line sensor, signals are read while moving the line sensor.

In these image reading devices, CCD type sensors are mainly used as image sensors. In a CCD sensor, photoelectric conversion is performed by a photodiode of each pixel, and the signal is read using a CCD. However, in recent years, there has been one type of MOS sensor manufactured using a single-crystal silicon substrate, taking advantage of the fact that peripheral circuits can be built-in, that it can be integrated into one chip, that it is suitable for real-time signal processing, and that power consumption is low. The department is showing signs of spread. At the research level, a MOS type sensor formed using a TFT on a glass substrate has also been developed. In the MOS sensor, photoelectric conversion is performed by a photodiode of each pixel, and a signal of each pixel is read using a switch formed by a MOS transistor.

Various types of pixel configurations have been developed for the MOS type sensor. They are divided into two types: passive sensors and active sensors.
They can be roughly classified. The passive sensor is a sensor that does not have a signal amplifying element mounted on each pixel, and the active sensor is a sensor that has a signal amplifying element mounted on each pixel.
Active sensors have the advantage of being more resistant to noise than passive sensors because signals are amplified in each pixel.

FIG. 3 shows a circuit example of a pixel in a passive sensor. The pixel 305 includes a switching transistor 301 and a photodiode 304. The photodiode 304 includes a power supply reference line 306 and the switch transistor 30.
1 is connected to the source terminal. A gate signal line 302 is connected to a gate terminal of the switching transistor 301, and a signal output line 303 is connected to a drain terminal. In the photodiode 304, photoelectric conversion is performed.
That is, charges are generated in accordance with the incident light, and the charges are stored therein. Then, the gate signal line 302 is controlled to make the switching transistor 301 conductive, and the charge of the photodiode 304 is read out through the signal output line 303.

[0007] As a configuration of the pixel of the active sensor,
There are various types. IEDM95: p17: CMOS Image Sensor
s, Electronic Camera On a Chip or IEDM97: p2
01: CMOS Image Sensors-Recent Advances and Devic
e Scaling Considerations, photodiode type,
It introduces the pixel configuration and operation of the photo gate type and so on.
ISSCC97: p180: A 1/4 Inch 330k Square Pixel Progr
In the essive Scan CMOS Active Pixel Image Sensor, pixel configurations are classified in terms of pixel selection method. That is, the case where a transistor or a capacitor is used as an element to be selected is described. As described above, there are various types regarding the number of transistors forming one pixel. JIEC Seminar: Prospects for CMOS Camera Development: On February 20, 1998, a general introduction to CMOS sensors was introduced, and the logarithm of light intensity was obtained by connecting the gate and drain electrodes of a reset transistor. It also describes a logarithmic conversion type that outputs the above signal.

As shown in FIG. 4, the most commonly employed pixel configuration of an active sensor is one pixel 408 composed of three N-channel transistors and one photodiode.
Is the type that constitutes The P channel side terminal of the photodiode 404 is connected to the power supply reference line 412, and the N channel side terminal is connected to the gate terminal of the amplification transistor 406. The power supply line 409 and the switching transistor 401
Is connected to the drain terminal. A gate signal line 402 is connected to a gate terminal of the switching transistor 401, and a signal output line 403 is connected to a source terminal. The gate terminal of the reset transistor 407 is connected to the reset signal line 405. The source terminal and the drain terminal of the reset transistor 407 are connected to the power supply line 409 and the gate terminal of the amplification transistor 406.

In the case of an area sensor, one signal output line 40
3, not only one pixel 408 but also many pixels are connected. However, the bias transistor 411 is
Only one signal output line 403 is arranged.
A bias signal line 410 is connected to a gate terminal of the bias transistor 411. A source terminal and a drain terminal of the bias transistor 411 are connected to a signal output line 403 and a bias power supply line 413.

Next, the basic operation of the pixel 408 will be described.

First, the reset transistor 407 is turned on. The P channel side terminal of the photodiode 404 is connected to the power supply reference line 412, and the N channel side terminal is connected to the power supply line 4.
09 is electrically connected, the potential of the power supply reference line 412 is the reference potential 0 V, and the potential of the power supply line 409 is the power supply potential Vd.
Since it is d, a reverse bias voltage is applied to the photodiode 404. Hereinafter, an operation in which the potential of the N-channel terminal of the photodiode 404 is charged to the potential of the power supply line 409 is referred to as reset. After that, the reset transistor 407 is turned off. Then, when light is emitted to the photodiode 404,
Electric charges are generated by photoelectric conversion. Therefore, as time passes, the potential of the N-channel terminal of the photodiode 404, which has been charged to the potential of the power supply line 409, gradually decreases due to charge generated by light. After a certain period of time, the switching transistor 401 is turned on. Then
A signal is output to the signal output line 403 through the amplification transistor 406.

However, when a signal is being output, a potential is applied to the bias signal line 410, and a current flows through the bias transistor 411. Therefore, the amplification transistor 406 and the bias transistor 411 operate as a so-called source follower circuit.

In FIG. 4, the wiring to which the P-channel terminal of the photodiode 404 is connected, that is, the power supply reference line 41 is shown.
2 may be called a diode-side power supply line. The potential of the diode-side power supply line changes depending on the direction of the photodiode 404. In FIG. 4, the P-channel terminal of the photodiode 404 is connected to the diode-side power supply line, and its potential is the reference potential 0V. Therefore, in FIG. 4, the diode-side power supply line is called a power supply reference line.

Similarly, in FIG. 4, the wiring to which the reset transistor 407 is connected, that is, the power supply line 409 may be called a reset-side power supply line. The potential of the reset-side power supply line changes depending on the direction of the photodiode 404. Figure 4
Then, the reset side power line has a reset transistor
The N-channel side terminal of the photodiode 404 is connected via 407, and its potential is the power supply potential Vdd. Therefore, in FIG. 4, the reset-side power supply line is called a power supply line.

Resetting the photodiode 404 is the same as applying a reverse bias voltage to the photodiode 404. Therefore, the magnitude relationship between the potentials of the diode-side power line and the reset-side power line changes depending on the orientation of the photodiode 404.

Next, FIG. 5 shows an example of the most basic source follower circuit. FIG. 5 illustrates a case where an N-channel transistor is used. A source follower circuit can be formed using P-channel transistors. The power supply potential Vdd is applied to the amplification-side power supply line 503. A reference potential of 0 V is applied to the bias-side power supply line 504. The drain terminal of the amplification transistor 501 is connected to the amplification-side power supply line 503, and the source terminal is connected to the drain terminal of the bias transistor 502. The source terminal of the bias transistor 502 is connected to the bias side power line 504
It is connected to the. A bias potential Vb is applied to a gate terminal of the bias transistor 502. Therefore, the bias current Ib
Will flow. The bias transistor 502
Basically, it operates as a constant current source. The gate terminal of the amplification transistor 501 becomes the input terminal 506. Therefore,
The input terminal Vin is connected to the gate terminal of the transistor 501 for amplification.
Is added. The source terminal of the amplification transistor 501 becomes the output terminal 507. Therefore, the potential of the source terminal of the amplification transistor 501 becomes the output potential Vout. The input / output relationship of the source follower circuit at this time is Vout = Vin−Vb.

4 and FIG. 5, the amplifying transistor 406 corresponds to the amplifying transistor 501. The bias transistor 411 includes a bias transistor 502
Corresponding to Since the switching transistor 401 is assumed to be in a conductive state, it can be considered to be omitted in FIG. N of photodiode 404
The potential of the channel side terminal corresponds to the input potential Vin (the gate potential of the amplification transistor 501, that is, the potential of the input terminal 506). The potential of the signal output line 403 is equal to the output potential Vout (the source potential of the amplifying transistor 501, that is, the output terminal 507).
Potential). The power supply line 409 corresponds to the amplification-side power supply line 503.

Therefore, in FIG.
The potential of the N-channel side terminal of 04 is Vpd, the potential of the bias signal line 410, that is, the bias potential is Vb, the potential of the signal output line 403 is Vout, and the potentials of the power supply reference line 412 and the bias side power supply line 413 are Assuming 0V, Vout = Vpd-Vb. Therefore, the potential V of the N-channel side terminal of the photodiode 404
When pd changes, Vout also changes, so that the change in Vpd is output as a signal, and the light intensity can be read.

Next, a signal timing chart at the pixel 409 is shown in FIG. First, the reset transistor 407 is turned on by controlling the reset signal line 405. Then, the potential of the N-channel side terminal of the photodiode 404 is charged to the power supply potential Vdd which is the potential of the power supply line 409. That is, the pixels are reset. Then, the reset transistor 407 is turned off by controlling the reset signal line 405. After that, when the photodiode 404 is irradiated with light, charges corresponding to the light intensity are generated. Therefore, the electric charge charged by the reset operation is gradually discharged. That is,
The potential of the N-channel side terminal of the photodiode 404 decreases. When dark light is applied, the amount of discharge is small, and the potential of the N-channel side terminal of the photodiode 404 does not decrease much. At some point, the switching transistor 401 is turned on,
The potential of the N-channel side terminal of the photodiode 404 is read as a signal. This signal is proportional to the light intensity. Then, the reset transistor 407 is turned on again to reset the photodiode 404, and the same operation is repeated.

Next, a transistor in the pixel 408 will be described. Regarding polarity, all are often of the N-channel type. In rare cases, the reset transistor may be a P-channel type (JIEC Seminar: Prospects for CMOS Camera Development: February 20, 1998: p9, see FIG. 11). As for the arrangement of the amplifying transistor and the selecting transistor, both transistors are of the N-channel type, and the power supply line 409 and the amplifying transistor 406 are connected as shown in FIG. In many cases, the switching transistor 401 is connected to the switching transistor 401 and the signal output line 403. Rarely, both transistors have N
In some cases, the power supply line 409 and the switching transistor 401 are connected, the switching transistor 401 and the amplification transistor 406 are connected, and the amplification transistor 406 and the signal output line 403 are connected using a channel type (ISSCC97). : P18
0: A 1/4 Inch 330k Square Pixel Progressive Scan
CMOS Active Pixel Image Sensor).

Next, a sensor unit for performing photoelectric conversion and the like will be described. Usually, light is converted into electricity using a PN type photodiode. Other examples include a PIN diode, an avalanche diode, an npn buried diode, and a Schottky diode. In addition, there are photoconductors for X-rays and sensors for infrared rays. This is described in Fundamentals of solid-state imaging devices: The mechanism of electronics: Takao Ando and Hirohito Kobuchi: Nippon Riko Publishing Co., Ltd.

Next, products to which the sensor is applied will be described. It is used for X-ray cameras in addition to ordinary digital still cameras and scanners. In such a case, a photoconductor that directly converts X-rays into an electric signal is used, or X-rays are converted into light by a fluorescent material or a scintillator, and then the light is read. Euro Display
99: p203: X-ray Detectors based on Amorphous Silicon
Active Matrix describes a case where a scintillator converts X-rays into light and then reads the light. IEDM 98: p21: amorphous silicon tft x-ray image
Sensors read using amorphous silicon, AM-LCD99: p45: real-time imaging flat panal
An x-ray detector has been reported for reading using a photoconductor.

[0023]

The potential of the conventional power supply line 409 is constant. On the other hand, the reset transistor 407
When light is irradiated when is off, charges are generated in the photodiode 404. Due to the charge, the charge charged by the reset operation is discharged. As a result, the potential of the N-channel side terminal of the photodiode 404 decreases. The situation at this time will be considered from the standpoint of the reset transistor 407.

A decrease in the potential of the N-channel terminal of the photodiode 404 means that the reset transistor
This is equivalent to an increase in the source-drain voltage Vds of 407. Here, FIG. 7 shows current characteristics of a general transistor at this time. The horizontal axis indicates the gate-source voltage Vgs, and the vertical axis indicates the logarithm of the drain-source current Ids. Then, a plurality of graphs are shown using the source-drain voltage Vds as a parameter. As can be seen from FIG. 7, the non-conductive state (gate-source voltage Vgs <
In the region 0), when the source-drain voltage Vds increases, that is, when the potential of the N-channel side terminal of the photodiode 404 decreases, the leakage current increases. Ideally, the source-to-source current Ids does not flow, so the drain-source current Ids that flows in the non-conductive state
This is sometimes called leakage current.) Therefore, the figure
As shown in FIG. 8, through the reset transistor 807,
A leak current 814 flows through the photodiode 804.
This leakage current 814 is transferred from the power line 809 to the photodiode 80.
4 and acts to bring the potential of the N-channel terminal of the photodiode 804 closer to the potential of the power supply line 809.
As a result, as shown in FIG.
It becomes difficult for the potential of the channel side terminal to drop.

Taking the above into consideration, the following problems are conceivable regarding the leakage current of the reset transistor 807.

First, assuming that the amount of charge per unit time generated by light in the photodiode 804 is Iphoto, if the light applied to the photodiode 804 is weak, the Iphoto leaks and is smaller than the current 814. . In such a case, no matter how much time passes, the potential of the photodiode 804 does not decrease. Therefore, in the case of weak light, it is considered that no signal can be obtained at all.

As can be seen from FIG. 7, the leakage current 814
Depends on the potential of the N-channel terminal of the photodiode 804 (that is, the voltage between the source and drain of the reset transistor 807). Therefore, the photodiode 80
The relationship between the potential of the N-channel side terminal 4 and the storage time becomes non-linear. Here, the accumulation time is a time period from the time when the photodiode 804 is reset to the time when the switching transistor 801 is turned on to output a signal. This is the period during which the accumulated charge is stored. If there is no leakage current 814, the potential of the N-channel terminal of the photodiode 804 decreases with time, and the relationship between the potential of the N-channel terminal of the photodiode 804 and the accumulation time becomes linear. However, when there is a leakage current 814, the potential of the N-channel terminal of the photodiode 804 decreases with time, but when the potential of the N-channel terminal of the photodiode 804 decreases, the leakage current of the reset transistor 807 decreases. Becomes larger. Therefore, the potential of the N-channel side terminal of the photodiode 804 does not easily decrease. Therefore, the relationship between the potential of the N-channel terminal of the photodiode 804 and the storage time is not linear. As a result, the relationship between the potential of the photodiode 804 and the light intensity becomes non-linear, and the gamma characteristics of the image sensor deteriorate.

More specifically, as shown in FIG. 10, as a result of the light, the potential of the N-channel terminal of the photodiode 804 is reduced by light, that is, the source-drain voltage Vds of the reset transistor 807 is reduced. As a result, the leakage current 814 may be equal to the charge Iphoto generated by light per unit time. In such a state, the photodiode
The potential of the N-channel terminal 804 does not decrease. In the case where there is no leakage current 814, even if the light is weak, the potential of the N-channel side terminal of the photodiode 804 can be reduced by increasing the time for accumulating the charge generated by the light. That is, the signal value could be increased. However, when the leakage current 814 is equal to the charge Iphoto generated per unit time generated by light, the potential of the N-channel side terminal of the photodiode 804 can be increased even if the time for storing the charge generated by light is lengthened. It does not change. Therefore, the signal value cannot be increased by increasing the accumulation time.

An object of the present invention is to solve the above-mentioned problems of the prior art.

[0030]

Conventionally, with respect to the source terminal or the drain terminal of a reset transistor, a wiring to which a terminal that is not connected to a photodiode is connected, that is, a power supply line (reset side) The potential of the power line was constant. In the present invention, at the time other than the reset operation, with respect to the source terminal or the drain terminal of the reset transistor, the potential value of the wiring to which the terminal which is not connected to the photodiode is connected, that is, the power supply line (the reset line) The potential of the power supply line is brought closer to the potential of the P-channel terminal of the photodiode, that is, the potential of the power supply reference line (diode-side power supply line). As a result, leakage current hardly flows from the power supply line (reset-side power supply line) to the photodiode.

When the potential of the N-channel terminal of the photodiode is higher than the potential of the power supply line, a leakage current flows from the photodiode to the power supply line. Therefore, the potential of the N-channel side terminal of the photodiode tends to decrease. When the potential of the N-channel side terminal of the photodiode is
Even when the potential is lower than the potential of the power supply line, the leakage current is smaller than in the related art because the source-drain voltage of the reset transistor is smaller. Therefore, the photodiode
It is possible to prevent the potential of the N-channel side terminal from becoming difficult to fall.

However, when the photodiode is reset, a potential for charging is required. Therefore,
At the time of reset operation, the potential of the wiring to which the terminal which is not connected to the photodiode is connected with the source terminal or the drain terminal of the reset transistor, that is, the potential value of the power supply line (reset-side power supply line) is , In the same manner as in the prior art.

As shown in FIG. 11, the power supply line 1109 (reset-side power supply line) is often connected to not only the resetting transistor 1107 but also the amplifying transistor 1106 and the switching transistor 1101. In that case, a problem arises when the potential of the power supply line 1109 (reset-side power supply line) is low when the amplifier transistor 1106 is operated by flowing a current. Therefore, power supply line 1109 (reset side power supply line)
Amplifying transistor 1106 and switching transistor 11
When 01 is also connected, the potential value of the power supply line 1109 (reset-side power supply line) is kept the same as in the related art while the amplifying transistor 1106 is operating.

As described above, by bringing the potential of the power supply line 1109 (reset-side power supply line) closer to the potential of the power supply reference line 1112 (diode-side power supply line), the reset transistor 11
07 The problem caused by leakage current can be improved. Therefore, even when the light applied to the photodiode 1104 is weak, the leakage current of the resetting transistor 1107 does not cancel the charge Iphoto generated per unit time by light in the photodiode 1104. Therefore, even in the case of weak light, the photodiode 1104 is discharged and its potential decreases, so that a signal can be read from the pixel. Thereby, the dynamic range is widened and the image quality is improved. In addition, since the leak current is reduced by reducing the source-drain voltage of the reset transistor, the nonlinear relationship between the potential of the photodiode 1104 and the storage time is improved. As a result, the gamma characteristics are improved.

The configuration of the present invention will be described below. According to the present invention, a semiconductor device having a reset transistor, a photoelectric conversion element, a reset-side power line, a diode-side power line, a reset signal line, and an amplifying transistor according to the above configuration, wherein a gate terminal of the reset transistor is A reset signal line, one of a drain terminal and a source terminal of the reset transistor is connected to the reset side power supply line, and the other is connected to the photoelectric conversion element, and the photoelectric conversion element Is connected to the diode-side power line, and the other terminal is connected to a source terminal or a drain terminal of the reset transistor, and is connected to a source terminal or a drain terminal of the reset transistor. A terminal connected to the photoelectric conversion element is connected to the amplification transistor. The gate terminal of Njisuta are connected,
A semiconductor device is provided, wherein the reset-side power supply line and the reset signal line are arranged in parallel.

According to the present invention, there is provided a semiconductor device having a reset transistor, a photoelectric conversion element, a reset-side power line, a diode-side power line, a reset signal line, an amplifying transistor, and a signal generator. A gate terminal of the reset transistor is connected to the reset signal line, one of a drain terminal and a source terminal of the reset transistor is connected to the reset power supply line, and the other is connected to the photoelectric conversion element. One terminal of the photoelectric conversion element is connected to the diode-side power line, the other terminal,
A gate terminal of the amplification transistor is connected to a source terminal or a drain terminal of the reset transistor, and a terminal connected to the source terminal or the drain terminal of the reset transistor and the photoelectric conversion element. And a signal generator operable to bring the potential of the reset-side power supply line closer to the potential of the diode-side power supply line is connected to the reset-side power supply line. .

According to the present invention, the above-described configuration has a reset transistor, a photoelectric conversion element, a reset-side power line, a diode-side power line, and a reset signal line, and a gate terminal of the reset transistor is connected to the reset signal line. One of a drain terminal and a source terminal of the reset transistor is connected to the reset-side power supply line, the other is connected to the photoelectric conversion element, and one terminal of the photoelectric conversion element is , The other terminal is connected to a source terminal or a drain terminal of the reset transistor, and when the reset transistor is non-conductive, the reset power line is The potential of the semiconductor device closer to the potential of the diode-side power supply line. A method is provided.

According to the above configuration, the present invention has a reset transistor, a photoelectric conversion element, a reset-side power line, a diode-side power line, and a reset signal line, and a gate terminal of the reset transistor is connected to the reset signal line. One of a drain terminal and a source terminal of the reset transistor is connected to the reset-side power supply line, the other is connected to the photoelectric conversion element, and one terminal of the photoelectric conversion element is A driving method of a semiconductor device, wherein the other terminal is connected to the source terminal or the drain terminal of the reset transistor, and the other terminal is connected to the diode-side power line. ,
A method for driving a semiconductor device is provided, wherein a potential of the reset-side power supply line is set to an intermediate potential between a potential when the reset transistor is in a conductive state and a potential of the diode-side power supply line.

According to the present invention, the reset transistor, the photoelectric conversion element, the reset-side power line, the diode-side power line, the reset signal line, and the amplifying transistor have the above-described configuration, and the gate terminal of the reset transistor is the reset terminal. Connected to a signal line, one of a drain terminal and a source terminal of the reset transistor is connected to the reset-side power supply line, and the other is connected to the photoelectric conversion element. One terminal is connected to the diode-side power line, the other terminal is connected to a source terminal or a drain terminal of the reset transistor, and the source terminal or the drain terminal of the reset transistor is connected to the reset terminal. The amplifying transistor is connected to a terminal connected to the photoelectric conversion element. Wherein the potential of the reset-side power supply line is made closer to the potential of the diode-side power supply line when the reset transistor is in a non-conductive state. Is provided.

According to the present invention, the present invention has a reset transistor, a photoelectric conversion element, a reset-side power line, a diode-side power line, a reset signal line, and an amplifying transistor, wherein the gate terminal of the reset transistor is the reset terminal. Connected to a signal line, one of a drain terminal and a source terminal of the reset transistor is connected to the reset-side power supply line, and the other is connected to the photoelectric conversion element. One terminal is connected to the diode-side power line, the other terminal is connected to a source terminal or a drain terminal of the reset transistor, and the source terminal or the drain terminal of the reset transistor is connected to the reset terminal. The amplifying transistor is connected to a terminal connected to the photoelectric conversion element. In the method of driving a semiconductor device to which the gate terminal is connected, when the reset transistor is in a non-conductive state, the potential of the reset-side power supply line is set to the potential when the reset transistor is in a conductive state and the potential of the diode side. There is provided a method for driving a semiconductor device, wherein the potential of the semiconductor device is set to an intermediate potential between the power supply lines.

[0041] The photoelectric conversion element may be an X-ray sensor or an infrared sensor.

The photoelectric conversion element is a photodiode,
It may be one of a Schottky diode, an avalanche diode, and a photoconductor.

The photodiode is a PN type, a PIN type,
Alternatively, it may be characterized by one of the NPN embedded type.

[0044]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment 1] Hereinafter, representative embodiments of the present invention will be described. First, FIG. 1 is a circuit diagram and FIG. 2 is a timing chart of an embodiment of the present invention when an active sensor is used.

The circuit diagram is the same as the conventional one. However, the reset-side power supply line 109 and the amplification-side power supply line 108 are conventionally connected in many cases. In the present embodiment, either connected or not connected may be used. First, a timing chart of a case where the connection is not performed will be described.

First, the reset signal line 105 is controlled to make the reset transistor 107 conductive, and the photodiode 104 is reset. After that, the reset transistor 107 is turned off and the storage time starts. At this time, the potential of the reset-side power supply line 109 is lowered to approach the potential of the diode-side power supply line 110. At that time, the most desirable potential of the reset-side power supply line 109 is an intermediate potential between the potential of the reset-side power supply line 109 at the time of reset and the potential of the diode-side power supply line 110.

Then, in the case of darkness, the photodiode 104
Is higher than the potential of the reset-side power supply line 109, the leakage current is
Flows to the reset-side power line 109 from the Therefore, even at darkness, the potential of the N-channel side terminal of the photodiode 104 tends to decrease.

In a bright case, the potential of the N-channel side terminal of the photodiode 104 changes as time passes.
Come down. Initially, the potential of the N-channel side terminal of the photodiode 104 is higher than the potential of the reset-side power supply line 109, so that leakage current flows from the photodiode 104 to the reset-side power supply line 109. Then, the potential of the N-channel side terminal of the photodiode 104
The potential of 109 becomes higher, and the leakage current flows from the reset power supply line 109 to the photodiode 104. As described above, since the direction in which the leakage current flows is reversed, the adverse effect of the leakage current can be offset. Further, since the source-drain voltage of the resetting transistor 107 is small, the leakage current itself is smaller than in the related art.

Before resetting the photodiode 104 again, the gate signal line 102 is controlled, the switching transistor 101 is turned on, and a signal is output to the signal output line 103. After that, the photodiode 104 is reset again. At that time, the potential of the reset-side power supply line 109 is returned to its original state.

However, when the reset-side power supply line 109 and the amplification-side power supply line 108 are connected, when outputting a signal to the signal output line 103, if the potential of the reset-side power supply line 109 decreases, Cannot output correct signal. Therefore, if the reset-side power line 109 and the amplification-side power line 108 are connected, the reset-side power line
The potential of 109 is restored.

In FIG. 2, the potential of the amplification-side power supply line 108 during the accumulation time was about the middle, but as shown in FIG. May be lowered.

In FIG. 1, the P-channel terminal of the photodiode 104 is connected to the diode-side power line 110.
However, as shown in FIG.
The N-channel side terminal 04 may be connected to the diode-side power supply line 1310. However, in that case, the magnitude relationship between the potentials is reversed. In FIG. 1, the potential of the reset-side power line 109 is higher than the potential of the diode-side power line 110. on the other hand,
In FIG. 13, the potential of the reset-side power supply line 1309 is lower than the potential of the diode-side power supply line 1310. This is because a reverse bias voltage is applied when the photodiode 1304 is reset. Figure 14 corresponding to Figure 2
FIG. 15 shows a diagram corresponding to FIG.

It should be noted that also in FIG.
Either the connection 1309 or the amplification side power supply line 1308 may or may not be connected.

In FIGS. 1 and 13, the amplifying transistor, the resetting transistor, and the switching transistor may be an N-channel type or a P-channel type.

In FIGS. 1 and 13, the switching transistor may be arranged between the power supply line on the amplification side and the transistor for amplification, or may be arranged between the transistor for amplification and the signal output line. Is also good.

[0056]

[Embodiment 1] Next, a driving circuit is mounted on the periphery,
An embodiment in which the present invention is applied to an area sensor in which pixels are arranged two-dimensionally will be described. FIG. 16 shows the entire circuit diagram. First, there is a pixel array unit 1605 in which pixels are two-dimensionally arranged. A driving circuit for driving a gate signal line, a reset signal line, and a power supply line of each pixel is provided in a pixel array section.
It is located to the left and right of 1605. In FIG. 16, the gate signal line reset signal line drive circuit 1606 is arranged on the left side, and the power supply line drive circuit 1607 is arranged on the right side.

A circuit for signal processing and the like are arranged above the pixel array section 1605. In FIG. 16, a bias circuit 1603 is arranged on the pixel array section 1605. The bias circuit 1603 forms a source follower circuit by pairing with the amplification transistor of each pixel.
Above the bias circuit 1603, a sample hold & signal processing circuit 1602 is arranged. Here, circuits for storing signals once, performing analog-to-digital conversion, and reducing noise are arranged. A signal output line driving circuit 1601 is arranged above the sample hold and signal processing circuit 1602. The signal output line driver circuit 1601 outputs a signal for sequentially outputting the signals stored temporarily. Then, before outputting a signal to the outside, a final output amplification circuit 1604 is arranged. Here, the signals sequentially output are amplified by the sample hold and signal processing circuit 1602 and the signal output line driving circuit 1601 before being output to the outside. Therefore, it is not necessary when the signal is not amplified, but is practically arranged in many cases.

Next, a circuit diagram of each part is shown. First, as an example, a circuit diagram of the pixel unit circuit 1608 in the i-th row and the j-th column from the two-dimensionally arranged pixel array unit 1605 is shown in FIG.
In FIG. 17, a P-channel reset transistor 1707,
It comprises a P-channel switch transistor 1701, an N-channel amplifier transistor 1706, and a photoelectric conversion element (here, the most typical photodiode 1704). In the photodiode 1704, the P channel side terminal is connected to the power supply reference line 1712, and the N channel side terminal is connected to the gate terminal of the amplification transistor 1706. The reset signal line 1705 of the i-th row is connected to the gate terminal of the reset transistor 1707, and the source terminal and the drain terminal are connected to the power supply line 1709 of the i-th row and the gate terminal of the transistor 1706 for amplification. The gate terminal of the switching transistor 1701 is connected to the i-th gate signal line 1702, and the source terminal and the drain terminal are connected to the i-th power supply line 1709 and the amplifying transistor 1706. Amplifying transistor 1706
Source and drain terminals are connected to the j-th column signal output line 1703.
And the switching transistor 1701. The j-th column signal output line 1703 and the i-th row gate signal line 1702 are arranged so as to intersect as before, and the j-th column signal output line 1703 extends in the vertical direction. i-th gate signal line 1702 and i
The row reset signal line 1705 has a wiring extending in the horizontal direction as usual, and is arranged in parallel. 16 and 17, the i-th power line 1709 also extends in the horizontal direction, and is arranged in parallel with the i-th reset signal line 1705. conventionally,
It stretched vertically. This is because the voltage of the power supply line can be changed for each row since the photodiode of the pixel is selected for each row.

In FIG. 17, the reset transistor 1707 is used.
Uses a P-channel type. However, the reset transistor may be an N-channel transistor. However, in the case of the N-channel type, a large gate-source voltage cannot be obtained during a reset operation. Therefore, the reset transistor operates in the saturation region, and the photodiode 17
04 cannot be charged sufficiently. Therefore, the reset transistor operates with an N-channel type, but a P-channel type is more preferable.

As for the switching transistor 1701,
It is desirable to arrange between the i-th power supply line 1709 and the amplifying transistor 1706 and use a P-channel type. However, as in the conventional case, since the N-channel type operates, the N-channel type may be used, or the N-channel type may be provided between the j-th column signal output line 1703 and the amplifying transistor 1706. However,
Since it is difficult to output a signal correctly, the switching transistor 1701 is connected to the i-th power line 1709 and the amplifying transistor 1706.
It is desirable to use a P-channel type.

As for the amplifying transistor 1706, FIG.
Uses an N-channel type. However, it is also possible to use a P-channel type. However, in that case, in order to operate as a source follower circuit in combination with a bias transistor, it is necessary to change a circuit connection method. That is, simply changing the polarity of the amplifying transistor 1706 in the circuit diagram of FIG. 17 does not operate.

FIG. 18 shows an example of a circuit configuration using a P-channel type amplifying transistor. The difference from FIG. 17 is that the polarity of the amplifying transistor 1806 is a P-channel type, the direction of the photodiode is reversed, and the power supply line and the power supply reference line are switched. When a P-channel transistor is used for the amplification transistor, it is necessary to use a P-channel transistor for the bias transistor. Because the bias transistor is
This is because it is necessary to operate as a constant current source. Therefore, in FIG. 18, for reference, the bias transistor 18
11 is also described. The i-th row and j-column pixel unit circuit 1608 shown in FIG.
Comprises an N-channel reset transistor 1807, an N-channel switch transistor 1801, a P-channel amplification transistor 1806, and a photoelectric conversion element (here, the most typical photodiode 1804). For the photodiode 1804, the N-channel side terminal is the power supply line 1809
In addition, the P-channel side terminal is connected to the gate terminal of the amplification transistor 1806. Reset transistor 18
The reset signal line 1805 of the i-th row is connected to the gate terminal of 07, and the source terminal and the drain terminal are connected to the power reference line 1 of the i-th row.
812 and the gate terminal of the amplifying transistor 1806. The gate terminal of the switching transistor 1801 is
The source terminal and the drain terminal are connected to the i-th row gate signal line 1802, and the i-th row power supply reference line 1812 and the amplifying transistor 1806 are connected. The source terminal and the drain terminal of the amplifying transistor 1806 are connected to the j-th column signal output line 1803 and the switching transistor 1801. A bias signal line is connected to the gate terminal of the bias transistor 1811.
1810 is connected, and the source terminal and the drain terminal are connected to the j-th column signal output line 1803 and the power supply line 1809.

In FIG. 18, the reset transistor 1807
Uses an N-channel type. However, the reset transistor may be of a P-channel type. However, in the case of the P-channel type, a large gate-source voltage cannot be obtained during a reset operation. Therefore, the reset transistor operates in the saturation region, and the photodiode 18
04 cannot be charged sufficiently. Therefore, although the reset transistor also operates with a P-channel type, an N-channel type is more preferable.

In FIG. 18, the switching transistor 1801 includes a j-th power supply reference line 1812 and an amplifying transistor.
It is desirable to arrange between 1806 and use the N-channel type. However, since it operates with a P-channel type, it may be a P-channel type, or may be arranged between the j-th column signal output line 1803 and the amplifying transistor 1806. However,
Since it is difficult to output a signal correctly, the switching transistor 1801 is connected to the j-th power supply reference line 1809 and the amplifying transistor.
It is desirable to arrange between 1806 and use the N-channel type.

As can be seen from a comparison between FIG. 17 and FIG. 18, when the polarities of the amplifying transistors are different, the optimum transistor configuration, the direction of the photodiode, and the like also differ.

In FIG. 17, current is supplied to both the switch transistor 1701 and the reset transistor 1707 from one power supply line. In FIG. 18, current is supplied to both the switch transistor 1801 and the reset transistor 1807 from one power supply reference line. In this manner, the wiring can be shared by matching the direction of the photodiode and the polarity of the amplifying transistor.

However, the number of wires for supplying current may be increased by one, and the current may be supplied separately. In that case, the potential of the wiring for supplying current to the switching transistor may be a constant potential. Also, there is no need to match the direction of the photodiode with the polarity of the amplifying transistor.

Next, FIG. 19 shows a circuit diagram of a j-th column peripheral circuit 1609 as a circuit for one column among the bias circuit 1603 and the sample hold & signal processing circuit 1602. A bias transistor 1911 is provided in the bias circuit 1603. The polarity is the same as the polarity of the amplification transistor of each pixel. Therefore, when the amplification transistor of the pixel is an N-channel type, the biasing transistor is also an N-channel type. In FIG. 19, the biasing bias transistor 1911 is of an N-channel type. A bias signal line 1910 is connected to a gate terminal of the bias transistor 1911, and a source terminal and a drain terminal
It is connected to the j-th column signal output line 1903 and the power supply reference line 1912 (when the bias transistor is a P-channel type,
Use a power line instead of a power reference line). The bias transistor 1911 operates as a source follower circuit in a pair with the amplification transistor of each pixel. The transfer signal line 1914 is connected to the gate terminal of the transfer transistor 1913.
Are connected, and the source terminal and the drain terminal are connected to the j-th column signal output line 1903 and the load capacitance 1915. The transfer transistor is operated when transferring the potential of the signal output line 1903 to the load capacitance 1915. Therefore, a P-channel transfer transistor may be added and connected in parallel with the N-channel transfer transistor 1914. Load capacity 1915
Are connected to the transfer transistor 1913 and the power supply reference line 1912. The role of the load capacitance 1915 is to temporarily store the signal output from the signal output line 1903. The gate terminal of the discharging transistor 1916 is connected to the pre-discharge signal line 1917
And the source and drain terminals are connected to the load capacitance 19
15 and the power supply reference line 1912. The discharging transistor 1916 operates so as to discharge the charge accumulated in the load capacitor 1915 before the potential of the signal output line 1903 is input to the load capacitor 1915.

Note that it is also possible to arrange an analog / digital signal conversion circuit, a noise reduction circuit, and the like.

Then, a final selection transistor 1919 is connected between the load capacitance 1915 and the final output line 1920. The source terminal and the drain terminal of the final selection transistor 1919 are connected to the load capacitance 1915 and the final output line 1920, and the gate terminal is connected to the j-th column final selection line 1918. The final selection line is scanned in order from the first column. Then, the j-th column final selection line 1918 is selected, and the final selection transistor 19 is selected.
When 19 becomes conductive, the potential of the load capacitance 1915 and the potential of the final output line 1920 become equal. As a result, the signal stored in the load capacitance 1915 can be output to the final output line 1920. However, before outputting the signal to the final output line 1920,
When electric charge is accumulated in the final output line 1920, the electric charge affects the potential when a signal is output to the final output line 1920. Therefore, before outputting a signal to the final output line 1920, the potential of the final output line 1920 must be initialized to a certain potential value. In FIG. 19, the final output line 1920
Between the power supply reference line 1912 and the final reset transistor
1922 is located. The gate terminal of the final reset transistor 1922 has a final reset line 1921 in the j-th column.
Is connected. Then, before selecting the j-th column final selection line 1918, the j-th column final reset line 1921 is selected, and the potential of the final output line 1920 is initialized to the potential of the power supply reference line 1912. After that, the j-th column final selection line 1918 is selected, and the signal stored in the load capacitance 1915 is output to the final output line 1920.

The signal output to the final output line 1920 may be taken out as it is. However, since the signal is weak, the signal is often amplified before being taken out. FIG. 20 shows a circuit for this purpose.
The circuit of 1610 is shown. There are various circuits for amplifying a signal, such as an operational amplifier. Any circuit may be used as long as the circuit amplifies a signal. Here, a source follower circuit is shown as the simplest circuit configuration. Fig. 20
Here, an N-channel type is shown. Circuit for final output amplification 1
The input to 604 is the final output line 2002. Final output line 200
2, a signal is output in order from the first column. The signal is amplified by the final output amplification circuit 1604 and output to the outside. The final output line 2002 is connected to the gate terminal of the amplification transistor 2004 for final output amplification. The drain terminal of the amplification transistor 2004 for final output amplification is connected to the power supply line 2006, and the source terminal is an output terminal. The gate terminal of the final output amplification bias transistor 2003 is connected to the final output amplification bias signal line 2005. The source terminal and the drain terminal are connected to the power supply reference line 2007 and the source terminal of the amplification transistor 2004 for final output amplification.

FIG. 21 is a circuit diagram in the case of using a source follower circuit of the P-channel type. The difference from FIG. 20 is that the power supply line and the power supply reference line are reversed. The final output line 2102 is an amplifying transistor for final output amplification
Connected to the gate terminal of 2104. The drain terminal of the amplification transistor 2104 for final output amplification is connected to the power supply reference line 2107.
And the source terminal becomes the output terminal. The gate terminal of the bias transistor 2103 for final output amplification is
Connected to final output amplification bias signal line 2105. The source terminal and the drain terminal are connected to the power supply line 2106 and the source terminal of the amplification transistor 2104 for final output amplification. The potential of the final output amplification bias signal line 2105 is the final output amplification bias signal line when the N-channel type is used.
The value is different from 2005.

In FIG. 20 and FIG.
It consisted only of columns. However, a plurality of stages may be used. For example, in the case of a two-stage configuration, the first-stage output terminal may be connected to the second-stage input terminal. In each stage, either an N-channel type or a P-channel type may be used.

Gate signal line reset signal line drive circuit 16
06 and power supply line drive circuit 1607 and signal output line drive circuit 1601
Is a circuit that simply outputs a pulse signal. Therefore, it can be implemented using a known technique.

Next, a signal timing chart will be described. First, timing charts of the circuits in FIGS. 16 and 17 are shown in FIGS. The reset signal line scans sequentially from the first row. For example, (i-1)
Select the row, then the i-th row, then (i + 1)
Select the line. A period until the same row is selected again corresponds to a frame period. Similarly, for the gate signal line,
Scan sequentially from the first line. However, the timing to start scanning the gate signal line is later than the timing to start scanning the reset signal line. For example,
Focusing on the pixels in the i-th row, the i-th row reset signal line is selected, and then the i-th gate signal line is selected. When the i-th gate signal line is selected, a signal is output from the i-th row pixel. The period from when the pixel is reset to when the signal is output is the accumulation time. During the accumulation time,
In the photodiode, charge generated by light is accumulated. In each row, the reset timing and the signal output timing are different. Therefore, the accumulation time is equal for all rows of pixels, but the accumulation time is different.

As for the power supply line 1709, after the reset transistor 1707 is turned off, the voltage of the power supply line 1709 is also reduced in order. The reason for delaying the timing of lowering the voltage of the power supply line 1709 is that the reset transistor 1707 is completely turned off in order to prevent the voltage of the photodiode 1704 from being affected by the power supply line 1709. This is because the voltage of the power supply line 1709 must be reduced later. In FIG. 22, the voltage of the power supply line 1709 at this time is not completely lowered but is reduced by about half. In FIG. 23, it is completely lowered. Then, photodiode 1704
Is irradiated with light, charges corresponding to the light intensity are generated in the photodiode 1704, and as a result, the voltage of the photodiode 1704 decreases according to the light intensity. The higher the light intensity, the more charges are generated, and the lower the voltage of the photodiode 1704 is.

In FIG. 22, the voltage of the power supply line 1709 is reduced by about half. Therefore, the reset transistor 17
The direction in which the leakage current flows in 07 changes depending on the value of the voltage of the photodiode 1704. First, when the light is weak, the voltage of the photodiode 1704 does not drop much. Therefore, the leakage current of the reset transistor 1707 flows from the photodiode 1704 to the power supply line 1709. Therefore, even if the amount of charge Iphoto per unit time generated by light is small, it contributes to a change in the voltage of the photodiode 1704, so that a signal can be obtained. Next, when light is strong, the voltage of the photodiode 1704 drops sufficiently. Therefore, the leakage current of the reset transistor 1707 is
It flows from 1709 to the photodiode 1704. However,
Since the source-drain voltage of the reset transistor 1707 is small, the reset transistor 1707 is
The leakage current is small. Also, first, a photodiode
It flows from 1704 to the power line 1709, and the photodiode 1704
Is lower than the voltage of the power supply line 1709, the leakage current flows from the power supply line 1709 to the photodiode 1704. That is, the direction of the leakage current of the reset transistor 1707 changes. Therefore, the effects of the leakage current of the reset transistor 1707 are reduced because they cancel each other. From the above, the non-linear relationship between the voltage of the photodiode 1704 and the storage time is improved. As a result, the gamma characteristics are improved.

In FIG. 23, the voltage of the power supply line 1709 is completely low. Therefore, leakage current of the reset transistor 1707 can be prevented from flowing from the power supply line 1709 to the photodiode 1704. Therefore, the problem that the voltage of the photodiode 1704 is hardly reduced when the photodiode 1704 is irradiated with dark light is improved.

Then, by controlling the gate signal line 1702,
Output a signal. In FIG. 17, the switching transistor 17
Current is supplied to both 01 and the reset transistor 1707 from one power supply line. In that case, the potential of the power supply line 1709 needs to be returned to the original level even when a signal is output. In the case where current is supplied using different wirings, the potential of the wiring for supplying current to the switching transistor 1701 may be constant without changing over time. At that time, it is not necessary to return the potential of the power supply line 1709 to the original.

Next, FIGS. 24 and 25 show timing charts in the circuits of FIGS. 16 and 18. FIG. Since the polarity of the transistor and the direction of the photodiode are different, the magnitude relationship of the potentials is different, but the operation itself is the same as in FIGS.

Next, FIG. 26 shows a timing chart of the signals in FIG. Since the operation is repeated, it is assumed that the gate signal line in the i-th row is selected as an example. First, after the gate signal line 1702 in the i-th row is selected,
Select the pre-discharge signal line 1917 and discharge transistor 1916
Is turned on. After that, the transfer signal line 1914 is selected. Then, a signal in each column is output from the pixel in the i-th row to the load capacitance 1915 in each column.

After accumulating the signals of all the pixels in the i-th row in the load capacitors 1915 of each column, the signals of each column are sequentially output to the final output line 1920. From when the transfer signal line 1914 is deselected to when the gate signal line is selected, the signal output line driver circuit 1601 scans all columns. First, the final reset line in the first column is selected, the final reset transistor 1922 is turned on, and the final output line 1920 is initialized to the potential of the power supply reference line 1912. Thereafter, the final selection line 1918 in the first column is selected, the final selection transistor 1919 is turned on, and the signal of the load capacitance 1915 in the first column is output to the final output line 1920. Next, the final reset line in the second column is selected, the final reset transistor 1922 is turned on, and the final output line 1920 is initialized to the potential of the power supply reference line 1912. Then, the final selection line 1918 in the second column is selected, the final selection transistor 1919 is turned on, and the signal of the load capacitance 1915 in the second column is output to the final output line 1920. Since then,
The same operation is repeated. In the case of the j-th column, select the final reset line in the j-th column,
1922 is turned on, and the final output line 1920 is connected to the power supply reference line 1912.
To the potential of. Then, the final selection line 1918 in the j-th column
Is selected, the final selection transistor 1919 is turned on, and the signal of the j-th column load capacitance 1915 is output to the final output line 1920. Next, the final reset line in the (j + 1) th column is selected, and the final reset transistor 1922 is turned on.
The final output line 1920 is initialized to the potential of the power supply reference line 1912.
After that, the final selection line 1918 in the (j + 1) th column is selected, the final selection transistor 1919 is turned on, and the signal of the load capacitance 1915 in the (j + 1) th column is output to the final output line 1920. Thereafter, the same operation is repeated, and the signals of all columns are sequentially output to the final output line. Meanwhile, the bias signal line
1910 remains constant. The signal output to the final output line 1920 is amplified by the final output amplifying circuit 1604 and output to the outside.

Next, the (i + 1) th gate signal line is selected. Soon, the operation is performed in the same manner as when the i-th gate signal line is selected. Then, the gate signal line of the next row is selected, and the same operation is repeated.

The sensor section for performing photoelectric conversion and the like includes a PIN diode, an avalanche diode, an npn buried diode, a Schottky diode, and an X-ray photodiode in addition to a normal PN photodiode. A conductor, a sensor for infrared rays, or the like may be used. Further, after converting X-rays into light with a fluorescent material or a scintillator, the light may be read.

As described above, the photoelectric conversion element is often connected to the input terminal of the source follower circuit. However, a switch may be interposed like a photogate type. Alternatively, a signal processed so as to be a logarithmic value of light intensity, such as a logarithmic conversion type, may be input to an input terminal.

In this embodiment, the area sensor in which the pixels are arranged two-dimensionally has been described. However, a line sensor in which the pixels are arranged one-dimensionally can be realized.

[Embodiment 2] The sensor of the present invention is replaced with a TFT
About the manufacturing method when manufacturing on glass using
This will be described with reference to FIGS.

First, as shown in FIG. 27A, a base film 201 is formed on a glass substrate 200 to a thickness of 300 nm. In this embodiment, a silicon nitride oxide film is stacked and used as the base film 201. At this time, the nitrogen concentration in contact with the glass substrate 200 is preferably set to 10 to 25 wt%. It is effective to give the base film 201 a heat radiation effect, and a DLC (diamond-like carbon) film may be provided.

Next, an amorphous silicon film (not shown) having a thickness of 50 nm is formed on the base film 201 by a known film forming method. Note that the present invention is not limited to an amorphous silicon film, and may be any semiconductor film including an amorphous structure (including a microcrystalline semiconductor film). Further, a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used. The film thickness is 2
The thickness may be 0 to 100 nm.

Then, the amorphous silicon film is crystallized by a known technique, and a crystalline silicon film (also referred to as a polycrystalline silicon film or a polysilicon film) 202 is formed. Known crystallization methods include a thermal crystallization method using an electric furnace, a laser annealing crystallization method using laser light, and a lamp annealing crystallization method using infrared light. In this embodiment, X
Crystallization is performed using excimer laser light using eCl gas.

In this embodiment, a pulse oscillation type excimer laser beam processed into a linear shape is used, but a rectangular shape may be used, or a continuous oscillation type argon laser beam or a continuous oscillation type excimer laser beam may be used. You can also.

In this embodiment, the crystalline silicon film is formed by using a TFT.
, But it is also possible to use an amorphous silicon film.

It is to be noted that the active layer of the reset transistor for which the off current needs to be reduced is formed of an amorphous silicon film,
It is effective to form the active layer of the amplifying transistor with a crystalline silicon film. Since the amorphous silicon film has a low carrier mobility, it is difficult for an electric current to flow and an off current is hard to flow. That is,
The advantages of both an amorphous silicon film through which a current is hard to flow and a crystalline silicon film through which a current easily flows can be utilized.

Next, as shown in FIG. 27B, a protective film 203 made of a silicon oxide film is
It is formed to a thickness of 0 nm. This thickness is 100-200n
m (preferably 130 to 170 nm). Further, any other insulating film containing silicon may be used.
The protective film 203 is provided to prevent the crystalline silicon film from being directly exposed to plasma when adding impurities and to enable fine concentration control.

Then, a resist mask 204 is formed thereon.
a, 204b, and 204c are formed, and an impurity element imparting n-type (hereinafter, referred to as an n-type impurity element) is added via the protective film 203. Note that, as the n-type impurity element, an element belonging to Group 15 of the periodic table, typically, phosphorus or arsenic can be used. In this embodiment, the phosphorous is doped with 1 × 10 ¹⁸ at by using a plasma doping method in which phosphine (PH ₃ ) is plasma-excited without mass separation.
Add at a concentration of oms / cm ³ . Of course, an ion implantation method for performing mass separation may be used.

In the n-type impurity regions (b) 205a and 205b formed in this step, 2 ×
10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ (typically 5 × 10 ¹⁷
The dose is adjusted so as to be contained at a concentration of about 5 × 10 ¹⁸ atoms / cm ³ ).

Next, as shown in FIG. 27C, the protective film 203 and the resist masks 204a, 204b, 204c
Is removed, and the added n-type impurity element is activated. As the activating means, a known technique may be used. In this embodiment, the activating means is activated by excimer laser light irradiation (laser annealing). Needless to say, a pulse oscillation type or a continuous oscillation type may be used, and it is not necessary to limit to an excimer laser beam. However, since the purpose is to activate the added impurity element,
It is preferable to irradiate with an energy that does not melt the crystalline silicon film. Note that laser light irradiation may be performed with the protective film 203 attached.

When activating the impurity element by the laser beam, activation by heat treatment (furnace annealing) may be used in combination. When activation by heat treatment is performed, heat treatment at about 450 to 550 ° C. may be performed in consideration of the heat resistance of the substrate.

By this step, n-type impurity region (b) 20
5a, 205b, that is, n-type impurity region (b) 2
A boundary portion (junction portion) between the region 05a and 205b and the region to which the n-type impurity element is not added becomes clear.
This means that when the TFT is completed later, the LD
This means that the D region and the channel forming region can form a very good junction.

Next, as shown in FIG. 27D, unnecessary portions of the crystalline silicon film are removed to form island-like semiconductor films (hereinafter, referred to as active layers) 206 to 210.

Next, as shown in FIG. 28A, a gate insulating film 211 is formed to cover the active layers 206 to 210. 10 to 200 nm as the gate insulating film 211,
Preferably, an insulating film containing silicon with a thickness of 50 to 150 nm is used. This may have a single-layer structure or a laminated structure. In this embodiment, a 110-nm-thick silicon nitride oxide film is used.

Next, a conductive film having a thickness of 200 to 400 nm is formed and patterned to form gate electrodes 212 to 216. Note that in this embodiment, the gate electrode and a wiring for wiring (hereinafter, referred to as a gate wiring) electrically connected to the gate electrode are formed of the same material. Of course, the gate electrode and the gate wiring may be formed of different materials. Specifically, a material having lower resistance than the gate electrode may be used for the gate wiring. This is because a material that can be finely processed is used for the gate electrode, and a material that does not allow fine processing and has low wiring resistance is used for the gate wiring. With such a structure, the wiring resistance of the gate wiring can be extremely reduced, so that a sensor portion having a large area can be formed. That is, the above-described pixel structure is extremely effective in realizing an area sensor having a sensor unit having a screen size of 10 inches or more (more preferably 30 inches or more) diagonally.

The gate electrode may be formed of a single-layer conductive film, but it is preferable to form a two-layer or three-layer film as needed. As the material of the gate electrodes 212 to 216, any known conductive film can be used.

Typically, aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo),
Tungsten (W), chromium (Cr), silicon (S
i) a film made of an element selected from the above, a nitride film of the element (typically, a tantalum nitride film, a tungsten nitride film, a titanium nitride film), or an alloy film combining the above elements (typically, Mo) -W alloy, Mo-Ta alloy) or a silicide film of the above element (typically, a tungsten silicide film or a titanium silicide film) can be used. Of course, they may be used as a single layer or stacked.

In this embodiment, a 30 nm thick tungsten nitride (WN) film and a 370 nm thick tungsten (W)
A laminated film composed of a film is used. This may be formed by a sputtering method. When an inert gas such as Xe or Ne is added as a sputtering gas, the film can be prevented from peeling due to stress.

At this time, the gate electrodes 213 and 216 are formed so as to overlap a part of the n-type impurity regions (b) 205a and 205b via the gate insulating film 211, respectively. The LD where this overlapped portion later overlaps the gate electrode
This is the D area.

Next, as shown in FIG. 28B, an n-type impurity element (phosphorus in this embodiment) is added in a self-aligned manner using the gate electrodes 212 to 216 as a mask. The n-type impurity regions (c) 217 to 224 formed in this manner have 1/2 to 1/1 of the n-type impurity regions (b) 205a and 205b.
Adjust so that phosphorus is added at a concentration of 0 (typically 1/3 to 1/4). Specifically, 1 × 10 ^{16 to} 5 × 1
0 ¹⁸ atoms / cm ³ (typically 3 × 10 ^{17 to} 3 × 10 ¹⁸ ato
A concentration of ms / cm ³ ) is preferred.

Next, as shown in FIG. 28C, resist masks 225a to 225c are formed so as to cover the gate electrodes 212, 214 and 215, and an n-type impurity element (phosphorus in this embodiment) is added. Then, n-type impurity regions (a) 226 to 233 containing phosphorus at a high concentration are formed. Also in this case, the ion doping method using phosphine (PH ₃ ) is performed, and the concentration of phosphorus in this region is 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ^3.
(Typically ^{2 × 10 2 0 ~5 × 10} 21 atoms / cm 3) is adjusted to be.

By this step, a source region or a drain region of the n-channel TFT is formed. And n
In the case of the channel type TFT, part of the n-type impurity regions 217, 218, 222, and 223 formed in the step of FIG. This remaining region becomes an LDD region.

Next, as shown in FIG. 28D, the resist masks 225a to 225c are removed, and new resist masks 234a and 234b are formed. Then, a p-type impurity element (boron in this embodiment) is added to form p-type impurity regions 235 and 236 containing boron at a high concentration.
Here, 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ (typically 5 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ ) by an ion doping method using diborane (B ₂ H ₆ ).
Boron is added to a concentration of (× 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ ).

Note that phosphorus is already added to the impurity regions 235 and 236 at a concentration of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ , and the boron added here is at least three times as large as that. It is added at a concentration. Therefore, the n-type impurity region formed in advance is completely inverted to p-type, and functions as a p-type impurity region.

Next, the resist masks 234a and 234b
Is removed, the n-type or p-type impurity element added at each concentration is activated. As the activation means, a furnace annealing method, a laser annealing method, or a lamp annealing method can be used. In this embodiment, heat treatment is performed in an electric furnace at 550 ° C. for 4 hours in a nitrogen atmosphere.

At this time, it is important to eliminate oxygen in the atmosphere as much as possible. This is because the surface of the exposed gate electrode is oxidized in the presence of even a small amount of oxygen, which causes an increase in resistance. Therefore, the oxygen concentration in the processing atmosphere in the activation step is 1 ppm or less, preferably 0.1 ppm or less.
It is desirable that the content be 1 ppm or less.

Next, as shown in FIG. 29A, a first interlayer insulating film 237 is formed. As the first interlayer insulating film 237, an insulating film containing silicon may be used as a single layer or a stacked film obtained by combining them. The film thickness is 400
It may be in the range of nm to 1.5 μm. In this embodiment, 200
A structure in which a silicon oxide film having a thickness of 800 nm is stacked over a silicon nitride oxide film having a thickness of nm.

Further, in an atmosphere containing 3 to 100% of hydrogen, a heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours to perform a hydrogenation treatment. This step is a step of terminating dangling bonds of the semiconductor film with thermally excited hydrogen.
As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

The hydrogenation process is performed for the first interlayer insulating film 237.
May be inserted during formation. That is, a hydrogenation treatment may be performed as described above after a 200-nm-thick silicon nitride oxide film is formed, and then a remaining 800-nm-thick silicon oxide film may be formed.

Next, contact holes are formed in the gate insulating film 211 and the first interlayer insulating film 237, and source wirings 238 to 242 and drain wirings 243 to 247 are formed. In the present embodiment, this electrode is used as a Ti film.
00 nm, an aluminum film containing Ti is 300 nm, T
An i film having a thickness of 150 nm is continuously formed by a sputtering method to form a laminated film having a three-layer structure. Of course, other conductive films may be used.

Next, 50 to 500 nm (typically 20 to 500 nm)
The first passivation film 24 with a thickness of
8 is formed. In this embodiment, the first passivation film 2
A silicon nitride oxide film having a thickness of 300 nm is used as 48. This may be replaced by a silicon nitride film. Note that it is effective to perform plasma treatment using a gas containing hydrogen such as H ₂ or NH ₃ before forming the silicon nitride oxide film. Hydrogen excited by this pretreatment is supplied to the first interlayer insulating film 237, and is subjected to a heat treatment so that the first passivation film 24
8 is improved. At the same time, the hydrogen added to the first interlayer insulating film 237 diffuses to the lower layer side, so that the active layer can be effectively hydrogenated.

Next, as shown in FIG. 29B, a second interlayer insulating film 249 made of an organic resin is formed. As the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used. In particular,
Since the second interlayer insulating film 249 has a strong meaning of flattening,
Acrylic having excellent flatness is preferable. In this embodiment, TF
An acrylic film is formed with a thickness that can sufficiently flatten a step formed by T. The thickness is preferably 1 to 5 μm (more preferably 2 to 4 μm).

Next, a contact hole reaching the drain wiring 245 is formed in the second interlayer insulating film 249 and the first passivation film 248, and a cathode electrode 250 of a photodiode is formed so as to be in contact with the drain wiring 245. In this embodiment, an aluminum film formed by a sputtering method is used as the cathode electrode 250, but other metals, for example, titanium, tantalum, tungsten, and copper can be used. Alternatively, a stacked film including titanium, aluminum, and titanium may be used.

Next, an amorphous silicon film containing hydrogen is formed over the entire surface of the substrate and then patterned to form a photoelectric conversion layer 251.
To form Next, a transparent conductive film is formed on the entire surface of the substrate.
In this embodiment, a 200 nm thick ITO is used as the transparent conductive film.
Is formed by a sputtering method. The anode electrode 252 is formed by patterning the transparent conductive film. (FIG. 29 (C))

Next, as shown in FIG. 30A, a third interlayer insulating film 253 is formed. By using a resin such as polyimide, polyamide, polyimide amide, or acrylic as the third interlayer insulating film 253, a flat surface can be obtained. In this embodiment, a polyimide film having a thickness of 0.7 μm is formed on the entire surface of the substrate as the third interlayer insulating film 253.

Next, a contact hole reaching the anode electrode 252 is formed in the third interlayer insulating film 253, and a sensor wiring 254 is formed. In this embodiment, an aluminum alloy film (an aluminum film containing 1 wt% of titanium) is 3
It is formed to a thickness of 00 nm.

Thus, a sensor substrate having a structure as shown in FIG. 30B is completed.

270 is an amplifying TFT, 271 is a switching TFT, 272 is a reset TFT, 273 is a bias TFT, and 274 is a discharge TFT.

In this embodiment, the amplifying TFT 270 and the biasing TFT 273 are n-channel TFTs, and have LDD regions 281 to 284 on both the source region side and the drain region side. This LD
The D regions 281 to 284 do not overlap the gate electrodes 212 and 215 with the gate insulating film 211 interposed therebetween. With the above configuration, the amplification TFT 270 and the bias TFT 2
73 can reduce injection of hot carriers as much as possible.

In this embodiment, the switching TFT 27 is used.
1 and the discharge TFT 274 are n-channel TFTs, and have LDD regions 283 and 286 only on the drain region side. This LDD region 28
Reference numerals 3 and 286 overlap the gate electrodes 213 and 216 with the gate insulating film 211 interposed therebetween.

The LDD region 283 is provided only on the drain region side.
The reason why 286 is formed is to reduce hot carrier injection and not to reduce the operation speed. The switch 271 and the discharge TFT 27
In the case of No. 4, it is not necessary to care much about the off-current value, and it is better to emphasize the operation speed. Therefore, LDD region 2
83 and 286 completely overlap the gate electrodes 213 and 216, and it is desirable to reduce the resistance component as much as possible.
That is, it is better to eliminate the so-called offset. In particular,
15 source signal line driving circuits or gate signal line driving circuits
In the case of driving at V to 20 V, the discharge TFT of this embodiment is used.
The above configuration of 274 reduces hot carrier injection,
In addition, it is effective in not lowering the operation speed.

In this embodiment, the reset TFT 27 is used.
Reference numeral 2 denotes a p-channel TFT, which does not have an LDD region. Since the p-channel TFT is hardly concerned about deterioration due to hot carrier injection, it is not necessary to particularly provide an LDD region. Of course, like the n-channel type TFT, LD
It is also possible to provide a D region and take measures against hot carriers. Further, the reset TFT 272 may be an n-channel TFT.

Further, a connector (flexible printed circuit: FP) for connecting terminals routed from elements or circuits formed on the substrate to external signal terminals.
C) is attached to complete the product.

In this embodiment, the sensor is manufactured using TFTs and photodiodes on glass.
A sensor can be manufactured using a transistor over a single crystal silicon substrate.

[Embodiment 3] A sensor formed by carrying out the present invention can be used for various electronic devices. Examples of such electronic devices of the present invention include scanners, digital still cameras, X-ray cameras, portable information terminals (mobile computers, mobile phones, and portable game machines), notebook personal computers, game devices, video phones, and the like. No.

FIG. 31A shows a scanner, which includes a reading area 3102, a sensor section 3101, a reading start switch 3103, and the like. The present invention can be used for the sensor unit 3101.

FIG. 31B shows a digital still camera including a finder 3105, a sensor unit 3104, and a shutter button.
3106 etc. The present invention can be used for the sensor unit 3104.

FIG. 32 shows an X-ray camera, and an X-ray generator 320.
1, including a sensor unit 3203, a signal processing computer 3204, and the like. A human 3202 enters between the X-ray generator 3201 and the sensor unit 3203 and takes an X-ray photograph. The present invention can be used for the sensor unit 3203.

FIG. 33 shows a personal computer, which includes a main body 3301, a housing 3302, a display device 3303, and a keyboard 33.
04, a sensor unit 3305, and the like. The present invention is a sensor unit 33
05.

Here, FIG. 34 shows a mobile phone, and the main body 340 is shown.
1. Audio output unit 3402, audio input unit 3403, display device 34
04, operation switch 3405, antenna 3406, sensor unit
Includes 3407. The present invention can be used for the sensor portion 3407.

Note that the first to third embodiments can be freely combined with each embodiment.

【The invention's effect】

According to the present invention, it is possible to reduce the adverse effect of the leakage current of the reset transistor on the photoelectric conversion element. Therefore, a sensor having high image quality is realized.

[0140]

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a pixel circuit according to the present invention.

FIG. 2 is a timing chart of a pixel circuit according to the present invention.

FIG. 3 is a circuit diagram of a pixel of a conventional passive sensor.

FIG. 4 is a circuit diagram of a pixel of a conventional active sensor.

FIG. 5 is a circuit diagram of a conventional source follower circuit.

FIG. 6 is a timing chart for an active sensor.

FIG. 7 is a current characteristic diagram of a transistor.

FIG. 8 is a circuit diagram of a pixel of a conventional active sensor and a diagram showing leakage current.

FIG. 9 is a timing chart of a conventional active sensor.

FIG. 10 is a timing chart of a conventional active sensor.

FIG. 11 is a circuit diagram of a pixel circuit according to the present invention.

FIG. 12 is a timing chart of the active sensor according to the present invention.

FIG. 13 is a circuit diagram of a pixel circuit according to the present invention.

FIG. 14 is a timing chart of the active sensor according to the present invention.

FIG. 15 is a timing chart of the active sensor according to the present invention.

FIG. 16 is a block diagram of an area sensor of the present invention.

FIG. 17 is a circuit diagram of a pixel of the active sensor of the present invention.

FIG. 18 is a circuit diagram of a pixel of the active sensor of the present invention.

FIG. 19 is a circuit diagram of a signal processing circuit according to the present invention.

FIG. 20 is a circuit diagram of a circuit for final output amplification of the present invention.

FIG. 21 is a circuit diagram of a circuit for amplifying final output according to the present invention.

FIG. 22 is a timing chart of the area sensor of the present invention.

FIG. 23 is a timing chart of the area sensor of the present invention.

FIG. 24 is a timing chart of the area sensor of the present invention.

FIG. 25 is a timing chart of the area sensor of the present invention.

FIG. 26 is a timing chart of the area sensor of the present invention.

FIG. 27 is a diagram showing a process of manufacturing the image sensor of the present invention.

FIG. 28 is a diagram showing a manufacturing process of the image sensor of the present invention.

FIG. 29 is a view showing a process of manufacturing the image sensor of the present invention.

FIG. 30 is a diagram showing a manufacturing process of the image sensor of the present invention.

FIG. 31 is a diagram of an electronic device using the image sensor of the present invention.

FIG. 32 is a diagram of an electronic device using the image sensor of the present invention.

FIG. 33 is a diagram of an electronic device using the image sensor of the present invention.

FIG. 34 is a diagram of an electronic device using the image sensor of the present invention.

[Explanation of symbols]

 101 Switching transistor 102 Gate signal line 103 Signal output line 104 Photodiode 105 Reset signal line 106 Amplification transistor 107 Reset transistor 108 Amplification side power line 109 Reset side power line 110 Diode side power line

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H04N 5/335 H01L 29/78 613Z 31/10 G F-term (Reference) 2G065 AB02 AB04 BA06 BA09 BC02 BC03 BC08 BC18 BC22 BE08 DA10 DA18 DA20 4M118 AA10 AB01 AB10 BA05 BA14 CA03 CA04 CA05 CA06 CB06 CB11 CB14 DD09 DD12 FA06 FB09 FB13 FB20 GA10 5C024 AX01 AX11 CY47 GX03 GX15 GY31 5F049 MA03 MA04 MA05 MA07 MA10 MA01 MA01 MA01 NA01 DD01 EE03 EE04 EE05 EE06 EE09 EE15 EE44 FF04 FF09 GG01 GG02 GG13 GG15 GG25 HJ01 HJ04 HJ12 HJ13 HJ18 HJ23 HL04 HL06 HL12 HL23 HM15 NN03 NN04 NN22 NN23 NN27 NN11 QQ25

Claims (17)

[Claims] 1. A semiconductor device having a reset transistor, a photoelectric conversion element, a reset-side power line, a diode-side power line, a reset signal line, and an amplifying transistor, wherein a gate terminal of the reset transistor has a reset signal. One of the drain terminal or the source terminal of the reset transistor is connected to the reset-side power supply line, the other is connected to the photoelectric conversion element, and one of the photoelectric conversion elements Is connected to the diode-side power line, and the other terminal is connected to a source terminal or a drain terminal of the reset transistor. The source terminal or the drain terminal of the reset transistor is connected to the photoelectric terminal. The terminal connected to the conversion element is connected to the gate of the amplification transistor. A reset terminal, and the reset-side power supply line and the reset signal line are arranged in parallel. 2. A semiconductor device comprising a reset transistor, a photoelectric conversion element, a reset-side power line, a diode-side power line, a reset signal line, an amplifying transistor, and a signal generator, wherein a gate terminal of the reset transistor is provided. Is connected to the reset signal line, one of a drain terminal and a source terminal of the reset transistor is connected to the reset side power supply line, and the other is connected to the photoelectric conversion element. One terminal of the conversion element is connected to the diode-side power line, and the other terminal is connected to a source terminal or a drain terminal of the reset transistor. A source terminal or a drain of the reset transistor A terminal connected to the terminal and the photoelectric conversion element is connected to the amplification amplifier. A gate terminal of a transistor is connected, and a signal generator operable to bring the potential of the reset-side power supply line closer to the potential of the diode-side power supply line is connected to the reset-side power supply line. Semiconductor device. 3. The semiconductor device according to claim 1, wherein the photoelectric conversion element is an X-ray sensor or an infrared sensor. 4. The semiconductor device according to claim 1, wherein the photoelectric conversion element is one of a photodiode, a Schottky diode, an avalanche diode, and a photoconductor. 5. The semiconductor device according to claim 4, wherein the photodiode is one of a PN type, a PIN type, and an NPN embedded type. 6. A scanner using the semiconductor device according to any one of claims 1 to 5. 7. A digital still camera using the semiconductor device according to any one of claims 1 to 5. 8. An X-ray camera using the semiconductor device according to any one of claims 1 to 5. 9. A portable information terminal using the semiconductor device according to any one of claims 1 to 5. 10. A computer using the semiconductor device according to any one of claims 1 to 5. 11. A reset transistor, a photoelectric conversion element, a reset-side power line, a diode-side power line, and a reset signal line, wherein a gate terminal of the reset transistor is connected to the reset signal line. One of a drain terminal and a source terminal of the reset transistor is connected to the reset-side power line, and the other is connected to the photoelectric conversion element. One terminal of the photoelectric conversion element is connected to the diode-side power supply. The other terminal is connected to a source terminal or a drain terminal of the reset transistor. When the reset transistor is in a non-conductive state, the potential of the reset side power supply line is set to the diode. A method for driving a semiconductor device, wherein the potential of the semiconductor device is approximated to a potential of a side power supply line. 12. A reset transistor, a photoelectric conversion element, a reset-side power line, a diode-side power line, and a reset signal line, wherein a gate terminal of the reset transistor is connected to the reset signal line. One of a drain terminal and a source terminal of the reset transistor is connected to the reset-side power line, and the other is connected to the photoelectric conversion element. One terminal of the photoelectric conversion element is connected to the diode-side power supply. A driving circuit for driving the semiconductor device, wherein the other terminal is connected to a source terminal or a drain terminal of the reset transistor. The potential of the line and the potential when the reset transistor is in a conductive state and the diode A method for driving a semiconductor device, wherein the potential is set to an intermediate potential between the potentials of the side power supply lines. 13. A reset transistor, a photoelectric conversion element, a reset-side power line, a diode-side power line, a reset signal line, and an amplification transistor, wherein a gate terminal of the reset transistor is connected to the reset signal line. One of a drain terminal and a source terminal of the reset transistor is connected to the reset-side power supply line, and the other is connected to the photoelectric conversion element. One terminal of the photoelectric conversion element is The other terminal is connected to the source terminal or the drain terminal of the reset transistor, and the other terminal is connected to the source terminal or the drain terminal of the reset transistor and the photoelectric conversion element. The gate terminal of the amplifying transistor is connected to the connected terminal. The method of driving a semiconductor device according to claim 1, wherein the potential of the reset-side power supply line is made closer to the potential of the diode-side power supply line when the reset transistor is off. 14. A reset transistor, a photoelectric conversion element, a reset-side power line, a diode-side power line, a reset signal line, and an amplifying transistor, wherein a gate terminal of the reset transistor is connected to the reset signal line. One of a drain terminal and a source terminal of the reset transistor is connected to the reset-side power supply line, and the other is connected to the photoelectric conversion element. One terminal of the photoelectric conversion element is The other terminal is connected to the source terminal or the drain terminal of the reset transistor, and the other terminal is connected to the source terminal or the drain terminal of the reset transistor and the photoelectric conversion element. The gate terminal of the amplifying transistor is connected to the connected terminal. The reset transistor is in a non-conducting state, the potential of the reset-side power supply line is intermediate between the potential of the reset transistor in a conducting state and the potential of the diode-side power line. A method for driving a semiconductor device, comprising: 15. The method according to claim 11, wherein:
In the paragraph, the method for driving a semiconductor device, wherein the photoelectric conversion element is an X-ray sensor or an infrared sensor. 16. The method according to claim 11, wherein:
In the paragraph, the method for driving a semiconductor device, wherein the photoelectric conversion element is one of a photodiode, a Schottky diode, an avalanche diode, and a photoconductor. 17. The method according to claim 16, wherein the photodiode is one of a PN type, a PIN type, and an NPN embedded type.