JP5470475B2 - Semiconductor device and electronic equipment - Google Patents

Description

The present invention relates to a semiconductor device and a driving method thereof. More specifically, the present invention relates to a MOS sensor device having an image sensor function and a driving method thereof.

In recent years, information devices such as personal computers have become widespread, and there is an increasing demand for reading various information into a personal computer as electronic information. For this reason, a digital still camera is attracting much attention as an alternative to the conventional silver salt camera, and a scanner as a means for reading what is printed on paper or the like.

In the digital still camera, an area sensor in which pixels are arranged two-dimensionally is used. In scanners and copiers, line sensors in which pixels are arranged one-dimensionally are used. When reading a two-dimensional image using a line sensor, the signal is read while moving the line sensor.

In these image reading devices, CCD type sensors are mainly used as image sensors. In a CCD sensor, photoelectric conversion is performed by a photodiode of each pixel, and the signal is read out using a CCD. However, in recent years, a single MOS-type sensor made using a single crystal silicon substrate has been developed with the advantage of being able to incorporate peripheral circuits, being able to be integrated into one chip, being suitable for real-time signal processing, and having low power consumption. Shows signs of widespread use. At the research level, MOS type sensors created using TFTs on glass substrates have also been developed. In the MOS sensor, photoelectric conversion is performed by a photodiode of each pixel, and a signal of each pixel is read using a switch formed by a MOS transistor.

Various types of pixel configurations for MOS sensors have been developed. They are,
It can be roughly classified into two types: passive sensors and active sensors.
A passive sensor is a sensor in which no signal amplification element is mounted on each pixel, and an active sensor is a sensor in which a signal amplification element is mounted on each pixel.
An active sensor has a merit that it is more resistant to noise than a passive sensor because a signal is amplified in each pixel.

FIG. 3 shows a circuit example of a pixel in the passive sensor. The pixel 305 includes a switching transistor 301 and a photodiode 304. Photodiode 304 is power supply reference line 3
06 and the source terminal of the switching transistor 301 are connected. A gate signal line 302 is connected to the gate terminal of the switching transistor 301, and a signal output line 30 is connected to the drain terminal.
3 is connected. In the photodiode 304, photoelectric conversion is performed. That is, a charge is generated according to incident light, and the charge is accumulated there. Then, the gate signal line 302 is controlled so that the switching transistor 301 is turned on, and the charge of the photodiode 304 is read through the signal output line 303.

There are various types of pixel configurations of the active sensor. IEDM95: p17: CMOS Im
age Sensors, Electronic Camera On a Chip, or IEDM97: p201: CMOS Image Senso
rs-Recent Advances and Device Scaling Considerations
It introduces the pixel configuration and operation of the photogate type. ISSCC97: p180: A 1/4 Inch 330
k Square Pixel Progressive Scan CMOS Active Pixel Image Sensor classifies pixel configurations in terms of pixel selection methods. That is, the case where a transistor is used as the element to be selected or the case where a capacitor is used is described. As described above, there are various types of transistors constituting one pixel. JIEC Seminar: CMOS Camera Development Outlook: Heisei
On February 20, 2010, we introduced a wide range of CMOS-type sensors, including a logarithmic conversion type that outputs a logarithmic signal of light intensity by connecting the gate electrode and drain electrode of a reset transistor. Also said.

As shown in FIG. 4, the pixel configuration of the active sensor most often adopted is a type in which one pixel 408 is composed of three N-channel transistors and one photodiode. The P-channel side terminal of the photodiode 404 is connected to the power supply reference line 412, and the N-channel side terminal is connected to the gate terminal of the amplifying transistor 406. Amplifying transistor 406
The drain terminal and the source terminal are connected to the power supply line 409 and the drain terminal of the switching transistor 401. A gate signal line 402 is connected to the gate terminal of the switching transistor 401, and a signal output line 403 is connected to the source terminal. Reset transistor 407
These gate terminals are connected to the reset signal line 405. The source terminal and the drain terminal of the reset transistor 407 are connected to the power supply line 409 and the gate terminal of the amplification transistor 406.

In the case of an area sensor, not only one pixel 408 but many pixels are connected to one signal output line 403. However, only one bias transistor 411 is arranged for one signal output line 403. A bias signal line 410 is connected to the gate terminal of the bias transistor 411. A source terminal and a drain terminal of the bias transistor 411 are connected to the signal output line 403 and the bias power supply line 413.

  Next, a basic operation of the pixel 408 will be described.

First, the reset transistor 407 is turned on. The P-channel side terminal of the photodiode 404 is connected to the power supply reference line 412, the N-channel side terminal is electrically connected to the power supply line 409, the potential of the power supply reference line 412 is the reference potential 0V, and the power supply line 409 Is a power supply potential Vdd, a reverse bias voltage is applied to the photodiode 404. Thereafter, the operation of charging the potential of the N channel side terminal of the photodiode 404 to the potential of the power supply line 409,
This is called reset. Thereafter, the reset transistor 407 is turned off.
Then, when light is irradiated to the photodiode 404, electric charge is generated by photoelectric conversion. Therefore, as time passes, the potential of the N-channel side terminal of the photodiode 404 that has been charged to the potential of the power supply line 409 gradually decreases due to the charge generated by light. Then, after a certain time has elapsed, the switching transistor 401 is turned on. Then, a signal is output to the signal output line 403 through the amplification transistor 406.

However, when a signal is output, a potential is applied to the bias signal line 410,
A current flows through the bias transistor 411. Therefore, the amplifying transistor 406 and the biasing transistor 411 operate as a so-called source follower circuit.

In FIG. 4, the wiring to which the P channel side terminal of the photodiode 404 is connected, that is, the power supply reference line 412 may be called a diode side power supply line. The potential of the diode side power supply line varies depending on the direction of the photodiode 404. In FIG. 4, the P-channel side terminal of the photodiode 404 is connected to the diode-side power supply line, and the potential thereof is the reference potential 0V. Therefore, in FIG. 4, the diode-side power supply line is called a power supply reference line.

Similarly, in FIG. 4, the wiring to which the reset transistor 407 is connected, that is, the power supply line
409 may be called a reset-side power line. The potential of the reset side power supply line varies depending on the direction of the photodiode 404. In FIG. 4, the reset-side power line has a reset transistor.
The N-channel side terminal of the photodiode 404 is connected via 407, and its potential is the power supply potential Vdd. Therefore, in FIG. 4, the reset-side power supply line is called a power supply line.

Resetting the photodiode 404 is the same as applying a reverse bias voltage to the photodiode 404. Therefore, depending on the orientation of the photodiode 404,
The magnitude relationship between the potentials of the diode-side power supply line and the reset-side power supply line changes.

Next, FIG. 5 shows an example of the most basic source follower circuit. FIG. 5 shows the case where an N-channel transistor is used. A source follower circuit can also be configured using a P-channel transistor. A power supply potential Vdd is applied to the amplification side power supply line 503. A reference potential 0 V is applied to the bias side power supply line 504. The drain terminal of the amplifying transistor 501 is connected to the amplifying side power supply line 503, and the source terminal is connected to the drain terminal of the biasing transistor 502. The source terminal of the bias transistor 502 is connected to the bias side power line 504. A bias potential is applied to the gate terminal of the bias transistor 502.
Vb has been added. Therefore, the bias current Ib flows through the bias transistor 502. The bias transistor 502 basically operates as a constant current source.
The gate terminal of the amplifying transistor 501 becomes the input terminal 506. Therefore, the input potential Vin is applied to the gate terminal of the amplifying transistor 501. The source terminal of the amplifying transistor 501 becomes the output terminal 507. Therefore, the potential of the source terminal of the amplifying transistor 501 becomes the output potential Vout. The input / output relationship of the source follower circuit at this time is Vout = Vin−Vb.

When comparing FIG. 4 and FIG. 5, the amplifying transistor 406 corresponds to the amplifying transistor 501. The bias transistor 411 corresponds to the bias transistor 502. Since the switching transistor 401 is assumed to be in a conductive state, it can be considered omitted in FIG. The potential of the N-channel side terminal of the photodiode 404 is the input potential V
This corresponds to in (the gate potential of the amplifying transistor 501, that is, the potential of the input terminal 506). The potential of the signal output line 403 corresponds to the output potential Vout (the source potential of the amplifying transistor 501, that is, the potential of the output terminal 507). The power line 409 corresponds to the amplification side power line 503.

Therefore, in FIG. 4, the potential of the N channel side terminal of the photodiode 404 is Vpd, the potential of the bias signal line 410, that is, the bias potential is Vb, the potential of the signal output line 403 is Vout, and the power supply reference line 412 When the potential of the bias side power supply line 413 is 0 V, Vout = Vpd−Vb. Therefore, when the potential Vpd of the N-channel side terminal of the photodiode 404 changes, Vout also changes, so that the change in Vpd can be output as a signal and the light intensity can be read.

Next, a signal timing chart of the pixel 409 is shown in FIG. First, the reset transistor 407 is turned on by controlling the reset signal line 405. Then, the potential of the N-channel side terminal of the photodiode 404 is charged to the power supply potential Vdd that is the potential of the power supply line 409. That is, the pixel is reset. Then, the reset transistor 407 is turned off by controlling the reset signal line 405. Thereafter, when the photodiode 404 is irradiated with light, a charge corresponding to the light intensity is generated. Therefore, the charge charged by the reset operation is gradually discharged. That is, the potential of the N channel side terminal of the photodiode 404 is lowered. When dark light is irradiated, since the amount of discharge is small, the potential of the N-channel side terminal of the photodiode 404 does not drop so much. At a certain point, the switching transistor 401 is turned on, and the potential of the N-channel terminal of the photodiode 404 is read as a signal. This signal is proportional to the light intensity. Then, again, the reset transistor 407 is turned on and the photodiode 4
Reset 04 and repeat the same operation.

Next, a transistor in the pixel 408 is described. The polarities are often all N-channel types. In rare cases, the reset transistor may be a P-channel type (JIEC Seminar: CMOS Camera Development Outlook: February 20, 1998: p9, see Fig. 11). As for the arrangement of the amplifying transistor and the selecting transistor, both transistors are N-channel type, and as shown in FIG. 4, the power line 409 and the amplifying transistor 406 are connected, and the amplifying transistor 406 and the switching transistor are connected. In many cases, 401 is connected, and the switch transistor 401 and the signal output line 403 are connected. In rare cases, both transistors use N-channel type,
In some cases, the power supply line 409 and the switching transistor 401 are connected, the switching transistor 401 and the amplification transistor 406 are connected, and the amplification transistor 406 and the signal output line 403 are connected (ISSCC97: p180: A 1 / 4 Inch 330k Square Pixel Progressive Scan CMOS Activ
e Pixel Image Sensor).

Next, a sensor unit that performs photoelectric conversion and the like will be described. Usually, light is converted into electricity using a PN photodiode. In addition, there are PIN type diodes, avalanche type diodes, npn buried type diodes, Schottky type diodes and the like. In addition, there are photoconductors for X-rays and infrared sensors. This is described in the basics of solid-state imaging devices-the mechanism of electronic eyes: Takao Ando and Hirohito Tsuji: Japan Science and Technology Publishing.

Next, the application products of the sensor will be described. In addition to ordinary digital still cameras and scanners, they are also used for X-ray cameras. In that case, there are a case where a photoconductor that directly converts X-rays into an electric signal is used, and a case where the light is read after being converted into light by a fluorescent material or a scintillator. Euro Display 99: p203: X-ray Detectors based o
n Amorphous Silicon Active Matrix describes a case where X-rays are converted to light by a scintillator and then the light is read. IEDM 98: p21: amorphous silicon tft x-ra
y image sensors read using amorphous silicon, AM-LCD99: p45: re
The al-time imaging flat panal x-ray detector has been reported for reading using a photoconductor.

The potential of the conventional power supply line 409 is constant. On the other hand, when light is irradiated when the reset transistor 407 is in a non-conductive state, electric charge is generated in the photodiode 404. Due to the charge, the charge charged by the reset operation is discharged. As a result, the potential of the N channel side terminal of the photodiode 404 is lowered. Consider this situation from the standpoint of the reset transistor 407.

A decrease in the potential of the N-channel side terminal of the photodiode 404 is equivalent to an increase in the source-drain voltage Vds of the reset transistor 407. Here, FIG. 7 shows current characteristics of a general transistor at this time. The horizontal axis represents the gate-source voltage Vgs, and the vertical axis represents the logarithm of the drain-source current Ids. A plurality of graphs are shown using the source-drain voltage Vds as a parameter. As can be seen from FIG. 7, when the source-drain voltage Vds increases in the non-conduction state (gate-source voltage Vgs <0) region, that is, when the potential of the N-channel side terminal of the photodiode 404 decreases. , Leakage current becomes large (It is ideal that the drain-source current Ids does not flow in the non-conducting state. Therefore, the drain-source current Ids that flows in the non-conducting state is Sometimes called leakage current). Therefore, as shown in FIG. 8, a leakage current 814 flows through the reset transistor 807 to the photodiode 804. This leakage current 814 flows from the power supply line 809 toward the photodiode 804, and acts so that the potential of the N-channel side terminal of the photodiode 804 approaches the potential of the power supply line 809. As a result, as shown in FIG. 9, the potential at the N-channel side terminal of the photodiode 804 is unlikely to drop.

Considering the above, the following problems can be considered regarding the leakage current of the reset transistor 807.

First, the amount of charge per unit time generated by light in the photodiode 804 is expressed as I
Assuming that the light irradiated to the photodiode 804 is weak, Iphoto leaks current 814
Smaller than that. In such a case, the potential of the photodiode 804 does not drop no matter how much time elapses. Therefore, in the case of weak light, it is considered that no signal can be obtained.

As can be seen from FIG. 7, the leakage current 814 varies depending on the potential of the N-channel terminal of the photodiode 804 (that is, the voltage between the source and drain of the reset transistor 807). Therefore, the relationship between the potential of the N-channel terminal of the photodiode 804 and the accumulation time becomes nonlinear. Here, the accumulation time is after the photodiode 804 is reset,
This is the time until the signal is output after the switching transistor 801 is turned on, that is, the period during which charges generated by light are accumulated in the photodiode 804. If there is no leakage current 814, the potential of the N-channel side terminal of the photodiode 804 decreases with time, and the relationship between the potential of the N-channel side terminal of the photodiode 804 and the accumulation time is linear. However, when there is a leakage current 814, the potential of the N-channel side terminal of the photodiode 804 decreases with time, but the photodiode 804
When the potential at the N channel side terminal of the reset transistor 807 becomes small, the leakage current of the reset transistor 807 increases. Therefore, the potential at the N-channel terminal of the photodiode 804 is difficult to decrease. Therefore, the relationship between the potential of the N-channel terminal of the photodiode 804 and the accumulation time is not linear. As a result, the relationship between the potential of the photodiode 804 and the light intensity also becomes non-linear, which deteriorates the gamma characteristics of the image sensor.

Considering in more detail, as shown in FIG.
As a result of the potential at the channel terminal dropping, that is, the source of the reset transistor 807
As a result of the increase of the drain-to-drain voltage Vds, the leakage current 814 and the charge Iphoto per unit time generated by light may be equal.
In such a state, the potential of the N-channel side terminal of the photodiode 804 can no longer be lowered. In the case where there was no leakage current 814, even if the light was weak, the potential of the N-channel terminal of the photodiode 804 could be lowered by increasing the time for accumulating the charge generated by the light. That is, the signal value could be increased. But,
When the leakage current 814 and the charge Iphoto per unit time generated by light are equal, the potential of the N-channel terminal of the photodiode 804 does not change even if the time for storing the charge generated by light is increased. . Therefore, it becomes impossible to increase the signal value by increasing the accumulation time.

  The object of the present invention is to solve the problems of the prior art.

Conventionally, with respect to the source terminal or drain terminal of the reset transistor, the wiring connected to the terminal not connected to the photodiode, that is, the potential of the power supply line (reset power supply line) is constant. there were. In the present invention, the potential value of the wiring to which the terminal not connected to the photodiode is connected with respect to the source terminal or drain terminal of the resetting transistor at a time other than the reset operation, that is, the power line (
The potential of the reset side power supply line) is brought close to the potential of the P channel side terminal of the photodiode, that is, the potential of the power supply reference line (diode side power supply line). As a result, it is difficult for leakage current to flow from the power line (reset power line) to the photodiode.

When the potential of the N channel side terminal of the photodiode is higher than the potential of the power supply line, a leakage current flows from the photodiode toward the power supply line. For this reason, the potential at the N-channel side terminal of the photodiode tends to decrease. The potential at the N-channel terminal of the photodiode is
Even when the potential is lower than the potential of the power supply line, the leakage current is small because the voltage between the source and drain of the resetting transistor is smaller than in the conventional case.
Therefore, it is possible to prevent the potential at the N-channel side terminal of the photodiode from being easily lowered.

However, when the photodiode is reset, a potential for charging is necessary. Therefore, during the reset operation, the potential of the wiring to which the terminal not connected to the photodiode is connected with respect to the source terminal or the drain terminal of the resetting transistor, that is, the potential of the power supply line (reset-side power supply line) The value is the same as before.

In addition, as shown in FIG. 11, not only the reset transistor 1107 but also the amplifying transistor 1106 and the switching transistor 1101 are often connected to the power line 1109 (reset-side power line). In that case, there is a problem that the potential of the power supply line 1109 (reset-side power supply line) is low when the amplifier transistor 1106 is operated by passing a current. Therefore, the power line 1109
When the amplifying transistor 1106 and the switching transistor 1101 are also connected to the (reset-side power line), the potential value of the power line 1109 (reset-side power line) during the operation of the amplifying transistor 1106 Same as above.

In this way, by bringing the potential of the power supply line 1109 (reset-side power supply line) close to the potential of the power supply reference line 1112 (diode-side power supply line), the problem caused by the leakage current of the reset transistor 1107 can be improved. Therefore, even when the light applied to the photodiode 1104 is weak, the leakage current of the reset transistor 1107 does not cancel the charge amount Iphoto per unit time generated by the light in the photodiode 1104. Therefore, even in the case of weak light, the photodiode 1104 is discharged and its potential is lowered, so that a signal can be read from the pixel. Thereby, the dynamic range is expanded and the image quality is improved. In addition, since the leakage current is reduced by reducing the source-drain voltage of the reset transistor, the nonlinear relationship between the potential of the photodiode 1104 and the accumulation time is improved. As a result, the gamma characteristic is improved.

The configuration of the present invention is shown below.
The present invention is a semiconductor device having a reset transistor, a photoelectric conversion element, a reset-side power line, a diode-side power line, a reset signal line, and an amplifying transistor according to the above configuration, wherein the gate terminal of the reset transistor is One of a drain terminal and a source terminal of the reset transistor is connected to the reset-side power line, and the other is connected to the photoelectric conversion element. One terminal is connected to the diode-side power line, and the other terminal is connected to the source terminal or drain terminal of the reset transistor, and the source terminal or drain terminal of the reset transistor The amplifier is connected to a terminal connected to the photoelectric conversion element. The gate terminal of the transistor is connected,
A semiconductor device is provided in which the reset-side power supply line and the reset signal line are arranged in parallel.

The present invention is a semiconductor device having a reset transistor, a photoelectric conversion element, a reset-side power line, a diode-side power line, a reset signal line, an amplifying transistor, and a signal generating device according to the above configuration, The gate terminal is connected to the reset signal line, one of the drain terminal or the source terminal of the reset transistor is connected to the reset-side power line, and the other is connected to the photoelectric conversion element, One terminal of the photoelectric conversion element is connected to the diode-side power line, and the other terminal is connected to a source terminal or a drain terminal of the reset transistor, and a source terminal of the reset transistor Or an end connected to the drain terminal and the photoelectric conversion element Further, a gate terminal of the amplifying transistor is connected, and a signal generator that operates to bring the potential of the reset-side power line close to the potential of the diode-side power line is connected to the reset-side power line A semiconductor device is provided.

The present invention has a reset transistor, a photoelectric conversion element, a reset side power line, a diode side power line, and a reset signal line, and the gate terminal of the reset transistor is connected to the reset signal line. One of the drain terminal and the source terminal of the reset transistor is connected to the reset-side power line, the other is connected to the photoelectric conversion element, and one terminal of the photoelectric conversion element is the diode The other terminal is connected to the source terminal or drain terminal of the reset transistor, and when the reset transistor is in a non-conductive state, the potential of the reset power line is A driving method of a semiconductor device, characterized in that the driving method is close to the potential of the diode side power supply line It is subjected.

The present invention has a reset transistor, a photoelectric conversion element, a reset side power line, a diode side power line, and a reset signal line, and the gate terminal of the reset transistor is connected to the reset signal line. One of the drain terminal and the source terminal of the reset transistor is connected to the reset-side power line, the other is connected to the photoelectric conversion element, and one terminal of the photoelectric conversion element is the diode In the method of driving a semiconductor device in which the other terminal is connected to the source terminal or drain terminal of the reset transistor, the reset terminal is connected when the reset transistor is in a non-conducting state. Side power supply line potential when the reset transistor is conductive The driving method of a semiconductor device which is characterized in that the intermediate potential between the potential of the diode-side power supply line is provided.

The present invention has a reset transistor, a photoelectric conversion element, a reset power line, a diode power line, a reset signal line, and an amplifying transistor, and the gate terminal of the reset transistor is connected to the reset signal line. One of the drain terminal and the source terminal of the reset transistor is connected to the reset-side power line, the other is connected to the photoelectric conversion element, and one terminal of the photoelectric conversion element Is connected to the diode-side power line, and the other terminal is connected to the source terminal or drain terminal of the reset transistor, and the source terminal or drain terminal of the reset transistor and the photoelectric conversion element And a terminal of the amplifying transistor connected to a terminal connected to A method for driving a semiconductor device to which a terminal is connected, characterized in that the potential of the reset-side power supply line is brought close to the potential of the diode-side power supply line when the reset transistor is non-conductive. A method is provided.

The present invention has a reset transistor, a photoelectric conversion element, a reset power line, a diode power line, a reset signal line, and an amplifying transistor, and the gate terminal of the reset transistor is connected to the reset signal line. One of the drain terminal and the source terminal of the reset transistor is connected to the reset-side power line, the other is connected to the photoelectric conversion element, and one terminal of the photoelectric conversion element Is connected to the diode-side power line, and the other terminal is connected to the source terminal or drain terminal of the reset transistor, and the source terminal or drain terminal of the reset transistor and the photoelectric conversion element And a terminal of the amplifying transistor connected to a terminal connected to In the method for driving a semiconductor device to which a terminal is connected, the potential of the reset-side power line when the reset transistor is non-conductive, the potential when the reset transistor is conductive and the diode-side power line There is provided a method for driving a semiconductor device, characterized in that the potential is set to an intermediate potential.

The photoelectric conversion element may be an X-ray sensor or an infrared sensor.

The photoelectric conversion element may be any one of a photodiode, a Schottky diode, an avalanche diode, or a photoconductor.

The photodiode may be any one of a PN type, a PIN type, and an NPN embedded type.

The present invention can reduce the adverse effect of the leakage current of the reset transistor on the photoelectric conversion element. Therefore, a sensor with high image quality is realized.

Circuit diagram of pixel circuit of the present invention Timing chart of pixel circuit of the present invention Circuit diagram of a conventional passive sensor pixel Conventional active sensor pixel circuit diagram Circuit diagram of conventional source follower circuit Timing chart with active sensor Current characteristics of transistor A circuit diagram of a pixel of a conventional active sensor. Timing chart with conventional active sensor Timing chart with conventional active sensor Circuit diagram of pixel circuit of the present invention Timing chart of the active sensor of the present invention Circuit diagram of pixel circuit of the present invention Timing chart of the active sensor of the present invention Timing chart of the active sensor of the present invention Block diagram of area sensor of the present invention Circuit diagram of pixel of active sensor of the present invention Circuit diagram of pixel of active sensor of the present invention Circuit diagram of signal processing circuit of the present invention Circuit diagram of final output amplification circuit of the present invention Circuit diagram of final output amplification circuit of the present invention Timing chart of area sensor of the present invention Timing chart of area sensor of the present invention Timing chart of area sensor of the present invention Timing chart of area sensor of the present invention Timing chart of area sensor of the present invention The figure which shows the preparation process of the image sensor of this invention The figure which shows the preparation process of the image sensor of this invention The figure which shows the preparation process of the image sensor of this invention The figure which shows the preparation process of the image sensor of this invention Diagram of an electronic device using the image sensor of the present invention Diagram of an electronic device using the image sensor of the present invention Diagram of an electronic device using the image sensor of the present invention Diagram of an electronic device using the image sensor of the present invention

[Embodiment 1] A typical embodiment of the present invention will be described below. First, FIG. 1 shows a circuit diagram and FIG. 2 shows a timing chart of an embodiment in which the present invention is implemented when an active sensor is used.

The circuit diagram is the same as the conventional one. However, the reset-side power supply line 109 and the amplification-side power supply line 108 are conventionally connected in many cases. In this embodiment, it may be either connected or not connected. First, a timing chart for the case where the connection is not made will be described.

First, the reset signal line 105 is controlled, the reset transistor 107 is turned on, and the photodiode 104 is reset. Thereafter, the reset transistor 107 is turned off, and the accumulation time starts. At that time, the potential of the reset side power supply line 109 is lowered to approach the potential of the diode side power supply line 110. At that time, the most desirable potential of the reset-side power line 109 is an intermediate potential between the potential of the reset-side power line 109 and the potential of the diode-side power line 110 at the time of reset.

Then, in the dark, the potential of the N-channel side terminal of the photodiode 104 is higher than the potential of the reset-side power line 109, so that the leakage current from the photodiode 104 to the reset-side power line 10
It flows toward 9. Therefore, even when it is dark, the potential at the N-channel side terminal of the photodiode 104 tends to decrease.

When it is bright, the potential of the N-channel side terminal of the photodiode 104 decreases as time passes. Initially, since the potential of the N channel side terminal of the photodiode 104 is higher than the potential of the reset side power line 109, the leakage current flows from the photodiode 104 toward the reset side power line 109. Thereafter, the potential of the reset-side power line 109 becomes higher than the potential of the N-channel side terminal of the photodiode 104, and the leakage current flows from the reset-side power line 109 toward the photodiode 104.
In this way, since the direction of leakage current is reversed, the adverse effect of the leakage current can be offset. Further, since the voltage between the source and the drain of the reset transistor 107 is small, the leakage current itself is less than that in the conventional case.

Then, before resetting the photodiode 104 again, the gate signal line 102 is controlled, the switching transistor 101 is turned on, and a signal is output to the signal output line 103. after that,
The photodiode 104 is reset again. At that time, the potential of the reset power line 109 is
Put it back.

However, if the reset-side power line 109 and the amplification-side power line 108 are connected, the signal output line
When outputting a signal to 103, if the potential of the reset-side power line 109 is lowered, a correct signal cannot be output. Therefore, when the reset-side power supply line 109 and the amplification-side power supply line 108 are connected, the potential of the reset-side power supply line 109 is returned to the original level when a signal is output.

In FIG. 2, the potential of the amplification side power supply line 108 during the accumulation time was about the middle.
As shown in FIG. 5, the potential may be lowered to substantially the same as the potential of the diode-side power supply line 110.

In FIG. 1, the P-channel side terminal of the photodiode 104 is connected to the diode-side power line 110. However, as shown in FIG. 13, the N-channel side terminal of the photodiode 1304 may be connected to the diode-side power line 1310. However, in that case, the magnitude relation of the potential is reversed. In FIG. 1, the potential of the reset side power line 109 is higher than the potential of the diode side power line 110. On the other hand, in FIG. 13, the potential of the reset-side power supply line 1309 is greater than the diode-side power supply line.
Lower than 1310 potential. This is because a reverse bias voltage is applied when the photodiode 1304 is reset. A diagram corresponding to FIG. 2 is shown in FIG. 14, and a diagram corresponding to FIG. 12 is shown in FIG.

Also in FIG. 13, the reset-side power supply line 1309 and the amplification-side power supply line 1308 may be either connected or not connected.

1 and 13, the amplifying transistor, the resetting transistor, and the switching transistor may be N-channel type or P-channel type.

In FIG. 1 and FIG. 13, the switching transistor may be disposed between the amplification-side power supply line and the amplification transistor, or may be disposed between the amplification transistor and the signal output line.

Next, an embodiment in which the present invention is applied to an area sensor in which a drive circuit is mounted in the periphery and pixels are two-dimensionally arranged will be described. The overall circuit diagram is shown in FIG. First, there is a pixel array unit 1605 in which pixels are arrayed two-dimensionally. In addition, driving circuits for driving the gate signal line, the reset signal line, and the power supply line of each pixel are arranged on the left and right sides of the pixel array portion 1605. In FIG.
A gate signal line reset signal line drive circuit 1606 is arranged on the left side, and a power supply line drive circuit 1607 is arranged on the right side.

A signal processing circuit or the like is disposed above the pixel array unit 1605. In FIG. 16, a bias circuit 1603 is arranged on the pixel array portion 1605. This bias circuit
A source follower circuit 1603 is paired with the amplifying transistor of each pixel. A sample hold & signal processing circuit 1602 is arranged on the bias circuit 1603.
Here, a circuit for temporarily storing the signal, performing analog / digital conversion, and reducing noise is arranged. Sample hold & signal processing circuit
A signal output line driving circuit 1601 is disposed on the 1602. Signal output line drive circuit 1601
Outputs a signal for sequentially outputting the temporarily stored signals. A final output amplification circuit 1604 is arranged before a signal is output to the outside. Here, the signals output in order by the sample hold & signal processing circuit 1602 and the signal output line driving circuit 1601 are amplified before being output. Therefore, it is not necessary when the signal is not amplified, but in reality, it is often arranged.

Next, a circuit diagram of each part is shown. First, as an example, a circuit diagram of an i-th row and j-th column pixel portion circuit 1608 from the two-dimensionally arranged pixel arrangement portion 1605 is shown in FIG. In FIG. 17, a P-channel reset transistor 1707, a P-channel switch transistor 1701, an N-channel amplification transistor 1706, and a photoelectric conversion element (here, the most typical photodiode 1704)
It is composed of In the photodiode 1704, the P channel side terminal is connected to the power supply reference line 1712, and the N channel side terminal is connected to the gate terminal of the amplifying transistor 1706. An i-th row reset signal line 1705 is connected to the gate terminal of the reset transistor 1707, and a source terminal and a drain terminal are connected to the i-th row power supply line 1709 and the gate terminal of the amplification transistor 1706. The gate terminal of the switching transistor 1701 is connected to the i-th gate signal line 1702, and the source terminal and the drain terminal are connected to the i-th power line 1709 and the amplifying transistor 1706. The source terminal and drain terminal of the amplifying transistor 1706 are connected to the j-th column signal output line 1703 and the switching transistor 1701. The j-th column signal output line 1703 and the i-th row gate signal line 1702 are arranged so as to cross each other as usual, and the j-th column signal output line 1703 extends in the vertical direction. The i-th gate signal line 1702 and the i-th reset signal line 1705 extend in the horizontal direction and are arranged in parallel as in the past. In FIG. 16 and FIG. 17, the i-th power line 1709 also extends in the horizontal direction and is arranged in parallel with the i-th reset signal line 1705. Conventionally, it has extended in the vertical direction. This is because the pixel photodiode is selected for each row, and similarly, the voltage of the power supply line can be changed for each row.

In FIG. 17, the reset transistor 1707 is a P-channel type. However, the reset transistor may be an N-channel type. However, in the N-channel type, the gate-source voltage cannot be increased during the reset operation. Therefore, the reset transistor operates in the saturation region, and the photodiode 1704 cannot be charged sufficiently. Therefore, the reset transistor operates with an N-channel type, but a P-channel type is more desirable.

For the switching transistor 1701, the i-th power line 1709 and the amplifying transistor 1706
It is desirable to use a P-channel type. However, since the N-channel type operates as in the conventional case, the N-channel type may be used, and it may be arranged between the j-th column signal output line 1703 and the amplifying transistor 1706. However, since it is difficult to output a signal correctly, the switching transistor 1701 is arranged between the i-th power line 1709 and the amplifying transistor 1706,
In addition, it is desirable to use the P channel type.

As the amplifying transistor 1706, an N-channel type is used in FIG.
However, it is also possible to use a P channel type. However, in that case, in order to operate as a source follower circuit in combination with the bias transistor, it is necessary to change the circuit connection method. That is, simply changing the polarity of the amplifying transistor 1706 in the circuit diagram of FIG.

Thus, FIG. 18 shows an example of a circuit configuration when a P-channel type amplifying transistor is used. The difference from FIG. 17 is that the polarity of the amplifying transistor 1806 is a P-channel type, the direction of the photodiode is reversed, and the power supply line and the power supply reference line are interchanged. When the P-channel type is used for the amplifying transistor, it is necessary to use the P-channel type for the bias transistor. This is because the biasing transistor needs to be operated as a constant current source. Therefore, in FIG. 18, a biasing transistor 1811 is also described for reference. 18 includes an N-channel reset transistor 1807, an N-channel switch transistor 1801, a P-channel amplification transistor 1806, a photoelectric conversion element (here, the most representative photo). Diode 1804). The photodiode 1804 has an N-channel terminal connected to the power supply line 1809 and a P-channel terminal connected to the gate terminal of the amplifying transistor 1806. The i-th reset signal line 1805 is connected to the gate terminal of the reset transistor 1807, and the source terminal and drain terminal are connected to the i-th power supply reference line 1812 and the gate terminal of the amplification transistor 1806. The gate terminal of the switching transistor 1801 is connected to the i-th gate signal line 1802, and the source terminal and drain terminal are connected to the i-th power supply reference line 1812 and the amplifying transistor 1806. The source terminal and drain terminal of the amplifying transistor 1806 are connected to the j-th column signal output line 1803.
And the switch transistor 1801. A bias signal line 1810 is connected to a gate terminal of the bias transistor 1811, and a source terminal and a drain terminal are connected to a j-th column signal output line 1803 and a power supply line 1809.

In FIG. 18, the reset transistor 1807 is an N-channel type. However, the reset transistor may be a P-channel type. However, in the case of the P channel type, the gate-source voltage cannot be increased during the reset operation. Therefore, the reset transistor operates in the saturation region, and the photodiode 1804 cannot be charged sufficiently. Therefore, the reset transistor operates with a P-channel type, but is preferably an N-channel type.

In FIG. 18, the switching transistor 1801 is preferably disposed between the j-th column power supply reference line 1812 and the amplifying transistor 1806, and is preferably an N-channel type. However, since the P-channel type also operates, the P-channel type may be used, or it may be disposed between the j-th column signal output line 1803 and the amplifying transistor 1806. However, since it is difficult to output a signal correctly, it is desirable that the switching transistor 1801 is disposed between the j-th column power supply reference line 1809 and the amplifying transistor 1806 and is an N-channel type.

Thus, as can be seen from a comparison between FIGS. 17 and 18, when the polarity of the amplifying transistor is different, the optimum transistor configuration, the direction of the photodiode, and the like are also different.

In FIG. 17, current is supplied from one power supply line to both the switching transistor 1701 and the resetting transistor 1707. In FIG. 18, current is supplied to both the switching transistor 1801 and the resetting transistor 1807 from one power supply reference line. Thus, the wiring can be shared by matching the direction of the photodiode and the polarity of the amplifying transistor.

However, it is also possible to increase the number of wires for supplying current and supply current separately. In that case, the potential of the wiring that supplies current to the switching transistor may be a constant potential.
Further, it is not necessary to match the direction of the photodiode and the polarity of the amplifying transistor.

Next, FIG. 19 shows a circuit diagram of a j-th column peripheral circuit 1609 as a circuit for one column out of the bias circuit 1603 and the sample hold & signal processing circuit 1602. A bias transistor 1911 is disposed in the bias circuit 1603. The polarity is the same as the polarity of the amplifying transistor of each pixel. Therefore, when the amplifying transistor of the pixel is an N channel type, the bias transistor is also an N channel type. In FIG. 19, the biasing transistor 1911 for biasing is an N-channel type. A bias signal line 1910 is connected to a gate terminal of the bias transistor 1911, and a source terminal and a drain terminal are connected to a j-th column signal output line 1903.
And the power supply reference line 1912 (when the bias transistor is a P-channel type,
Use a power line instead of a power line.) The biasing transistor 1911 is paired with the amplifying transistor of each pixel and operates as a source follower circuit. A transfer signal line 1914 is connected to the gate terminal of the transfer transistor 1913, and the source terminal and the drain terminal are
The j-th column signal output line 1903 and the load capacitor 1915 are connected. The transfer transistor is operated when the potential of the signal output line 1903 is transferred to the load capacitor 1915. Therefore, a P-channel transfer transistor may be added and connected in parallel with the N-channel transfer transistor 1914. The load capacitor 1915 is connected to the transfer transistor 1913 and the power supply reference line 1912.
The role of the load capacitor 1915 is to temporarily store a signal output from the signal output line 1903. The gate terminal of the discharging transistor 1916 is connected to the pre-discharge signal line 1917, and the source terminal and the drain terminal are connected to the load capacitor 1915 and the power supply reference line 1912. Before the discharge transistor 1916 inputs the potential of the signal output line 1903 to the load capacitor 1915, the discharge capacitor 1916
It operates to discharge the charge accumulated in 1915.

An analog / digital signal conversion circuit, a noise reduction circuit, or the like can be arranged.

A final selection transistor 1919 is connected between the load capacitor 1915 and the final output line 1920. The source terminal and the drain terminal of the final selection transistor 1919 are connected to the load capacitor 1915 and the final output line 1920, and the gate terminal is connected to the j-th column final selection line 1918. The final selection line is scanned sequentially from the first column. When the j-th column final selection line 1918 is selected and the final selection transistor 1919 becomes conductive, the potential of the load capacitor 1915 and the potential of the final output line 1920 become equal. As a result, the signal accumulated in the load capacitor 1915 can be output to the final output line 1920. However, if charges are accumulated in the final output line 1920 before the signal is output to the final output line 1920, the electric potential when the signal is output to the final output line 1920 is affected by the charge. Therefore, before the signal is output to the final output line 1920, the potential of the final output line 1920 must be initialized to a certain potential value. In Figure 19, the final output line 1920 and the power reference line
A final reset transistor 1922 is disposed between 1912. The j-th column final reset line 1921 is connected to the gate terminal of the final reset transistor 1922. Then, before selecting the j-th column final selection line 1918, the j-th column final reset line 1921 is selected, and the potential of the final output line 1920 is initialized to the potential of the power supply reference line 1912. Thereafter, the j-th column final selection line 1918 is selected, and the signal accumulated in the load capacitor 1915 is output to the final output line 1920.

The signal output to the final output line 1920 may be taken out as it is. However,
Since the signal is weak, the signal is often amplified before being taken out. As a circuit for that purpose, FIG. 20 shows a circuit of the final circuit 1610. There are various circuits such as operational amplifiers for amplifying signals. Any circuit may be used as long as it is a circuit that amplifies a signal. Here, a source follower circuit is shown as the simplest circuit configuration. FIG. 20 shows an N channel type case. An input to the final output amplification circuit 1604 is a final output line 2002. Signals are output to the final output line 2002 in order from the first column. The signal is amplified by the final output amplification circuit 1604 and output to the outside. The final output line 2002 is connected to the gate terminal of the amplifying transistor 2004 for final output amplification. The drain terminal of the amplifying transistor 2004 for final output amplification is connected to the power supply line 2006, and the source terminal is an output terminal. The gate terminal of the final output amplification bias transistor 2003 is connected to the final output amplification bias signal line 2005. The source terminal and the drain terminal are connected to the power supply reference line 2007 and the source terminal of the amplification transistor 2004 for final output amplification.

FIG. 21 shows a circuit diagram in the case of using a source follower circuit in the case of the P channel type. FIG.
The difference is that the power supply line and the power supply reference line are reversed. The final output line 2102 is connected to the gate terminal of the amplification transistor 2104 for final output amplification. The drain terminal of the amplifying transistor 2104 for final output amplification is connected to the power supply reference line 2107, and the source terminal is an output terminal. The gate terminal of the final output amplification bias transistor 2103 is connected to the final output amplification bias signal line 2105. The source terminal and the drain terminal are connected to the power supply line 2106 and the source terminal of the amplification transistor 2104 for final output amplification. The potential of the final output amplification bias signal line 2105 is the same as that of the final output amplification bias signal line 2005 when the N-channel type is used.
And the value is different.

In FIG. 20 and FIG. 21, the source follower circuit is composed of only one stage. However, it may be composed of a plurality of stages. For example, in the case of two stages, the first stage output terminal may be connected to the second stage input terminal. In each stage, either an N channel type or a P channel type may be used.

The gate signal line reset signal line drive circuit 1606, the power supply line drive circuit 1607, and the signal output line drive circuit 1601 are circuits that simply output pulse signals. Therefore, it can be implemented using a known technique.

Next, a timing chart of signals will be described. First, timing charts in the circuits of FIGS. 16 and 17 are shown in FIGS. The reset signal line is scanned sequentially from the first row. For example, the (i-1) -th row is selected, the i-th row is then selected, and then the (i + 1) -th row is selected. A period until the same row is selected again corresponds to a frame period. Similarly, the gate signal lines are scanned sequentially from the first row. However, the timing to start scanning the gate signal line is later than the timing to start scanning the reset signal line.
For example, when focusing on the pixel in the i-th row, the i-th row reset signal line is selected, and then the i-th gate signal line is selected. When the i-th gate signal line is selected, a signal is output from the i-th row pixel. The period from when the pixel is reset to when a signal is output is the accumulation time. During the accumulation time, charges generated by light are accumulated in the photodiode. In each row, the reset timing and the signal output timing are different. Therefore, the accumulation time is the same for all rows of pixels, but the accumulation time is different.

For the power supply line 1709, after the reset transistor 1707 is turned off, the power supply line 17
The voltage of 09 is also lowered in order. The reason for delaying the timing to lower the voltage of the power supply line 1709 is that the reset transistor 1707 is completely turned off so that the voltage of the photodiode 1704 is not affected by the power supply line 1709. This is because the voltage of the power supply line 1709 must be lowered later. At this time, the voltage of the power supply line 1709 is not lowered completely in FIG. In FIG. 23, it is fully lowered. Thereafter, when the photodiode 1704 is irradiated with light, a charge corresponding to the light intensity is generated in the photodiode 1704. As a result, the voltage of the photodiode 1704 decreases according to the light intensity. When the light intensity is higher, more charges are generated, and thus the voltage drop of the photodiode 1704 is also greater.

In FIG. 22, the voltage of the power supply line 1709 is lowered by about half. Therefore, the direction of leakage current flowing through the reset transistor 1707 varies depending on the voltage value of the photodiode 1704. First, when the light is weak, the voltage of the photodiode 1704 does not drop much. Therefore, the leakage current of the reset transistor 1707 flows from the photodiode 1704 toward the power supply line 1709. Therefore, even if the charge amount Iphoto per unit time generated by light is small, it contributes to the change in the voltage of the photodiode 1704, so that a signal can be obtained. Next, when the light is strong, the voltage of the photodiode 1704 decreases sufficiently. Therefore, the leakage current of the reset transistor 1707 flows from the power supply line 1709 toward the photodiode 1704. However, since the voltage between the source and the drain of the reset transistor 1707 is small, the leakage current of the reset transistor 1707 is smaller than that of the conventional transistor. Initially, the power line from the photodiode 1704
When the voltage of the photodiode 1704 flows toward 1709 and the voltage of the power supply line 1709 falls, the leakage current flows from the power supply line 1709 to the photodiode 1704.
That is, the direction of the leakage current of the reset transistor 1707 changes. Accordingly, since they cancel each other, the influence of the leakage current of the reset transistor 1707 is reduced. From the above, the nonlinear relationship between the voltage of the photodiode 1704 and the accumulation time is improved. as a result,
Improved gamma characteristics.

In FIG. 23, the voltage of the power supply line 1709 is completely low. Thus, leakage current of the reset transistor 1707 from the power supply line 1709 to the photodiode 1704 can be prevented. Therefore, the problem that the voltage of the photodiode 1704 is difficult to decrease when dark light is irradiated on the photodiode 1704 is improved.

Then, the gate signal line 1702 is controlled to output a signal. In FIG. 17, current is supplied from one power supply line to both the switching transistor 1701 and the resetting transistor 1707. In that case, it is necessary to restore the potential of the power supply line 1709 even when a signal is output. If current is supplied using separate wirings, the potential of the wiring that supplies current to the switching transistor 1701 may be a constant potential without being changed with time. At that time, power line 1709
There is no need to restore the original potential.

Next, timing charts in the circuits of FIGS. 16 and 18 are shown in FIGS. 24 and 25. FIG. Since the polarity of the transistor and the direction of the photodiode are different, the potential relationship is different, but the operation itself is the same as in FIGS.

Next, FIG. 26 shows a timing chart of signals in FIG. Since this is a repetitive operation, consider the case where the i-th gate signal line is selected as an example. First, after the gate signal line 1702 in the i-th row is selected, the pre-discharge signal line 1917 is selected, and the discharging transistor 1916 is turned on. Thereafter, the transfer signal line 1914 is selected. Then, the signal of each column is output to the load capacitance 1915 of each column from the pixel in the i-th row.

After the signals of all the pixels in the i-th row are accumulated in the load capacitance 1915 of each column, the signals of each column are sequentially output to the final output line 1920. The signal output line driving circuit 1601 scans all the columns until the gate signal line is selected after the transfer signal line 1914 is deselected. First, the final reset line in the first column is selected, the final reset transistor 1922 is turned on, and the final output line 1920 is initialized to the potential of the power supply reference line 1912. Then the last selection line 19 in the first column
18 is selected, the final selection transistor 1919 is turned on, and the signal of the load capacitor 1915 in the first column is output to the final output line 1920. Next, the final reset line in the second column is selected, the final reset transistor 1922 is turned on, and the final output line 1920 is initialized to the potential of the power supply reference line 1912. Thereafter, the final selection line 1918 in the second column is selected, the final selection transistor 1919 is turned on, and the signal of the load capacitor 1915 in the second column is output to the final output line 1920. Thereafter, the same operation is repeated. Also in the j-th column, the final reset line in the j-th column is selected, the final reset transistor 1922 is turned on, and the final output line 1920 is initialized to the potential of the power supply reference line 1912.
Thereafter, the final selection line 1918 in the jth column is selected, the final selection transistor 1919 is turned on, and the signal of the load capacitor 1915 in the jth column is output to the final output line 1920. Next, the final reset line in the (j + 1) th column is selected, the final reset transistor 1922 is turned on, and the final output line 1920 is initialized to the potential of the power supply reference line 1912. Thereafter, the final selection line 1918 in the (j + 1) th column is selected, the final selection transistor 1919 is turned on, and the signal of the load capacitor 1915 in the (j + 1) th column is output to the final output line 1920. Thereafter, the same operation is repeated, and the signals of all the columns are sequentially output to the final output line. Meanwhile, the bias signal line 1910 remains constant. Final output line 19
The signal output to 20 is amplified by the final output amplification circuit 1604 and output to the outside.

Next, the (i + 1) th row gate signal line is selected. Then, the operation is performed in the same manner as when the i-th gate signal line is selected. Further, the gate signal line in the next row is selected, and the same operation is repeated.

For sensor units that perform photoelectric conversion, in addition to ordinary PN type photodiodes, PIN type diodes, avalanche type diodes, npn buried type diodes, Schottky type diodes, X-ray photoconductors, infrared rays For example, a sensor may be used. Also,
After converting X-rays into light using a fluorescent material or scintillator, the light may be read.

As described above, the photoelectric conversion element is often connected to the input terminal of the source follower circuit. However, a switch may be interposed between them as in the photogate type. Or you may input the signal after processing so that it may become the logarithm value of light intensity like a logarithmic conversion type | mold to an input terminal.

In the present embodiment, the area sensor in which the pixels are two-dimensionally described has been described, but a line sensor in which the pixels are one-dimensionally arranged can also be realized.

About the production method when producing the sensor of the present invention on glass using TFT,
This will be described with reference to FIGS.

First, as shown in FIG. 27A, a base film 201 is formed to a thickness of 300 nm over a glass substrate 200. In this embodiment, a silicon nitride oxide film is stacked and used as the base film 201. At this time, the nitrogen concentration in contact with the glass substrate 200 is preferably set to 10 to 25 wt%. In addition, it is effective to provide the base film 201 with a heat dissipation effect, and a DLC (diamond-like carbon) film may be provided.

Next, an amorphous silicon film (not shown) having a thickness of 50 nm is formed on the base film 201 by a known film formation method. Note that the semiconductor film is not limited to an amorphous silicon film, and any semiconductor film including an amorphous structure (including a microcrystalline semiconductor film) may be used. Further, a compound semiconductor film including an amorphous structure such as an amorphous silicon germanium film may be used. The film thickness may be 20 to 100 nm.

Then, the amorphous silicon film is crystallized by a known technique to form a crystalline silicon film (also referred to as a polycrystalline silicon film or a polysilicon film) 202. Known crystallization methods include a thermal crystallization method using an electric furnace, a laser annealing crystallization method using laser light, and a lamp annealing crystallization method using infrared light. In this embodiment, crystallization is performed using excimer laser light using XeCl gas.

In this embodiment, a pulse oscillation type excimer laser beam processed into a linear shape is used. However, a rectangular shape, a continuous oscillation type argon laser beam, or a continuous oscillation type excimer laser beam may be used. .

In this embodiment, a crystalline silicon film is used as an active layer of a TFT, but an amorphous silicon film can also be used.

Note that it is effective to form the active layer of the resetting transistor that needs to reduce the off current from an amorphous silicon film and the active layer of the amplifying transistor from a crystalline silicon film. Since the amorphous silicon film has low carrier mobility, it is difficult for an electric current to flow and an off current is difficult to flow. That is,
Advantages of both an amorphous silicon film that hardly allows current to flow and a crystalline silicon film that easily allows current to flow can be utilized.

Next, as shown in FIG. 27B, a protective film 2 made of a silicon oxide film is formed on the crystalline silicon film 202.
03 is formed to a thickness of 130 nm. This thickness is 100-200 nm (preferably 130
It may be selected in the range of ˜170 nm. Any other film may be used as long as it is an insulating film containing silicon.
This protective film 203 is provided to prevent the crystalline silicon film from being directly exposed to plasma when impurities are added, and to enable fine concentration control.

Then, resist masks 204a, 204b, and 204c are formed thereon, and the protective film 20
Impurity element imparting n-type via 3 (hereinafter referred to as n-type impurity element)
Add. As the n-type impurity element, typically, an element belonging to Group 15 of the periodic table,
Typically, phosphorus or arsenic can be used. In this embodiment, phosphine (PH
₃ ) Using a plasma doping method in which plasma is excited without mass separation, phosphorus is 1 × 10 ¹
Add at a concentration of ⁸ atoms / cm ³ . Of course, an ion implantation method for performing mass separation may be used.

In the n-type impurity regions (b) 205a and 205b formed by this step, an n-type impurity element is 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ (typically 5 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³
) Adjust the dose so that it is included at the concentration of

Next, as shown in FIG. 27C, the protective film 203 and the resist masks 204a and 204b
, 204c are removed, and the added n-type impurity element is activated. As the activation means, a known technique may be used. In this embodiment, activation is performed by irradiation with excimer laser light (laser annealing). Of course, the pulse oscillation type or the continuous oscillation type may be used, and it is not necessary to limit to the excimer laser beam. However, since the purpose is to activate the added impurity element, it is preferable to irradiate with energy that does not melt the crystalline silicon film. Note that laser light may be irradiated with the protective film 203 attached.

When the impurity element is activated by the laser beam, activation by heat treatment (furnace annealing) may be used in combination. When activation by heat treatment is performed, heat treatment at about 450 to 550 ° C. may be performed in consideration of the heat resistance of the substrate.

By this step, the end portions of n-type impurity regions (b) 205a and 205b, that is, the boundary portions (junctions) with regions not added with the n-type impurity element existing around n-type impurity regions (b) 205a and 205b. Part) becomes clear. This is because when the TFT is completed later, the LD
This means that the D region and the channel formation region can form a very good junction.

Next, as shown in FIG. 27D, unnecessary portions of the crystalline silicon film are removed to form island-shaped semiconductor films (hereinafter referred to as active layers) 206 to 210.

Next, as illustrated in FIG. 28A, the gate insulating film 211 is covered with the active layers 206 to 210.
Form. The gate insulating film 211 is 10 to 200 nm, preferably 50 to 150.
An insulating film containing silicon with a thickness of nm may be used. This may be a single layer structure or a laminated structure.
In this embodiment, a silicon nitride oxide film having a thickness of 110 nm is used.

Next, a conductive film having a thickness of 200 to 400 nm is formed and patterned to form gate electrodes 212 to
216 is formed. In this embodiment, the gate electrode and the wiring for electrical connection (hereinafter referred to as gate wiring) electrically connected to the gate electrode are formed of the same material. Of course, the gate electrode and the gate wiring may be formed of different materials. Specifically, a material having a lower resistance than the gate electrode may be used as the gate wiring. This is because a material that can be finely processed is used for the gate electrode, and a material that has a low wiring resistance is used for the gate wiring even though it cannot be finely processed. With such a structure, the wiring resistance of the gate wiring can be extremely reduced, so that a sensor portion having a large area can be formed. That is, the above pixel structure is extremely effective in realizing an area sensor having a sensor portion with a screen size of 10 inches or more (or 30 inches or more) diagonally.

The gate electrode may be formed of a single-layer conductive film, but it is preferable to form a stacked film of two layers or three layers as necessary. Any known conductive film can be used as a material for the gate electrodes 212 to 216.

Typically, a film made of an element selected from aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), silicon (Si), or the above Element nitride films (typically tantalum nitride films, tungsten nitride films,
Titanium nitride film) or an alloy film combining the above elements (typically Mo—W alloy, Mo
-Ta alloy), or a silicide film of the element (typically a tungsten silicide film,
Titanium silicide film) can be used. Of course, it may be used as a single layer or may be laminated.

In this embodiment, a stacked film including a tungsten nitride (WN) film having a thickness of 30 nm and a tungsten (W) film having a thickness of 370 nm is used. This may be formed by sputtering. Further, when an inert gas such as Xe or Ne is added as a sputtering gas, peeling of the film due to stress can be prevented.

At this time, the gate electrodes 213 and 216 are n-type impurity regions (b) 205a and 2a, respectively.
It is formed so as to overlap a part of 05b with the gate insulating film 211 interposed therebetween. This overlapped portion later becomes an LDD region overlapping with the gate electrode.

Next, as shown in FIG. 28B, an n-type impurity element (phosphorus in this embodiment) is added in a self-aligning manner using the gate electrodes 212 to 216 as masks. The n-type impurity regions (c) 217 to 224 thus formed have 1/2 to 1/1 of the n-type impurity regions (b) 205a and 205b.
Adjust so that phosphorus is added at a concentration of 0 (typically 1/3 to 1/4). Specifically, a concentration of 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ (typically 3 × 10 ^{17 to} 3 × 10 ¹⁸ atoms / cm ³ ) is preferable.

Next, as shown in FIG. 28C, resist masks 225a to 225c are formed so as to cover the gate electrodes 212, 214, and 215, and an n-type impurity element (phosphorus in this embodiment) is added to form a high concentration. N-type impurity regions (a) 226 to 233 containing phosphorus are formed. Again, the ion doping method using phosphine (PH ₃ ) is used, and the phosphorus concentration in this region is 1 × 10 ²⁰ to
It is adjusted to 1 × 10 ²¹ atoms / cm ³ (typically 2 × 10 ^{20 to} 5 × 10 ²¹ atoms / cm ³ ).

By this step, the source region or drain region of the n-channel TFT is formed. In the n-channel TFT, the n-type impurity region 217 formed in the step of FIG.
218, 222 and 223 are left. This remaining region becomes an LDD region.

Next, as illustrated in FIG. 28D, the resist masks 225a to 225c are removed, and new resist masks 234a and 234b are formed. Then, a p-type impurity element (boron in this embodiment) is added to form p-type impurity regions 235 and 236 containing boron at a high concentration.
Here, 3 × 10 ^{20 to} 3 × 10 ²¹ atom is formed by ion doping using diborane (B ₂ H ₆ ).
Boron is added so as to have a concentration of s / cm ³ (typically 5 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ ).

Note that phosphorus is already added to the impurity regions 235 and 236 at a concentration of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ , but the boron added here is added at a concentration at least three times higher than that. Is done. Therefore, the n-type impurity region formed in advance is completely inverted to the p-type and functions as a p-type impurity region.

Next, after removing the resist masks 234a and 234b, the n-type or p-type impurity elements added at the respective concentrations are activated. As activation means, furnace annealing method,
Laser annealing or lamp annealing can be used. In this embodiment, heat treatment is performed in an electric furnace in a nitrogen atmosphere at 550 ° C. for 4 hours.

At this time, it is important to eliminate oxygen in the atmosphere as much as possible. This is because the presence of even a small amount of oxygen oxidizes the exposed surface of the gate electrode, leading to an increase in resistance. Therefore, the oxygen concentration in the treatment atmosphere in the activation step is 1 ppm or less, preferably 0.
It is desirable to set it to 1 ppm or less.

Next, as shown in FIG. 29A, a first interlayer insulating film 237 is formed. As the first interlayer insulating film 237, an insulating film containing silicon may be used as a single layer, or a laminated film combined therewith may be used. The film thickness may be 400 nm to 1.5 μm. In this embodiment, 200
A silicon oxide film having a thickness of 800 nm is stacked on a silicon nitride oxide film having a thickness of nm.

Further, a hydrogenation treatment is performed by performing a heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen. This step is a step in which the dangling bonds of the semiconductor film are terminated with hydrogen by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Note that the hydrogenation treatment may be performed while the first interlayer insulating film 237 is formed. That is, 200
After forming a silicon nitride oxide film having a thickness of nm, hydrogenation is performed as described above, and then the remaining 8
A silicon oxide film having a thickness of 00 nm may be formed.

Next, contact holes are formed in the gate insulating film 211 and the first interlayer insulating film 237, and source wirings 238 to 242 and drain wirings 243 to 247 are formed. In this embodiment, this electrode is made of a Ti film of 100 nm, an aluminum film containing Ti of 300 nm, T
A laminated film having a three-layer structure in which an i film of 150 nm is continuously formed by sputtering is used. Of course, other conductive films may be used.

Next, a first passivation film 248 is formed with a thickness of 50 to 500 nm (typically 200 to 300 nm). In this embodiment, the first passivation film 248 is 300 nm.
A thick silicon nitride oxide film is used. This may be replaced by a silicon nitride film. Note that it is effective to perform plasma treatment using a gas containing hydrogen such as H ₂ or NH ₃ prior to formation of the silicon nitride oxide film. Hydrogen excited by this pretreatment is supplied to the first interlayer insulating film 237 and heat treatment is performed, whereby the film quality of the first passivation film 248 is improved. At the same time, hydrogen added to the first interlayer insulating film 237 diffuses to the lower layer side, so that the active layer can be effectively hydrogenated.

Next, as shown in FIG. 29B, a second interlayer insulating film 249 made of an organic resin is formed.
As the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used. In particular, since the second interlayer insulating film 249 has a strong meaning of planarization,
Acrylic having excellent flatness is preferred. In this embodiment, the acrylic film is formed with a film thickness that can sufficiently flatten the step formed by the TFT. The thickness is preferably 1 to 5 μm (more preferably 2 to 4 μm).

Next, the drain wiring 245 is formed on the second interlayer insulating film 249 and the first passivation film 248.
Is formed, and a cathode electrode 250 of the photodiode is formed so as to be in contact with the drain wiring 245. In this embodiment, an aluminum film formed by sputtering is used as the cathode electrode 250, but other metals such as titanium, tantalum, tungsten, and copper can be used.
Alternatively, a laminated film made of titanium, aluminum, or titanium may be used.

Next, an amorphous silicon film containing hydrogen is formed over the entire surface of the substrate and then patterned to form a photoelectric conversion layer 251. Next, a transparent conductive film is formed on the entire surface of the substrate. In this embodiment, ITO having a thickness of 200 nm is formed as a transparent conductive film by a sputtering method. The transparent conductive film is patterned to form the anode electrode 252. (FIG. 29C)

Next, as shown in FIG. 30A, a third interlayer insulating film 253 is formed. Third interlayer insulating film 2
By using a resin such as polyimide, polyamide, polyimide amide, or acrylic as 53, a flat surface can be obtained. In this example, a polyimide film having a thickness of 0.7 μm was formed on the entire surface of the substrate as the third interlayer insulating film 253.

Next, a contact hole reaching the anode electrode 252 is formed in the third interlayer insulating film 253, and a sensor wiring 254 is formed. In this embodiment, an aluminum alloy film (an aluminum film containing 1 wt% titanium) is formed to a thickness of 300 nm.

  In this way, a sensor substrate having a structure as shown in FIG. 30B is completed.

270 is an amplifying TFT, 271 is a switching TFT, 272 is a resetting TFT, 27
3 is a bias TFT, and 274 is a discharge TFT.

In this embodiment, the amplification TFT 270 and the bias TFT 273 are n-channel TFTs.
LDD regions 281-2 on both the source region side and the drain region side, respectively.
84. The LDD regions 281 to 284 do not overlap with the gate electrodes 212 and 215 with the gate insulating film 211 interposed therebetween. With the above configuration, the amplification TFT 270 and the bias TFT 273 can reduce hot carrier injection as much as possible.

In this embodiment, the switching TFT 271 and the discharging TFT 274 are n-channel T
The FT has LDD regions 283 and 286 only on the drain region side. The LDD regions 283 and 286 overlap with the gate electrodes 213 and 216 with the gate insulating film 211 interposed therebetween.

The reason why the LDD regions 283 and 286 are formed only on the drain region side is to reduce hot carrier injection and not to reduce the operation speed. Further, the switch 271 and the discharge TFT 274 do not need to worry about the off-current value so much, and it is better to focus on the operation speed than that. Therefore, the LDD regions 283 and 286 are completely formed in the gate electrode 2.
13 and 216, and it is desirable to reduce the resistance component as much as possible. That is, it is better to eliminate the so-called offset.
In particular, when the source signal line drive circuit or the gate signal line drive circuit is driven at 15 V to 20 V, the above-described configuration of the discharge TFT 274 of this embodiment is effective for reducing hot carrier injection and not reducing the operation speed. It is.

In this embodiment, the reset TFT 272 is a p-channel TFT and does not have an LDD region. In the p-channel TFT, since deterioration due to hot carrier injection is hardly noticed, it is not particularly necessary to provide an LDD region. Of course, like n-channel TFT, LD
It is also possible to provide a D region and take measures against hot carriers. Reset TFT
272 may be an n-channel TFT.

Further, a connector (flexible printed circuit: FPC) for connecting a terminal routed from an element or circuit formed on the substrate and an external signal terminal is attached to complete the product.

Note that in this embodiment, a sensor is manufactured using a TFT or a photodiode on glass, but a sensor can be manufactured using a transistor on a single crystal silicon substrate.

A sensor formed by implementing the present invention can be used in various electronic devices. Examples of such an electronic device of the present invention include a scanner, a digital still camera, an X-ray camera, a portable information terminal (mobile computer, mobile phone, portable game machine), a notebook personal computer, a game device, a video phone, and the like. Can be mentioned.

FIG. 31A shows a scanner, which includes a reading area 3102, a sensor portion 3101, a reading start switch 3103, and the like. The present invention can be used for the sensor portion 3101.

FIG. 31B shows a digital still camera, which includes a finder 3105, a sensor portion 3104, a shutter button 3106, and the like. The present invention can be used for the sensor portion 3104.

FIG. 32 shows an X-ray camera, which includes an X-ray generator 3201, a sensor unit 3203, and a signal processing computer 32.
Including 04. A person 3202 enters between the X-ray generator 3201 and the sensor unit 3203 and takes an X-ray photograph. The present invention can be used for the sensor portion 3203.

FIG. 33 shows a personal computer, which includes a main body 3301, a housing 3302, a display device 3303, a keyboard 3304, a sensor portion 3305, and the like. The present invention can be used for the sensor portion 3305.

FIG. 34 shows a mobile phone, which includes a main body 3401, an audio output unit 3402, an audio input unit 3403, a display device 3404, an operation switch 3405, an antenna 3406, and a sensor unit 3407. The present invention can be used for the sensor portion 3407.

  In addition, Example 1- Example 3 can be freely combined with each Example.

101 Switch transistor
102 Gate signal line
103 Signal output line
104 photodiode
105 Reset signal line
106 Amplifying transistor
107 Reset transistor
108 Amplified power line
109 Reset power line
110 Diode side power supply line

Claims (6)

A semiconductor device having a photoelectric conversion element and first and second transistors,
One of a source and a drain of the first transistor is electrically connected to the first wiring;
The other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor;
The photoelectric conversion element is electrically connected to the gate of the second transistor via a switch,
A second wiring electrically connected to the gate of the first transistor;
The second wiring has a region arranged in parallel with the first wiring,
The amplitude value of the voltage of the first signal supplied to the first wiring is smaller than the amplitude value of the voltage of the second signal supplied to the second wiring,
The number of potentials of the first signal is two;
The second transistor has a function of outputting a signal from one of a source and a drain of the second transistor to a third wiring,
The semiconductor device has a function of changing the second signal before the first signal is changed so that the first transistor can be turned off. In claim 1,
The other of the source and the drain of the second transistor is electrically connected to the first wiring. In claim 1 or 2,
Having a third transistor;
The semiconductor device is characterized in that the third transistor is electrically connected in series with the second transistor. In claim 3,
The other of the source and the drain of the second transistor is electrically connected to the first wiring through the third transistor. In any one of Claims 1 thru | or 4,
The photoelectric conversion element includes a photodiode, a Schottky diode, an avalanche diode, or a photoconductor. An electronic apparatus comprising the semiconductor device according to claim 1 and an operation switch, a shutter, or an antenna.

Images