JPH11205693A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device with which a cut-off frequency can be increased without restricting an input voltage range to ensure linear operation. SOLUTION: This image pickup device is provided with plural photoelectric transducers 1, a charge transfer part 2 for transferring signals converted by the respective photoelectric transducers 1, a floating diffusing layer 3 for detecting the output of the charge transfer part 2 as a voltage, and an impedance converting part 4 connected to the floating diffusing layer 3 so as to perform impedance conversion. The impedance coverting part 4 is composed of series-connected two source follower circuits 41 and 42, which have driver transistors QD1 and QD2 and load transistors QL1 and QL2. Since a threshold voltage VTHL1 of the load transistor QL1 on a first stage is made lower than that of the load transistor QL2 on the following stage, a cut-off frequency can be increased, without restricting an input voltage range to ensure linear operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device having a plurality of photoelectric conversion units and a transfer unit for transferring signal charges photoelectrically converted by each photoelectric conversion unit, and more particularly to an output stage of the solid-state imaging device. Circuit configuration.

[0002]

2. Description of the Related Art FIG. 6 is a diagram showing a schematic configuration of a conventional solid-state imaging device. The solid-state imaging device in FIG. 6 includes a plurality of photoelectric conversion units 1 provided corresponding to respective pixels, and a charge transfer unit 2 that sequentially transfers signal charges photoelectrically converted by each photoelectric conversion unit 1.
A floating diffusion layer 3 (or a floating electrode) for outputting a voltage corresponding to the signal charge output from the charge transfer unit 2; and an impedance conversion unit 4 connected to the floating diffusion layer 3.

The floating diffusion layer 3 includes a MOS transistor Q1 for resetting the floating diffusion layer to a constant bias,
The capacitor CJ for storing the signal charge transferred from the charge transfer unit 2 is connected, and the voltage of the floating diffusion layer 3 changes according to the charge stored in the capacitor CJ when the MOS transistor Q1 is off.

[0004] The impedance converter 4 is composed of two cascade-connected source follower circuits 41 and 42. The source follower circuit 41 has a driver transistor QD1 and a load transistor QL1 connected in series. Similarly, the source follower circuit 42 has a driver transistor QD2 and a load transistor QL2 connected in series. Each of these transistors is constituted by an n-type MOS transistor. Driver transistor Q
The power supply voltage VD is applied to one ends of D1 and QD2, and one ends of the load transistors QL1 and QL2 are grounded.

Both driver transistors QD1 and QD2 are surface channel transistors that do not perform ion implantation in the channel region.
1, the threshold voltages VTHD1 and VTHD2 of QD2 are 0V.

On the other hand, each of the load transistors QL1 and QL2 is a depletion type transistor in which phosphorus ions are implanted for adjusting the threshold voltage, and the threshold voltages VTHL1 and VTHL2 of the load transistors QL1 and QL2 are ( -2) Set to V.

A typical first stage driver transistor QD1
Dimension ratio (W / L) D1 of channel width W and channel length L
Is about 6 μm / 2 μm, the dimensional ratio (W / L) L1 of the load transistor QL1 is about 20 μm / 15 μm, and the dimensional ratio (W / L) D2 of the subsequent driver transistor QD2 is about 150 μm / 2μ
m, the dimensional ratio (W / L) L2 of the load transistor QL2 is approximately
40 μm / 2 μm. The gate oxide films of the driver transistors QD1 and QD2 and the load transistors QL1 and QL2 are set to about 500 Å, and the power supply voltage VD is set to about 15V.

In FIG. 6, MOS transistors Q1, Q
The parasitic capacitance between the gate and drain of D1 and QD2 is C
1 to C3, the total ground capacitance C of the floating diffusion layer 3 is C
= CJ + C1 + C2, and the charge-to-voltage conversion ratio is 1 /
(CJ + C1 + C2).

[0009]

In order to reduce the influence of the noise generated by the two-stage source follower circuits 41 and 42 on the output signal as shown in FIG. It is desirable to reduce the parasitic capacitance C1, for example. For this reason, conventionally, as described above, the gate width W of the first-stage driver transistor QD1 has been designed to be as small as about 6 μm.

It is not desirable that the gate length L of the driver transistor QD1 in the first stage is shorter than about 2 μm in order to prevent deterioration of characteristics and reliability due to the short channel effect. For this reason, as described later, it is difficult to increase the cutoff frequency of the first-stage source follower circuit 41, and the solid-state imaging device in FIG. 6 cannot obtain a good output waveform when driven at high speed. There was a problem.

Here, a measure for increasing the cutoff (cutoff) frequency will be discussed.

To increase the cutoff frequency, one of the dimensional ratios (W / L) D1 and (W / L) L1 of the driver transistor QD1 and the load transistor QL1 in the first stage may be increased. However, the first-stage driver transistor Q
As described above, the dimensional ratio (W / L) D1 of D1 cannot be increased due to the restriction of the charge-voltage conversion ratio.

To increase the dimensional ratio (W / L) L1 of the first-stage load transistor QL1, the load transistor Q
Although it is conceivable to shorten the gate length L of L1, it is known that flicker noise (1 / f noise) increases in inverse proportion to the area of the load transistor QL1. In addition, when the gate width W is increased, a side effect that the parasitic capacitance C4 increases due to an increase in the area of the drain diffusion layer and the coupling capacitance between the drain and the gate occurs, and as a result, the cutoff frequency does not increase.

On the other hand, by changing the amount of impurity (phosphorus) ions implanted into the load transistors QL1 and QL2 to adjust the threshold voltages of the load transistors QL1 and QL2,
It is also conceivable to increase the cutoff frequency.

For example, FIG. 7 shows that more phosphorus ions are implanted into the load transistors QL1 and QL2 in the cascade-connected two-stage source follower circuits 41 and 42, and the threshold voltages VTHL1 and VTHL2 are increased. (-4) is a circuit diagram illustrating an example in which the voltage is reduced to V. FIG. When the threshold voltages VTHL1 and VTHL2 are reduced, the cutoff frequency can be increased. On the other hand, the output voltage level of the source follower circuit 42 at the subsequent stage decreases, and the input voltage range in which linear operation can be performed is reduced. It becomes narrow.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to reduce the input voltage range in which linear operation can be performed without complicating circuits and manufacturing processes. An object of the present invention is to provide a solid-state imaging device capable of increasing a cutoff (cut-off) frequency.

[0017]

In order to solve the above-mentioned problems, the invention according to claim 1 comprises a plurality of photoelectric conversion units, a transfer unit for transferring signal charges photoelectrically converted by these photoelectric conversion units, and A voltage output unit that outputs a voltage corresponding to the signal charge output from the transfer unit; and an impedance conversion unit that converts the output impedance of the voltage output unit. The impedance conversion unit includes a series-connected drive transistor. And a solid-state imaging device configured to cascade two or more source follower circuits each including a load transistor and supplying an output voltage of the voltage output unit to a gate terminal of the drive transistor in the first-stage source follower circuit. One end of the load transistor in each source follower circuit is set to a reference voltage, and each of the source follower circuits Of the drive to one end of the transistor predetermined voltage is applied, the absolute value of the threshold voltage of the load transistor in the source follower circuit of the first stage,
The threshold voltages of all the load transistors in the source follower circuits other than the first stage are larger than the absolute values of the threshold voltages.

According to a third aspect of the present invention, a plurality of photoelectric conversion units are provided.
A transfer unit that transfers the signal charges photoelectrically converted by these photoelectric conversion units, a voltage output unit that outputs a voltage corresponding to the signal charges output from the transfer unit, and an impedance that converts the output impedance of the voltage output unit A conversion unit, wherein the impedance conversion unit is configured by cascading two or more source follower circuits each including a drive transistor and a load transistor connected in series, and a gate of the drive transistor in the first-stage source follower circuit. In a solid-state imaging device that supplies an output voltage of the voltage output unit to a terminal, one end of each of the load transistors in each of the source follower circuits is set to a reference voltage, and one end of the drive transistor in each of the source follower circuits. A predetermined voltage is applied, and the load in the first stage source follower circuit is The absolute value of the gate voltage of the transistor, is made larger than the absolute values of all of the gate voltage of the load transistor in the source follower circuit other than the first stage.

According to a fifth aspect of the present invention, a plurality of photoelectric conversion units are provided.
A transfer unit that transfers the signal charges photoelectrically converted by these photoelectric conversion units, a voltage output unit that outputs a voltage corresponding to the signal charges output from the transfer unit, and an impedance that converts the output impedance of the voltage output unit A conversion unit, wherein the impedance conversion unit is configured by cascading two or more source follower circuits each including a drive transistor and a load transistor connected in series, and a gate of the drive transistor in the first-stage source follower circuit. In a solid-state imaging device that supplies an output voltage of the voltage output unit to a terminal, one end of each of the load transistors in each of the source follower circuits is set to a reference voltage, and one end of the drive transistor in each of the source follower circuits. Is a predetermined voltage, and all the transistors in each of the source follower circuits are Is comprised of one of an n-type MOS transistor and a p-type MOS transistor, and when all the transistors in each of the source follower circuits are comprised of n-type MOS transistors, the The threshold voltages of the driving transistors are made higher than the threshold voltages of all the driving transistors in the source follower circuits except the first stage, and all the transistors in each of the source follower circuits are p-type MOS transistors.
When configured with transistors, the threshold voltage of the drive transistor in the source follower circuit of the first stage is smaller than the threshold voltage of all the drive transistors in the source follower circuit other than the first stage. Things.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A solid-state imaging device according to the present invention will be specifically described below with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of a solid-state imaging device according to the present invention. In FIG. 1, the same components as those in FIG. 6 are denoted by the same reference numerals.

The solid-state image pickup device shown in FIG. 1 has substantially the same configuration as the conventional device shown in FIG. 6, and includes a plurality of photoelectric conversion units 1 provided corresponding to respective pixels, and the photoelectric conversion units 1 Transfer section 2 for transferring the converted signal charges, a floating diffusion layer 3 (or a floating electrode) for detecting the signal charges output from the charge transfer section 2 as a voltage, and an impedance connected to the floating diffusion layer 3 and performing impedance conversion. And a conversion unit 4. The impedance conversion unit 4 includes two cascade-connected source follower circuits 41 and 42, as in FIG. The source follower circuit 41 has a driver transistor QD1 and a load transistor QL1 connected in series, and the source follower circuit 42 has a driver transistor QL2 and a load transistor QL2 connected in series. Each of these transistors is constituted by an n-type MOS transistor, and driver transistors QD1, QD2
The power supply voltage VD is applied to one end of the load transistor, and one ends of the load transistors QL1 and QL2 are grounded.

This embodiment is characterized in that the threshold voltage VTHL1 of the load transistor QL1 in the first stage source follower circuit 41 is lower than that of the conventional circuit shown in FIG. That is, in the present embodiment, the threshold voltage VTH of the load transistor QL1 in the source follower circuit 41 of the first stage is
L1 is about (-4) V, and the threshold voltage VTHL2 of the load transistor QL2 in the source follower circuit 42 at the subsequent stage is (-2).
V is set.

The adjustment of the threshold voltage is performed by adjusting the amount of impurity (phosphorus) ions implanted into the channel regions of the load transistors QL1 and QL2.
More specifically, more phosphorus ions are implanted into the first-stage load transistor QL1 than the latter-stage load transistor QL2, and the threshold voltages VTHL1 and VTHL2 of each of the load transistors QL1 and QL2 are set to the above-described values. .

Next, the cutoff frequency of the solid-state imaging device of FIG. 1 will be described.

As is well known, a single n-type MOS
The VI characteristic of the transistor is in the saturation region (VDS ≧ VGS−V
TH, where VDS is the drain-source voltage, and VGS is the gate-source voltage.) IDS = kn · (W / L) · (VGS−VTH) ² (1) where kn = μεox / (2tox), where tox is the thickness of the gate oxide, μ is the mobility, and εox is the relative dielectric constant of the oxide film. Rate.

Using the equation (1), the output Vout1 of the first-stage source follower circuit 41 shown in FIG. 1 is given by the equation (2). Here, (W / L) L1 is the dimensional ratio of the gate width W to the gate length L of the load transistor QL1, and (W / L) D1 is the dimensional ratio of the driver transistor QD1.

[0027]

(Equation 1) The cutoff frequency f of the first-stage source follower circuit 41 is given by equation (3). Here, C3 is the parasitic capacitance of QD2, and C4 is the input capacitance of QD2.

[0028]

(Equation 2) Next, the range of the input voltage in which the source follower circuit 42 in the subsequent stage shown in FIG.

The output Vout2 of the conventional source follower circuit 42 shown in FIG. 6 is given by equation (4). However,
(W / L) L2 is the dimensional ratio of the load transistor L2, (W / L)
L) D2 is a dimensional ratio of the driver transistor D2.

[0030]

(Equation 3) From the saturation condition of the first stage driver transistor QD1,
Equation (5) holds. Here, VIN is the output of the charge transfer unit 2, and VD is the power supply voltage. VIN <VD (5) Also, from the saturation condition of the load transistor QL2 in the subsequent stage,
Equation (6) holds. Vout2 <VTHL2 (6) From the expressions (4) to (6), the range of the input voltage capable of performing the linear operation is given by the expression (7).

[0031]

(Equation 4) In the conventional solid-state imaging device shown in FIG. 6, the threshold voltages VTHL1 and VTHL2 of the load transistors QL1 and QL2 at the first and second stages are set.
Are set to (−2) V, but in this embodiment,
The threshold voltage VTHL1 of the first-stage load transistor QL1 is set to (-4) V, and the threshold voltage VTHL2 of the second-stage load transistor QL2 is set to (-2) V. This allows
As can be seen from the equation (4), the cutoff frequency of the solid-state imaging device according to the present embodiment is twice the conventional one.

At this time, as can be seen from equation (7), the input voltage range in which the source follower circuits 41 and 42 can operate linearly decreases slightly, but the threshold voltage VTHL2 of the load transistor QL2 at the subsequent stage is reduced. Has the same voltage value as in the prior art, so that the amount of decrease in the input voltage range in which the linear operation can be performed can be kept within a practically acceptable range.

That is, according to the first embodiment, the input voltage range in which the linear operation can be performed is hardly narrowed.
The cutoff (cutoff) frequency of the output stage of the solid-state imaging device can be increased. In the first embodiment, since the gate terminals of the load transistors QL1 and QL2 in the two-stage source follower circuits 41 and 42 are both connected to the source terminals, the gate voltages of the load transistors QL1 and QL2 are generated. No circuit is required, and the configuration of the solid-state imaging device can be simplified.

Each MOS transistor QD shown in FIG.
The threshold voltages of 1, QD2, QL1, and QL2 are not limited to the illustrated values. That is, the first-stage load transistor Q
The threshold voltage VTHL1 of L1 is equal to the load transistor QL2 in the subsequent stage.
It is only necessary that the threshold voltage is lower than the threshold voltage VTHL2 of (1), and each threshold voltage is not limited to (−4) V and (−2) V. Also,
The threshold voltages VTHD1, VTH of the driving transistors QD1, QD2
THD2 may be a voltage other than 0V.

[Second Embodiment] In the first embodiment,
Although the gate terminal of the first-stage load transistor QL1 is grounded, the same effect as in the first embodiment can be obtained by applying a predetermined voltage to the gate terminal.

FIG. 2 is a circuit diagram of an output stage of the solid-state imaging device according to the second embodiment. The circuit of FIG. 2 sets the threshold voltages of the four n-type MOS transistors QD1, QD2, QL1, and QL2 in the two-stage source follower circuits 41 and 42 to 0 V, and sets the load transistors in the first stage. QL1
The first embodiment shown in FIG. 1 differs from the first embodiment shown in FIG. 1 in that 4 V is applied to the gate terminal of the load transistor QL2 and 2 V is applied to the gate terminal of the subsequent load transistor QL2.

In each of the circuits of FIGS. 1 and 2, (VGS-VTH) in the equation (1) has the same value.
The VI characteristics are the same as in the first embodiment. Also, (3)
Since (-VTHL1) in the equation also has the same value as in the first embodiment, the same cutoff frequency as in the first embodiment can be obtained in the second embodiment.

In the second embodiment, since the threshold voltages of all the transistors in the two-stage source follower circuits 41 and 42 are set to 0 V, the step of implanting phosphorus ions into the channel region becomes unnecessary. The manufacturing process can be simplified.

In the second embodiment, a circuit for generating a voltage of 4 V or 2 V is newly required. This circuit includes a photoelectric conversion unit 1, a charge transfer unit 2, a floating diffusion layer shown in FIG. 3 and the impedance converter 4 may be integrated on the same substrate, or may be supplied from an external circuit.

Each source follower circuit 4 shown in FIG.
The voltages applied to the gate terminals of the load transistors QL1 and QL2 in the first and second transistors 42 are not limited to the illustrated voltage values. However, in order to increase the cutoff frequency, it is necessary to make the gate voltage of the preceding load transistor QL1 higher than the gate voltage of the following load transistor QL2. further,
Each threshold voltage in each of the source follower circuits 41 and 42 may be a voltage value other than 0V.

[Third Embodiment] As in the conventional circuit (FIG. 7), the load transistors QL1 and QL2
Threshold voltages VTHL1 and VTHL2 from (-2) V to (-
4) When the voltage is lowered to V, the cutoff frequency increases, but as can be seen from the equation (7), the input voltage range in which the linear operation can be performed is narrowed. This is because the output voltage level of the source follower circuit 42 at the subsequent stage decreases. Therefore, in a third embodiment described below,
It is characterized in that the output voltage level of the source follower circuit 42 at the subsequent stage is not reduced.

FIG. 3 is a circuit diagram of an output stage of the solid-state imaging device according to the third embodiment. The circuit shown in FIG. 3 includes load transistors Q in source follower circuits 41 and 42 having a two-stage configuration.
The threshold voltages of L1 and QL2 are set to (-4) V, the threshold voltage of the first driver transistor QD1 is set to 0 V, and the threshold voltage of the second driver transistor QD2 is set to (-2) V. ing.

As described above, by setting the threshold voltage of the driver transistor QD2 at the subsequent stage lower than 0 V, the output voltage level of the source follower circuit 42 at the subsequent stage becomes higher than the conventional one, and the input voltage at which the linear operation can be performed. The range expands. In the third embodiment, the load transistor QL
1, the threshold voltage of QL2 is lower than (-2) V (-
4) Since it is set to V, the cutoff frequency can be made higher than before. Further, according to the third embodiment, similarly to the first embodiment, the load transistors QL1,
A circuit for generating the gate voltage of QL2 becomes unnecessary, and the configuration of the solid-state imaging device can be simplified.

Each source follower circuit 4 shown in FIG.
The threshold voltage of each transistor in the transistors 1 and 42 is not limited to the illustrated voltage value. That is, the threshold voltage VTHD2 of the driver transistor QD2 in the subsequent stage only needs to be lower than the threshold voltage VTHD1 of the driver transistor QD1 in the preceding stage, and each threshold voltage may be a voltage value other than that shown. .

In each of the embodiments described above, the example in which the source follower circuits 41 and 42 are cascaded in two stages has been described. However, three or more source follower circuits may be cascaded. If three or more source follower circuits are connected in cascade, the first
In the embodiment, the first-stage source follower circuit 41
In this case, the threshold voltage of the load transistor QL1 may be lower than the threshold voltages of the load transistors QL2 and the like in all the source follower circuits other than the first stage. In the second embodiment, if the gate voltage of the load transistor QL1 in the first-stage source follower circuit 41 is set higher than the gate voltage of the load transistors QL2 and the like in all other source-follower circuits except the first-stage. Good.
In the third embodiment, the threshold voltage of the driving transistor QD1 in the source follower circuit 41 of the first stage is set higher than the threshold voltage of the driving transistor QD2 in all the source follower circuits other than the first stage. Should also be increased.

In each of the above embodiments, the n-type MOS
Although the example in which the source follower circuits 41 and 42 are configured by transistors has been described, the source follower circuits 41 and 42 may be configured by p-type MOS transistors. For example, FIGS. 4 and 5 are circuit diagrams each showing an example in which the first and third embodiments are constituted by p-type MOS transistors. As shown in these figures, in the case of a p-type MOS transistor, the configuration is the same as that of an n-type MOS transistor except that the polarities of the power supply voltage, threshold voltage and gate voltage are reversed. .

[0047]

As described above in detail, according to the present invention, for example, the threshold voltage of the load transistor in the first-stage source follower circuit is changed to the threshold voltage of all the load transistors in the source-follower circuits other than the first stage. Since the threshold voltage is lower than the threshold voltage, the cutoff frequency of the output stage of the solid-state imaging device can be made higher than before without narrowing the range of the input voltage at which the linear operation can be performed. Performance is improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is a circuit diagram of an output stage of a solid-state imaging device according to a second embodiment.

FIG. 3 is a circuit diagram of an output stage of a solid-state imaging device according to a third embodiment.

FIG. 4 is a circuit diagram in which the first embodiment is configured by p-type MOS transistors.

FIG. 5 is a circuit diagram in which the third embodiment is configured by p-type MOS transistors.

FIG. 6 is a diagram showing a schematic configuration of a conventional solid-state imaging device.

FIG. 7 is a circuit diagram showing an example in which the threshold voltage of a load transistor is lowered.

[Explanation of symbols]

 Reference Signs List 1 photoelectric conversion unit 2 charge transfer unit 3 floating diffusion layer 4 impedance conversion unit 41, 42 source follower circuit

Claims (6)

[Claims] A plurality of photoelectric conversion units; a transfer unit configured to transfer signal charges photoelectrically converted by the photoelectric conversion units; and a voltage output unit configured to output a voltage corresponding to the signal charges output from the transfer units. An impedance conversion unit that converts the output impedance of the voltage output unit. The impedance conversion unit is configured by cascade-connecting two or more source follower circuits each including a drive transistor and a load transistor connected in series. In the solid-state imaging device for supplying an output voltage of the voltage output unit to a gate terminal of the drive transistor in the source follower circuit, one end of each of the load transistors in each of the source follower circuits is set to a reference voltage, A predetermined voltage is applied to one end of the driving transistor in each source follower circuit, The absolute value of the threshold voltage of the load transistor in the source follower circuit is made larger than the absolute values of the threshold voltages of all the load transistors in the source follower circuit except the first stage. Solid-state imaging device. 2. The threshold voltage of all of the driving transistors in each of the source follower circuits is set to 0V, and the absolute value of the threshold voltage of the load transistor in the first stage of the source follower circuit is the first. The absolute values of the threshold voltages of all the load transistors in the source follower circuits other than the first stage are set to a second voltage smaller than the first voltage, 2. The solid-state imaging device according to claim 1, wherein a gate terminal and a source terminal of each of the load transistors in the circuit are set to the reference voltage. 3. A plurality of photoelectric conversion units, a transfer unit for transferring signal charges photoelectrically converted by the photoelectric conversion units, and a voltage output unit for outputting a voltage corresponding to the signal charges output from the transfer units. An impedance conversion unit that converts the output impedance of the voltage output unit. The impedance conversion unit is configured by cascade-connecting two or more source follower circuits each including a drive transistor and a load transistor connected in series. In the solid-state imaging device for supplying an output voltage of the voltage output unit to a gate terminal of the drive transistor in the source follower circuit, one end of each of the load transistors in each of the source follower circuits is set to a reference voltage, A predetermined voltage is applied to one end of the driving transistor in each source follower circuit, A solid-state imaging device, wherein the absolute value of the gate voltage of the load transistor in the source follower circuit is larger than the absolute values of the gate voltages of all the load transistors in the source follower circuit other than the first stage. 4. The threshold voltage of all the driving transistors and the load transistors in each of the source follower circuits is set to 0 V. The absolute value of the gate voltage of the load transistors in the first stage source follower circuit is: The absolute value of the gate voltage of all the load transistors in the source follower circuit other than the first stage is set to a first voltage, and the absolute value of the gate voltage is set to a second voltage lower than the first voltage. The solid-state imaging device according to claim 3. 5. A plurality of photoelectric conversion units, a transfer unit for transferring signal charges photoelectrically converted by the photoelectric conversion units, and a voltage output unit for outputting a voltage corresponding to the signal charges output from the transfer units. An impedance conversion unit that converts the output impedance of the voltage output unit. The impedance conversion unit is configured by cascade-connecting two or more source follower circuits each including a drive transistor and a load transistor connected in series. In the solid-state imaging device for supplying an output voltage of the voltage output unit to a gate terminal of the drive transistor in the source follower circuit, one end of each of the load transistors in each of the source follower circuits is set to a reference voltage, A predetermined voltage is applied to one end of the driving transistor in each source follower circuit. All transistors in the source follower circuit are n-type
MOS transistors and p-type MOS transistors, and all transistors in each of the source follower circuits are n-type MOS transistors.
When constituted by S transistors, the threshold voltage of the drive transistor in the source follower circuit of the first stage is set higher than the threshold voltages of all the drive transistors in the source follower circuit other than the first stage. And all the transistors in each of the source follower circuits are p-type MO
When configured with S transistors, the threshold voltage of the drive transistor in the source follower circuit of the first stage is smaller than the threshold voltage of all the drive transistors in the source follower circuit other than the first stage. A solid-state imaging device characterized by the following. 6. The threshold voltage of the driving transistor in the source follower circuit of the first stage is set to 0 V, and the gate terminal and the source terminal of all the load transistors in each source follower circuit are set to the reference voltage. All transistors in each source follower circuit are n-type MO
When configured with S transistors, the threshold voltages of the drive transistors in the source follower circuits other than the first stage are set to a first voltage lower than 0 V, and all transistors in each of the source follower circuits are p-type MO
6. The transistor according to claim 5, wherein, when configured with an S transistor, a threshold voltage of the driving transistor in the source follower circuit other than the first stage is set to a second voltage higher than 0V. 7. Solid-state imaging device.