JP3253179B2 - Photoelectric conversion device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image input device for a digital (color) copying machine, and a desktop publishing (D).
The present invention relates to a photoelectric conversion device used for an image data input device such as TP), a document reading device such as a facsimile, and an imaging device such as a VDT.

[0002]

2. Description of the Related Art Conventionally, a photoelectric conversion device using, for example, a depletion type N-channel MOS field effect transistor (MOS • FET) as an amplifying element is known. This type of photoelectric conversion device is generally configured such that a plurality of photoelectric conversion elements are arranged in an array or a matrix, and output electric signals in accordance with the amount of incident light in time series.
FIG. 31 is a configuration diagram of such a conventional photoelectric conversion device. In this photoelectric conversion device, a plurality of photoelectric conversion elements (for example, n photoelectric conversion elements) are arranged in an array or a matrix as described above, and a photoelectric conversion cell corresponding to the number n of photoelectric conversion elements is provided. (N) are provided, but since the n photoelectric conversion cells have the same configuration, only one photoelectric conversion cell (that is, one bit) is shown in FIG. 31 for simplicity. Have been.

Referring to FIG. 31, one photoelectric conversion cell of this photoelectric conversion device includes a photoelectric conversion element PD of a photodiode and a depletion-type N-channel MOSFET.
Of the amplifying element Q and the gate potential of the amplifying element Q
A first initializing means (specifically, a switching element) S1 for initializing the source element and a source potential of the amplifying element Q are set to a potential VR.
Second initializing means (specifically, a switch element) S2 for initializing to 2, and reading means for outputting the source potential of the amplifying element Q to the common signal line CM as an output signal from the photoelectric conversion cell. (Specifically, a switch element) S3. Here, one terminal of the photoelectric conversion element PD is
The other terminal of the photoelectric conversion element PD is connected to the first initialization means S1 and the gate of the amplification element Q, and is maintained at the voltage Vcc applied to the drain of the amplification element Q. Also,
In FIG. 31, the output signal output to the common signal line CM is amplified by a final-stage amplifier AMP of the signal and finally output.

In the photoelectric conversion device having such a configuration, first, the first initializing means S1 and the second initializing means S2 are closed so that the gate potential of the amplifying element Q is reduced to the potential VR.
1 and the source potential of the amplification element Q is initialized to the potential VR2. When the first initialization means S1 and the second initialization means S2 are opened and the initialization is completed, the source of the amplifying element Q is turned off.
The potential drops to a potential higher than the gate potential by the gate-source voltage Vth of the amplifier element Q while charging the floating capacitance of the signal line. In this state, when a photocurrent according to the amount of incident light flows through the photoelectric conversion element PD, this photocurrent is generated by the parasitic capacitance of the first initialization means S1, the parasitic capacitance of the amplifier Q, and the parasitic capacitance of the photoelectric conversion element PD. Charge capacity. That is, the capacitor (storage capacitor) connected to the gate of the amplification element Q is charged. In this way, when the capacitance (storage capacitance) connected to the gate of the amplifier element Q is charged by the photocurrent, the gate potential of the amplifier element Q rises. A source current (drain current) corresponding to the rise of the gate potential flows through the amplifying element Q, which charges the stray capacitance of the source of the amplifying element Q and the parasitic capacitance of the second initialization means S2. Therefore, the source potential also rises by the rise of the gate potential. That is, the amplifying element Q functions as a source follower, and the source potential of the amplifying element Q changes following the gate potential. Since the gate potential changes depending on the magnitude of the photocurrent, the source potential reflects the magnitude of the photocurrent. Therefore, this source potential is used as a result of photoelectric conversion of one photoelectric conversion cell, that is, It can be read as an output signal.

[0005]

In this type of photoelectric conversion device, the factors that determine the sensitivity are the sensitivity of the photoelectric conversion element PD (the ratio of the photocurrent to the amount of incident light) and the capacitance (storage) connected to the gate of the amplification element Q. Capacity). In order to increase the overall sensitivity, it is necessary to increase the sensitivity of the photoelectric conversion element PD or reduce the storage capacity.
That is, usually, the quantum efficiency of the photoelectric conversion element PD is as high as 90% or more, and the photocurrent is substantially determined by the size of the photoelectric conversion element PD. It is necessary to reduce the storage capacity. However, in the photoelectric conversion device having the configuration of FIG. 31, most of the storage capacitance is the parasitic capacitance of the photoelectric conversion element PD, and if the sensitivity of the photoelectric conversion element PD is increased, the parasitic capacitance of the photoelectric conversion element PD increases. As a result, the storage capacity increases. As described above, in the conventional photoelectric conversion device, increasing the sensitivity of the photoelectric conversion element PD and reducing the storage capacitance are contradictory, and thus it is difficult to increase the overall sensitivity. Specifically, except for the CCD, in other conventional technologies, the parasitic capacitance of the photoelectric conversion element PD is large,
Since this works as a storage capacity, it is difficult to reduce the storage capacity. In addition, since the CCD has a large capacity for converting a charge into a voltage, a higher sensitivity cannot be obtained. Therefore, in the configuration of FIG. 31, the amplifier AMP is provided at the last stage of the signal.
However, since the signal from the amplifying element Q is transmitted by a small signal over a distance of several tens of millimeters, it is easily affected by external noise and transmission noise, and the noise of the amplifier AMP cannot be ignored. Therefore, there is a problem that it is difficult to obtain a high SN ratio when the sensitivity is improved by the amplifier AMP.

[0006] Further, since the amplification type photoelectric conversion device has a large number of elements in one photoelectric conversion cell, there is a limit to high integration by simply arranging the elements when integrating the elements on a semiconductor substrate. For example, application to a sensor using a reduction optical system has been difficult.

The present invention overcomes the above disadvantages of the prior art,
It is an object of the present invention to provide an amplifying photoelectric conversion device having high sensitivity and good SN ratio.

Another object of the present invention is to provide an amplifying photoelectric conversion device which can be highly integrated while utilizing the characteristics of high speed and high sensitivity.

[0009]

In order to achieve the above object, the present invention provides a photoelectric conversion device in which a photoelectric conversion device is a gate of an amplification device.
And a gate-source voltage of the amplifying element is applied to the photoelectric conversion element. As a result, the effect of the parasitic capacitance of the photoelectric conversion element on the capacitance (storage capacitance) connected to the gate of the amplification element can be extremely reduced, and the storage capacitance can be apparently reduced, resulting in high sensitivity and high SN. A ratio output signal can be obtained.

According to a second aspect of the present invention, the reading means has a function of reading out the source potential of the amplifying element as an output signal, and the reading means immediately after reading out the source potential as an output signal.
It also has a function of initializing a potential. This allows
It is not necessary to separately provide a means for initializing the source potential of the amplification element, and the size of the photoelectric conversion device can be reduced.

In the invention according to claims 5 and 13, the back gate of the amplifying element is electrically connected to the source of the amplifying element. Thereby, the substrate bias effect of the amplifying element can be eliminated, and the input / output characteristics of the photoelectric conversion device can be improved.

The invention according to claim 9 is a MOS-F
The back gate of the first initialization means formed as ET is electrically connected to the source of the amplification element. As a result, the capacitance between the source and the substrate or between the drain and the substrate of the first initialization means can be reduced apparently, and the capacitance connected to the gate of the amplifier can be further reduced. Thus, the photoelectric conversion device can have higher sensitivity.

[0013] Further, claim 3, claim 4, claim 6, claim 7, claim 8, claim 10, claim 11, and claim 1 are provided.
According to the inventions of claims 14 and 15, by devising the structure of the photoelectric conversion device, the characteristics of the photoelectric conversion device can be improved and high integration can be achieved.

According to a sixteenth aspect of the present invention, the amplifying means for amplifying an output signal from the common signal line to obtain a final output signal is provided for the output signal from the photoelectric conversion cell together with the impedance conversion. A sample hold is performed. As a result, the time during which the output signal is stable increases, and high-speed operation can be easily realized.

According to a seventeenth aspect of the present invention, the photoelectric conversion device according to the sixteenth aspect is regarded as one block, and a plurality of (m) blocks are connected in parallel. Each block operates with a clock having a predetermined period, and each block is selected with a phase shift of 1 / m from the predetermined period. Thereby, reading from a plurality of blocks can be performed at high speed.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a first embodiment of a photoelectric conversion device according to the present invention. Referring to FIG. 1, this photoelectric conversion device has a plurality of photoelectric conversion elements arranged in an array or a matrix, similar to the photoelectric conversion device shown in FIG. 31, and corresponds to the number n of photoelectric conversion elements. The n photoelectric conversion cells C1 to Cn are provided. The n photoelectric conversion cells have the same configuration, for example, n
The second photoelectric conversion cell Cn includes a photoelectric conversion element PDn of a photodiode and a depletion type N-channel MOS.
FET amplifying element Qn, first initializing means (specifically, switch element) Sn1 for initializing the gate potential of amplifying element Qn to potential VR1, and the source potential of amplifying element Qn to potential VR2. Initialization means (specifically, a switch element) Sn2 for performing the conversion, and reading means (specifically, for outputting the source potential of the amplification element Qn to the common signal line CM as an output signal from the photoelectric conversion cell. Is provided with a switch element) Sn3, but the photoelectric conversion element PDn
Is connected between the gate and source of the amplification element Qn. That is, the photoelectric conversion element PD
n is connected to the first initialization means Sn1 and the gate of the amplification element Qn, and the other terminal of the photoelectric conversion element PDn is connected to the second initialization means Sn2 and the reading means Sn3.
31 is connected to the source of the amplifying element Qn.
And different. The potential of the drain of the amplification element Qn is maintained at the voltage Vcc. The common signal line CM has a third initialization means (specifically, a switch element) S4 for initializing the potential of the common signal line CM to the potential VR3.
And an amplifier AMP for converting the potential of the common signal line CM into impedance, amplifying the potential by A times and outputting the amplified output signal as a final output signal Vout.

Next, the operation of the photoelectric conversion device shown in FIG. 1 will be described with reference to a time chart shown in FIG. It is assumed that the photoelectric conversion device of FIG. 1 operates in synchronization with a clock CLK (not shown in FIG. 1) having a predetermined period, and after the first photoelectric conversion cell C1 is initialized, In the same manner, the second photoelectric conversion cell C2 is initialized in the same clock cycle, so that the n-th photoelectric conversion cell Cn
Are sequentially initialized, and when initialization is performed for a certain photoelectric conversion cell, the photoelectric conversion processing for that photoelectric conversion cell is started.

For example, focusing on the first photoelectric conversion cell C1, first, S11 and S12 are turned on to set the gate potential of the amplifier element Q1 to the potential VR1 and the source potential to the potential VR2. The photoelectric conversion cell C1 is initialized. Next, when S12 is turned off, the source potential of the amplification element Q1 charges the parasitic capacitance of S12 and the floating capacitance of the source, and becomes (VR1 + Vth). That is, the potential drops to a potential higher by the gate-source voltage Vth than the gate potential. Thereafter, when S11 is turned off and a photocurrent corresponding to the amount of incident light flows through the photoelectric conversion element PD1, this photocurrent starts to be stored in a capacitor (storage capacitor) connected to the gate of the amplifier Q1.

As described above, the charge based on the photocurrent is accumulated in the capacitor (storage capacitor) connected to the gate of the amplifier element Q1, so that the gate potential of the amplifier element Q1 rises and the gate potential rises. At the same time, the source potential is also S12
While charging the parasitic capacitance of the source and the floating capacitance of the source, the gate potential rises by the rise amount. Thus, the amplification element Q1 is
It functions as a source follower in which the source voltage changes following the gate voltage, and the gate-source voltage of the amplifier element Q1 maintains a constant voltage Vth.

Here, in the configuration of FIG. 1, the photoelectric conversion element P
Since D1 is connected between the gate and the source of the amplifying element Q1, the voltage between the gate and the source of the amplifying element Q1 acting as a source follower, that is, a constant voltage is applied to the photoelectric conversion element PD1. Since Vth is added, the electric charge of the parasitic capacitance of the photoelectric conversion element PD1 is almost always constant and hardly fluctuates. Therefore, the photoelectric conversion element PD1
Of the photoelectric conversion element PD1 can be substantially subtracted from the storage capacitance, and the storage capacitance can be apparently reduced. For the same reason, the capacitance between the gate and the source of the amplifier element Q1 does not affect the storage capacitance. Accordingly, even when the size of the photoelectric conversion element PD1 is increased in order to increase the sensitivity and the parasitic capacitance of the photoelectric conversion element PD1 is increased, the storage capacitance can be apparently kept small, and therefore the sensitivity of the entire photoelectric conversion cell can be maintained. Can be significantly increased.

The photoelectric conversion cell C1 is initialized again after a lapse of a predetermined reading time (accumulation time). However, S13 is turned on in a half cycle of the clock CLK immediately before the initialization, and the source immediately before the initialization is turned on. The potential is output to the common signal line CM as an output signal, and is amplified by the amplifier AMP.
The photoelectric conversion result of the photoelectric conversion cell C1 is output as a final output signal Vout. Thereafter, S13 is turned off and S4 is turned on in a half cycle of the next clock CLK, and the potential of the common signal line CM is initialized to VR3.
At the same time, S11 and S12 are turned on to initialize the amplifying element Q1. The clock CLK is also applied to the second to n-th photoelectric conversion cells C2 to Cn.
The same processing is sequentially performed with a shift of a predetermined period in synchronization with.

As described above, in the photoelectric conversion device as shown in FIG. 1, the voltage applied to the photoelectric conversion elements PD1 to PDn is configured to be substantially constant in the photoelectric conversion cells C1 to Cn. The effect of parasitic capacitance on storage capacitance is very small (specifically,
As a result, the storage capacity can be set to an apparently small value (specifically, about several tens of fF) and high sensitivity (20 to 30 V / lx /
(approximately sec: about 10 times the current value). In addition, since high sensitivity enables signal transmission with a large voltage, the signal is hardly affected by external noise and noise of the amplifier AMP provided in the final stage (or output stage), and the output signal (6 -10 dB).

FIG. 3 is a configuration diagram of a second embodiment of the photoelectric conversion device according to the present invention. Referring to FIG. 3, in the photoelectric conversion device of the second embodiment, the second initialization means Sn2 is omitted in each photoelectric conversion cell as compared with the first embodiment, and the second initialization is performed. The function of the means Sn2 is changed to the first initializing means Sn1, the reading means Sn3, and the third initializing means S4.
This is realized by controlling the operation timing.

FIG. 4 is a time chart showing the operation of the photoelectric conversion device of FIG. In FIG. 4, for example, focusing on the first photoelectric conversion cell C1, S13 is turned on only for one period of the clock (CLK), as in S11. However, S13 is turned on by a half cycle earlier than S11. Therefore, the output signal of the photoelectric conversion cell C1 is read during the clock half cycle in which only S13 is on, and S4 is further added during the clock half cycle in which S11 and S13 are simultaneously turned on. By turning on, initialization of the potential of the common signal line CM and initialization of the source potential of the amplification element Q1 can be performed simultaneously.

As described above, even if the second initialization means Sn2 is not provided, the first photoelectric conversion can be performed by controlling the operation timing of the first initialization means Sn1, the reading means Sn3, and the third initialization means S4. The same photoelectric conversion processing as that of the device can be performed, and the size of the photoelectric conversion device can be further reduced.

The photoelectric conversion device shown in FIGS. 1 and 3 can be integrated on a semiconductor substrate such as silicon. In this case, a depletion-type N-channel MOSFET can be used as the amplification element Qn, and the first initialization means S11 and the readout means S11
The N-channel MOS-FET 13 can also be used as 13.

FIG. 5 shows the first initialization means S11 in one photoelectric conversion cell C1 of the photoelectric conversion device shown in FIG.
FIG. 4 is a diagram showing a configuration example in the case of using an N-channel MOS • FET for the read means S13.

The photoelectric conversion cell C1 as shown in FIG. 5 can be actually formed on a silicon substrate as shown in FIG. Referring to FIG. 6, a P-type silicon substrate 10
In FIG. 1, an N-type well 111 is formed, and a high-concentration P-type region (P ⁺ -type region) 112 is formed in the N-type well 111. The photoelectric conversion element PD1 is configured as a P ⁺ N type photodiode. Also, a P-type silicon substrate 1
01, a source 123 and a drain 124 of a depletion type N-channel MOSFET serving as an amplifying element Q1, and a source 133 and a drain 134 of an N-channel MOSFET serving as a first initialization means S11 are formed. I have. Further, on the P-type silicon substrate 101, the gate electrode 121 of the amplifying element Q1 and the first initializing unit S1 are interposed via the gate insulating films 122 and 132.
One gate electrode 131 is formed. The N-type well 111 is provided with a high-concentration N-type region (N ⁺ -type region) 113 for taking an N-side electrode (electrode of the N-type well) of the photoelectric conversion element PD1. Each element, that is, the photoelectric conversion element PD1, the amplification element Q1, and the first
Are separated from each other by the field oxide film 105. Here, the photoelectric conversion element PD
1 is connected to the source 123 of the amplifying element Q1.
The high-concentration P-type region 112 of the photoelectric conversion element PD1 is connected to the gate electrode 121 of the amplification element Q1 and the drain 134 of the initialization means S11.
Are connected to each other by an electrode wiring L2. In FIG. 6, the illustration of the structure corresponding to the reading means S13 is omitted.

The inventor of the present application actually produced a layer configuration as shown in FIG. 6 by the following process. First, an N-type well 111 is formed on the surface of a P-type silicon substrate 101 having a resistivity of 10 Ωcm. That is, using the resist pattern as a mask, phosphorus ions are implanted into the surface of the P-type silicon substrate 101 at 2.0E12 / cm ² at 150 keV, the resist is removed, and then annealed in an electric furnace at 1100 ° C. in a nitrogen atmosphere for 10 hours. Then, the implanted ions are activated to form the N-type well 111.

Next, amplifying element Q1, photoelectric conversion element PD
1. A field region in which the first initializing means S11, reading means S13, etc. are formed is prepared. That is, first, P
Silicon nitride film over the entire surface of the silicon substrate 101
After a film is formed, a resist pattern is formed in the field region, and then the silicon nitride film is patterned using a dry etching method. Next, boron ions are implanted at 40 keV at 8.0E12 / cm ² so that a parasitic field transistor is not formed, and the resist is removed. Then, 900 times using the usual pyrogenic method
By performing thermal oxidation at 5 ° C. for 5 hours, a 5000 ° field oxide film 105 is grown to perform element isolation. After removing the oxide film grown on the surface of the silicon nitride film with hydrofluoric acid, the silicon nitride film is removed with phosphoric acid at 200 ° C. to form a field region.

Next, a resist pattern is formed in the region where the amplifying element Q1 is to be formed in order to perform channel doping for threshold voltage control, and phosphorus ions are added at 90 keV to 4.0E1.
Implant ² / cm ² and remove the resist. After a while
A resist pattern is formed in a region where the first initializing means S11 is to be formed, in order to perform channel doping for controlling a threshold voltage.
Implant in cm ² and remove the resist. Subsequently, to form the gate insulating films 122 and 132, a thermal oxide film is grown at 200 ° C. in a dry oxygen atmosphere at 910 ° C.

Next, the gate electrode 121 of the amplification element Q1
In order to form the gate electrode 131 of the first initializing means S11, polysilicon is deposited by LPCVD method.
Deposit 00Å. To lower the resistance of polysilicon,
Phosphorous ions at 40 keV over the entire surface 5.0E15 / cm
^{2 is} implanted, and then a resist pattern is formed and patterned by dry etching in order to pattern the polysilicon into a gate shape. Thereafter, a resist pattern is formed on the source 123 and the drain 124 of the amplifying element Q1 and the source 133 and the drain 134 of the first initialization means S11, and arsenic ions are added at 40 keV and 5.0.
E15 / cm ^{2 is} implanted to remove the resist.

Further, a resist pattern is formed in the high-concentration P-type region 112 of the photoelectric conversion element PD1, and BF ₂ ions are implanted at 40 keV at 4.0E15 / cm ² to remove the resist. 95 to activate the implanted ions
Anneal for 30 minutes in an electric furnace at 0 ° C. in a nitrogen atmosphere. Thereafter, a contact hole was formed and metal wiring was performed using a normal LSI process, thereby producing a photoelectric conversion device having a layer configuration shown in FIG. When this device was measured, a sensitivity approximately 10 times as high as that of a conventional device was obtained.

As described above, the photoelectric conversion cells C1 to Cn of the amplification type photoelectric conversion device can be realized as those having the structure as shown in FIG. 6, and high sensitivity can be achieved.
In the structure of FIG. 6, since the number of elements in one pixel is large, there is a limit to achieving high integration by simply arranging the elements.

Therefore, the inventor of the present application has devised a photoelectric conversion device having a structure capable of high integration by further devising the element structure.

FIG. 7 is a diagram showing an example in which one photoelectric conversion cell C1 shown in FIG. 5 is formed on a silicon substrate with higher integration than the structure shown in FIG. FIG.
In FIG. 6, the same parts as those in FIG. 6 are denoted by the same reference numerals.

In the photoelectric conversion device having the structure shown in FIG.
Similarly to the photoelectric conversion device having the structure shown in FIG.
1 is configured as a P ⁺ N-type photodiode, and the amplifying element Q1 is configured as a depletion-type N-channel MOSFET. However, as compared with FIG. 6, the N-type well 111 of the photoelectric conversion element PD1 has Is different in that it contains a part of That is, in the configuration of FIG.
High-concentration N-type region 113 for taking N-side electrode (electrode of N-type well 111) of photoelectric conversion element PD1 and amplifying element Q
1 and the high-concentration N-type region 113.
Are configured to also function as the source 123 of the amplification element Q1. In such a configuration, the N-type well 111 of the photoelectric conversion element PD1 required in the configuration of FIG.
This eliminates the need for the electrode wiring L1 between the source and the source 123 of the amplifying element Q1, so that high integration can be achieved and the connection wiring resistance can be reduced.

The photoelectric conversion device having the layer configuration shown in FIG. 7 can be manufactured by using the same manufacturing method as the photoelectric conversion device having the layer configuration shown in FIG. 6. However, in the photoelectric conversion device shown in FIG. When forming a resist pattern in the field region, the first initializing means S11 sets the P-type silicon substrate 101
At the same time, a part of the high-concentration P-type region 112 of the photoelectric conversion element PD1 and a part of the source 123 of the amplification element Q1 are formed in the N-type well 111. Except for this, the photoelectric conversion device illustrated in FIG. 7 was actually manufactured using the same manufacturing method as that of the photoelectric conversion device illustrated in FIG.

In the photoelectric conversion device having the layer configuration of FIG. 7, since a part of the source 123 of the amplifying element Q1 is formed in the N-well 111, the device is different from the photoelectric conversion device having the layer configuration of FIG. The area was reduced to about 90%, and the photoelectric conversion device could be highly integrated.

FIG. 8 is a diagram showing an example in which one photoelectric conversion cell C1 shown in FIG. 5 is formed on a silicon substrate with further higher integration. Referring to FIG.
On the P-type silicon substrate 101, the reading means S13 is formed as an N-channel MOS • FET. That is,
8, a source (or drain) 143 and a drain (or source) 144 of the reading means S13 are formed on a P-type silicon substrate 101, and a gate insulation is provided on the P-type silicon substrate 101. The gate electrode 141 of the reading means S13 is formed via the film 142.

6 and 7, the reading means S13
Is formed on a P-type silicon substrate 101 as an N-channel MOS • FET in the same manner as in FIG.
The reading means S13 is not shown in FIG. 7 for simplicity), and the source 1 of the amplifying element Q1 is shown in FIGS.
23 and the source (or drain) 14 of the reading means S13
3 is connected by electrode wiring. In contrast,
8 is different from the structure shown in FIG. 8 in that the N-type well 111 of the photoelectric conversion element PD1 further includes a part of the source (or drain) 143 of the reading means S13. That is, in the structure shown in FIG. 8, in the structure of FIG. 6, the high-concentration N-type region 113 for taking the electrode of the N-type well 111, the source 123 of the amplification element Q1, and the source (or drain) 143 of the reading means S13 And the high-concentration N-type region 113 functions not only as the source 123 of the amplifying element Q1 but also as the source (or drain) 143 of the reading means S13. In such a configuration,
The electrode wiring between the source 123 of the amplifying element Q1 and the source (or drain) 143 of the reading means S13, which was required in the configurations of FIGS. 6 and 7, is not required, and further higher integration can be achieved. At the same time, the connection wiring resistance can be further reduced. In FIG. 8,
Illustration of the field oxide film 105 is omitted.

Specifically, the photoelectric conversion device having the layer configuration shown in FIG. 8 can be manufactured by using the same manufacturing method as the photoelectric conversion device having the layer configuration shown in FIG. The method for manufacturing the source (or drain) 143 is different from the method for manufacturing in FIG. That is, in the photoelectric conversion device shown in FIG. 7, when the resist pattern is formed in the field region, the first initializing means S11 is used for the P-type silicon substrate 101.
At the same time, the high-concentration P-type region 112 of the photoelectric conversion element PD1, at least a part of the source 123 of the amplifying element Q1, and the source of the reading means S13.
At least a part of the source (or drain) 143 is formed in the N-type well 111. After this, FIG.
8 using the same manufacturing process as the photoelectric conversion device of FIG.
Was manufactured.

In the photoelectric conversion device having the layer configuration shown in FIG. 8, since at least a part of the source (or drain) 143 of the reading means S13 is formed in the N well 111, the photoelectric conversion device having the layer configuration shown in FIG. The element area was about 85% as compared with the device, and the photoelectric conversion device could be further integrated.

In the structures shown in FIGS. 5 to 8, the back gate of the depletion-type N-channel MOS FET functioning as the amplifying element Q1 is the P-type silicon substrate 101 itself, and the source of the amplifying element Q1 is 12
When the potential of No. 3 is read as the output signal Vout of the photoelectric conversion cell, there arises a problem that the linearity of the photoelectric conversion device, that is, the input / output characteristics is deteriorated due to the substrate bias effect of the amplification element Q1.

In order to avoid such a problem, the inventor of the present application has further devised a photoelectric conversion device in which the back gate of the amplifying element Q composed of a MOS-FET is connected to the source of the amplifying element. did.

FIG. 9 is a diagram showing a configuration example of one photoelectric conversion cell C1 of such a photoelectric conversion device. In the configuration of FIG. 9, the back gate of the amplifier Q1 is connected to the source of the amplifier Q1. It is connected to the. As described above, by connecting the back gate of the amplifying element Q1 to the source of the amplifying element Q1, the potential of the back gate of the amplifying element Q1 increases as the source potential of the amplifying element Q1 increases. I do. As a result, the substrate bias effect of the amplifier element Q1 can be eliminated,
The linearity of the photoelectric conversion device, that is, the input / output characteristics can be improved.

When a photoelectric conversion device provided with n photoelectric conversion cells having the configuration shown in FIG. 9 is formed on a semiconductor substrate, that is, an amplifying element Qi composed of a MOS-FET.
The back gate (i = 1 to n) is connected to the amplifying element Qi (i = 1).
To n), the amplifying element Qi (i = 1)
Note that the source potentials of the amplifying elements Qi (i = 1 to n) are electrically separated for each photoelectric conversion cell. I have to do it. FIG. 10 is a diagram showing an example in which the photoelectric conversion cell C1 shown in FIG. 9 is formed on a silicon substrate with the intention of electrically separating the back gate of the amplifying element for each photoelectric conversion cell. is there.

In the structure shown in FIG. 10, an N-type well 111 is formed in a P-type silicon substrate 101, and a high-concentration P-type region 112 is formed in the N-type well 111. With the mold region 112, the photoelectric conversion element PD1 is configured as a P ⁺ N type photodiode. Further, an N-type well 126 is formed in the P-type silicon substrate 101, and a P-type well 125 is further formed in the N-type well 126. In this P-type well 125, a depletion-type N-type functioning as an amplification element Q1 is provided. A source 123 and a drain 124 of a channel MOSFET are formed. Also, a P-type silicon substrate 1
01 includes a source 133 and a drain 1 of an N-channel MOS-FET functioning as a first initializing means S11.
34 are formed. Further, the P-type silicon substrate 10
A gate electrode 121 of the amplifying element Q1 and a gate electrode 131 of the first initializing means S11 are formed on the gate electrode 1 via gate insulating films 122 and 132, respectively. here,
P-type well 125 is electrically separated from P-type silicon substrate 101 by N-type well 126.

The N-type well 111 is provided with a high-concentration N-type region 113 for taking the N-side electrode of the photoelectric conversion element PD1 (the electrode of the N-type well 111). Is a high-concentration N-type region 1 for forming an electrode.
27, and a high-concentration P-type region 128 for taking an electrode is provided in the P-type well 125;
High concentration N region 113 of P type well 111 and P type well 12
5 high-concentration P-type region 128 and the source 12 of the amplifying element Q1.
3 is connected by the electrode wiring L3. In addition,
As shown by the broken line, the high-concentration N-type region 127 of the N-type well 126 is connected to the source 123 of the amplifying element Q1 and the electrode wiring L4.
Or may be connected to the drain 124 of the amplifying element Q1 by the electrode wiring L5. Alternatively, it may be set to another independent potential.

In the structure shown in FIG.
Functions as a back gate of the amplifying element Q1, and the P-type well 125, that is, the back gate of the amplifying element Q1
The N-type well 126 is electrically separated from the P-type silicon substrate 101. Also, this back gate 125
Is connected to the source 123 of the amplifier element Q1 and has the same potential as the source 123 of the amplifier element Q1. Therefore,
When operating as a photoelectric conversion cell, as described above,
As the potential of the source 123 of the amplifying element Q1 increases,
The potential of the P-type well 125 (that is, the back gate of the amplifying element Q1) also increases, so that the substrate bias effect can be eliminated and the input / output characteristics (linear characteristics) can be improved.

Specifically, the photoelectric conversion device having the layer configuration shown in FIG. 10 can be manufactured by using the same manufacturing method as the photoelectric conversion device having the layer configuration shown in FIG. Then, the N-type well 126 is formed in the P-type silicon substrate 101.
Is formed, and a P-type well 1 is formed in the N-type well 126.
25 is different from the manufacturing method of FIG.
Actually, the photoelectric conversion device of FIG. 10 was manufactured as follows.

First, the surface of the P-type silicon substrate 101 is
A resist pattern is formed so that an N-type well 126 is formed at the same time as the N-type well 111, and ion implantation and annealing are performed.
26 is manufactured. Next, P
In order to form the mold well 125, a resist pattern is formed, and boron ions are applied to the surface of the N-type well 126 by 40K.
After implanting 8.0E12 cells / cm ² at eV and removing the resist, annealing is performed for 8 hours in an electric furnace at 1050 ° C. in a nitrogen atmosphere to activate the implanted ions, thereby forming the P-type well 125. Make it. Thereafter, the photoelectric conversion device in FIG. 10 was manufactured using the same steps as those in the photoelectric conversion device in FIG.

In the photoelectric conversion device having the layer configuration shown in FIG. 10, the P-type well 12 functioning as a back gate of the amplification element Q1 is provided.
5 is a P-type silicon substrate 10
1, the back gate of the amplifier Q1 can be connected to the source 123, and the substrate bias effect of the amplifier Q1 can be eliminated.
A photoelectric conversion device having good input / output characteristics (specifically, the linear characteristics were improved by about 5% at 3 V output) was realized.

Incidentally, in the structure of FIG. 10, the N-type well 126 is the N-type well 111 of the photoelectric conversion element PD1.
Focusing on the fact that the N-type well 126 and the N-type well 111 of the photoelectric conversion element PD1 can be shared, the inventor of the present application has found that the N-type well 126 and the N-type well 111 of the photoelectric conversion element PD1 can be shared.

FIG. 11 shows the photoelectric conversion cell C shown in FIG.
FIG. 1 is a diagram illustrating an example in which an N-type well 126 and an N-type well 111 are formed on a silicon substrate in common.

In the configuration shown in FIG. 11, the high-concentration N-type region 113 of the N-type well 111 and the N-type well 126 are formed as shown in FIG.
Need not be provided separately from the high-concentration N-type region 127, and one electrode portion, for example, the high-concentration N-type region 1
It can be only 27. Accordingly, there is no need to separately provide the electrode wiring L4 or L5. Further, there is no need to provide a space for separating the N-type well 111 and the N-type well 126. Thus, high integration of the photoelectric conversion device can be easily achieved.

FIG. 12 is a diagram showing a configuration example of a photoelectric conversion cell in which at least a part of the source 123 of the amplifying element Q1 is included in the N-type well 126 in the structure shown in FIG.

In the configuration as shown in FIG. 12, at least a part of the source 123 of the amplifying element Q1 is included in the N-type well 126, so that the source 123 and the N-type well 126 of the amplifying element Q1 and the amplifying element It is not necessary to provide the electrode wiring L3 between the high-concentration P-type region 128 of the P-type well 125 functioning as the back gate of Q1, and the field oxide film 105 can be omitted. Can be highly integrated.

It should be noted that the photoelectric conversion device having the layer structure as shown in FIGS.
As shown in FIGS. 6, 7, 8, and 10 by a simple method that only changes the resist pattern at the time of forming the shielded region, the case of forming the high concentration N-type region, and the case of forming the high concentration P-type region. The photoelectric conversion device having a simple layer configuration can be manufactured by partially changing the manufacturing method, and as a result of actual manufacturing, high integration can be achieved.

In the configuration shown in FIG. 5, when the area of the photoelectric conversion element is reduced as in a sensor using a reduction optical system, the capacitance (storage capacitance) connected to the gate of the amplification element is used as the capacitance of the photoelectric conversion element. When a MOS-FET is used as the first initialization means, not only the parasitic capacitance, but also the capacitance between the source (or drain) and the substrate of the MOS-FET as the first initialization means cannot be ignored.

FIG. 13 shows a photoelectric conversion device intended to further reduce the influence of the capacitance between the source (or drain) and the substrate of the MOS-FET as the first initialization means in the configuration of FIG. FIG. 3 is a diagram showing a configuration example of one photoelectric conversion cell C1. In the configuration as shown in FIG. 13, as in the case of one photoelectric conversion cell C1 of the photoelectric conversion device in FIG. The first initialization means (MOS / FE
T) The difference is that the back gate of S11 is connected to the source of the amplifying element Q1. As described above, since the back gate of the first initializing means (MOS • FET) S11 is connected to the source of the amplifying element Q1, FIG.
According to the same principle as described in the photoelectric conversion device of
The influence of the capacitance between the source (or drain) of the MOS FET as the first initialization means and the substrate can be reduced, and the sensitivity of the photoelectric conversion device can be further increased. In FIG. 13, an N channel M is used as the first initialization means S11.
Although a P-channel MOSFET is used instead of an OS-FET, this is because a depletion type N-channel MOSFET is used for the amplifier Q1.
Is higher than the gate potential of the amplifying element Q1.

When a photoelectric conversion device provided with n photoelectric conversion cells having the structure shown in FIG. 13 is formed on a semiconductor substrate, that is, first initialization means Si1 (i = 1 When the back gates of the amplifier elements Qi (i = 1 to n) are connected to the source of the amplifier element Qi (i = 1 to n), the output potential of each photoelectric conversion cell is And the first initialization means Si
The back gate 1 (i = 1 to n) must be electrically separated for each photoelectric conversion cell. FIG.
FIG. 14 is a diagram showing an example in which the photoelectric conversion cell C1 shown in FIG. 13 is formed on a silicon substrate for the purpose of electrically separating the back gate of the initialization means for each photoelectric conversion cell.

In the configuration shown in FIG. 14, as in FIG.
A photoelectric conversion element PD1 is formed as a P ⁺ N type photodiode on a silicon substrate 101, and an amplifying element Q1
Are formed as depletion-type N-channel MOS-FETs. In the P-type silicon substrate 101, an independent N-type well 135 is further formed for each pixel. In the N-type well 135, a P-channel MOS-FET is provided. 6 in that the source 134 and the drain 133 of the first initialization means S11 are formed.

A high-concentration N-type region 136 for taking an electrode is formed in the N-type well 135, and the N-type well 111 of the photoelectric conversion element PD1 is connected to the source 1 of the amplification element Q1.
23 and the high-concentration N-type region 136 of the N-type well 135 via the electrode wiring L1.
The high-concentration P-type region 112 of D1 is connected to the gate electrode 121 of the amplification element Q1 and the source 13 of the first initialization means S11.
4 is connected to an electrode wiring L2. Each element, that is, the photoelectric conversion element PD1, the amplification element Q1, and the first
Are separated from each other by the field oxide film 105. In FIG. 14, the structure corresponding to the reading means S13 is the same as in FIG.
Illustration is omitted.

In the configuration shown in FIG. 14, since the N-type well 135 in which the first initialization means S11 is formed is independent for each pixel, the N-type well 135 is connected to the source 123 of the amplifying element Q1 as described above. Can be connected. This N-type well 135
Is a back gate of a P-channel MOS-FET functioning as a first initializing means S11, which is connected to the source 123 of the amplifying element Q1 so that the source 134 of the first initializing means S11 and the substrate 135 can be apparently reduced, and the gain of the amplifying element Q1 can be reduced.
In this way, the capacity leading to the load can be further reduced.
This makes it possible to further increase the sensitivity of the photoelectric conversion device.

Specifically, a photoelectric conversion device having a layer configuration as shown in FIG. 14 was manufactured as follows.

That is, N-type wells 111 and 135 are formed on the surface of the P-type silicon substrate 101 by using the same manufacturing method as that of the photoelectric conversion device shown in FIG. 6, and then a field region is formed. Phosphorous ions at 90 KeV at 4.0E12 / c for controlling the threshold voltage in the region where the amplifying element Q1 is formed.
m ^{2 is} implanted, and then boron ions are applied to the region where the first initializing means S11 is to be formed for controlling the threshold voltage by 25 KeV.
Then, 3.0E12 / cm ^{2 are} implanted, and then gate insulating films 122 and 132 are formed.

Next, after forming the gate electrodes 121 and 131, the source 123 and the drain 124 of the amplification element Q1 are formed.
Arsenic ions are implanted at 40 KeV at 5.0E15 ions / cm ^2, and the high-concentration P-type region 112 and the first initialization means S11 are implanted.
Of BF ₂ ions into the source 133 and the drain 134
After injection of 4.0E15 / cm ² with KeV, 950 ° C.
For 30 minutes in an electric furnace in a nitrogen atmosphere. Thereafter, the photoelectric conversion device having the layer configuration in FIG. 14 was manufactured by using the method for manufacturing the photoelectric conversion device in FIG.

In the photoelectric conversion device having the layer configuration shown in FIG.
N-type well 1 which is the back gate of the initialization means S11
35 is independent for each pixel and can be connected to the source 123 of the amplifying element Q1, so that the first initialization means S11
The effect of the capacitance between the drain 134 and the substrate 135 can be sensed, and the sensitivity is about three times higher than that of the photoelectric conversion device having the layer configuration of FIG.

FIG. 15 shows that, in the structure shown in FIG. 14, the N-type well 135 functioning as a back gate of the first initializing means S11 has a source of the amplifying element Q1.
3 is a diagram illustrating a configuration example of a photoelectric conversion cell including at least a part of a cell 123. FIG. In the structure of FIG. 15, the N-type well 135 in which the first initializing means S11 is formed includes at least a part of the source 123 of the amplifying element Q1,
High concentration N-type region 1 for taking an electrode of N-type well 135
The reference numeral 36 also functions as the source 123 of the amplifier element Q1. In such a configuration, there is no need to connect the N-type well 135 serving as the back gate of the first initialization means S11 and the source 123 of the amplifier element Q1 with the electrode wiring L1 as shown in FIG. , N-type well 1
35 and the source 123 of the amplifying element Q1 are connected in the P-type silicon substrate 101, so that the photoelectric conversion device can be more highly integrated as compared with the structure of FIG. Resistance can be further reduced.

Further, in the configuration of FIG. 15, the N-type well 135 functioning as a back gate of the first initialization means S11 may be configured to function also as one conductivity type region of the photoelectric conversion element. .

FIG. 16 is a diagram showing an example of the configuration of one photoelectric conversion cell C1 of a photoelectric conversion device in which the N-type well 135 also functions as one conductivity type region of the photoelectric conversion element in the configuration of FIG. It is. That is, in FIG. 16, the source 134 of the P-channel MOSFET serving as the first initialization unit S11 and the high-concentration P-type region 112 of the photoelectric conversion element PD1 are shared, and the back gate of the first initialization unit S11 is used. The N-type well 135 serving as the gate and the N-type well 111 of the photoelectric conversion element PD1 are shared.
Further, at least a part of the source 123 of the amplifying element Q1 is included in the common N-type well (111, 135),
A high-concentration N-type region (113, 136) for taking an electrode of the common N-type well (111, 135)
It is configured to function also as one source 123.

In such a configuration, the first initialization means S
11 and the high-concentration P-type region 112 of the photoelectric conversion element PD1 are shared, and the N-type well 135 and the photoelectric conversion element P serving as a back gate of the first initialization means S11.
Since the N-type well 111 of D1 is shared, and the shared N-type well (111, 135) and the source 123 of the amplifier element Q1 are connected in the P-type silicon substrate 101, Further higher integration can be achieved, and the connection wiring resistance can be further reduced.

FIG. 17 shows the configuration of FIG.
Further, one photoelectric conversion cell C of the photoelectric conversion device in which the back gate of the amplifier Q1 is connected to the source of the amplifier Q1.
1 is a diagram illustrating a configuration example of FIG.

FIG. 18 is a diagram showing an example in which the photoelectric conversion cell C1 of FIG. 17 is formed on a silicon substrate. Note that the structure shown in FIG. 18 corresponds to the structure shown in FIG. 14, and only the part related to the amplification element Q1 is different from the structure shown in FIG. That is, in the structure of FIG. 18, an N-type well 126 is formed in the P-type silicon substrate 101, and a P-type well 1 is further formed in the N-type well 126.
A source 123 and a drain 124 of an N-channel MOSFET serving as an amplifying element Q1 are formed in the P-type well 125. Here, the P-type well 125 functions as a back gate of the amplifying element Q 1, and the P-type well 125 functioning as the back gate is separated from the P-type silicon substrate 101 by the N-type well 126. Also, N
A high-concentration N-type region 127 for forming an electrode is formed in the mold well 126, and a high-concentration P-type region 128 for forming an electrode is formed in the P-type well 125. 127, high-concentration P-type region 128 and amplifying element Q1
Is connected to the source 123 by an electrode wiring L3. That is, the amplification element Q
The back gate 1, that is, the P-type well 125 is electrically connected to the source 123 of the amplifying element Q 1.

In the photoelectric conversion device having such a configuration, the back gate of the amplifying element Q1 and the source 123 of the amplifying element Q1 are used.
Are electrically connected to each other, and the potential of the back gate of the amplification element Q1 is held at the source potential of the amplification element Q1, so that the substrate bias effect of the amplification element Q1 can be ignored, and the photoelectric conversion device Can also have good input / output characteristics (linear characteristics).

FIG. 19 is a diagram showing another example of the structure of the photoelectric conversion cell C1 shown in FIG. In the structure shown in FIG. 19, the N-type well 135 of the first initialization means S11, the N-type well 111 of the photoelectric conversion element PD1, and the N-type well 126 of the amplification element Q1 are shared. The drain 134 of S11 and the high-concentration P-type region 112 of the photoelectric conversion element PD1 are shared, and the shared N
A high-concentration N-type region (113, 136) for taking an electrode of the mold well (111, 135) is a source 1 of the amplifying element Q1.
It is configured to function also as 23. As a result, higher integration can be achieved and the connection wiring resistance can be further reduced.

A photoelectric conversion device having a layer structure as shown in FIGS. 15 and 16 and a photoelectric conversion device having a layer structure as shown in FIGS. The layer structure shown in FIG. 6, FIG. 7, FIG. 8, FIG. 10, and FIG. 14 can be obtained by a simple method such as changing the resist pattern at the time of forming the high concentration N type region or the high concentration P type region. The photoelectric conversion device was manufactured by partially changing the manufacturing method.

In each of the above-described elements, the features shown in the circuit configuration of the present invention can be obtained, and high integration can be achieved.

FIG. 20 is a diagram showing a specific example of the photoelectric conversion device shown in FIG. In the photoelectric conversion device in FIG. 20, n photoelectric conversion cells have the same configuration. For example, the n-th photoelectric conversion cell Cn includes a photoelectric conversion element PDn configured by a photodiode, and an amplifying element. Qn
Is constituted by a depletion type N-channel MOS-FET, and the first initialization means Sn1 is an N-channel MOS-FE
T, and the second initialization means Sn2 is an N-channel M
The reading means Sn3 is constituted by an OS-FET, and the reading means Sn3 is constituted by an N-channel MOS-FET. Further, an N-channel MOS-FET is used for the third initialization means S4, and all the initialization potentials VR1 to VR3 are set to "0" V (GN
D). Further, instead of the amplifier AMP, a first-stage source including an amplifying element QB1 and an amplifying element QB2 is used.
Follower circuit SF1, amplifying element QB3 and amplifying element Q
A second source follower circuit SF2 comprising B4,
A switch S6 is provided. The switch S6
Are driven in a phase opposite to that of the third initialization means S4.

FIG. 21 is a time chart showing the operation of the photoelectric conversion device of FIG. Referring to FIG. 21, FIG.
1 operates in synchronization with the clock CLK of the predetermined period, and initializes the first photoelectric conversion cell C1, and then executes the next clock, as described in the photoelectric conversion device of FIG. The second photoelectric conversion cell C2 is similarly initialized in a cycle, so that the nth photoelectric conversion cell Cn is sequentially initialized every clock cycle, and initialization is performed for a certain photoelectric conversion cell. Then, the photoelectric conversion process for the photoelectric conversion cell is started. For example, focusing on the first photoelectric conversion cell C1, first, S11
And S12 are turned on, and the gate potential and the source potential of the amplifying element Q1 are set to GND.
Is initialized. Next, when S12 is turned off, the source potential of the amplifying element Q1 charges the parasitic capacitance of S12 and the floating capacitance of the source, and drops to a potential higher than the gate potential by the gate-source voltage Vth. .

Thereafter, when S11 is turned off and a photocurrent corresponding to the amount of incident light flows through the photoelectric conversion element PD1, this photocurrent starts to be accumulated in a capacitor (storage capacitor) connected to the gate of the amplifier Q1. Thus, the amplifying element Q
By accumulating the electric charge based on the photocurrent in the capacitor connected to the gate of No. 1, the gate potential of the amplifying element Q1 increases, and at the same time the gate potential increases, the source potential also increases.
While charging the parasitic capacitance of the source and the floating capacitance of the source, the gate potential rises by the rise of the gate potential. Thus, the amplification element Q1
It functions as a source follower in which the source voltage changes following the gate voltage, and the gate-source voltage of the amplifier element Q1 maintains a constant voltage Vth.

Here, in the configuration of FIG. 20, since the photoelectric conversion element PD1 is connected between the gate and the source of the amplification element Q1, the photoelectric conversion element PD1 functions as a source follower. Since a voltage between the gate and the source of the amplifying element Q1, that is, a constant voltage Vth is applied, the charge of the parasitic capacitance of the photoelectric conversion element PD1 is always substantially constant.
There is almost no change. Therefore, the effect of the parasitic capacitance of the photoelectric conversion element PD1 on the storage capacitance can be extremely reduced, and the parasitic capacitance of the photoelectric conversion element PD1 can be substantially subtracted from the storage capacitance, so that the storage capacitance is apparently small. can do.

As a result, the photoelectric conversion device shown in FIG. 20 can obtain about 10 times higher sensitivity than the conventional photoelectric conversion device.

The photoelectric conversion cell C1 is initialized again after a lapse of a predetermined reading time (accumulation time). However, S13 is turned on in a half cycle of the clock CLK immediately before the initialization, and the source immediately before the initialization is started. The potential is output to the common signal line CM as an output signal. The source potential output to the common communication line CM is applied to a first-stage source follower circuit SF1 including an amplifier element QB1 and an amplifier element QB2, and the impedance is applied by the first-stage source follower circuit SF1. It is converted to VO1.

Thereafter, S13 is turned off and S4 is turned on in the half cycle of the next clock CLK, and the potential of the common signal line CM is initialized to GND (“0” V). At the same time, S11 and S12 are turned on to initialize the amplifying element Q1. Similar processing is sequentially performed on the second to n-th photoelectric conversion cells C2 to Cn at predetermined intervals synchronized with the clock CLK.

Further, in the photoelectric conversion device shown in FIG. 20, by driving the switch S6 in a phase opposite to that of the third initialization means S4, a sample-and-hold operation using the input capacitance of the amplification element QB3 as a hold capacitor is performed. The final output signal Vout from the converter continues to be output for one clock cycle.

That is, in the circuit configuration shown in FIG. 20, the first source follower circuit SF1, the second source follower circuit SF2, and the switch S6 perform impedance conversion and sample hold. It is possible,
Since the output signal Vout is output during one clock cycle, the time during which the output signal is stable is increased, and the speeding up is facilitated.

FIG. 22 is a diagram showing a specific example of the photoelectric conversion device shown in FIG. In the photoelectric conversion device of FIG. 22, similarly to the photoelectric conversion device of FIG. 20, the n photoelectric conversion cells have the same configuration, for example, the n-th photoelectric conversion cell Cn Element PDn
Is composed of a photodiode, the amplifying element Qn is composed of a depletion-type N-channel MOS-FET,
The initializing means Sn1 is composed of an N-channel MOS • FET, and the second initializing means Sn2 is composed of an N-channel MOS • F
ET, and the reading means Sn3 is an N-channel MOS
It is composed of an FET. Further, the third initialization means S4
, An N-channel MOS.FET is used, and the potentials VR1 to VR3 for initialization are all set to “0” V (GND). Further, instead of the amplifier AMP, the amplifying element QB
1 and a first-stage source follower circuit SF1 comprising an amplifier element QB2, a second-stage source follower circuit SF2 comprising an amplifier element QB3 and an amplifier element QB4, and a switch S
6 are provided. The switch S6 is driven in a phase opposite to that of the third initialization means S4.

FIG. 23 is a time chart showing the operation of the photoelectric conversion device of FIG. Referring to FIG.
Operates in synchronism with the clock CLK of the predetermined period, and after the initialization of the first photoelectric conversion cell C1, the next clock The second photoelectric conversion cell C2 is similarly initialized in a cycle, so that the nth photoelectric conversion cell Cn is sequentially initialized every clock cycle, and initialization is performed for a certain photoelectric conversion cell. Then, the photoelectric conversion process for the photoelectric conversion cell is started. For example, focusing on the first photoelectric conversion cell C1, first, S13
Are turned on only during the period of synchronization with the clock CLK1 as in S11. However, S13 is turned on by a half cycle earlier than S11. The output signal of the photoelectric conversion cell C1 is read during a half cycle of the clock in which only S13 is ON.

Next, during the period of the clock half cycle in which S11 and S13 are similarly turned on, S4 is further turned on, so that the potential of the common signal line CM, the source potential of the amplifying element Q1, and the amplifying element The gate potential of Q1 is set to GND (“0” V)
By doing so, the photoelectric conversion cell C1 is initialized.

Next, when S13 is turned off, the amplifying element Q
The source potential of 1 charges the parasitic capacitance of S13 and the floating capacitance of the source, and settles to a potential higher than the gate potential by the gate-source voltage Vth.

Thereafter, when S11 is turned off and a photocurrent corresponding to the amount of incident light flows through the photoelectric conversion element PD1, this photocurrent starts to be stored in a capacitor (storage capacitor) connected to the gate of the amplifier Q1. Thus, the amplification element Q1
The electric charge based on the photocurrent is accumulated in the capacitor connected to the gate of the amplifying device Q1, and the gate potential of the amplifying element Q1 rises.
At the same time as the gate potential rises, the source potential rises by the rise of the gate potential while charging the parasitic capacitance of S13 and the floating capacitance of the source. As described above, the amplifier element Q1 functions as a source follower whose source voltage changes following the gate voltage, and the gate-source voltage of the amplifier element Q1 maintains a constant voltage Vth.

Here, in the configuration of FIG. 22, since the photoelectric conversion element PD1 is connected between the gate and the source of the amplification element Q1, the photoelectric conversion element PD1 functions as a source follower. Since a voltage between the gate and the source of the amplifying element Q1, that is, a constant voltage Vth is applied, the charge of the parasitic capacitance of the photoelectric conversion element PD1 is almost always constant and hardly fluctuates. Therefore, the photoelectric conversion element PD1
Of the photoelectric conversion element PD1 can be substantially subtracted from the storage capacitance, and the storage capacitance can be apparently reduced.

Thus, in the photoelectric conversion device shown in FIG.
It is possible to obtain about 10 times higher sensitivity than a conventional photoelectric conversion device.

The photoelectric conversion cell C1 is initialized again after a lapse of a fixed reading time (accumulation time). However, S13 is turned on in a half cycle of the clock CLK immediately before the initialization, and the source immediately before the initialization is turned on. The potential is output to the common signal line CM as an output signal. The source potential output to the common signal line CM is applied to a first-stage source follower circuit SF1 including an amplifier element QB1 and an amplifier element QB2, and is impedance-converted to VO1.

Thereafter, S4 is turned on in a half cycle of the next clock CLK, and the potential of the common signal line CM and the source potential of the amplifier Q1 are initialized to GND ("0" V).
At the same time, S11 turns on, and the amplifying element Q1
Is also initialized to GND ("0" V). The second to n-th photoelectric conversion cells C2 to Cn are also shifted by a predetermined period synchronized with the clock CLK, and
Similar processing is sequentially performed.

Further, in the photoelectric conversion device shown in FIG. 22, by driving the switch S6 in a phase opposite to that of the third initialization means S4, a sample hold using the input capacitance of the amplifying element QB3 as a hold capacitor can be obtained. The final output signal Vout from the photoelectric conversion device is continuously output for one clock cycle.

That is, in this circuit configuration, the sample hold and the impedance conversion can be performed by the first source follower circuit SF1, the second source follower circuit SF2, and the switch S6. Since the output signal Vout is output during one clock cycle, the time during which the output signal is stable is increased, and the speeding up is facilitated.

Further, in the photoelectric conversion device of FIG.
0, the second initializing unit Sn2 is omitted, and the functions of the second initializing unit Sn2 are replaced by the first initializing unit Sn1, the reading unit Sn3, and the third initializing unit S4. 2 is realized by the operation timing of FIG.
Area of the photoelectric conversion cell is about 85
%, And high integration of the photoelectric conversion device has become possible.

In each of the examples described above, the case where a depletion type N-channel MOS FET is used as the amplifying element Q1 has been described. However, similar effects can be obtained by using other field effect transistors.

FIG. 24 and FIG. 25 are diagrams showing a configuration example of the photoelectric conversion cell C1 in the case where an enhancement type N-channel MOSFET is used for the amplification element Q1. Note that, in this case, unlike the depletion type, since the potential of the gate is higher than the source, the polarity of the photoelectric conversion element PD1 is reversed. Further, a resistor R is added between the source of the amplifier element Q1 and the reference potential VR4 in order to operate the amplifier element Q1 normally.

FIGS. 26 and 27 show a photoelectric conversion cell C1 when an N-channel J-FET is used for the amplifying element Q1.
FIG. 3 is a diagram showing an example of the configuration. 26 and 27, the PN junction between the gate and the source of the N-channel J-FET acts as the photodiode PD1 to provide the N-channel J-FET.
Photodiode PD provided separately by OS / FET
1 becomes unnecessary, and the required area of one photoelectric conversion cell C1 can be reduced.

In each of the above examples, an N-channel type device is used. However, a P-channel type MOS • FET or J • FET may be used instead. In this case, connection is made. By changing the potential and the polarity of the photoelectric conversion element PD1, the same effect as in the case of the N-channel type can be obtained.

Further, in each of the above-described examples, a P-type silicon substrate is used. However, an N-type silicon substrate may be used instead. The type is the opposite. That is, P
The type becomes N type, and the N type becomes P type.
1 is a P-channel type. In this case, the same effect as described above can be obtained.

The structure shown in FIGS. 14 to 16, that is, the structure in which the capacitance between the source (or drain) and the substrate of the first initialization means is reduced, is shown in FIG.
As shown in FIG. 8, the present invention can be applied to a case where one end of the photodiode PD1 which is a photoelectric conversion element is not connected to the source of the amplification element Q1, and is useful in the case of a photoelectric conversion layer laminated type. is there. Also in this case, similarly to FIG. 18, the back gate of the amplifier Q1 may be connected to the source of the amplifier Q1.

FIG. 29 is a view showing a third embodiment of the photoelectric conversion device according to the present invention. The photoelectric conversion device of FIG. 29 regards the configuration of the photoelectric conversion device shown in the first or second embodiment (for example, the configuration of FIG. 1 or FIG. 3) as one block, and includes m blocks # 1 to #m. Are connected in parallel, and a switch S1 for selecting a block is provided.
5 to Sm5 are further provided. Note that these switches S15 to Sm5 are controlled so that any one of them is turned on. Also, S14 to Sm4 are the first
Or, it corresponds to S4 of the second embodiment. Further, the amplifiers AMP1 to AMPm may have lower driving capability than the amplifier AMP of the first or second embodiment, but the amplifier AMP0 of the last stage has the amplifier A of the first or second embodiment.
A driving capability equivalent to MP is required.

FIG. 30 shows the photoelectric conversion device shown in FIG.
6 is a time chart illustrating an operation when the number m of blocks is “4”. Here, the main clock MCLK is a reference for the timing of the entire photoelectric conversion device in FIG. 8, and the clocks CLK1 to CLK4 of each of the blocks # 1 to # 4 are obtained by dividing the main clock MCLK by four. ing. The phases of the clocks CLK1 to CLK4 are shifted by １ ／ cycle, and the blocks # 1 to # 4
Output signals Vout1 to Vout4 are similarly shifted by つ period. Therefore, if the block is selected for only one cycle of the main clock MCLK immediately before the signal of each block is initialized in S15 to S45, the output Vout from the amplifier AMP0 is changed for each cycle of the main clock MCLK as shown in FIG. The signals from blocks # 1 to # 4 are output, and high-speed signal output is possible. Further, since the bit rate of each block is 1 / the number of blocks with respect to the output bit rate, it is easier to increase the speed.

That is, the photoelectric conversion device having the configuration as shown in FIG. 1, FIG. 20 or FIG. 3, FIG. 22 is regarded as one block, and a plurality (m) of the blocks are connected in parallel. In the apparatus, each block operates with a clock having a predetermined period, and each block is selected with a phase shift of 1 / m at a predetermined period. Reading from the block can be performed at high speed.

[0110]

As described above, claims 1 to 1 are provided.
According to the invention as set forth in claim 5, the photoelectric conversion element is a gate of the amplification element.
Since the gate-source voltage of the amplifying element is applied to the photoelectric conversion element, the parasitic capacitance of the photoelectric conversion element reduces the gate capacitance of the amplifying element. Has a very small effect on the capacity (storage capacity)
The storage capacitance can be apparently reduced, and an output signal with high sensitivity and a high SN ratio can be obtained.

According to the second aspect of the present invention, the reading means has the function of reading out the source potential of the amplifying element as an output signal, and the readout means sets the source potential immediately after reading the source potential as an output signal. It also has a function of initializing, so that it is not necessary to separately provide means for initializing the source potential of the amplifying element, and the size of the photoelectric conversion device can be reduced.

According to the fifth and thirteenth aspects of the present invention, since the back gate of the amplifying element is electrically connected to the source of the amplifying element, the substrate bias effect of the amplifying element can be eliminated. As a result, the input / output characteristics of the photoelectric conversion device can be improved.

According to the ninth aspect of the present invention, the MO
Since the back gate of the first initialization means formed as an S-FET is electrically connected to the source of the amplifying element, the back gate of the first initialization means is provided between the source and the substrate of the first initialization means, or The capacitance between the drain and the substrate can be reduced apparently,
The capacitance connected to the gate of the amplification element can be further reduced, and the sensitivity of the photoelectric conversion device can be further increased.

Further, claim 3, claim 4, claim 6, claim 7, claim 8, claim 10, claim 11, and claim 1
According to the inventions described in claims 14 and 15, by devising the structure of the photoelectric conversion device, the characteristics of the photoelectric conversion device can be improved and high integration can be achieved.

According to the sixteenth aspect of the present invention, the amplifying means for amplifying the output signal from the common signal line to obtain the final output signal,
Since the sample hold is performed together with the impedance conversion, the time during which the output signal is stable increases, and the speed can be easily increased.

According to the seventeenth aspect of the present invention, the photoelectric conversion device according to the sixteenth aspect is regarded as one block, and a plurality of (m) blocks are connected in parallel. Each block operates with a clock having a predetermined period, and each block is selected with a phase shift of 1 / m with respect to the predetermined period. Can be read at high speed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of a photoelectric conversion device according to the present invention.

FIG. 2 is a time chart for explaining the operation of the photoelectric conversion device of FIG. 1;

FIG. 3 is a configuration diagram of a second embodiment of the photoelectric conversion device according to the present invention.

FIG. 4 is a time chart for explaining the operation of the photoelectric conversion device of FIG. 3;

FIG. 5 is a diagram showing a configuration example of one photoelectric conversion cell of the photoelectric conversion device according to the present invention.

6 is a diagram illustrating an example of the structure of the photoelectric conversion cell illustrated in FIG.

FIG. 7 is a diagram showing an improved example of the structure of the photoelectric conversion cell shown in FIG.

8 is a diagram showing an improved example of the structure of the photoelectric conversion cell shown in FIG.

FIG. 9 is a diagram showing a configuration example of one photoelectric conversion cell of the photoelectric conversion device according to the present invention.

10 is a diagram illustrating an example of the structure of the photoelectric conversion cell illustrated in FIG.

11 is a diagram showing an improved example of the structure of the photoelectric conversion cell shown in FIG.

12 is a diagram showing an improved example of the structure of the photoelectric conversion cell shown in FIG.

FIG. 13 is a diagram showing a configuration example of one photoelectric conversion cell of the photoelectric conversion device according to the present invention.

14 is a diagram illustrating an example of the structure of the photoelectric conversion cell illustrated in FIG.

15 is a diagram showing an improved example of the structure of the photoelectric conversion cell shown in FIG.

16 is a diagram showing an improved example of the structure of the photoelectric conversion cell shown in FIG.

FIG. 17 is a diagram showing a configuration example of one photoelectric conversion cell of the photoelectric conversion device according to the present invention.

18 is a diagram showing an example of the structure of the photoelectric conversion cell shown in FIG.

19 is a diagram showing an improved example of the structure of the photoelectric conversion cell shown in FIG.

20 is a diagram showing a specific example of the photoelectric conversion device shown in FIG.

FIG. 21 is a time chart for explaining the operation of the photoelectric conversion device of FIG. 20;

FIG. 22 is a diagram showing a specific example of the photoelectric conversion device shown in FIG.

FIG. 23 is a time chart for explaining the operation of the photoelectric conversion device of FIG. 22;

FIG. 24 is a diagram showing another configuration example of the photoelectric conversion cell of the photoelectric conversion device according to the present invention.

FIG. 25 is a diagram showing another configuration example of the photoelectric conversion cell of the photoelectric conversion device according to the present invention.

FIG. 26 is a diagram showing another configuration example of the photoelectric conversion cell of the photoelectric conversion device according to the present invention.

FIG. 27 is a diagram showing another configuration example of the photoelectric conversion cell of the photoelectric conversion device according to the present invention.

FIG. 28 is a diagram showing another configuration example of the photoelectric conversion cell of the photoelectric conversion device according to the present invention.

FIG. 29 is a diagram illustrating a configuration example of a photoelectric conversion device according to the present invention.

FIG. 30 is a time chart for explaining the operation of the photoelectric conversion device of FIG. 29;

FIG. 31 is a configuration diagram of a photoelectric conversion cell of a conventional photoelectric conversion device.

[Explanation of symbols]

C1 to Cn photoelectric conversion cell Q, Q1 to Qn amplifying element PD, PD1 to PDn photoelectric conversion element S1, S11 to Sn1 First initialization means S2, S12 to Sn2 Second initialization means S3, S13 to Sn3 Reading means S4, S14 to Sm4 Third initialization means S15 to Sm5 Block selection switch # 1 to #m Block CM Common signal line AMP, AMP0 to AMPm Amplifier 101 P-type silicon substrate 105 Field oxide film 111 N of photoelectric conversion element
Type well 112 High-concentration P-type region of photoelectric conversion element 113 High-concentration N-type region for taking an electrode of N-type well 111 121 Gate electrode of amplifying element 122 Gate insulating film of amplifying element 123 Source of amplifying element 124 Source of amplifying element Drain 125 P-type well 126 N-type well 127 High-concentration N-type region for taking an electrode of N-type well 126 128 High-concentration P-type region for taking an electrode of P-type well 125 131 Gate of first initialization means Electrode 132 Gate insulating film of first initializing means 133 Source (or drain) of first initializing means 134 Drain (or source) of first initializing means 135 N-type well 136 Electrode of N-type well 135 High-concentration N-type region 141 to be taken 141 Gate electrode of reading means 142 Gate insulating film of reading means 143 Reading means Source (or drain) 144 reading means of the drain (or source) L1 to L5 electrode wirings

──────────────────────────────────────────────────続 き Continued on the front page (31) Priority claim number Japanese Patent Application No. 4-217259 (32) Priority date July 23, 1992 (1992.7.23) (33) Priority claim country Japan (JP) (31) Priority claim number Japanese Patent Application No. 4-247348 (32) Priority date August 24, 1992 (1992.8.24) (33) Priority claim country Japan (JP) (72) Inventor Takeshi Ken Nanjo 10 Ricoh-Applied Electronics Research Laboratories Co., Ltd., located at 5-5 Kokata Kumanodo characters in Natori city, Miyagi prefecture (72) Inventor Yutaka Yudena Inside Research Institute Co., Ltd. (72) Inventor Mitsuhiro Oizumi 10 Ricoh-Applied Electronics Research Institute Co., Ltd., located at No. 5 Takakata Kumanodo, Natori City, Miyagi Prefecture 10 Rico 5 in the upper part of the character (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 1/024-1/036

Claims (17)

(57) [Claims] 1. A photoelectric conversion device having at least one photoelectric conversion cell, wherein the photoelectric conversion cell comprises a photoelectric conversion element for generating a photocurrent according to the amount of incident light, and a field effect transistor, which follows a gate voltage. And an amplifying element that functions as a source follower whose source voltage changes, and readout means for reading out the source voltage of the amplifying element as an output signal, wherein the photoelectric conversion element includes a gate and a source of the amplifying element. A photoelectric conversion device, wherein a gate-source voltage of the amplification device is applied to the photoelectric conversion device. 2. The photoelectric conversion device according to claim 1, wherein
First initialization means for initializing the gate potential is further connected to the gate of the amplifying element, and the read means reads the source potential and outputs an output signal to a common signal line. In this case, the reading means has a function of reading out the source potential of the amplifying element as an output signal, and cooperates with means for initializing the potential of the common signal line. A photoelectric conversion device having a function of initializing a source potential immediately after reading the source potential as an output signal. 3. The photoelectric conversion device according to claim 1, wherein the second conductivity type well is formed in the first conductivity type substrate, and the first conductivity type region is formed in the second conductivity type well. The photoelectric conversion element is formed as a photodiode by the second conductivity type well and the first conductivity type region;
The amplifying element is formed as a second conductivity type MOS-FET on the first conductivity type substrate.
The photoelectric conversion device, wherein the conductivity type well includes at least a part of the source of the amplification element. 4. The photoelectric conversion device according to claim 3, wherein
The reading means is formed as a second conductivity type MOS • FET on the first conductivity type substrate, and the second conductivity type well has a second conductivity type MOS • F which is the reading means.
A photoelectric conversion device comprising at least a part of a source or a drain of ET. 5. The photoelectric conversion device according to claim 1, wherein the amplifying element is formed as a MOS-FET, and a back gate of the amplifying element is connected to a source of the amplifying element. A photoelectric conversion device, which is connected. 6. The photoelectric conversion device according to claim 5, wherein
A second conductivity type well X2 is formed in the first conductivity type substrate, a first conductivity type region X1 is formed in the second conductivity type well X2, and the second conductivity type well X2 is formed by the first conductivity type region X1. The photoelectric conversion element is formed as a photodiode, a second conductivity type well Y2 is formed on the first conductivity type substrate, and a first conductivity type well Y1 is further formed in the second conductivity type well Y2. Is formed, and the first conductivity type well Y1 is formed.
Wherein the amplifying element further comprises a second conductivity type MOS-FET.
A photoelectric conversion device characterized by being formed as: 7. The photoelectric conversion device according to claim 6, wherein
The photoelectric conversion device, wherein the second conductivity type well X2 is shared with the second conductivity type well Y2 in the first conductivity type substrate. 8. The photoelectric conversion device according to claim 6, wherein
The photoelectric conversion device, wherein the second conductivity type well Y2 includes at least a part of the source of the amplification element. 9. The photoelectric conversion device according to claim 1, wherein said first initialization means includes a MOS-FE.
A photoelectric conversion device formed as T, wherein a back gate of the first initialization means is connected to a source of the amplifying element. 10. The photoelectric conversion device according to claim 9, wherein the back gate of the MOS-FET as the first initialization means is formed by one well formed independently for each pixel on the substrate. A photoelectric conversion device characterized by being performed. 11. The photoelectric conversion device according to claim 10, wherein said well functioning as a back gate of a MOS-FET as said first initializing means forms at least a part of a source of said amplifying element. A photoelectric conversion device comprising: 12. The photoelectric conversion device according to claim 10, wherein said well functioning as a back gate of a MOS-FET as said first initialization means is also used as one conductivity type region of said photoelectric conversion element. A photoelectric conversion device, which is configured to function. 13. The photoelectric conversion device according to claim 9, wherein the back gate of the MOS-FET and the back gate of the amplifying element, which are the first initialization means, are electrically connected to the source of the amplifying element. A photoelectric conversion device, which is electrically connected. 14. The photoelectric conversion device according to claim 13, wherein the back gate of the amplifying element is formed by one well formed independently for each pixel on the substrate. Conversion device. 15. The photoelectric conversion device according to claim 14, wherein in one well independently formed for each pixel in the substrate, not only the MOS-FET as the first initializing means but also the amplification. A photoelectric conversion device, wherein a source or a drain of a MOS-FET as a first initialization means is shared with one conductivity type region of the photoelectric conversion device. . 16. any of claims 1 to 15 one
The photoelectric conversion device according to item 1 , wherein the common signal line is provided with an amplification unit that amplifies an output signal from the photoelectric conversion cell output to the common signal line, and the amplification unit includes the photoelectric conversion unit. A photoelectric conversion device characterized in that an output signal is output by performing a sample hold together with an impedance conversion on an output signal from a conversion cell. 17. A photoelectric conversion device comprising the photoelectric conversion device according to claim 16 as one block and a plurality of (m) blocks connected in parallel, wherein each block has a predetermined period. The photoelectric conversion device is configured to operate with a clock, and each block is selected with a phase shift of 1 / m from the predetermined period.