JP3142943B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device. In particular, it relates to a linear image sensor having a buffer circuit for each pixel.

[0002]

2. Description of the Related Art Conventional linear image sensors include:
CCD (Charge Coupled Device)
e) A linear image sensor or a contact image sensor using amorphous silicon has been put to practical use.

[0003] In the case of the above-mentioned CCD sensor, generally, CC
Since signals are read out using a D analog shift register, the manufacturing process is complicated and disadvantageously expensive. On the other hand, in the case of a contact type image sensor using amorphous silicon, the output is obtained in the form of a photocurrent, so that a suitable integrator needs to be provided externally and a sufficient S / N ratio cannot be obtained. was there.

As a conventional technique for solving the above-mentioned disadvantage, there is a linear image sensor having a buffer circuit for each pixel as disclosed in Japanese Patent Application Laid-Open No. Hei 2-131681. Less than,
A linear image sensor (hereinafter, abbreviated as an active sensor) having a buffer circuit for each pixel will be described with reference to FIGS. 8 to 10.

FIG. 8 shows the (i−1) -th photoelectric conversion cell among a plurality (for example, 436) of photoelectric conversion cells of a linear image sensor.
The i-th and i + 1-th are extracted and shown. The i-th photoelectric conversion cell includes a photosensitive pixel, a capacitor, and a selector.
Photosensitive pixel consists of a photodiode D _i to generate a signal charge corresponding to the amount of incident light in a predetermined time the node N. Capacitance means comprises a capacitor C _i for converting the amount of charge the photodiode D _i is generated in the voltage. The selection means receives a MOS transistor MR _{i having} a gate connected to the node R _i , a drain connected to the potential of 12 V, a source connected to the node N, and having a threshold value of, for example, −3 V, and receives the potential of the node N with a high input impedance and has a low level. buffer B _i to be output with an output impedance, the output of gate buffer B _i, the drain 12
MOS transistors MB _i , MO connected to the potential of V
Source of S transistor MB _i and common output line 101
Between the source and the drain and the gate is the node S
consisting of connected MOS transistor MA _i to _i. The constant current source 103 is connected to the common output line 101. The potential of the common output line 101 is output to the output node O through the output buffer 105.

Next, the operation of the circuit shown in FIG. 8 will be described with reference to FIG. A reset pulse φ _Ri applied to the node R _i and a selection pulse φ applied to the node S _i
Si has a waveform as shown in FIG.

[0007] voltage MOS transistor MR _i is the amount of incident light within a certain time went by sufficient time since the off appears at the node N. When the selection pulse phi _Si rises at time t _0, the buffer B _i is activated, the voltage of the node N is applied to the gate of the MOS transistor MB _i. Also, MOS transistor MA _i is to become turned on, the signal corresponding to the potential of the node N to be selectively transferred to the common output line 101. That is, the MOS transistor MB _i
Is determined in accordance with the voltage applied to the gate, that is, the potential of the node N, a voltage corresponding to the amount of incident light within a certain time is output to the output node O. The potential of the output node O is indicated by φ _O.

[0008] At time t ₁ rises reset pulse phi _Ri, MOS transistor MR _i is turned on because the threshold value is set to -3 V, 12V is applied to the node N. Therefore, voltage φ _{N at} node N rises in a step-like manner. In response, the potential φ _O of output node _O also rises in a step-like manner.

When the reset pulse φ _Ri falls at time t ₂ , the MOS transistor MR _i turns off even at a threshold of −3 V, and the potential φ _N of the node N slightly rises due to the parasitic capacitance between the source and the gate. It falls to a constant potential. In response, the potential φ _O of output node _O also falls to a certain constant potential.

When the selection pulse φ _Si falls at time t ₃ , the MOS transistor MA _i is turned off. Therefore, because the corresponding MOS transistors MA _i of all the cells are turned off, the potential phi _O of the output node O falls.

Here, the potential φ _O of the output node O from time t ₀ to time t _{1 and} the output node O from time t ₂ to time t ₃
Differential voltage 107 between the potential phi _O of a signal output i th photosensitive pixel has detected.

The manner in which the signal detected by the i-th photosensitive pixel is output has been described. As shown in FIG. 9, the selection pulses φ _Si−1 and φ input to the photoelectric conversion cells i−1 and i + 1
_{Since Si + 1} has no overlap, outputs from two or more cells are not simultaneously transmitted to the common output line 101,
By sequentially performing the above operation on each photoelectric conversion cell, a time-series signal output can be obtained.

FIG. 10 shows a part of a sectional view of a linear image sensor as described above. P-type semiconductor substrate 201
A photodiode 204 having an N-type semiconductor region 203 and a high-concentration P-type semiconductor region 205 on its surface, the N-type semiconductor region 203 and the high-concentration N-type semiconductor region 208 as source / drain regions, and a polysilicon electrode 209 as a gate. MOS transistor 206 is formed. Photodiode 204 corresponds to the D _i of FIG. 8], MOS
Transistor 206 is equivalent to the MOS transistor MR _i. Capacitor C _i is formed at the junction of the high-concentration N-type semiconductor region 207 and the P-type semiconductor substrate 201.

[0014] capacitor C _i is the dark current is generated without light is incident since it is formed by the PN junction including a high concentration of N-type semiconductor region 207, electric charges generated by this is converted into a voltage by the capacitor C _i The signal component is dark output. Therefore, the dark output of this portion is extremely large, and there is a disadvantage that the image quality is greatly impaired when the solid-state imaging device is used at low illuminance.

[0015]

As described above, the conventional active sensor has a drawback that the output in the dark is large and the image quality is greatly impaired when used at low illuminance. SUMMARY OF THE INVENTION It is an object of the present invention to provide an active sensor that eliminates the above-mentioned drawbacks and has a small output in darkness.

[0016]

[0017]

[MEANS FOR SOLVING THE PROBLEMS] To achieve the above object
In the present application, the solid-state imaging device includes a plurality of photoelectric conversion cells that output a voltage corresponding to the amount of incident light, and a selection unit that selects the plurality of photoelectric conversion cells and outputs an output of the selected photoelectric conversion cell to the outside. In the device, after inputting the (i-1) -th first and second control signals to the (i-1) -th photoelectric conversion cell, the i-th first and second control signals are supplied to the i-th photoelectric conversion cell.
A photosensitive pixel in which the i-th photoelectric conversion cell generates a signal charge corresponding to the amount of incident light; a capacitance means for converting the charge amount into a voltage;
Reset means for setting the potential of the capacitor means to a predetermined value in response to the first second control signal; and signal charge of the photosensitive pixel to the capacitor means in response to the i-th first control signal. And a transfer means for transferring the photosensitive pixel, wherein a predetermined potential is supplied to one end of the photosensitive pixel, and only the transfer means is connected to the other end .

Further, a solid-state imaging device comprising: a plurality of photoelectric conversion cells for outputting a voltage corresponding to the amount of incident light; and selecting means for selecting the plurality of photoelectric conversion cells and outputting the output of the selected photoelectric conversion cell to the outside. In the device, after inputting the (i-1) th control signal to the (i-1) th photoelectric conversion cell,
Signal generating means for inputting an i-th control signal to the i-th photoelectric conversion cell, wherein the i-th photoelectric conversion cell generates a signal charge corresponding to an incident light amount, and converts the charge amount into a voltage. Capacitance means for resetting the potential of the capacitance means to a predetermined value in response to the (i-1) th control signal; and transferring the signal charge of the photosensitive pixel to the capacitance means in response to the i-th control signal. And a transfer means for transferring the photosensitive pixel, wherein a predetermined potential is supplied to one end of the photosensitive pixel, and only the transfer means is connected to the other end. Further, when the transfer means is conducted,
All of the signal charges generated in the photosensitive pixels are transferred to the capacitance means.
Provided is a solid-state imaging device characterized by being transmitted. Ma
In addition, the transfer means is configured to control the i-th first control signal,
In response, the photosensitive pixel responds to the i-th control signal.
Transferring the generated signal charges to the capacitance means, and
The transfer means has one end of a current path connected to the photosensitive pixel.
The first MOS transistor and one end of the current path
Connected to the other end of the current path of the first MOS transistor
The other end is connected to the capacitance means, and a predetermined
Having a second MOS transistor supplied with a constant voltage of
A solid-state imaging device is provided.

[0019]

When the means provided by the present invention is used, each photoelectric conversion cell has a reset means, which discharges the electric charge accumulated in the capacity means in response to the first control signal and sets the potential to a predetermined value. Substantially all the charge generated by the dark current is discharged. After that, the signal charge of the photosensitive pixel is transferred to the capacitance means by the second control pulse, and the charge is converted into a voltage, whereby an output signal with a small output in the dark can be obtained.

When each of the photoelectric conversion cells is used by being connected to signal generating means such as a shift register, the signal generating means may be i
The (i-1) -th control signal input to the (-1) -th photoelectric conversion cell is used for resetting the i-th photoelectric conversion cell, and the i-th control signal is used for charge transfer. Accordingly, since the charge generated by the dark current is discharged, the signal charge of the photosensitive pixel is converted into a voltage by the capacitance means, so that an output signal with a small dark output can be obtained.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows the (i−1) -th, i-th, and i + 1-th cells of a plurality (for example, 436) of photoelectric conversion cells of the linear image sensor according to the first embodiment. The i-th photoelectric conversion cell includes photosensitive pixels, capacitance means, reset means, transfer means, and selection means. The photosensitive pixel includes a photodiode D' _i that generates a signal charge at a node M 'according to the amount of incident light within a predetermined time. The capacitance means includes a capacitor C ′ _i that converts the amount of charge at the node N ′ into a voltage. Reset means' the potential of the _i-1 to the drain 12V, the source node N 'gate node S threshold is connected to is -3 V MOS transistor MR' _i
Consists of Transfer means consists of MOS transistors MT _i whose gate is connected to the source and drain connected to a node R _'i between node M' and the node N '. The selecting means includes a buffer B ′ _i that receives the potential of the node N ′ at a high input impedance and outputs it at a low output impedance, a MOS transistor MB ′ _{i having} a gate connected to the output of the buffer B ′ _i and a drain connected to a potential of 12 V. , A MOS transistor MA ′ _i whose source and drain are connected between the source of the MOS transistor MB ′ _i and the common output line 201 and whose gate is connected to the node S ′ _i . A constant current source 203 is connected to the common output line 201. Further, the potential of the common output line 201 is output to the output node O ′ through the output buffer 205.

Next, the operation of the circuit shown in FIG. 1 will be described with reference to FIG. 'Transfer pulse is applied to the _{i φ R' R i, i} ' selection pulse phi _S is applied to _i' where S is the waveform as shown in FIG. 2.

At time t ₀ , selection pulse φ _{S 'i-1} rises and a voltage of 12 V is applied to node S' _i-1.
S transistor MR _'i is turned on because the threshold value is set to -3 V, the node N' 12V is applied. Thereby, the charge is discharged from the node N, so that the voltage φ _N 'of the node N' rises in a step-like manner.

When the selection pulse φ _{S 'i-1} falls at time t ₁ , the MOS transistor MR' _i is turned off even with the threshold voltage of -3 V, and the potential of the node N 'is caused by the parasitic capacitance between the source and the gate. φ _N 'falls slightly and settles at a constant potential.

When the selection pulse φ _{S 'i} rises at time t ₂ , the buffer B ′ _i operates, and the voltage of the node N ′ becomes MOS
It is applied to the gate of the transistor MB _'i. Also, M
The OS transistor MA ′ _i is turned on. Since MOS transistors MB 'source potential of _i is the applied voltage, that the node N to the gate' varies with voltage, a voltage corresponding to the source potential of _i is output 'MOS transistor MB is the' output node O.

The time t ₃ at the transfer pulse phi _{R 'i} rises the MOS transistor MT _i is turned on, the photodiode D' charge generated within a predetermined time by _i is transferred to the capacitor C _'i. Here, the MOS transistor MT
The potential φ _N ′ at the node N ′ slightly increases due to the parasitic capacitance between the source and the gate of _i .

When the transfer pulse φ _{R 'i} falls at time t ₄ , the transfer of the charge of the capacitor C ′ _i ends, and a voltage change corresponding to the transferred total charge is caused at the capacitor terminal. Therefore, the potential φ _N ′ of the node N ′,
Further, a signal corresponding to the amount of incident light within a certain time is output to the potential φ _O ′ of the output node O ′.

[0029] _'and falls _i, MOS transistor MA' at time t ₅ selection pulse φ _{S i} are all turned off, because the corresponding MOS transistor MA _i of all of the cell is turned off, the potential of the output node O 'φ _O 'falls.

Here, the difference voltage 307 between the potential φ _O ′ of the output node O ′ from time t ₂ to time t ₃ and the potential φ _O ′ of the output node O ′ from time t ₄ to time t ₅ is the i-th voltage. This is the signal output detected by the photosensitive pixel.

The manner in which the signal detected by the i-th photosensitive pixel is output has been described. As shown in FIG. 2, since the selection pulses φ _{S ′ i−1} and φ _{S ′ i + 1} input to the photoelectric conversion cells i−1 and _{i + 1} do not overlap, two pulses are simultaneously output to the common output line 301. By sequentially performing the above operation on each photoelectric conversion cell without transmitting the output from the above cells, a time-series signal output can be obtained.

FIG. 3 shows a part of a sectional view of the linear image sensor as described above. An N-type semiconductor region 403 and a high-concentration P-type semiconductor region 4 are formed on the surface of a P-type semiconductor substrate 401.
A photodiode 404 made of the N.sub.05 and a MOS transistor 406 using the N-type semiconductor region 403 and the high-concentration N-type semiconductor region 408 as source / drain regions and a polysilicon electrode 409 as a gate are formed. Further, a MOS transistor 415 is formed in which the high-concentration N-type semiconductor regions 408 and 411 are used as source / drain regions and the polysilicon electrode 413 is used as a gate. The photodiode 404 corresponds to D ′ _i in FIG.
Transistor 406 to the MOS transistor MT _i, M
The OS transistor 415 is connected to the MOS transistor MR ′ _i
Is equivalent to The capacitor C ′ _i is formed at a junction between the high-concentration N-type semiconductor region 408 and the P-type semiconductor substrate 401.

Since the capacitor C ′ _i is formed of a PN junction, a dark current is generated even if no light is incident, and the generated charge is converted into a voltage by the capacitor C ′ _i to generate a dark output. However, MOS transistors MR 'MOS transistor 406 corresponding to _i is the capacitor C' acts as a reset means for _i, the MOS transistor 406 is turned to release the electric charges generated in the capacitor C _'i, clearing the dark current output.

FIG. 4 shows a potential diagram when the MOS transistor 406 is turned on to transfer charges. When the MOS transistor 406 is turned on, the potential energy of the channel portion decreases, and the charge generated in the photodiode 404 is reduced to a high concentration N
It flows into the type semiconductor region 408. Here, the charge amount is converted into a voltage.

The first embodiment has been described above. Each photoelectric conversion cell has reset means, and the selection pulse φ
_In response to _{S ′ i−1} , the MOS transistor MR ′ _i is turned on, and the amount of charge stored in the capacitance means is set to a constant value. That is,
All charges generated by the dark current are discharged, and the dark current output is cleared. Then, MOS transistor MT _i is transferred signal charges of the on and photosensitive pixels in the capacitor means in response to the transfer pulse phi _{R 'i,} and converts the charge into a voltage. This makes it possible to obtain an output signal having a small output when dark. Further, since the selection pulse φ _{S ′ i−1} is used as a signal for controlling the reset means, a shift register similar to the conventional _one can be used, and the circuit is not complicated.

FIG. 4 shows the transfer of charges when the N-type diffusion region 403 of the photodiode D' _i is in a completely depleted state. At this time, the MOS transistor 40
When 6 is turned on, all the charges accumulated in the N-type diffusion region 403 are transferred to the high-concentration N-type diffusion region 408. Here, the effect of the first embodiment is not changed even when the N-type semiconductor region 403 is not in a completely depleted layer state, such as when the impurity concentration of the N-type semiconductor region 403 is high. At this time, the potential well in the N-type semiconductor region 403 in FIG. 4 becomes deeper than the potential of the channel in the ON state of the MOS transistor 406. Photodiode D 'capacity _i Cd, capacitor C' charge Q _t of the capacity of the _i and Cc charges generated in the photodiode D _'i is transferred to the Q _{is, Q t = QCc / (Cd} + Cc) , and the Only the values divided by volume are transferred. But,
The terminal voltage V of the capacitor C _'i is, V = Q / (Cd + Cc) next, no problem such as that a voltage amplitude if the value of Cc is smaller drops. Next, a second embodiment will be described with reference to FIGS.
This will be described with reference to FIG.

FIG. 5 shows an extracted i-th photoelectric conversion cell of the second embodiment. Besides MOS transistor MC _i a suitable DC voltage is applied to the gate between the MOS transistor MT _i and the node N 'is added is exactly the same as the first embodiment. Therefore, the same numbers and symbols are given and the description of the operation is omitted.

FIG. 6 shows a part of a sectional view of the second embodiment. An N-type semiconductor region 50 is formed on the surface of the P-type semiconductor substrate 501.
Transfer gates 507 and 511 are provided between the photodiode 504 including the P. 3 and the high-concentration P-type semiconductor region 505, the high-concentration N-type diffusion layer 509, and the N-type semiconductor region 504. In addition, an N-type semiconductor region 508 is implanted below the gate 507 to give directionality during transfer, and ions are implanted into a channel portion of the gate 511 to adjust the threshold voltage of the gate 511. Further, a MOS transistor 516 is formed in which the high-concentration N-type semiconductor regions 509 and 515 are used as source / drain regions and the polysilicon electrode 517 is used as a gate. The photodiode 504 corresponds to D ′ _i in FIG.
Transistor 506 to the MOS transistor MT _i, M
OS transistor 513 is MOS transistor MC
to _i, MOS transistor 516 is equivalent to the MOS transistor MR _'i. The capacitor C ′ _i is formed at the junction between the high-concentration N-type semiconductor region 509 and the P-type semiconductor substrate 501.

Since the capacitor C ′ _i is formed of a PN junction, a dark current is generated even when light is not incident, and the generated charge is converted into a voltage by the capacitor C ′ _i to generate a dark output. However, MOS transistors MR 'MOS transistor 516 corresponding to _i is the capacitor C' acts as a reset means for _i, the MOS transistor 516 is turned to release the electric charges generated in the capacitor C _'i, clearing the dark current output.

FIG. 7 shows a potential diagram when the MOS transistor 506 is turned on to transfer charges. When the MOS transistor 506 is turned on, the potential energy of the channel portion decreases, and the charge generated by the photodiode 504 flows into the N-type semiconductor region 508 where the potential is the minimum. Next, when the MOS transistor 506 is turned off, the potential of the N-type semiconductor region 508 increases, and the charge once flows into the high-concentration N-type semiconductor region 509 having the lowest potential. Here, the charge amount is converted into a voltage.

Although the second embodiment has been described above, this prevents the gate voltage of the MOS transistor 506, ie, the transfer signal φ _R ′ _i , from flowing into the high-concentration N-type semiconductor region 509. In the first embodiment, as shown in FIG. 3, there is a parasitic capacitive coupling 420 between the polysilicon electrode 409 and the high-concentration N-type semiconductor region 408, and the former potential change affects the latter. In particular, the high-concentration N-type semiconductor region 408 forms a capacitor C ′ _i with the substrate 401 and affects the output signal because it is in a floating state. However, such a problem does not occur when the charge transfer means used in the second embodiment is used. That is, in FIG. 5, the transfer signal φ _R ′ _i does not affect the potential of the node N ′.

Although the first and second embodiments have been described above, the power supply voltage and the threshold value of the reset transistor are 1
It is not necessary to limit to 2V and -3V, and it may be changed according to the use condition. In addition, a photodiode or M
An OS transistor and the like are integrated, but a P-well is selectively formed on an N-type semiconductor substrate, and an N-channel MOS
A transistor or the like may be formed. Further, a P-channel MOS transistor or the like may be integrated on an N-type semiconductor substrate, and a solid-state imaging device in which PN is inverted in the above circuit configuration may be configured.

[0043] In the first and second embodiments, with _i 'MOS transistor MR to reset the _i' capacitor C, and is used to select pulse phi _{S 'i-1} to the control signal, the selection pulse The same effect can be obtained by using φ _{R ′ i−1} . This is because it suffices _i is reset 'capacitor C before the charge of the photodiode is transferred to the _i' capacitor C.

[0044]

According to the present invention, it is possible to construct an active sensor having a small output in the dark.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing a first embodiment of the present invention.

FIG. 3 is a sectional view showing a first embodiment of the present invention.

FIG. 4 is a sectional view showing a first embodiment of the present invention.

FIG. 5 is a sectional view showing a second embodiment of the present invention.

FIG. 6 is a sectional view showing a second embodiment of the present invention.

FIG. 7 is a sectional view showing a second embodiment of the present invention.

FIG. 8 is a sectional view showing a conventional example.

FIG. 9 is a sectional view showing a conventional example.

FIG. 10 is a sectional view showing a conventional example.

[Explanation of symbols]

101, 301 Common output line 103, 303 Current source 105, 305 Output buffer 201, 401, 501 P-type semiconductor substrate 203, 403, 503, 508 N-type semiconductor region 205, 405, 505 High-concentration P-type semiconductor region 204, 404 , 504 Photodiodes 206, 406, 415, 516 MOS transistors 208, 408, 411, 509, 515 High concentration N
Type semiconductor region 209, 409, 413, 517 polysilicon electrode 507, 511 gate 420 parasitic capacitance

Claims (5)

(57) [Claims] 1. A solid-state imaging device comprising: a plurality of photoelectric conversion cells for outputting a voltage corresponding to the amount of incident light; and selecting means for selecting the plurality of photoelectric conversion cells and outputting an output of the selected photoelectric conversion cell to the outside. In the apparatus, after inputting the (i-1) th first and second control signals to the (i-1) th photoelectric conversion cell, the (i) th first and second control signals are supplied to the (i) th photoelectric conversion cell. The i-th photoelectric conversion cell generates a signal charge corresponding to the amount of incident light; a capacitance means for converting the charge amount into a voltage; and an (i-1) -th second photoelectric conversion cell. Resetting means for setting the potential of the capacitance means to a predetermined value in response to the control signal, and transfer means for transferring the signal charge of the photosensitive pixel to the capacitance means in response to the i-th first control signal. A predetermined potential is supplied to one end of the photosensitive pixel. A solid-state imaging device, wherein only the transfer means is connected to the other end. 2. A solid-state imaging device comprising: a plurality of photoelectric conversion cells for outputting a voltage corresponding to the amount of incident light; and a selection unit for selecting the plurality of photoelectric conversion cells and outputting the output of the selected photoelectric conversion cell to the outside. The apparatus further comprises: signal generation means for inputting an (i−1) th control signal to the (i−1) th photoelectric conversion cell and then inputting an (i) th control signal to the (i) th photoelectric conversion cell. A photosensitive pixel in which the photoelectric conversion cell generates a signal charge corresponding to the amount of incident light, a capacitance means for converting the charge amount into a voltage, and a potential of the capacitance means in response to an (i-1) th control signal. Reset means, and transfer means for transferring the signal charge of the photosensitive pixel to the capacitance means in response to the i-th control signal, wherein a predetermined potential is supplied to one end of the photosensitive pixel, and the other end. Only the transfer means is connected to A solid-state imaging device. Wherein when said transfer means is conductive, the solid-state imaging device according to claim 1 or 2 wherein all of the signal charges generated in the photosensitive pixels, characterized in that it is transferred to the capacitive means . 4. The i-th first control means comprises:
Signal charge generated in the photosensitive pixel in response to the
The first MOS transistor having one end of a current path connected to the photosensitive pixel, and one end of a current path connected to the other end of the current path of the first MOS transistor. is connected to the other end thereof is connected to the capacitive means, a predetermined constant voltage to the gate electrode is characterized in that it has a second MOS transistor which is supplied claims
2. The solid-state imaging device according to 1 . 5. The control unit according to claim 5, wherein the transfer unit is configured to control the i-th control signal.
The signal charge generated in the photosensitive pixel in response to
Transfer means, and said transfer means is connected to one end of a current path.
Is a third MOS transistor connected to the photosensitive pixel
And one end of the current path is connected to the third MOS transistor.
The other end of the current path is connected, and the other end is connected to the capacitance means.
And the fourth M having a predetermined constant voltage supplied to the gate electrode.
3. The semiconductor device according to claim 2, further comprising an OS transistor.
Solid-state imaging device.