JP2005183978A - Signal charge converter for charge transfer element, output circuit, and imaging system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal charge converter for a charge transfer element. <P>SOLUTION: The signal converter includes a first driver FET of a first stage that receives a signal charge and converts the signal charge to a voltage. Subsequent driver FETs are connected to an output of the first driver FET, and gate insulating films of subsequent drivers include reduced thicknesses. The subsequent driver FETs constitute a second stage or a third stage. The reduced thicknesses of the gate insulating films of the subsequent driver FETs increase a voltage gain AV<SB>total</SB>without decreasing charge transfer efficiency, and raises the entire sensitivity of the signal converter. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a charge transfer device such as a CCD (Charge Coupled Device) in an imaging system, and more particularly to a signal charge converter that converts signal charge from the charge transfer device into a voltage with high sensitivity.

  FIG. 1 illustrates an imaging system 100 that includes a photodiode array, such as photodiode 102.

  Referring to FIG. 1, each photodiode accumulates a signal charge indicating the illuminance at the pixel position of the photodiode. A vertical embedded charge coupled device (hereinafter referred to as a BCCD) is disposed along each column of photodiodes. For example, the first vertical BCCD is arranged in the first column, and the second vertical CCD (second CCD) is arranged in the second column. The second vertical type BCCD is arranged in the column, and the last vertical type BCCD is arranged in the last column.

Each vertical BCCD transmits the signal charge from the photodiode row to the horizontal BCCD 110. The horizontal type BCCD 110 transmits the signal charge from the vertical type BCCD to the output circuit 112 indicated by a dotted line in FIG. The output circuit 112 changes the signal charge from the horizontal type BCCD 110 to the voltage _Vout .

An output MOS field effect transistor (hereinafter referred to as a MOSFET) 114 is connected between the horizontal BCCD 110 and the charge storage region 116 in the output circuit 112. In addition, a reset MOSFET 118 is connected between the reset voltage V _reset source and the charge storage region 116. The charge storage region 116 is typically a heavily doped junction that stores signal charge from the horizontal BCCD 110. A bias is applied to the output MOSFET 114 to transmit the signal charge from the last stage of the horizontal type BCCD to the charge load 120 of the charge storage region 116.

The reset MOSFET 118 is turned on to reset the charge load 120 in the charge storage region 116 to the reset voltage V _reset . The reset control signal RESET is applied to the gate of the reset MOSFET 118. In general, the reset MOSFET 118 maintains a turn-off state when the signal charge from the horizontal type BCCD 110 is accumulated by the charge accumulation region 116.

The signal converter 122 is connected to the charge storage region 116 and converts the signal charge stored in the charge storage region 116 into a corresponding voltage _Vout . Such a voltage _Vout level indicates the amount of signal charge stored in the charge storage region 116, and thus indicates the intensity of illuminance corresponding to such signal charge.

  FIG. 2 is a diagram illustrating an example of the signal converter 122 indicated by a dotted line in the related art. 2, elements having the same reference numerals as those in FIG. 1 have the same structure and function.

  Referring to FIG. 2, the signal converter 122 includes a first driver MOSFET 132 and a first load MOSFET 134 that constitute a first source follower stage 133. In addition, a second driver MOSFET 136 and a second load MOSFET 138 constituting the second source follower stage 139 are included. Further, a third driver MOSFET 140 and a third load MOSFET 142 constituting the third source follower stage 143 are included.

  Within each source follower stage, the source of the respective driver MOSFET is coupled to the drain of the respective load MOSFET. The drains of the driver MOSFETs 132, 136, 140 are connected to a high bias voltage VDD, and the sources of the load MOSFETs 134, 138, 142 are connected to a low bias voltage GND. The gates of the load MOSFETs 134, 138, and 142 are connected to a gate bias voltage indicated by GND in the example of FIG.

  The gate of the first driver MOSFET 132 is connected to the charge storage region 116. The gate of the next driver MOSFET is coupled to the source of the previous driver MOSFET. Accordingly, the gate of the second driver MOSFET 136 is connected to the source of the first driver MOSFET 132, and the gate of the third driver MOSFET 140 is connected to the source of the second driver MOSFET 132. The gate of each driver MOSFET and the source of the driver MOSFET are the input and output of the corresponding source follower stage, respectively.

The first driver MOSFET 132 is implemented as an enhancement type MOSFET, while the other MOSFETs 134, 136, 138, 140, and 142 are implemented as depletion type MOSFETs. Typically, the enhancement-type MOSFET, the gate - to be conductive is not generated when the voltage _{V GS} between the source is 0V, depletion type MOSFET, gate - when the voltage _{V GS} between the source is 0V A conductive channel is provided between the source and the drain.

The sensitivity _Sv of the signal converter 122 is a property indicating the quality of the signal converter 122. The sensitivity Sv of the signal converter 122 is expressed by the following formula 1.

[Equation 1]
S _v = CE × AV _total

In Equation 1, CE represents the charge transfer efficiency, and AV _total represents the overall voltage gain through the three source follower stages 133, 139 and 142 of the signal converter 122. This AV _total is expressed by Equation 2 below.

[Equation 2]
AV _total = AV _1st × AV _2nd × AV _3rd

In Equation 2, AV _1st represents the voltage gain of the first source follower stage 133, AV _2nd represents the voltage gain of the second source follower stage 139, and AV _3rd represents the voltage gain of the third source follower stage 143. . The voltage gain AV of each source follower stage is expressed by Equation 3 below.

[Equation 3]
_{AV = g m / (g m} + g ds + g mb)

In Equation 3, g _m represents transconductance, g _ds represents conductance through the channel, and g _mb represents back gate transconductance for the driver MOSFET of the source follower stage. The transconductance _{g m} for the driver MOSFET is shown in Equation 4 below.

[Equation 4]
g _m = [2 μ _OX C _OX (W / L) _ID ] ^1/2

In Equation 4, μ _OX represents charge mobility, C _OX represents gate capacitance, W represents gate width, L represents gate length, and _ID represents drain current. In addition, the charge transfer efficiency CE is expressed by Equation 5 below.

[Equation 5]
CE = q / C _S [C _FD + C _GS + C _GD + C _G ]

In Equation 5, q denotes the electron charge, C _S denotes the total capacitance at the storage node 120 of the charge accumulation region 116.

  FIG. 3 is a layout diagram of the output MOSFET 114, the charge storage region 116, the reset MOSFET 118, and the first driver MOSFET 132.

Referring to FIG. 3, each component is connected to the storage load 120 of the charge storage region 116. Output MOSFET 114 includes a gate 152 disposed between drain 154 and source 156. Reset MOSFET 118 includes a gate 158 disposed between drain 160 and source 154. In addition, the first driver MOSFET 132 includes a gate 162 disposed between the drain 164 and the source 166. Accordingly, the total capacitance C _S at storage load 120 is between capacitance C _FD of floating diffusion junction 116 and between gate 158 and source 154 of reset MOSFET 118, ie, in the overlap region 172 shown in dotted lines in FIG. The overlap capacitance C _GS , the overlap capacitance C _GD between the gate 152 and the drain 154 of the output MOSFET 114, that is, in the overlap region 174 shown by the dotted line in FIG. 3, and the gate capacitance C of the first driver MOSFET 132 _G.

FIG. 4 is a diagram showing an embodiment 122A of a signal converter disclosed in Patent Document 1. In FIG.
US Pat. No. 5,432,364

  Referring to FIG. 4, the signal converter 122A uses three driver MOSFETs 132, 136, 140 for three source follower stages and three corresponding load MOSFETs 134, 138, 142. The drain of the first driver MOSFET 132 is connected to the power supply VDD via the resistor 182, and the source of the second load MOSFET 138 is connected to the ground GND via the resistor 184. Gate bias voltage source 188 and gate bias capacitor 190 are coupled to the gates of load MOSFETs 134, 138, 142.

  The operation of the signal converter 122A in FIG. 4 is similar to the operation of the signal converter 122 in FIG. However, as shown in FIGS. 4 and 5, the gate insulating film 192 of the first driver MOSFET 132 is thinner than the gate insulating film 194 of the second driver MOSFET 136.

  FIG. 5 is a cross-sectional view of the first and second driver MOSFETs 132 and 136 disclosed in the patent document.

  Referring to FIG. 5, the first and second driver MOSFETs 132 and 136 are formed in the P well 196. The first driver MOSFET 132 includes a gate 132A, a drain 132B, and a source 132C, and the second driver MOSFET 136 includes a gate 136A, a drain 136B, and a source 136C. The wiring structure 198 connects the source 132C of the first driver MOSFET 132 and the gate 136A of the third driver MOSFET 136.

Referring to FIGS. 4 and 5 together, the thickness of the gate insulating film 192 of the first driver MOSFET 132 is thinner than that of other MOSFETs in the signal converter 122A, such as the second driver MOSFET 136, thereby reducing the 1 / f Noise is reduced. Besides, as the transconductance _{g m} of the first driver MOSFET132 increases, so does the voltage gain _{AV 1st} of the first source follower stage.

  However, the reduced thickness of the gate insulating film 192 increases the gate capacitance CG of the first driver MOSFET 132, thus reducing the charge transfer efficiency. As a result, the overall sensitivity of the signal converter 122A according to the prior art does not necessarily increase, and it may be further deteriorated simply by reducing the thickness of the gate insulating film 192 of the first driver MOSFET 132.

  Nevertheless, increasing the overall sensitivity of the signal converter makes the imaging system even higher quality. Therefore, the signal converter is required to have an increased overall sensitivity in order to improve the quality of the imaging system.

  The technical problem to be achieved by the present invention is to increase the overall sensitivity of the signal converter by reducing the thickness of the gate insulating film of at least one driver FET subsequent to the first driver FET.

  In order to achieve the above technical problem, a signal converter according to an embodiment of the present invention is a signal converter that converts a signal charge into a voltage, and includes a first driver FET that receives the signal charge, and a first driver FET that receives the signal charge. A subsequent driver FET coupled to the first driver FET having a gate insulation thickness that is coupled to an output but having a thickness less than a gate insulation thickness of at least one other FET of the signal converter; It is characterized by providing.

  Preferably, the first driver FET is disposed in a first stage, and the subsequent driver FET is disposed in a second stage next to the first stage.

  In that case, the thickness of the gate insulating film of the subsequent driver FET may be smaller than the thickness of the gate insulating film of the first driver FET. The thickness of the gate insulating film of the subsequent driver FET may be the same as the thickness of the gate insulating film of the first driver FET. The gate insulating film of the subsequent driver FET may be thicker than the gate insulating film of the first driver FET.

  Preferably, the first driver FET is disposed on a first stage, and the subsequent driver FET is disposed on a third stage connected to the first stage via a second stage having a second driver FET.

  In that case, the thickness of the gate insulating film of the subsequent driver FET may be smaller than the thickness of the gate insulating film of the first driver FET. The thickness of the gate insulating film of the subsequent driver FET may be the same as the thickness of the gate insulating film of the first driver FET. The gate insulating film of the subsequent driver FET may be thicker than the gate insulating film of the first driver FET. The gate insulating film of the subsequent driver FET may be thinner than the same gate insulating film of the first and second driver FETs.

  In this embodiment, a final driver FET connected to the subsequent driver FET to generate an output voltage may be further included.

  In that case, the thickness of the gate insulating film of the subsequent driver FET may be smaller than the thickness of the gate insulating film of the final driver FET. The thickness of the gate insulating film of the subsequent driver FET may be the same as the thickness of the gate insulating film of the final driver FET. The gate insulating film of the final driver FET may be thinner than the gate insulating film of the subsequent driver FET. The gate insulating film of the subsequent driver FET may be thinner than the same gate insulating film of the first and final driver FETs. The respective driver FETs can be connected to respective load FETs. At this time, each of the driver FETs may have the same gate insulating film thickness that is thinner than the thickness of at least one of the load FETs.

  The respective driver FETs can be coupled to respective load FETs.

  In that case, the thickness of the gate insulating film of the subsequent driver FET may be smaller than the thickness of at least one gate insulating film of the load FET. The thickness of the gate insulating film of the subsequent driver FET may be smaller than the thickness of the respective gate insulating film of every load FET. Each load FET can be coupled to ground through a respective resistor. Each load FET can be coupled together to ground through the same resistor.

  The thickness of the gate insulating film of the subsequent driver FET may be thinner than the thickness of the respective gate insulating film of every other FET of the signal converter.

  Preferably, the first driver FET is an enhancement type MOSFET, and every other FET of the signal converter is a depletion type MOSFET.

  Each of the driver FETs can be composed of a source follower.

  The first driver FET may be formed in an isolated well.

  The signal charge can be output from a charge coupled device.

  In order to achieve the above technical problem, a signal converter according to another embodiment of the present invention includes a driver FET and a load FET in a signal converter for converting a signal charge into a voltage, and the signal charge from the first stage. And each subsequent stage comprises a plurality of stages configured to receive a voltage from the previous stage, and voltage gain increasing means for increasing the voltage gain without decreasing the charge transfer efficiency of the signal converter. It is characterized by.

  Each of the driver FETs preferably constitutes a source follower.

  The source of each stage load FET may be coupled to ground through a respective resistor.

  The source of each stage load FET may be coupled to ground through the same resistor.

  The first stage driver FET may be formed in an isolated well.

  The first stage driver FET is sized to minimize gate capacitance, and the final stage driver FET is sized to provide sufficient current to drive a load coupled to the output of the final stage. The intermediate stage driver FET preferably has a magnitude for amplifying a current between the first stage and final stage driver FETs.

  In order to achieve the technical problem, an output circuit of a signal transmission element according to the present invention includes a signal accumulation region for accumulating charge from the signal transmission element to generate a signal charge, and a first receiving the signal charge. A driver FET and a subsequent driver FET coupled to the output of the first driver FET and having a gate insulating film thickness less than a gate insulating film thickness of at least one other FET of the signal converter; A signal converter that converts the signal charge into a voltage; a reset FET that is turned on to reset the signal storage region to a reset voltage; and a turn-on that transmits charge from the charge transfer element to the signal storage region. And an output FET.

  The first driver FET may constitute a first stage, and the subsequent driver FET may constitute a second stage subsequent to the first stage.

  The first driver FET may constitute a first stage, and the subsequent driver FET may constitute a third stage connected to the first stage via a second stage.

  The present invention may further include a final driver FET connected to the output of the subsequent driver FET to generate an output voltage.

  In that case, the respective driver FETs may be coupled to respective load FETs. In this case, each of the driver FETs may have the same gate insulating film thickness that is thinner than the thickness of at least one gate insulating film of the load FET.

  Each of the driver FETs can constitute a source follower.

  The respective driver FETs can be coupled to respective load FETs. In that case, the thickness of the gate insulating film of the subsequent driver FET may be smaller than the thickness of at least one gate insulating film of the load FET. Each load FET can be coupled to ground through a respective resistor. Each load FET can be coupled together to ground through the same resistor.

  Preferably, the first driver FET is an enhancement type MOSFET, and every other FET of the signal converter is a depletion type MOSFET.

  The first driver FET may be formed in an isolated well.

  The charge transfer element may be a charge coupled element.

  In order to achieve the above technical problem, an imaging system according to the present invention includes a photodiode array that includes respective photodiodes that accumulate respective signal charges, and is connected to the photodiode array, and is connected to each photodiode. At least one signal transfer element that shifts each signal charge, a signal storage region that stores each signal charge shifted from the charge transfer element, and a first driver FET that receives each signal charge, And a subsequent driver FET coupled to the output of the first driver FET and having a gate insulating film thickness that is less than a gate insulating film thickness of at least one other FET of the signal converter. Each signal charge accumulated in the area is converted to voltage While it includes a signal converter, characterized in that it comprises an output circuit coupled to at least one of the signal transmission element.

  The first driver FET may constitute a first stage, and the subsequent driver FET may constitute a second stage subsequent to the first stage.

  The first driver FET may constitute a third stage connected to the first stage through a second stage.

  The signal converter may further comprise a final driver FET coupled to the output of the subsequent driver FET to generate an output voltage.

  In that case, the respective driver FETs may be coupled to respective load FETs. At this time, each of the driver FETs may have the same gate insulating film thickness that is thinner than the thickness of at least one gate insulating film of the load FET.

  Each driver FET is. Each load FET can be connected.

  In that case, the thickness of the gate insulating film of the subsequent driver FET may be smaller than the thickness of at least one gate insulating film of the load FET. Each load FET can be coupled to ground through a resistor. And each load FET may be connected together to the ground through the same resistor.

  Each of the driver FETs can constitute a source follower.

  Preferably, the first driver FET is an enhancement type MOSFET, and every other FET of the signal converter is a depletion type MOSFET.

  The first driver FET may be formed in an isolated well.

  The charge transfer element may be a charge coupled element.

  The output circuit includes a reset FET that is turned on to reset the charge storage region to a reset voltage, and a reset FET that is turned on to transmit each signal charge from the charge transfer element to the charge storage region. And an output FET that turns the FET off.

  According to the signal charge converter for the charge transfer device according to the present invention, the thickness of the gate insulating film of at least one driver FET subsequent to the first driver FET is decreased to increase the overall sensitivity of the signal converter. The signal converter which can be made to provide can be provided.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments of the present invention can be modified in various forms, and the scope of the present invention is not limited to the embodiments described in detail below.

Referring to FIG. 6, the signal converter 202 increases the sensitivity while converting the signal charge accumulated in the charge accumulation region 204 into a voltage _Vout . In one embodiment of the present invention, the charge storage region 116 of FIG. 6 is formed of a heavily doped junction similar to the charge storage region 116 of FIGS. In addition, the present invention may be implemented with other forms of charge storage regions.

  The signal converter 202 includes a first source follower stage 206, a second source follower stage 208, and a third source follower stage 210. The first source follower stage 206 includes a first driver MOSFET 212 and a first load MOSFET 214. The second source follower stage 208 includes a second driver MOSFET 216 and a second load MOSFET 218. The third source follower stage 210 includes a third driver MOSFET 220 and a third load MOSFET 222.

  The first driver MOSFET 212 has a drain connected to the high bias voltage VDD, a source connected to the drain of the first load MOSFET 214, and a gate connected to the charge storage region 204. The first load MOSFET 214 has a gate connected to the gate bias voltage VGG and a source connected to the ground via the first load resistor R1.

  Similarly, the second driver MOSFET 216 has a drain connected to the high bias voltage VDD and a source connected to the drain of the second load MOSFET 218. The gate of the second driver MOSFET 220 is connected to the output of the first source follower stage 206, that is, the source of the first driver MOSFET 212. The second load MOSFET 218 has a gate connected to the gate bias voltage VGG and a source connected to ground through the second load resistor R2.

The third driver MOSFET 220 has a drain connected to the high bias voltage VDD and a source connected to the drain of the third load MOSFET 222. The gate of the third driver MOSFET 220 is connected to the output of the second source follower stage 206, that is, the source of the second driver MOSFET 216. The third load MOSFET 222 has a gate connected to the gate bias voltage VGG and a source connected to the ground via the third load resistor R3. The output of the third source follower stage 210 provides an output voltage _Vout .

The reason why the three source follower stages 206, 208, and 210 are used is that the third driver MOSFET 220 of the final stage 210 is large enough to drive a load capacitor 224 having a sufficient speed. For example, although usually load capacitance _{C L} is about 10 pF, the width of the third driver MOSFET220 for driving such load capacitance at a sufficient rate is about 1,000 .mu.m.

  On the other hand, the size of the first driver MOSFET 212 of the first stage 206 and the resulting gate capacitance are required to be minimized so that the charge transfer efficiency of the signal converter 202 can be maximized. The second driver MOSFET 216 smoothly transitions between the first driver MOSFET 212 and the third driver MOSFET 220 by providing current amplification from the first driver MOSFET 212 to the third driver MOSFET 220.

The first driver MOSFET 212 is implemented as an enhancement type MOSFET, while the other MOSFETs 214, 216, 218, 220, and 222 are each implemented as a depletion type MOSFET. As usual, the enhancement-type MOSFET, the gate - when the voltage _{V GS} between the source is 0V, - to the conductive does not occur when the voltage _{V GS} between the source is 0V, depletion type MOSFET gate A conductive channel is provided between the source and the drain.

  7 is a cross-sectional view of the MOSFETs 212, 214, 216, 218, 220, 222 of the signal converter 202 of FIG. The MOSFETs 212, 214, 216, 218, 220, and 222 are, for example, N-channel MOSFETs formed in the P well 230 of the semiconductor substrate 232 of a silicon wafer.

  The first driver MOSFET 212 includes a gate 212A, a gate insulating film 212B, a drain 212C, and a source 212D. The first load MOSFET 214 includes a gate 214A, a gate insulating film 214B, a drain 214C, a source 214D, and a conductive channel 214E ion-implanted as a depletion type MOSFET. The wiring structure 234 connects the source 212D of the first driver MOSFET 212 and the drain 214C of the first load MOSFET 214.

  Similarly, the second driver MOSFET 216 includes a gate 216A, a gate insulating film 216B, a drain 216C, a source 216D, and a conductive channel 216E ion-implanted as a depletion type MOSFET. The second load MOSFET 218 includes a gate 218A, a gate insulating film 218B, a drain 218C, a source 218D, and a conductive channel 218E ion-implanted as a depletion type MOSFET. The wiring structure 236 connects the source 216D of the second driver MOSFET 216 and the drain 218C of the second load MOSFET 218.

  The third driver MOSFET 220 includes a gate 220A, a gate insulating film 220B, a drain 220C, a source 220D, and a conductive channel 220E ion-implanted as a depletion type MOSFET. The third load MOSFET 222 includes a gate 222A, a gate insulating film 222B, a drain 222C, a source 222D, and a conductive channel 222E ion-implanted as a depletion type MOSFET. The wiring structure 238 connects the source 220D of the third driver MOSFET 220 and the drain 222C of the third load MOSFET 222.

  The thickness of the gate insulating film 216B of the second driver MOSFET 216 is thinner than the thickness of each gate insulating film of the other MOSFETs 212, 214, 218, 220, 222. As described with reference to the signal converter 122 of FIG. 2, the sensitivity of the signal converter 202 is expressed by the following Equation 6.

[Equation 6]
S _v = CE × AV _total

In Equation (6), CE represents the charge transfer efficiency, and AV _total represents the overall voltage gain through the three source follower stages 206, 208, and 210. This AV _total is _expressed by Equation 7 below.

[Equation 7]
AV _total = AV _1st × AV _2nd × AV _3rd

In Equation 7, AV _1st represents the voltage gain of the first source follower stage 206, AV _2nd represents the voltage gain of the second source follower stage 208, and AV _3rd represents the voltage gain of the third source follower stage 210. . The voltage gain AV of each source follower stage is expressed by Equation 8 below.

[Equation 8]
_{AV = g m / (g m} + g ds + g mb)

In Equation 8, g _m represents transconductance, g _ds represents channel conductance, and g _mb represents a back gate for the driver MOSFET of the source follower stage. The transconductance g _m for the driver MOSFET is expressed by Equation 9 below.

[Equation 9]
g _m = [2 μ _OX C _OX (W / L) _ID ] ^1/2

In Equation 9, μ _OX represents the charge mobility of the driver MOSFET, C _OX represents the gate capacitance, W represents the gate width, L represents the gate length, and _ID represents the drain current.

  Still referring to FIGS. 6 and 19, the signal converter 202 is part of the output circuit 302 used in the imaging system 300. Referring to FIGS. 1 and 19, the photodiode array 102 and the charge coupled device CCD (104, 106, 108, 11 in FIG. 19) operate in the same manner as described with reference to FIG. In addition, the output MOSFET 114 and the reset MOSFET 118 of the output circuit 302 in FIG. 19 operate in the same manner as described with reference to FIG.

  The charge transfer efficiency CE of the signal converter 202 is expressed by Equation 10 below.

[Equation 10]
CE = q / C _S [C _FD + C _GS + C _GD + C _G ]

In Equation 10, q represents an electron charge, as shown in FIGS. 6 and 19, C _S denotes the total capacitance at the storage node 205 of the charge accumulation region 204. Similar to that described with reference to FIGS. 1 and 4, the overall capacitance Cs of the storage load (FIGS. 6 and 19) is the capacitance C _FD of the floating diffusion junction 204, the gate 158 and the source 154 of the reset MOSFET 118. including overlap capacitance _{C GS} between the overlap capacitance _{C GD} between the gate 152 and drain 154 of the output MOSFET 114, also a gate capacitance _{C G} of the first driver MOSFET 212.

In the present embodiment, the thickness of the gate insulating film 216B of the second driver MOSFET 216 decreases so as to increase the voltage gain AV _2nd of the second source follower stage 208. Therefore, the overall voltage gain AV _total of the signal converter 202 increases. However, the decrease in the thickness of the gate insulating film of the second driver MOSFET 216 does not affect the charge transfer efficiency CE of the signal converter 202. As a result, the overall sensitivity (S _V = AV _total × CE) of the signal converter 202 increases from the prior art as in the embodiment of FIG.

  Referring to FIG. 8, which is another embodiment of the present invention, the thickness of the gate insulating film 212B of the first driver MOSFET 212 is reduced in the same manner as the thickness of the gate insulating film 216B of the second driver MOSFET 216. Accordingly, the thicknesses of the gate insulating films of the first and second driver MOSFETs 212 and 216 are substantially the same as the thicknesses of the gate insulating films of the other MOSFETs 214, 218, 220 and 222, or even more. thin.

In such a case, the voltage gains AV _1st and AV _2nd of the first and second stages 206 and 208 are respectively increased, and the overall voltage gain AV _total of the signal converter 202 is sequentially increased. As the thickness of the gate insulating film 212B of the first driver MOSFET 212 increases, the charge transfer efficiency CE of the signal converter 202 also decreases. However, the increase in the overall voltage gain AV _total is due to the fact that the overall sensitivity (S _V = AV _total × CE) of the signal converter 202 is still increased from the prior art as in the embodiment of FIG. 8, and the charge transfer efficiency CE is reduced. Exceeds offset amount.

  Referring to FIG. 9, which is still another embodiment of the present invention, the thickness of the gate insulating film 212 </ b> B of the first driver MOSFET 212 is further thinner than the thickness of the gate insulating film 216 </ b> B of the second driver MOSFET 216. Therefore, the gate insulating films of the first and second driver MOSFETs 212 and 216 are thinner than the gate insulating films of the other MOSFETs 214, 218, 220, and 220. In addition, the thickness of the gate insulating film 212B of the first driver MOSFET 212 is further reduced than the thickness of the gate insulating film of the second driver MOSFET 216.

In such a case, the voltage gain of the first stage 206 of FIG. 9 is further increased compared to the embodiment of FIG. Accordingly, the overall voltage gain AV _total of the signal converter 202 of FIG. 9 is further increased from the embodiment of FIG. However, as the thickness of the gate insulating film 212B of the first driver MOSFET 212 is further reduced, the charge transfer efficiency CE of the signal converter 202 is further reduced as compared with the embodiment of FIG. Nevertheless, a further increase in the overall voltage gain AV _total is that the overall sensitivity of the signal converter 202 (S _V = AV _total × CE) is still increased from the prior art as in the embodiment of FIG. Exceeds offset as a reduction in efficiency CE.

Referring to FIG. 10, which is still another embodiment of the present invention, the thickness of the gate insulating film 220B of the third driver MOSFET 220 is the thickness of the gate insulating film of each of the other MOSFETs 212, 214, 216, 218, 222. It decreases to become even thinner. In such a case, the voltage gain AV _3rd of the third stage 210 is increased, and the overall voltage gain AV _total of the signal converter 202 is sequentially increased.

However, reducing the thickness of the gate insulating film of the third driver MOSFET 220 has no effect on the charge transfer efficiency CE of the signal converter 202. As a result, the overall sensitivity (S _V = AV _total × CE) of the signal converter 202 increases from the prior art as in the embodiment of FIG.

  Referring to FIG. 11, which is still another embodiment of the present invention, the thickness of the gate insulating film 212B of the first driver MOSFET 212 is substantially the same as the thickness of the gate insulating film 220B of the third driver MOSFET 220. To decrease. Therefore, the thicknesses of the gate insulating films of the first and third driver MOSFETs 212 and 220 are substantially the same and are smaller than the thicknesses of the gate insulating films of the other MOSFETs 214, 216, 218 and 222.

In such a case, the voltage gains AV _1st and AV _3rd of the first and third stages 206 and 210 are increased to sequentially increase the overall voltage gain AV _total of the signal converter 202. As the thickness of the gate insulating film 212B of the first driver MOSFET 212 decreases, the charge transfer efficiency CE of the signal converter 202 also decreases. However, the increase in the overall voltage gain AV _total is due to the fact that the overall sensitivity (S _V = AV _total × CE) of the signal converter 202 is still increased from the prior art as in the embodiment of FIG. 11, and the charge transfer efficiency CE is reduced. Exceeds offset amount.

  Referring to FIG. 12, which is still another embodiment of the present invention, the thickness of the gate insulating film 212B of the first driver MOSFET 212 is further reduced and is thinner than the thickness of the gate insulating film 220B of the third driver MOSFET 220. Therefore, the gate insulating films of the first and third driver MOSFETs 212 and 220 are thinner than the gate insulating films of the other MOSFETs 214, 216, 218 and 222.

In such a case, the voltage gain of the first stage 206 of FIG. 12 is further increased than the embodiment of FIG. Accordingly, the overall voltage gain AV _total of the signal converter 202 of FIG. 12 is further increased from the embodiment of FIG. However, as the thickness of the gate insulating film 212B of the first driver MOSFET 212 is reduced, the charge transfer efficiency CE of the signal converter 202 is further reduced as compared with the embodiment of FIG. Nevertheless, a further increase in the overall voltage gain AV _total is that the overall sensitivity of the signal converter 202 (S _V = AV _total × CE) is still increased from the prior art as in the embodiment of FIG. The offset amount as a further decrease in CE is exceeded.

Referring to FIG. 13, which is still another embodiment of the present invention, the thickness of the gate insulating film 216B of the second driver MOSFET 216 and the thickness of the gate insulating film 220B of the third driver MOSFET 220 are substantially the same. Each of the other MOSFETs 212, 214, 218, 222 is thinner than the gate insulating film. In such a case, the voltage gains AV _2nd and AV _3rd of the second and third stages 208 and 210 are respectively increased, and the overall voltage gain AV _total of the signal converter 202 is sequentially increased.

However, the decrease in the thickness of the gate insulating film of the second and third driver MOSFETs 216 and 220 does not affect the charge transfer efficiency CE of the signal converter 202. As a result, the overall sensitivity (S _V = AV _total × CE) of the signal converter 202 increases from the prior art as in the embodiment of FIG. In addition, the thicknesses of the gate insulating films of the second and third driver MOSFETs 216 and 220 are both reduced, and the thickness of one gate insulating film of the second and third driver MOSFETs 216 and 220 is reduced. Alternatively, the overall sensitivity of the signal converter 202 is further increased than the embodiment of FIG.

Referring to FIG. 14, which is still another embodiment of the present invention, the thicknesses of the gate insulating films 212B, 216B and 220B of the first, second and third driver MOSFETs 212, 216 and 220 are substantially the same. The thickness of the gate conductive film of each of the load MOSFETs 214, 218, and 222 is even thinner. In such a case, the voltage gains AV _1st , AV _2nd , and AV _3rd of the first, second, and third stages 206, 208, and 210 are increased to sequentially increase the overall voltage gain AV _total of the signal converter 202. .

As the thickness of the gate insulating film 212B of the first driver MOSFET 212 decreases, the charge transfer efficiency CE of the signal converter 202 also decreases. However, the increase in the overall voltage gain AV _total is due to the fact that the overall sensitivity (S _V = AV _total × CE) of the signal converter 202 is still increased from the prior art as in the embodiment of FIG. 14, and the charge transfer efficiency CE is reduced. Exceeds offset amount.

  Referring to FIG. 15, which is still another embodiment of the present invention, the thickness of the gate insulating film 212B of the first driver MOSFET 212 is further reduced than in the case of FIG. Accordingly, the thickness of the gate insulating film of the first driver MOSFET 212 is further thinner than the thickness of the same gate insulating film of the second and third driver MOSFETs 216 and 220. The thicknesses of the gate insulating films of the second and third driver MOSFETs 216 and 220 are still thinner than the thicknesses of the respective gate insulating films of the load MOSFETs 214, 218 and 222 in FIG. In addition, the thickness of the gate insulating film 212B of the first driver MOSFET 212 is further reduced than the thickness of the gate insulating films of the second and third driver MOSFETs 216 and 220.

In such a case, the voltage gain of the first stage 206 of FIG. 15 is further increased from the embodiment of FIG. Accordingly, the overall voltage gain AV _total of the signal converter 202 of FIG. 15 is further increased from the embodiment of FIG. However, as the thickness of the gate insulating film 212B of the first driver MOSFET 212 is further reduced, the charge transfer efficiency CE of the signal converter 202 is further reduced as compared with the embodiment of FIG. Nevertheless, a further increase in the overall voltage gain AV _total is that the overall sensitivity of the signal converter 202 (S _V = AV _total × CE) is still increased from the prior art as in the embodiment of FIG. The offset amount as a further decrease in CE is exceeded.

In this manner, in the embodiment of the present invention as shown in FIGS. 7 to 15, the thickness of the gate insulating film is at least one of the first driver MOSFET 212 disposed in the signal converter 202. Decrease by two subsequent driver MOSFETs 216 and / or 220. By reducing the thickness of such a gate insulating film, the overall voltage gain AV _total is increased, but the overall sensitivity of the signal converter 202 (S _V = AV _total × CE) is advantageously increased from the prior art, and the charge It does not affect the transmission efficiency CE. Therefore, the thickness of the gate insulating film of at least one of the subsequent driver MOSFETs 216 and / or 220 is preferably as thin as possible within a limit not limited by the breakdown voltage of the thin gate insulating film.

  In addition, the present invention can be implemented with a different gate insulating film thickness relationship from the various embodiments shown in FIGS. For example, the gate insulating film of the third driver MOSFET 220 may be thinner than the gate insulating film of the second driver MOSFET 216 or vice versa. In any case, the gate insulating films of the MOSFETs 216 and 220 are thinner than the gate insulating films of the other MOSFETs 212, 214, 218, and 222. In the present invention, the thickness of the gate insulating film is reduced with respect to at least one subsequent driver MOSFET 216 and / or 220 disposed next to the first driver MOSFET 212.

In addition, in some of the embodiments of the present invention of FIGS. 7 to 15, the thickness of the gate insulating film is reduced by the first driver MOSFET 212, but the charge transfer efficiency CE decreases as the thickness decreases. However, since the thickness of the gate insulating film also decreases in at least one of the subsequent driver MOSFETs 216 and / or 220, the increase in the overall voltage gain AV _total is caused by the overall sensitivity of the signal converter 202 (S _V = AV _total × CE ) Still increases from the prior art and exceeds the offset amount as a decrease in the charge transfer efficiency CE.

  Although six source follower stages 206, 208, and 210 are shown in FIGS. 6 to 15, for example, they can be implemented together with stages interposed therebetween. The present invention can be implemented when the thickness of the gate insulating film of at least one subsequent driver MOSFET disposed after the first source follower stage 206 is decreased so as to increase the overall sensitivity of the signal converter. .

  In addition, the signal converter having the increased overall sensitivity according to the present invention can be implemented by a method different from the embodiments shown in FIGS. For example, referring to FIG. 16, which is yet another embodiment of the present invention, a first driver MOSFET 212 is formed in an isolated P-well 402. Isolated P-well 402 is isolated from P-well 230 having other MOSFETs 214, 216, 218, 220, 222.

In the embodiment of FIG. 16, the isolated P-well 402 reduces the noise of the signal converter 202. The reason is that the first driver MOSFET 212 connected to the charge accumulation region 204 is isolated from the other MOSFETs 214, 216, 218, 22, and 222. In addition, the dopant concentration of the isolated P-well 402 may be decreased to reduce the back gate transconductance g _mb of the first driver MOSFET 212 and thereby increase the overall voltage gain AV _total of the signal converter 202. The embodiment of FIG. 16 is similar to the embodiment of FIG. 7 except that the first driver MOSFET 212 is in an isolated P-well 402. In addition, an isolated P-well 402 for the first driver MOSFET 212 can be formed in any of the other embodiments of FIGS.

  Referring to FIG. 17, which is yet another embodiment of the present invention, the source of the driver MOSFET is coupled to the drain of the load MOSFET of each of the source follower stages 206, 208, 210. Accordingly, referring to FIGS. 7 and 17, the source 212D of the first driver MOSFET 212 and the drain 214C of the first load MOSFET 214 are coupled together at one junction 404. Similarly, the source 216D of the second driver MOSFET 216 and the drain 218C of the second load MOSFET 218 are coupled together at one junction 406. Further, the source 220D of the third driver MOSFET 220 and the drain 222C of the third load MOSFET 222 are coupled together by a single junction 406.

  In such an embodiment of FIG. 17, the wiring structure 234, 236, 238 is not necessarily used advantageously in connecting the source of the respective driver MOSFET of each source follower stage 206, 208, 210 to the drain of the load MOSFET. It is not something that can be done. Also, the area occupied by the source of the driver MOSFET and the drain of the load MOSFET may advantageously reduce such coupling, as shown in FIG.

  FIG. 18 shows a signal converter 410 according to yet another embodiment of the present invention.

  Referring to FIG. 18, the signal converter 410 is similar to the signal converter 202 of FIG. However, in this embodiment, the sources of the load MOSFETs 214, 218, 222 are coupled together to ground via the same resistor RS. On the other hand, in the case of FIG. 6, the sources of the load MOSFETs 214, 218, and 222 are connected to the ground via respective resistors R 1, R 2, and R 3. In either case, the resistor at the source of the load MOSFET increases the effective load resistance at the drain of the load MOSFET.

  The resistance value of one resistor RS can be adjusted more easily for a more consistent operation of each of the source follower stages. On the other hand, since the source follower stage is connected via the common resistor RS, the signal converter 410 of FIG. 18 is more susceptible to noise. Therefore, to operate in a noisy environment, the signal converter 202 of FIG. 6 is more desirable.

  Although the present invention has been described in detail with reference to the preferred embodiments, the present invention is not limited to the above embodiments, and various modifications can be made by those skilled in the art within the scope of the technical idea of the present invention.

  The present invention can be applied to application fields using a charge transfer element such as a charge coupled element in an imaging system.

It is a block diagram of the conventional photodiode imaging system. FIG. 2 is a circuit diagram illustrating an example of a signal converter in an output circuit of the photodiode imaging system of FIG. 1. FIG. 2 is a layout diagram showing components of an output circuit of the photodiode imaging system of FIG. 1. FIG. 6 is a circuit diagram showing another example of a signal converter in the output circuit of the photodiode imaging system of FIG. 1. FIG. 5 is a cross-sectional view showing first and second driver MOSFETs in the signal converter of FIG. 4. FIG. 5 is a circuit diagram illustrating a signal converter having improved sensitivity according to an embodiment of the present invention. FIG. 7 is a cross-sectional view for explaining that the MOSFET in the signal converter of FIG. 6 has various gate insulating film thicknesses according to an embodiment of the present invention. FIG. 7 is a cross-sectional view for explaining that the MOSFET in the signal converter of FIG. 6 has various gate insulating film thicknesses according to an embodiment of the present invention. FIG. 7 is a cross-sectional view for explaining that the MOSFET in the signal converter of FIG. 6 has various gate insulating film thicknesses according to an embodiment of the present invention. FIG. 7 is a cross-sectional view for explaining that the MOSFET in the signal converter of FIG. 6 has various gate insulating film thicknesses according to an embodiment of the present invention. FIG. 7 is a cross-sectional view for explaining that the MOSFET in the signal converter of FIG. 6 has various gate insulating film thicknesses according to an embodiment of the present invention. FIG. 7 is a cross-sectional view for explaining that the MOSFET in the signal converter of FIG. 6 has various gate insulating film thicknesses according to an embodiment of the present invention. FIG. 7 is a cross-sectional view for explaining that the MOSFET in the signal converter of FIG. 6 has various gate insulating film thicknesses according to an embodiment of the present invention. FIG. 7 is a cross-sectional view for explaining that the MOSFET in the signal converter of FIG. 6 has various gate insulating film thicknesses according to an embodiment of the present invention. FIG. 7 is a cross-sectional view for explaining that the MOSFET in the signal converter of FIG. 6 has various gate insulating film thicknesses according to an embodiment of the present invention. 7 is a cross-sectional view of a MOSFET in the signal converter of FIG. 6 having a first driver MOSFET formed in an isolated P-well, according to another embodiment of the present invention. FIG. 7 is a cross-sectional view of a MOSFET in the signal converter of FIG. 6 having a source of a driver MOSFET and a drain of a load MOSFET, according to yet another embodiment of the present invention. FIG. 5 is a circuit diagram illustrating a signal converter having improved sensitivity according to still another embodiment of the present invention. 7 is a diagram illustrating an imaging system using the signal converter of FIG. 6 according to another embodiment of the present invention.

Explanation of symbols

202 signal converter 204 charge storage region 205 storage load 206 first source follower stage 208 second source follower stage 210 third source follower stage 212 first driver MOSFET
214 First load MOSFET
216 Second driver MOSFET
218 Second load MOSFET
220 Third Driver MOSFET
222 Third load MOSFET
224 Load capacitor VDD Bias voltage VGG Gate bias voltage _Vout voltage C _L Load capacitance R1 First load resistor R2 Second load resistor R3 Third load resistor

Claims (62)

In a signal converter that converts signal charge into voltage,
A first driver FET receiving the signal charge;
Connected to the output of the first driver FET, but connected to the first driver FET having a gate insulating film having a thickness smaller than the thickness of the gate insulating film of at least one other FET of the signal converter. And a subsequent driver FET.   The signal converter according to claim 1, wherein the first driver FET is disposed in a first stage, and the subsequent driver FET is disposed in a second stage next to the first stage.   3. The signal converter according to claim 2, wherein a thickness of the gate insulating film of the subsequent driver FET is thinner than a thickness of the gate insulating film of the first driver FET.   3. The signal converter according to claim 2, wherein a thickness of the gate insulating film of the subsequent driver FET is the same as a thickness of the gate insulating film of the first driver FET.   3. The signal converter according to claim 2, wherein a thickness of the gate insulating film of the first driver FET is smaller than a thickness of the gate insulating film of the subsequent driver FET.   The first driver FET is disposed in a first stage, and the subsequent driver FET is disposed in a third stage connected to the first stage through a second stage having a second driver FET. The signal converter according to claim 1.   The signal converter according to claim 6, wherein a thickness of the gate insulating film of the subsequent driver FET is smaller than a thickness of the gate insulating film of the first driver FET.   7. The signal converter according to claim 6, wherein the thickness of the gate insulating film of the subsequent driver FET is the same as the thickness of the gate insulating film of the first driver FET.   The signal converter according to claim 6, wherein a thickness of the gate insulating film of the first driver FET is thinner than a thickness of the gate insulating film of the subsequent driver FET.   The signal converter according to claim 6, wherein a thickness of the gate insulating film of the subsequent driver FET is thinner than a thickness of the same gate insulating film of the first and second driver FETs.   The signal converter of claim 1, further comprising a final driver FET coupled to the subsequent driver FET to generate an output voltage.   12. The signal converter according to claim 11, wherein the thickness of the gate insulating film of the subsequent driver FET is thinner than the thickness of the gate insulating film of the final driver FET.   12. The signal converter according to claim 11, wherein the thickness of the gate insulating film of the subsequent driver FET is the same as the thickness of the gate insulating film of the final driver FET.   12. The signal converter according to claim 11, wherein the thickness of the gate insulating film of the final driver FET is smaller than the thickness of the gate insulating film of the subsequent driver FET.   12. The signal converter according to claim 11, wherein the thickness of the gate insulating film of the subsequent driver FET is thinner than the thickness of the same gate insulating film of the first and final driver FETs.   The signal converter according to claim 11, wherein each of the driver FETs is coupled to a respective load FET.   17. The signal converter according to claim 16, wherein each of the driver FETs has the same gate insulating film thickness that is smaller than the thickness of at least one gate insulating film of the load FET.   The signal converter according to claim 1, wherein each of the driver FETs is coupled to a respective load FET.   19. The signal converter according to claim 18, wherein a thickness of the gate insulating film of the subsequent driver FET is thinner than a thickness of at least one gate insulating film of the load FET.   19. The signal converter according to claim 18, wherein the thickness of the gate insulating film of the subsequent driver FET is smaller than the thickness of the respective gate insulating films of all the load FETs.   19. The signal converter of claim 18, wherein each load FET is coupled to ground through a respective resistor.   The signal converter of claim 18, wherein each load FET is coupled together to ground through the same resistor.   2. The signal converter according to claim 1, wherein a thickness of the gate insulating film of the subsequent driver FET is thinner than a thickness of each gate insulating film of every other FET of the signal converter.   2. The signal converter according to claim 1, wherein the first driver FET is an enhancement type MOSFET, and all other FETs of the signal converter are depletion type MOSFETs.   The signal converter according to claim 1, wherein each of the driver FETs constitutes a source follower.   The signal converter according to claim 1, wherein the first driver FET is formed in an isolated well.   The signal converter according to claim 1, wherein the signal charge is output from a charge coupled device. In a signal converter that converts signal charge into voltage,
A plurality of stages, each comprising a driver FET and a load FET, configured to receive a signal charge from an initial stage and each subsequent stage receives a voltage from a previous stage;
Voltage gain increasing means for increasing the voltage gain without decreasing the charge transfer efficiency of the signal converter.   The signal converter according to claim 28, wherein each of the driver FETs constitutes a source follower.   29. The signal converter according to claim 28, wherein the source of each stage load FET is coupled to ground through a respective resistor.   30. The signal converter of claim 28, wherein the source of each stage load FET is coupled to ground through the same resistor.   29. The signal converter of claim 28, wherein the first stage driver FET is formed in an isolated well.   The first stage driver FET is sized to minimize gate capacitance, and the final stage driver FET is sized to provide sufficient current to drive a load coupled to the output of the final stage. 29. The signal of claim 28, wherein the intermediate stage driver FET is sized to allow current amplification to occur between the first and last stage driver FETs. converter. In the output circuit of the signal transmission element,
A signal accumulation region for accumulating charges from the signal transmission element to generate signal charges;
The first driver FET that receives the signal charge and the output of the first driver FET have a gate insulating film thickness that is smaller than the gate insulating film thickness of at least one other FET of the signal converter. A signal converter comprising a subsequent driver FET for converting the signal charge into a voltage;
A reset FET that is turned on to reset the signal storage region to a reset voltage;
And an output FET that is turned on so as to transfer charges from the charge transfer element to the signal storage region.   35. The output circuit according to claim 34, wherein the first driver FET constitutes a first stage, and the subsequent driver FET constitutes a second stage subsequent to the first stage.   The method of claim 34, wherein the first driver FET constitutes a first stage, and the subsequent driver FET constitutes a third stage connected to the first stage via a second stage. Output circuit.   35. The output circuit of claim 34, further comprising a final driver FET coupled to the output of the subsequent driver FET to generate an output voltage.   38. The output circuit of claim 37, wherein each of the driver FETs is coupled to a respective load FET.   39. The output circuit according to claim 38, wherein each of the driver FETs has the same gate insulating film thickness that is thinner than the thickness of at least one gate insulating film of the load FET.   The output circuit according to claim 34, wherein each of the driver FETs constitutes a source follower.   35. The output circuit of claim 34, wherein each of the driver FETs is coupled to a respective load FET.   42. The output circuit according to claim 41, wherein a thickness of the gate insulating film of the subsequent driver FET is thinner than a thickness of at least one gate insulating film of the load FET.   42. The output circuit of claim 41, wherein each load FET is coupled to ground through a respective resistor.   42. The output circuit of claim 41, wherein each load FET is coupled together to ground through the same resistor.   35. The output circuit according to claim 34, wherein the first driver FET is an enhancement type MOSFET, and every other FET of the signal converter is a depletion type MOSFET.   35. The output circuit according to claim 34, wherein the first driver FET is formed in an isolated well.   The output circuit according to claim 34, wherein the charge transfer element is a charge coupled element. A photodiode array comprising respective photodiodes for storing respective signal charges;
At least one signal transmission element coupled to the photodiode array and configured to shift a signal charge from each photodiode;
A signal storage region for storing each signal charge shifted from the charge transfer element;
The first driver FET that receives the respective signal charges and the gate insulating film thickness that is coupled to the output of the first driver FET and is thinner than the gate insulating film thickness of at least one other FET of the signal converter An output circuit coupled to at least one of the signal transmission elements, including a signal converter that converts each signal charge accumulated in the signal accumulation region into a voltage. An imaging system characterized by that.   49. The imaging system according to claim 48, wherein the first driver FET constitutes a first stage, and the subsequent driver FET constitutes a second stage subsequent to the first stage.   49. The imaging system according to claim 48, wherein the first driver FET constitutes a third stage connected to the first stage via a second stage.   49. The imaging system of claim 48, wherein the signal converter further comprises a final driver FET coupled to the output of the subsequent driver FET to generate an output voltage.   52. The imaging system of claim 51, wherein each of the driver FETs is coupled to a respective load FET.   53. The imaging system according to claim 52, wherein each of the driver FETs has the same gate insulating film thickness that is thinner than the thickness of at least one gate insulating film of the load FET.   49. The imaging system of claim 48, wherein each of the driver FETs is coupled to a respective load FET.   55. The imaging system according to claim 54, wherein a thickness of the gate insulating film of the subsequent driver FET is thinner than a thickness of at least one gate insulating film of the load FET.   The imaging system of claim 54, wherein each load FET is coupled to ground through a resistor.   The imaging system of claim 54, wherein each load FET is coupled together to ground through the same resistor.   The imaging system according to claim 48, wherein each of the driver FETs constitutes a source follower.   49. The imaging system according to claim 48, wherein the first driver FET is an enhancement type MOSFET, and every other FET of the signal converter is a depletion type MOSFET.   49. The imaging system according to claim 48, wherein the first driver FET is formed in an isolated well.   The imaging system according to claim 48, wherein the charge transfer element is a charge coupled element. The output circuit is
A reset FET that is turned on to reset the charge storage region to a reset voltage;
49. The imaging system according to claim 48, further comprising: an output FET that is turned on to transmit each signal charge from the charge transfer element to the charge storage region and that turns off the reset FET. .

Images