CN1674297A - Signal charge converter for charge transfer element - Google Patents
Signal charge converter for charge transfer element Download PDFInfo
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- CN1674297A CN1674297A CNA2004100997717A CN200410099771A CN1674297A CN 1674297 A CN1674297 A CN 1674297A CN A2004100997717 A CNA2004100997717 A CN A2004100997717A CN 200410099771 A CN200410099771 A CN 200410099771A CN 1674297 A CN1674297 A CN 1674297A
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- 238000003384 imaging method Methods 0.000 claims description 24
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- 230000035945 sensitivity Effects 0.000 abstract description 37
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000009825 accumulation Methods 0.000 description 19
- 230000001965 increasing effect Effects 0.000 description 17
- 238000010586 diagram Methods 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 230000002708 enhancing effect Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- 239000012535 impurity Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14806—Structural or functional details thereof
- H01L27/14812—Special geometry or disposition of pixel-elements, address lines or gate-electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L27/14643—Photodiode arrays; MOS imagers
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Abstract
The present invention provided a signal charge converter for a charge transfer element. The signal converter includes a first driver FET of a first stage that receives a signal charge and converts the signal charge to a voltage. Subsequent driver FETs are connected to an output of the first driver FET, and gate insulating films of subsequent drivers include reduced thicknesses. The subsequent driver FETs constitute a second stage or a third stage. The reduced thicknesses of the gate insulating films of the subsequent driver FETs increase a voltage gain AV<SB>total</SB>without decreasing charge transfer efficiency, and raises the entire sensitivity of the signal converter.
Description
Technical field
The present invention relates generally to the charge-transfer device in the imaging system, CCD (charge coupled device) for example, more particularly, the signal charge that relates to self charge transfer element in a kind of future converts the signal charge converter of the voltage of the sensitivity with enhancing to.
Background technology
Fig. 1 has shown the example of imaging system 100, and this imaging system 100 comprises photodiode array, for example the photodiode 102 of example.Each photodiode accumulation signal charge, this signal charge indication is in the exposure intensity of the location of pixels of photodiode.Photodiode along every row is provided with vertical BCCD (buried regions (buried) charge coupled device), comprises the first vertical BCCD 104 that is used for first row, the last vertical BCCD 108 that is used for the second vertical BCCD 106 of secondary series and is used for last row.
Each vertical BCCD transfers to horizontal BCCD 110 with signal charge from the photodiode of these row.This horizontal BCCD 110 transfers to output circuit 112 (shown in dotted outline Fig. 1) with signal charge from vertical BCCD.Output circuit 112 will convert voltage to from the signal charge of horizontal BCCD 110, V
Out
In output circuit 112, output mos FET (mos field effect transistor) 114 is connected between horizontal BCCD 110 and the accumulation district 116.In addition, the MOSFET118 that resets is coupled in resetting voltage V
ResetBetween source and the accumulation district 116.The knot (junction) that accumulation district 116 is normally highly doped is used to assemble the signal charge from horizontal BCCD 110.Output mos FET 114 is setovered, so that will transfer to the electric charge node 120 in accumulation district 116 from the signal charge of the horizontal BCCD 110 of last level.
The unlatching MOSFET 118 that resets is used for the electric charge node 120 in accumulation district 116 is reset (reset) to resetting voltage V
ResetOn the grid of MOSFET 118 that resets, apply the RESET control signal.When the signal charge from horizontal BCCD 110 just had been collected at accumulation district 116, the MOSFET 118 that resets kept closing usually.
Signal converter 122 is connected to accumulation district 116, and the signal charge that is used for accumulating in district 116 converts correspondent voltage V to
OutSuch voltage V
OutLevel indication accumulate in the quantity of the signal charge in district 116, represent exposure intensity thus corresponding to such signal charge.
Fig. 2 has shown the exemplary realization according to the signal converter 122 (dotted outline) of prior art.In Fig. 1,2,3,4 and 5, has the element that the element of same reference numbers represents to have similar structures and function.The signal converter 122 of Fig. 2 comprises the first driver MOSFET 132 and the first load MOSFET 134 that comprises first source follower stage 133.In addition, the second driver MOSFET 136 and the second load MOSFET 138b comprise second source follower stage 139.And the 3rd driver MOSFET 140 and the 3rd load MOSFET 142 comprise the 3rd source follower stage 143.
In each source follower stage, the source electrode of each driver MOSFET is connected to the drain electrode of each load MOSFET.Each driver MOSFET 132,136 and 140 drain electrode are connected to high bias voltage VDD, and the source electrode of load MOSFET 134,138 and 142 is connected to low bias voltage GND.Load MOSFET 134,138 and 142 grid are connected to gate bias voltage, and gate bias voltage is GND in the example of Fig. 2.
The grid of the first driver MOSFET 132 is connected to accumulation district 116.The grid of each subsequent driver MOSFET is connected to the source electrode of previous driver MOSFET.Therefore, the grid of the second driver MOSFET136 is connected to the source electrode of the first driver MOSFET 132, and the grid of the 3rd driver MOSFET 140 is connected to the source electrode of the second driver MOSFET 136.For each corresponding source follower stage among Fig. 2, the grid of each driver MOSFET is an input, and the source electrode of each driver MOSFET is an output.The source electrode of the 3rd driver MOSFET 140 provides the output voltage V of signal converter 122
Out
Referring again to Fig. 2, the first driver MOSFET 132 is implemented as the MOSFET of enhancement mode, and other each MOSFET 134,136,138,140 and 142 is implemented as the MOSFET of depletion type.Usually, the MOSFET of enhancement mode is at V
GSNot conducting during=0V, and the MOSFET of depletion type has the conductive channel that injects formation between source electrode and drain electrode, it is at V
GSConducting during=0V.
The sensitivity S of signal converter 122
VIt is the feature of the quality of indication signal converter 122.The sensitivity S of signal converter 122
VCalculate by following formula:
S
V＝CE×AV
total
CE is a charge transfer effciency, and AV
TotalBe by three source follower stage 133,139 of signal converter 122 and total voltage gain of 143.Therefore, AV
TotalCalculate by following formula:
AV
total＝AV
1st×AV
2nd×AV
3rd
AV
1stBe the voltage gain of first source follower stage 133, AV
2ndBe the voltage gain of second source follower stage 139, AV
3rdIt is the voltage gain of the 3rd source follower stage 143.
The voltage gain AV of any source follower stage can be calculated by following formula:
AV＝g
m/(g
m+g
ds+g
mb)
For the driver MOSFET of source follower stage, g
mBe mutual conductance, g
DsThe electricity that is passage is led, g
MbBe the mutual conductances of back of the body grid.The mutual conductance g of driver MOSFET
mUsually calculate by following formula:
g
m=[2 μ
OxC
Ox(W/L) I
D]
1/2For driver MOSFET, μ
OxBe charge mobility, C
OxBe grid capacitance, W is the grid level widths, and L is the grid level lengths, I
DIt is drain current.
In addition, charge transfer effciency CE is calculated by following formula:
CE＝q/C
S＝q/[C
FD+C
GS+C
GD+C
G]
Q is an electron charge, with reference to Fig. 1 and 2, and C
SIt is the total capacitance at memory node 120 places in accumulation district 116.Fig. 3 has shown output mos FET 114, accumulation district 116, the layout example of the MOSFET 118 and the first driver MOSFET 132 resets.Such assembly is connected to the memory node 120 in accumulation district 116.
C
FD, be the electric capacity of unsteady diffused junction 116;
C
GS, be the reset grid 158 of MOSFET 118 and the overlap capacitance between the source electrode 154 (that is, in Fig. 3 in the overlapping region shown in the dotted outline 172);
C
GD, be overlap capacitance between 154 of the grid 152 of output mos FET 114 and drain electrode (that is, in Fig. 3 in the overlapping region shown in the dotted outline 174);
C
G, be the grid capacitance of the first driver MOSFET 132.
Fig. 4 has shown a replaceable execution mode 122A of disclosed signal converter in No. the 5th, 432,364, people's such as Ohki United States Patent (USP).Such signal converter 122A uses three source follower stage has corresponding three load MOSFET 134,138 and three driver MOSFET 132,136 and 140 of 142.In addition, the drain electrode of the first driver MOSFET 132 is connected to VDD through resistance 182, and the source electrode of the second load MOSFET 138 is connected to GND through resistance 184.The first and the 3rd load MOSFET 134 and 142 source electrode are connected to GND together through capacitor 186.Gate bias voltage source 188 and gate bias capacitor 190 are connected to the grid of load MOSFET 134,138 and 142.
The class of operation of the signal converter 122A of Fig. 4 is similar to the signal converter 122 of Fig. 2.But with reference to Figure 4 and 5, the gate-dielectric 194 of gate-dielectric 192 to the second driver MOSFET136 of the first driver MOSFET 132 is thin.Fig. 5 has shown the profile of the first and second driver MOSFET 132 and 136, as United States Patent (USP) the 5th, 432, described in No. 364.
With reference to Fig. 5, the first and second driver MOSFET 132 and 136 are formed in the P trap 196.The first driver MOSFET 132 is made up of grid 132A, drain electrode 132B and source electrode 132C, and the second driver MOSFET 136 is made up of grid 136A, drain electrode 136B and source electrode 136C.Interconnection structure 198 is connected to the source electrode 132C of the first driver MOSFET 132 the grid 136A of the second driver MOSFET 136.
With reference to Figure 4 and 5, in signal converter 122A, make the thickness of the gate-dielectric 192 of the first driver MOSFET 132 be reduced to the thickness of the gate-dielectric of other MOSFET, for example be lower than the thickness of the gate dielectric of the second driver MOSFET 136, so that reduce 1/f noise.In addition in the case, because the mutual conductance g of the first driver MOSFET 132
mIncrease, so the voltage gain AV of first source follower stage
1stIncrease.
But, because the thickness of the reduction of gate-dielectric 192 has increased by the grid capacitance C of the first driver MOSFET 132
GSo, reduced charge transfer effciency nocuously.Therefore, the overall sensitivity of the signal converter 122A of prior art does not have inevitable enhancing, and only the gate-dielectric 192 by reducing by the first driver MOSFET132 thickness in addition may cause variation.
Yet the overall sensitivity that increases signal converter can produce higher-quality imaging system.Therefore, the desired signal transducer has the overall sensitivity of increase, to improve the quality of imaging system.
Summary of the invention
Therefore, of the present invention general aspect in, reduce the gate dielectric thickness of at least one the subsequent driver FET after the first driver FET, with the overall sensitivity of enhancing signal transducer.
In an embodiment of the present invention, be used for the signal converter that signal charge is walked around into voltage is comprised the first driver FET of received signal electric charge.In addition, subsequent driver FET is connected to the output of the first driver FET, and the gate dielectric thickness of subsequent driver FET is less than the gate dielectric thickness of at least one other FET of signal converter.Each driver FET is configured to source follower in an exemplary embodiment of the present invention.
In one embodiment of the invention, the first driver FET is used for the first order, and subsequent driver FET is used for the second level after the first order.In the case, the gate dielectric thickness of subsequent driver FET is less than the gate dielectric thickness of the first driver FET, or is substantially equal to the gate dielectric thickness of the first driver FET.Selectively, the gate dielectric thickness of the first driver FET descends, even less than the gate dielectric thickness of subsequent driver FET.
In another embodiment of the present invention, the first driver FET is used for the first order, and subsequent driver FET is used for the third level, and this third level is connected to the first order through the second level with second driver FET.In the case, the gate dielectric thickness of subsequent driver FET is less than the gate dielectric thickness of the first driver FET, or is substantially equal to the gate dielectric thickness of the first driver FET.Selectively, the gate dielectric thickness of the first driver FET descends, even less than the gate dielectric thickness of subsequent driver FET.In another embodiment of the present invention, the gate dielectric thickness of subsequent driver FET is less than the identical gate dielectric thickness of the first and second driver FET.
In yet another embodiment of the present invention, last driver FET is connected to the output of subsequent driver FET, to produce output voltage.In the case, the gate dielectric thickness of subsequent driver FET is less than the gate dielectric thickness of last driver FET, or is substantially equal to the gate dielectric thickness of last driver FET.Selectively, the gate dielectric thickness of last driver FET descends, even less than the gate dielectric thickness of subsequent driver FET.In another embodiment of the present invention, the gate dielectric thickness of subsequent driver FET less than first with the identical gate dielectric thickness of last driver FET.
In another embodiment of the present invention, each driver FET is connected to load FET separately.In the case, in one embodiment of the invention, each driver FET has identical gate dielectric thickness, and this thickness is less than the gate dielectric thickness of at least one load FET.
In another embodiment of the present invention, the gate dielectric thickness of subsequent driver FET is less than the gate dielectric thickness of at least one load FET, perhaps less than each gate dielectric thickness separately of all load FET.
The signal converter of embodiment like this of the present invention can be advantageously used in according to signal charge and produce voltage, and this signal charge is to be exported by the CCD of photodiode imaging system (charge coupled device).
In this way, reduce the gate dielectric thickness of first order driver FET at least one subsequent driver FET afterwards.The gate dielectric thickness that so reduces at least one subsequent driver FET can increase total voltage gain AV
Total, and can not reduce the charge transfer effciency of signal converter.Therefore, strengthened the overall sensitivity of signal converter.
Detailed description of the present invention subsequently by considering to use accompanying drawing to represent will be better understood these and other aspect of the present invention and advantage.
Description of drawings
Fig. 1 has shown the block diagram according to the photodiode imaging system of prior art;
Fig. 2 has shown the circuit diagram according to the illustrative embodiments of the signal converter in the output circuit of Fig. 1 of prior art;
Fig. 3 has shown the layout according to the element in the output circuit of Fig. 1 of prior art;
Fig. 4 has shown the circuit diagram of the signal converter of another kind of execution mode as described in the prior art;
Fig. 5 has shown the profile according to the first and second driver MOSFET in the signal converter of Fig. 4 of prior art;
Fig. 6 has shown the circuit diagram with the signal converter that strengthens sensitivity according to the embodiment of the invention;
Fig. 7,8,9,10,11,12,13,14 and 15 has shown the profile according to the MOSFET in the signal converter of Fig. 6 of the embodiment of the invention, and described MOSFET has various possible gate dielectric thickness;
Figure 16 has shown the optional profile of the MOSFET that the signal converter of Fig. 6 according to another embodiment of the invention is interior, and it has the first interior driver MOSFET of P trap of the insulation of being formed on;
Figure 17 has shown the optional profile according to the MOSFET in the signal converter of Fig. 6 of another embodiment of the present invention, and wherein each has the source electrode of the driver MOSFET that segmentation combines and the drain electrode of load MOSFET;
Figure 18 has shown the optional circuit diagram that has the signal converter that strengthens sensitivity in accordance with another embodiment of the present invention; And
Figure 19 has shown the imaging system of using the signal converter of Fig. 6 in accordance with another embodiment of the present invention.
The clearness that accompanying drawing cited herein illustrates is for example drawn, and does not strictly proportionally draw.Has the element that the element of same reference numerals represents to have similar structures and function among Fig. 1 to 19.
Embodiment
With reference to Fig. 6, the signal charge that will accumulate in 204 places, accumulation district according to the signal converter 202 of the embodiment of the invention converts to has the voltage V that strengthens sensitivity
OutIn one embodiment of the invention, the accumulation district 204 of Fig. 6 is formed highly doped knot usually, is similar to Fig. 1,2,3 and 4 accumulation district 116.Perhaps, can use the accumulation district of any other type to implement the present invention.
In one embodiment of the invention, signal converter 202 comprises: first source follower stage 206, second source follower stage 208 and the 3rd source follower stage 210.First source follower stage 206 comprises the first driver MOSFET (mos field effect transistor) 212 and the first load MOSFET 214.Second source follower stage 208 comprises the second driver MOSFET 216 and the second load MOSFET 218.The 3rd source follower stage 210 comprises the 3rd driver MOSFET 220 and the 3rd load MOSFET 222.
The source electrode of the drain electrode that the first driver MOSFET 212 has the drain electrode that is connected to high bias voltage VDD, be connected to the first load MOSFET 214 and the grid that is connected to accumulation district 204.In addition, the first load MOSFET 214 has the grid that is connected to gate bias voltage VGG and through the source electrode of the first load resistance R1 ground connection.
Similarly, the second driver MOSFET 216 has the drain electrode that is connected to high bias voltage VDD and is connected to the source electrode of the drain electrode of the second load MOSFET 218.In addition, the grid of the second driver MOSFET 216 is connected to the output (that is the source electrode of the first driver MOSFET 212) of first source follower stage 206.And the second load MOSFET 218 has the grid that is connected to gate bias voltage VGG and through the source electrode of the second load resistance R2 ground connection.
In addition, the 3rd driver MOSFET 220 has the drain electrode that is connected to high bias voltage VDD and is connected to the source electrode of the drain electrode of the 3rd load MOSFET 222.In addition, the grid of the 3rd driver MOSFET 220 is connected to the output (that is the source electrode of the second driver MOSFET 216) of second source follower stage 208.And the 3rd load MOSFET 222 has the grid that is connected to gate bias voltage VGG and through the source electrode of the 3rd load resistance R3 ground connection.The output of the 3rd source follower stage 210 provides output voltage V
Out
Usually, use three source follower stage 206,208 and 210, this is because the 3rd driver MOSFET 220 of afterbody 210 is made with the size with enough speed drive load capacitances 224.For example, typical load capacitance CL approximately is 10pF (pico farad), and for the such load capacitance of enough speed drive is arranged, the width of the 3rd driver MOSFET 220 approximately is 1000 microns.
On the other hand, expect that the size of the first driver MOSFET 212 of prime 206 and grid capacitance thus are minimized, so that the charge transfer effciency maximum of signal converter 202.The second driver MOSFET 216 offers the 3rd driver MOSFET 220 by amplifying from the electric current of the first driver MOSFET 212, and transition smoothly (smoothly transition) between the first driver MOSFET 212 and the 3rd driver MOSFET 220.
Referring again to Fig. 6, the first driver MOSFET 212 is implemented to the MOSFET of enhancement mode, and each other MOSFET 214,216,218,220 and 222 is implemented to the MOSFET of depletion type.Usually, the MOSFET of enhancement mode is at V
GSNot conducting during=0V, and the MOSFET of depletion type has the conductive channel that injects formation between source electrode and drain electrode, it is at V
GSConducting during=0V.
Fig. 7 has shown the MOSFET212,214,216,218 of the signal converter 202 of the Fig. 6 in the exemplary embodiment of the present, 220 and 222 profile.MOSFET 212,214,216,218,220 and 222 for example is formed in and is the N-channel MOS FET in the P trap 230 of the Semiconductor substrate 232 of silicon wafer.
Referring again to Fig. 7, the first driver MOSFET 212 comprises grid 212A, gate-dielectric 212B, drain electrode 212C and source electrode 212D.The first load MOSFET 214 comprises grid 214A, gate-dielectric 214B, drain electrode 214C, source electrode 214D and as the injection conductive channel 214E of the MOSFET of depletion type.Interconnection structure 234 is connected to the source electrode 212D of the first driver MOSFET 212 the drain electrode 214C of the first load MOSFET214.
Similarly, the second driver MOSFET 216 comprises grid 216A, gate-dielectric 216B, drain electrode 216C, source electrode 216D and as the injection conductive channel 216E of the MOSFET of depletion type.The second load MOSFET 218 comprises grid 218A, gate-dielectric 218B, drain electrode 218C, source electrode 218D and as the injection conductive channel 218E of the MOSFET of depletion type.Interconnection structure 236 is connected to the source electrode 216D of the second driver MOSFET216 drain electrode 218C of the second load MOSFET 218.
In addition, the 3rd driver MOSFET 220 comprises grid 220A, gate-dielectric 220B, drain electrode 220C, source electrode 220D and as the injection conductive channel 220E of the MOSFET of depletion type.The 3rd load MOSFET 222 comprises grid 222A, gate-dielectric 222B, drain electrode 222C, source electrode 222D and as the injection conductive channel 222E of the MOSFET of depletion type.Interconnection structure 238 is connected to the source electrode 220D of the 3rd driver MOSFET220 the drain electrode 222C of the 3rd load MOSFET 222.
Referring again to Fig. 7, in one embodiment of the invention, reduce by the thickness (that is, gate dielectric thickness) of the gate-dielectric 216B of the second driver MOSFET 216, make it less than each other MOSFET212,214,218,220 and 222 gate dielectric thickness.Be similar to the signal converter 122 among above-mentioned Fig. 2, the sensitivity S of the signal converter 202 of Fig. 6
VCalculate by following formula:
S
V＝CE×AV
total
CE is a charge transfer effciency, AV
TotalIt is total voltage gain by three source follower stage 206,208 and 210.Therefore, AV
TotalCalculate by following formula:
AV
total＝AV
1st×AV
2nd×AV
3rd
AV
1stBe the voltage gain of first source follower stage 206, AV
2ndBe the voltage gain of second source follower stage 208, AV
3rdIt is the voltage gain of the 3rd source follower stage 210.
The voltage gain AV of any source follower stage can be calculated by following formula:
AV＝g
m/(g
m+g
ds+g
mb)
For the driver MOSFET of source follower stage, g
mBe mutual conductance, g
DsThe electricity that is passage is led, g
MbBe the mutual conductances of back of the body grid.The mutual conductance g of driver MOSFET
mUsually calculate by following formula:
g
m＝[2μ
oxC
ox(W/L)I
D]
1/2
For driver MOSFET, μ
OxBe charge mobility, C
OxBe grid capacitance, W is a grid width, and L is a grid length, I
DIt is drain current.
In addition, with reference to Fig. 6 and 19, signal converter 202 is parts of the output circuit 302 of use in the imaging system 300.With reference to Fig. 1 and 19, photodiode 102 arrays among Figure 19 and the class of operation of CCD (charge coupled device) 104,106,108 and 110 are similar to as above described with reference to Fig. 1.In addition, the class of operation of the output mos FET in the output circuit 302 of Figure 19 114 and the MOSFET 118 that resets is similar to as above described with reference to Fig. 1.
The charge transfer effciency CE of signal converter 202 is calculated by following formula:
CE＝q/C
S＝q/[C
FD+C
GS+C
GD+C
G]
Q is an electron charge, with reference to Fig. 6 and 19, C
SIt is the total capacitance at memory node 205 places in accumulation district 204.Be similar to reference to Fig. 1 and 4 described the total capacitance C of Fig. 6 and 19 memory node 205
SComprise:
C
FD, the electric capacity of the diffused junction 204 that floats;
C
GS, the grid of the MOSFET 118 that resets and the overlap capacitance between the source electrode;
C
GD, the overlap capacitance between the grid of output mos FET 114 and the drain electrode;
C
G, the grid capacitance of the first driver MOSFET 212.
In the embodiment of Fig. 7, reduce the thickness of the gate-dielectric 216B of the 2nd MOSFET 216, so that increase the voltage gain AV of second source follower stage 208
2ndTherefore, increased total voltage gain AV of signal converter 202
TotalBut the thickness that reduces by the gate-dielectric of the second driver MOSFET 216 can not influence the charge transfer effciency CE of signal converter 202.Therefore, the overall sensitivity S of the signal converter 202 of Fig. 7 embodiment
V=CE * AV
TotalOverall sensitivity than prior art increases to some extent.
With reference to Fig. 8, for another embodiment of the present invention, reduce by the thickness of the gate-dielectric 212B of the first driver MOSFET 212, thickness with the gate-dielectric 216B of the second driver MOSFET 216 is identical basically to make it.Therefore, the first and second driver MOSFET 212 and 216 gate dielectric thickness are substantially the same, and all less than the gate dielectric thickness of each other MOSFET 214,218,220 and 222.
In the case, increased by first and second grade 206 and 208 every grade voltage gain AV
1stAnd AV
2ndThereby, increased total voltage gain AV of signal converter 202
TotalAlong with the reduction of the gate-dielectric 212B thickness of the first driver MOSFET 212, the charge transfer effciency CE of signal converter 202 has also reduced.But, total voltage gain AV
TotalIncrease can have more than this reduction of charge transfer effciency CE, so the overall sensitivity S of the signal converter 202 of Fig. 8 embodiment
V=CE * AV
TotalStill the overall sensitivity that surpasses prior art.
With reference to Fig. 9, for another embodiment of the present invention, reduce by the thickness of the gate-dielectric 212B of the first driver MOSFET 212, make it even less than the thickness of the gate-dielectric 216B of the second driver MOSFET 216.Therefore, the first and second driver MOSFET 212 and 216 gate dielectric thickness are less than the gate dielectric thickness of each other MOSFET 214,218,220 and 222.In addition, the reduction of the gate-dielectric 212B thickness of the first driver MOSFET 212 even surpass the gate dielectric thickness of the second driver MOSFET 216.
In the case, the increase of the voltage gain of the first order among Fig. 9 206 even surpass embodiment among Fig. 8.Therefore, the total voltage gain AV of the signal converter among Fig. 9 202
TotalIncrease in addition surpassed the embodiment among Fig. 8.But along with the further reduction of the gate-dielectric 212B thickness of the first driver MOSFET 212, the further reduction of the charge transfer effciency CE of the signal converter 202 among Fig. 9 has also surpassed the embodiment among Fig. 8.Yet, total voltage gain AV
TotalFurther increase can have more than this further reduction of charge transfer effciency CE, so the overall sensitivity S of the signal converter 202 of Fig. 9 embodiment
V=CE * AV
TotalStill the overall sensitivity that surpasses prior art.
With reference to Figure 10, for another embodiment of the present invention, reduce the thickness (that is, gate dielectric thickness) of the gate-dielectric 220B of the 3rd driver MOSFET 220, make it less than each other MOSFET212,214,216,218 and 222 gate dielectric thickness.In the case, increased the voltage gain AV of the third level 210
3rdThereby, increased total voltage gain AV of signal converter 202
Total
But the gate dielectric thickness that reduces the 3rd driver MOSFET 220 does not influence the charge transfer effciency CE of signal converter 202.Therefore, the overall sensitivity S of the signal converter 202 of Figure 10 embodiment
V=CE * AV
TotalThe overall sensitivity that surpasses prior art.
With reference to Figure 11, for another embodiment of the present invention, also reduce by the thickness of the gate-dielectric 212B of the first driver MOSFET 212, thickness with the gate-dielectric 220B of the 3rd driver MOSFET 220 is identical basically to make it.Therefore, the first and the 3rd driver MOSFET 212 and 220 gate dielectric thickness are substantially the same, and all less than the gate dielectric thickness of each other MOSFET 214,216,218 and 222.
In the case, increased by first and the third level 206 and 210 every grade voltage gain AV
1stAnd AV
3rdThereby, increased total voltage gain AV of signal converter 202
TotalAlong with the reduction of the gate-dielectric 212B thickness of the first driver MOSFET 212, the charge transfer effciency CE of signal converter 202 also reduces.But, total voltage gain AV
TotalIncrease can have more than this reduction of charge transfer effciency CE, so the overall sensitivity S of the signal converter 202 of Figure 11 embodiment
V=CE * AV
TotalStill the overall sensitivity that surpasses prior art.
With reference to Figure 12, for another embodiment of the present invention, reduce by the thickness of the gate-dielectric 212B of the first driver MOSFET 212, make it even less than the thickness of the gate-dielectric 220B of the 3rd driver MOSFET 220.Therefore, the first and the 3rd driver MOSFET 212 and 220 gate dielectric thickness are less than the gate dielectric thickness of each other MOSFET 214,216,218 and 222.In addition, the reduction of the gate-dielectric 212B thickness of the first driver MOSFET 212 even surpassed the gate dielectric thickness of the 3rd driver MOSFET 220.
In the case, the increase of the voltage gain of the first order 206 even surpassed the embodiment among Figure 11 among Figure 12.Therefore, the total voltage gain AV of the signal converter among Figure 12 202
TotalIncrease in addition surpassed the embodiment among Figure 11.But along with the further reduction of the gate-dielectric 212B thickness of the first driver MOSFET 212, the further reduction of the charge transfer effciency CE of the signal converter 202 among Figure 12 has also surpassed the embodiment among Figure 11.Yet, total voltage gain AV
TotalFurther increase can have more than the further reduction of charge transfer effciency CE, so the overall sensitivity S of the signal converter 202 of Figure 12 embodiment
V=CE * AV
TotalStill the overall sensitivity that surpasses prior art.
With reference to Figure 13, for another embodiment of the present invention, the thickness of the gate-dielectric 216B of the second driver MOSFET 216 is substantially the same with the thickness of the gate-dielectric 220B of the 3rd driver MOSFET 220, and is lowered and makes its gate dielectric thickness less than each other MOSFET 212,214,218 and 222.In the case, increased by second and the third level 208 and 210 every grade voltage gain AV
2ndAnd AV
3rdThereby, increased total voltage gain AV of signal converter 202
Total
But the gate dielectric thickness that reduces the second and the 3rd driver MOSFET 216 and 220 does not influence the charge transfer effciency CE of signal converter 202.Therefore, the overall sensitivity S of the signal converter 202 of Figure 13 embodiment
V=CE * AV
TotalThe overall sensitivity that surpasses prior art.In addition, reduce the second and the 3rd driver MOSFET 216 and 220 both overall sensitivity of the signal converter that gate dielectric thickness increased by 202 among Figure 12, even surpass and only reduce the second or the 3rd driver MOSFET 216 or 220 one of them the situations of gate dielectric thickness among Fig. 7 or 10 embodiment.
With reference to Figure 14, for another embodiment of the present invention, the thickness of first, second and the 3rd driver MOSFET212,216 and 220 gate-dielectric 212B, 216B and 220B is substantially the same, and is lowered and makes its gate dielectric thickness less than each load MOSFET 214,218 and 222.In the case, first, second and the third level 206,208 and 210 every grade voltage gain AV have been increased
1st, AV
2ndAnd AV
3rdThereby, increased total voltage gain AV of signal converter 202
Total
Along with the reduction of the gate-dielectric 212B thickness of the first driver MOSFET 212 among Figure 14, the charge transfer effciency CE of signal converter 202 also reduces.But, total voltage gain AV
TotalIncrease can have more than this reduction of charge transfer effciency CE, make the overall sensitivity S of signal converter 202 of Figure 14 embodiment
V=CE * AV
TotalStill the overall sensitivity that surpasses prior art.
With reference to Figure 15, for another embodiment of the present invention, the reduction of the gate-dielectric 212B thickness of the first driver MOSFET 212 even surpass embodiment among Figure 14.Therefore, the gate dielectric thickness of the first driver MOSFET212 less than second with the 3rd driver MOSFET 216 and 220 identical gate dielectric thickness.The second and the 3rd driver MOSFET 216 and 220 gate dielectric thickness are still less than the gate dielectric thickness of each load MOSFET 214,218 and 222 among Figure 15.In addition, the reduction of the gate-dielectric 212B thickness of the first driver MOSFET 212 even surpassed the gate dielectric thickness of the second and the 3rd driver MOSFET 216 and 220.
In the case, the increase of the voltage gain of the first order 206 even surpass embodiment among Figure 14 among Figure 15.Therefore, the total voltage gain AV of the signal converter among Figure 15 202
TotalIncrease in addition surpassed the embodiment among Figure 14.But along with the further reduction of the gate-dielectric 212B thickness of the first driver MOSFET 212, the reduction of the charge transfer effciency CE of signal converter 202 has also surpassed the embodiment among Figure 14 among Figure 15.Yet, total voltage gain AV
TotalFurther increase can have more than the further reduction of charge transfer effciency CE, make the overall sensitivity S of signal converter 202 of Figure 15 embodiment
V=CE * AV
TotalStill the overall sensitivity that surpasses prior art.
In this way, for these embodiment of the present invention shown in Fig. 7 to 15, reduce at least one the subsequent driver MOSFET 216 that is arranged in the signal converter 202 after the first driver MOSFET 212 and/or 220 gate dielectric thickness.By reducing such gate dielectric thickness, increased total voltage gain AV
Total, and can not influence charge transfer effciency CE, so compared with prior art advantageously increased the overall sensitivity S of signal converter 202
V=CE * AV
TotalTherefore, preferably reduce the gate dielectric thickness of at least one subsequent driver MOSFET 216 and/or 220 as much as possible, but it can be subjected to the restriction of the puncture voltage of so thin gate-dielectric.
In addition, can use other gate dielectric thickness that is different from Fig. 7 to 15 illustrated embodiment to concern and implement the present invention.For example, compare the gate dielectric thickness that can further reduce the 3rd driver MOSFET 220 with the second driver MOSFET 216, otherwise the same, make that the described gate dielectric thickness of MOSFET 216 and 220 also can be less than each gate dielectric thickness of each other MOSFET 212,214,218 and 222.For the present invention, usually reduce be arranged on after the first driver MOSFET 212 at least one subsequently MOSFET 216 and/or 220 gate dielectric thickness.
In addition, in some embodiment of Fig. 7 to 15 of the present invention, reduce by the gate dielectric thickness of the first driver MOSFET 212, corresponding reduction charge transfer effciency CE.But, owing to also reduced the gate dielectric thickness of at least one subsequent driver MOSFET 216 and/or 220, so total voltage gain AV
TotalIncrease can have more than this reduction of charge transfer effciency CE, so the overall sensitivity S of signal converter 202
V=CE * AV
TotalStill the overall sensitivity that surpasses prior art.
Aforesaid embodiment be exemplary be not restrictive.Any size that for example, herein point out or illustrational, quantity and material are exemplary.In addition, be to be understood that the term of for example " afterwards " used herein and " subsequently " and phrase are meant relative position and the direction of each several part structure about other parts, rather than refer to be essential or require about any concrete absolute direction of external object.
For example, although Fig. 6 to 15 has exemplified three source follower stage 206,208 and 210, also can use the intergrade between occuping to implement the present invention.The gate dielectric thickness of at least one subsequent driver MOSFET after reduction is arranged on first source follower stage 206 can be implemented the present invention usually so that when increasing the overall sensitivity of signal converter.
In addition, the alternate manner that also can be different from Fig. 6 to 15 illustrated embodiment is implemented the signal converter that has the overall sensitivity of enhancing according to of the present invention.For example, with reference to Figure 16, for another embodiment of the present invention, form the first driver MOSFET 212 in the P trap 402 of isolating, P trap 402 separates with the P trap 230 that wherein is formed with other MOSFET 214,216,218,220 and 222.
In the embodiment of Figure 16, isolate because be connected to the first driver MOSFET212 and other MOSFET 214,216,218,220 and 222 in accumulation district 204, so the P trap 402 of isolating makes signal converter 202 have lower noise.In addition, can reduce the impurity concentration of the P trap 402 of isolation, to reduce by the back of the body grid mutual conductance g of the first driver MOSFET 212
Mb, increase total voltage gain AV of signal converter 202 thus
TotalThe embodiment of Figure 16 is similar to the embodiment of Fig. 7, but has the P trap 402 of isolation for the first driver MOSFET 212.In addition, also can be formed for the P trap 402 of the isolation of the first driver MOSFET 212 for any other embodiment of Fig. 8 to 15.
With reference to Figure 17, for another embodiment of the present invention, the source electrode of the driver MOSFET in each source follower stage 206,208 and 210 and the drain electrode of load MOSFET merge.Therefore, become a knot 404 with reference to the source electrode 212D of Fig. 7 and 17, the first driver MOSFET 212 and the drain electrode 214C merging of the first load MOSFET 214.Similarly, the drain electrode 218C of the source electrode 216D of the second driver MOSFET 216 and the second load MOSFET 218 merges becomes a knot 406.In addition, the drain electrode 222C of the source electrode 220D of the 3rd driver MOSFET 220 and the 3rd load MOSFET 222 merges becomes a knot 406.
Use the embodiment of Figure 17,, can advantageously not use interconnection structure 234,236 to be connected the drain electrode of source electrode and the load MOSFET of driver MOSFET with 238 for each source follower stage 206,208 and 210.In addition, by merging such among Figure 17, can advantageously reduce the source electrode of driver MOSFET and the shared area of drain electrode of load MOSFET.
Figure 18 has shown the signal converter 410 according to another embodiment of the present invention.The signal converter 410 of Figure 18 is similar to the signal converter 202 of Fig. 6.But in Figure 18, load MOSFET 214,218 and 222 source electrode are through same resistance R S ground connection together.Opposite in Fig. 6, load MOSFET214, each source electrode of 218 and 222 pass through resistance R 1, R2 and R3 ground connection respectively.In any case the resistance at load MOSFET source electrode place has increased the pay(useful) load resistance of load MOSFET drain electrode place.
In the embodiment of Figure 18, for the more consistency operation of each source follower stage, the easier control of the resistance value of a resistance R S.On the other hand, owing to be to connect source follower stage by public resistance R S, so signal converter 410 shown in Figure 180 more is easy to generate noise.Therefore, the signal converter 202 of Fig. 6 can be operated in the noise circumstance preferably.
In any case Fig. 6 to 18 has schematically shown exemplary embodiments of the present invention.Can use does not have other embodiment of concrete example and explanation to implement the present invention herein yet.The present invention is only limited to claim and the defined scope of equivalent thereof subsequently.
The present invention requires the priority of korean patent application P2003-0091868 number under the 35 U.S.C. § 119 that submitted on December 16th, 2003, quotes it here in full as a reference.
Claims (62)
1. signal converter that is used for signal charge is converted to voltage comprises:
The first driver FET of received signal electric charge; With
Be connected to the subsequent driver FET of the output of the first driver FET,
Wherein, the gate dielectric thickness of subsequent driver FET is less than the gate dielectric thickness of at least one other FET of signal converter.
2. signal converter according to claim 1, wherein, the first driver FET is used for the first order, and wherein, subsequent driver FET is used for the second level after the first order.
3. signal converter according to claim 2, wherein, the gate dielectric thickness of subsequent driver FET is less than the gate dielectric thickness of the first driver FET.
4. signal converter according to claim 2, wherein, the gate dielectric thickness of subsequent driver FET is substantially equal to the gate dielectric thickness of the first driver FET.
5. signal converter according to claim 2, wherein, the gate dielectric thickness of the first driver FET is less than the gate dielectric thickness of subsequent driver FET.
6. signal converter according to claim 1, wherein, the first driver FET is used for the first order, and wherein subsequent driver FET is used for the third level, and this third level is connected to the first order through the second level with second driver FET.
7. signal converter according to claim 6, wherein, the gate dielectric thickness of subsequent driver FET is less than the gate dielectric thickness of the first driver FET.
8. signal converter according to claim 6, wherein, the gate dielectric thickness of subsequent driver FET is substantially equal to the gate dielectric thickness of the first driver FET.
9. signal converter according to claim 6, wherein, the gate dielectric thickness of the first driver FET is less than the gate dielectric thickness of subsequent driver FET.
10. signal converter according to claim 6, wherein, the gate dielectric thickness of subsequent driver FET is less than the identical gate dielectric thickness of the first and second driver FET.
11. signal converter according to claim 1 also comprises:
Be connected to the last driver FET of the output of subsequent driver FET, be used to produce output voltage.
12. signal converter according to claim 11, wherein, the gate dielectric thickness of subsequent driver FET is less than the gate dielectric thickness of last driver FET.
13. signal converter according to claim 11, wherein, the gate dielectric thickness of subsequent driver FET is substantially equal to the gate dielectric thickness of last driver FET.
14. signal converter according to claim 11, wherein, the gate dielectric thickness of last driver FET is less than the gate dielectric thickness of subsequent driver FET.
15. signal converter according to claim 11, wherein, the gate dielectric thickness of subsequent driver FET less than first with the identical gate dielectric thickness of last driver FET.
16. signal converter according to claim 11 wherein, is connected to separately load FET with each driver FET.
17. signal converter according to claim 16, wherein, each driver FET has identical gate dielectric thickness, and this identical gate dielectric thickness is less than the gate dielectric thickness of at least one load FET.
18. signal converter according to claim 1, wherein, each driver FET is connected to load FET separately.
19. signal converter according to claim 18, wherein, the gate dielectric thickness of subsequent driver FET is less than the gate dielectric thickness of at least one load FET.
20. signal converter according to claim 18, wherein, the gate dielectric thickness of subsequent driver FET is less than each gate dielectric thickness separately of all load FET.
21. signal converter according to claim 18, wherein, each load FET is through separately grounding through resistance.
22. signal converter according to claim 18, wherein, each load FET passes through same resistance ground connection together.
23. signal converter according to claim 1, wherein, the gate dielectric thickness of subsequent driver FET is less than each gate dielectric thickness separately of all other FET of signal converter.
24. signal converter according to claim 1, wherein, the first driver FET is the MOSFET of enhancement mode, and wherein all other FET of signal converter are MOSFET of depletion type.
25. signal converter according to claim 1, wherein, each driver FET is configured to source follower.
26. signal converter according to claim 1, wherein, the first driver FET is formed in the trap of an insulation.
27. signal converter according to claim 1, wherein, signal charge is exported from CCD (charge coupled device).
28. a signal converter that is used for signal charge is converted to voltage comprises:
A plurality of level, each level has driver FET and load FET, prime received signal electric charge, and each subsequently level receive voltage from first prime; And
The device that is used to increase voltage gain and can not reduces the charge transfer effciency of signal converter.
29. signal converter according to claim 28, wherein, each driver FET is configured to source follower.
30. signal converter according to claim 28, wherein, the source electrode of every grade load FET is through separately grounding through resistance.
31. signal converter according to claim 28, wherein, the source electrode of every grade load FET is through same grounding through resistance.
32. signal converter according to claim 28, wherein, the driver FET of prime is formed in the trap of an insulation.
33. signal converter according to claim 28, wherein, the driver FET of prime is made into to make the size of grid capacitance minimum; And
The driver FET of wherein last level is made into to supply the size of the load of enough electric currents are connected to last level with driving output; And
Wherein the driver FET of intergrade is made into to be used for to carry out the size that electric current amplifies between the driver FET of prime and last level.
34. an output circuit that is used for charge-transfer device comprises:
Be used to assemble electric charge from charge-transfer device to produce the zone of signal charge;
Be used for signal charge is converted to the signal converter of voltage, this signal converter comprises:
The first driver FET of received signal electric charge; With
Be connected to the subsequent driver FET of the output of the first driver FET,
Wherein the gate dielectric thickness of subsequent driver FET is less than at least one of signal converter
The gate dielectric thickness of other FET;
Reset transistor is reset to resetting voltage with described zone when being used for conducting; With
Output transistor, when being used for conducting in the future the electric charge of self charge transfer element transfer to described zone.
35. output circuit according to claim 34, wherein, the first driver FET is used for the first order, and wherein subsequent driver FET is used for the first order second level afterwards.
36. output circuit according to claim 34, wherein, the first driver FET is used for the first order, and wherein subsequent driver FET is used for the third level, and this third level is connected to the first order through the second level.
37. output circuit according to claim 34, wherein, signal converter also comprises:
Be connected to the last driver FET of the output of subsequent driver FET, be used to produce output voltage.
38. according to the described output circuit of claim 37, wherein, each driver FET is connected to load FET separately.
39. according to the described output circuit of claim 38, wherein, each driver FET has identical gate dielectric thickness, this identical gate dielectric thickness is less than the gate dielectric thickness of at least one load FET.
40. output circuit according to claim 34, wherein, each driver FET is configured to source follower.
41. output circuit according to claim 34, wherein, each driver FET is connected to load FET separately.
42. according to the described output circuit of claim 41, wherein, the gate dielectric thickness of subsequent driver FET is less than the gate dielectric thickness of at least one load FET.
43. according to the described output circuit of claim 41, wherein, each load FET is through separately grounding through resistance.
44. according to the described output circuit of claim 41, wherein, each load FET is through same resistance ground connection together.
45. output circuit according to claim 34, wherein, the first driver FET is the MOSFET of enhancement mode, and wherein all other FET of signal converter are MOSFET of depletion type.
46. output circuit according to claim 34 wherein, is formed on the first driver FET in the trap of one insulation.
47. output circuit according to claim 34, wherein, charge-transfer device is CCD (charge coupled device).
48. an imaging system comprises:
Photodiode array, each photodiode is assembled signal charge separately;
At least one charge-transfer device is connected to photodiode array, is used to shift each signal charge from each photodiode; With
Be connected to the output circuit of at least one charge-transfer device, this output circuit comprises:
Be used to assemble zone from each signal charge of charge-transfer device transfer; With
Each signal charge that is used for accumulating in described zone converts the signal converter of voltage to,
This signal converter comprises:
Be used to receive the first driver FET of each signal charge; With
Be connected to the subsequent driver FET of the output of the first driver FET,
Wherein the gate dielectric thickness of subsequent driver FET less than signal converter at least
The gate dielectric thickness of other FET.
49. according to the described imaging system of claim 48, wherein, the first driver FET is used for the first order, and wherein subsequent driver FET is used for the first order second level afterwards.
50. according to the described imaging system of claim 48, wherein, the first driver FET is used for the first order, and wherein subsequent driver FET is used for being connected to through the second level third level of the first order.
51. according to the described imaging system of claim 48, wherein, signal converter also comprises:
Be connected to the last driver FET of the output of subsequent driver FET, be used to produce output voltage.
52., wherein, each driver FET is connected to separately load FET according to the described imaging system of claim 51.
53. according to the described imaging system of claim 52, wherein, each driver FET has identical gate dielectric thickness, this identical gate dielectric thickness is less than the gate dielectric thickness of at least one load FET.
54. according to the described imaging system of claim 48, wherein, each driver FET is connected to load FET separately.
55. according to the described imaging system of claim 54, wherein, the gate dielectric thickness of subsequent driver FET is less than the gate dielectric thickness of at least one load FET.
56. according to the described imaging system of claim 54, wherein, each load FET is through separately grounding through resistance.
57. according to the described imaging system of claim 54, wherein, each load FET passes through same grounding through resistance.
58. according to the described imaging system of claim 48, wherein, each driver FET is configured to source follower.
59. according to the described imaging system of claim 48, wherein, the first driver FET is the MOSFET of enhancement mode, and wherein all other FET of signal converter are MOSFET of depletion type.
60. according to the described imaging system of claim 48, wherein, the first driver FET is formed in the trap of an insulation.
61. according to the described imaging system of claim 48, wherein, charge-transfer device is CCD (charge coupled device).
62. according to the described imaging system of claim 48, wherein, described output circuit also comprises:
Reset transistor resets to resetting voltage with described zone when being used for conducting; With
Output transistor, when being used for conducting in the future each signal charge of self charge transfer element transfer to described zone,
Wherein reset transistor is closed when the output transistor conducting.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR91868/2003 | 2003-12-16 | ||
| KR20030091868 | 2003-12-16 | ||
| US10/874,042 US20050127457A1 (en) | 2003-12-16 | 2004-06-22 | Signal charge converter for charge transfer element |
| US10/874,042 | 2004-06-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1674297A true CN1674297A (en) | 2005-09-28 |
Family
ID=34797854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2004100997717A Pending CN1674297A (en) | 2003-12-16 | 2004-12-16 | Signal charge converter for charge transfer element |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2005183978A (en) |
| KR (1) | KR100640605B1 (en) |
| CN (1) | CN1674297A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105572486A (en) * | 2016-01-29 | 2016-05-11 | 西北核技术研究所 | Charge transfer efficiency test method of post-neutron irradiation charge coupled device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100718786B1 (en) | 2005-12-29 | 2007-05-16 | 매그나칩 반도체 유한회사 | Cmos image sensor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000068492A (en) | 1998-08-25 | 2000-03-03 | Nec Corp | Solid-state image pickup device and manufacture of the same |
-
2004
- 2004-12-09 KR KR1020040103635A patent/KR100640605B1/en not_active IP Right Cessation
- 2004-12-16 JP JP2004365083A patent/JP2005183978A/en not_active Withdrawn
- 2004-12-16 CN CNA2004100997717A patent/CN1674297A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105572486A (en) * | 2016-01-29 | 2016-05-11 | 西北核技术研究所 | Charge transfer efficiency test method of post-neutron irradiation charge coupled device |
| CN105572486B (en) * | 2016-01-29 | 2018-07-13 | 西北核技术研究所 | A kind of charge transfer effciency test method after charge coupling device neutron irradiation |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20050061311A (en) | 2005-06-22 |
| JP2005183978A (en) | 2005-07-07 |
| KR100640605B1 (en) | 2006-11-01 |
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