JP2008160344A - Solid-state imaging apparatus, camera system, and driving method of solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus and an imaging apparatus, wherein the current variation, the supply power variation, the bias voltage variation, and the sensor output variation within one horizontal scan period are suppressed. <P>SOLUTION: In the solid-state imaging apparatus, one horizontal scan period includes: a vertical read period 201 when signals outputted from pixels are read out through vertical signal lines; and a horizontal read period 202 when signals of respective columns read out in the vertical read period 201 are successively outputted from an output part SOUT of an output circuit. A current Ih flowing to the output circuit 72 is reduced or stopped in the vertical read period 201, and a current flowing to source-follower circuits of pixels is reduced or stopped in the horizontal read period 202. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and an image signal reading method for the solid-state imaging device.

  In recent years, various signal readout methods for CMOS image sensors have been proposed. In general, a column parallel output type CMOS image sensor that selects pixels in one row in the pixel array and simultaneously reads signals generated in these pixels in the column direction is often used. Among them, a conventional CMOS image sensor disclosed in Patent Document 1 will be described with reference to FIG.

  FIG. 20 is a circuit configuration diagram showing an example of a conventional solid-state imaging device which is a column parallel output type CMOS sensor. In the figure, amplification transistors 1002-1-1, 1002-1-2, and 1002 for amplifying signals generated in the photodiodes 1001-1-1, 1001-1-2, 1001-2-1, and 1001-2-2. -2-1, 1002-2-2, vertical selection transistors 1003-1-1, 1003-1-2, 1003-2-1, 1003-2-2 for selecting a signal readout line, reset signal charges For example, 2 × 2 unit cells each having one set of each component of the reset transistors 1004-1-1, 1004-1-2, 1004-2-1, and 1004-2-2 are arranged two-dimensionally. ing. Actually, more unit cells are arranged.

  In addition, horizontal address lines 1006-1 and 1006-2 wired in the horizontal direction from the vertical shift register 1005 are connected to the gates of the vertical selection transistors, and determine lines from which signals are read. The reset lines 1007-1 and 1007-2 are connected to the gate of the reset transistor. The sources of the amplification transistors 1002-1-1, 1002-2-1 are connected to the vertical signal line 1008-1, and the sources of the amplification transistors 1002-1-2, 1002-2-2 are connected to the vertical signal line 1008-2, respectively. At one end, load transistors 1009-1 and 1009-2 are provided. The other ends of the vertical signal lines 1008-1 and 1008-2 receive signals for one line (one row) via signal capture transistors 1018-1 and 1018-2 that capture signals for one line (one row). Connected to the sample hold capacitors 1019-1 and 1019-2, respectively, and connected to the horizontal signal line 1050 via the horizontal selection transistors 1012-1 and 1012-2 selected by the selection pulse supplied from the horizontal shift register 1013. Has been.

  FIG. 21 is a timing diagram showing pulse signals for driving a conventional solid-state imaging device. As shown in the figure, when the address pulse 1101 for setting the horizontal address line 1006-1 to the high level is applied, only the selection transistors 1003-1-1 and 1003-1-2 in this row are turned on, and the amplification transistors in this row are turned on. 1002-1-1, 1002-1-2 and load transistors 1009-1, 1009-2 constitute a source follower circuit. The gate voltages of the amplification transistors 1002-1-1, 1002-1-2, that is, the photodiodes A voltage substantially equal to the voltage appears on the vertical signal lines 1008-1 and 1008-2, respectively. At this time, a clamp pulse 1109 is applied to the common gate 1055 of the clamp transistor, the clamp transistors 1017-1 and 1017-2 are turned on, and the voltage on the clamp transistor side of the clamp capacitors 1016-1 and 1016-2 is shared by the clamp transistors. After fixing to the voltage of the source 1054, it is turned OFF.

  Next, the signal reset pulse 102-1 is applied from the reset line 1007-1 to the reset transistors 1004-1-1 and 1004-1-2, and the signals of the photodiodes 1001-1-1 and 1001-1-2 are applied. When the electric charge is discharged, a noise voltage due to threshold variation of the amplification transistors 1002-1-1 and 1002-1-2 appears on the vertical signal lines 1008-1 and 1008-2.

  At this time, the voltage on the clamp transistor side of the clamp capacitors 1016-1 and 1016-2 is a voltage change of the vertical signal line, that is, a noise-free signal voltage obtained by subtracting the noise voltage from the signal voltage, and the common source 1054 of the clamp transistor. Appears superimposed on the voltage of. Here, the voltages of the common sources 1007-1 and 1007-2 also do not include noise.

  Next, a sample and hold pulse 1110 is applied to the common gate 1056 of the sample and hold transistors, and the signal voltage without noise is transmitted to the hold capacitors 1019-1 and 1019-2 through the sample and hold transistors 1018-1 and 1018-2. .

  Next, horizontal selection pulses 1104-1 and 1104-2 are sequentially applied from the horizontal shift register 1013 to the gates of the horizontal selection transistors 1012-1 and 1012-2, and an output signal 1105 for one row is output from the horizontal signal line 1050. 1, 1105-2 is taken out.

  By repeating the above operation sequentially from the next line to the next line, signals from all the pixels arranged in a two-dimensional manner can be read out.

  However, in this type of solid-state imaging device, since current always flows through the source follower circuit including the load transistors 1009-1 and 1009-2 shown in FIG. 20, power consumption tends to increase. When the solid-state imaging device is applied to a television camera, the number of cells in the horizontal direction is at least 600 or more, so even if the current flowing through one cell is small, the entire current becomes very large.

In order to solve this problem, Japanese Patent Application Laid-Open No. H10-228561 passes a current through a load transistor when a signal generated by a photodiode is taken out to a vertical signal line, and does not pass a current through the load transistor when a signal is not taken out or is small. A technique for making an electric current is disclosed. As shown in FIG. 20, the voltage applied to the common gate 1051 of the load transistors 1009-1 and 1009-2 can be varied, and the solid-state imaging device is driven as shown in the timing chart of FIG. During the period 1201 in which the photodiode signal is taken out from the vertical signal lines 1008-1 and 1008-02 to the amplified signal storage capacitor, the load transistor activation pulse 1106 is applied to the common gate 1051 of the load transistors 10091 and 1009-2, and the load A current is passed through the transistor. In the other period 1202, the gate voltage of the load transistor is reduced and the current is reduced. By doing so, power consumption can be reduced.
Japanese Patent Laid-Open No. 9-247537

  In the current consumption suppression method disclosed in Patent Document 1, a current is supplied to the load transistor only during a period 1201 in which a photodiode signal is extracted from the vertical signal line to the amplified signal storage capacitor, and a current is supplied during the other period 1202. Therefore, there is a first problem that current fluctuation within one horizontal scanning period becomes large.

  Further, the conventional solid-state imaging device has a second problem that the power supply voltage supplied to the solid-state imaging device varies greatly within one horizontal scanning period due to a large current fluctuation within one horizontal scanning period. is doing.

  Further, in the conventional solid-state imaging device, the power supply voltage supplied to the solid-state imaging device greatly varies within one horizontal scanning period, so that the bias voltage generated within the solid-state imaging device varies greatly within one horizontal scanning period. There is a third problem.

  In the conventional solid-state imaging device, since the bias voltage generated in the solid-state imaging device greatly varies within one horizontal scanning period within one horizontal scanning period, the sensor output varies greatly during the horizontal readout period 1202. There was also a fear (fourth problem).

  The first to fourth problems will be described in detail.

  FIG. 22A is an example of a camera system using a solid-state imaging device, and FIG. 22B is a diagram for explaining a driving method of a conventional camera system.

  A DSP (Digital Signal Proccessing) supplies a power supply voltage and a control pulse to the solid-state imaging device. The solid-state imaging device outputs a sensor signal to the DSP. Focusing on the power supply voltage, there is a signal line for supplying the power supply voltage between the DSP and the solid-state imaging device. The signal line has a wiring resistance R (1094) and a wiring load capacitance C1 (1095). The wiring resistance R and load capacitance C1 of the signal line may include the output resistance and output load capacitance of the power supply voltage supply source in the DSP.

  In FIGS. 22A and 22B, I (t) represents a current flowing through a signal line for supplying a power supply voltage to the solid-state imaging device. When the amount of current consumed by the solid-state imaging device changes, the amount of current I (t) supplied to the solid-state imaging device also changes. As a result, the voltage VDD (t) supplied to the solid-state imaging device changes by a current change ΔI (t) × R. This is the first and second problems described above.

  Further, when the power supply voltage supplied to the solid-state imaging device changes, the bias voltage Bias (t) generated by the solid-state imaging device also changes. FIG. 22A shows an example of a bias circuit that generates a bias voltage. In this example, a transistor is provided in series between the bias circuit power supply and the ground, and the bias voltage Bias is generated using a divided voltage applied according to the resistance value of the transistor. Therefore, the third problem described above that the Bias output changes when the power supply voltage changes occurs.

  FIG. 22B is a timing chart showing temporal changes in one horizontal scanning period of current consumption, power supply voltage, and bias voltage in a conventional solid-state imaging device.

  In order to reduce the current I (t) at the boundary between the horizontal blanking period 1201 for performing vertical reading and the period 1202 for performing horizontal reading, as shown in FIG. 22B, the power supply voltage VDD (t) is set to the vertical reading period. It decreases to 1201 (first and second problems). The slope of the power supply voltage change with respect to the time axis is determined by the time constant R × C1 of the power supply line. Here, Iv is a current related to vertical reading, and Ih is a current related to horizontal reading.

  Further, the bias voltage Bias also decreases during the vertical readout period 1201 as shown in FIG. 22B (third problem).

  In particular, the present inventors have discovered that when the power supply voltage and the bias voltage fluctuate in the horizontal readout period 1202, a new fourth problem occurs in addition to the first to third problems. This problem will be described in detail with reference to FIGS. 20 and 23 to 25.

  The output circuit shown in FIG. 20 includes an output circuit 1072 that amplifies a signal on the horizontal signal line 1050 and an output reset transistor 1046 that resets an input terminal of the output circuit 1072. A φSIGRS pulse is applied to the gate input of the reset transistor to reset the input signal.

  FIG. 23 is a timing chart of various signals in the output circuit. When a pulse is applied to the gates of the horizontal selection transistors 1012-1 and 1012-2, an output signal SOUT is output from the output unit of the output circuit 1072. On the other hand, when φSIGRS is applied to the gate of the output reset transistor 1046, the output signal SOUT output from the output circuit 1072 is reset to the reference voltage VCL.

  FIG. 24 is a timing chart showing the timing of vertical reading and horizontal reading. Here, a description will be given by taking reading at the leftmost pixel row shown in FIG. 20 as an example.

  First, when a clamp pulse is applied to the gate (common gate 55) of the clamp transistor 1017-1, the voltage applied to the hold capacitor 1019-1 is clamped to VCL. Next, by applying a reset pulse to the common gate 1007-1 of the reset transistor, “VCL + signal amplitude” from which noise has been removed is read out to the hold capacitor unit 1019. This operation is performed simultaneously in each pixel column.

  Subsequently, when a selection pulse is applied to the horizontal selection transistor 1012-1, a signal of “VCL voltage fluctuation + signal amplitude” is amplified by the output circuit 1072 and output as an output signal SOUT.

  Next, the fourth problem will be described using the circuit configuration and drive timing of the conventional solid-state imaging device described above. FIG. 25 is obtained by adding the power supply voltage VDD, the current Iv related to vertical reading, the current Ih related to horizontal reading, the total current I = Iv + Ih, and φSIGRS to the timing chart shown in FIG.

  As described in the first to third problems, the bias voltage VCL varies at the boundary between the vertical readout period 1201 and the horizontal readout period 1202 within one horizontal scanning period. Since the voltage of the output signal SOUT at the time of reset is VCL, SOUT that is the pixel signal output varies as shown in the figure in the horizontal readout period. Specifically, the first column signal read to the horizontal signal line is “VCL voltage fluctuation + signal amplitude”, and a signal having a higher amplitude than the signal amplitude read from the pixel is output. Is selected, the signal amplitude converges to the signal amplitude read from the pixel as shown in the figure. In this case, as a defect of the output image, a phenomenon that the left side of the screen floats white occurs (fourth problem). Depending on the polarity of the signal, an image defect may occur in which the left side of the screen sinks black.

  In view of the above, an object of the present invention is to provide a solid-state imaging device and an imaging device in which current fluctuation, power supply fluctuation, bias voltage fluctuation, and sensor output fluctuation are suppressed in one horizontal scanning period.

  The solid-state imaging device of the present invention includes a photoelectric conversion unit and a signal amplification unit that amplifies the charge generated by the photoelectric conversion unit, and a plurality of pixels arranged in a two-dimensional matrix, and the plurality of pixels And a vertical signal line connected to each pixel and connected to one end of each of the vertical signal lines and supplying a current to the signal amplifier. A source, a row signal accumulator connected to the vertical signal line and accumulating signals from the pixels transmitted through the vertical signal line, and a horizontal signal from which the signal accumulated in the row signal accumulator is read out A signal line; an output circuit for outputting the signal read out through the horizontal signal line; and a first current control circuit for controlling an amount of current flowing through the output circuit.

  According to this configuration, since the first current control circuit changes the current flowing through the output circuit, the current flowing through the output circuit is stopped or reduced for a predetermined period, so that the power supply voltage supply unit (for example, a DSP or the like) The change in current supplied to the imaging device can be reduced throughout one horizontal scanning period. For this reason, in the solid-state imaging device of the present invention, fluctuations in the power supply voltage and bias voltage can be suppressed, and fluctuations in the output voltage can be reduced. Furthermore, since the fluctuation of the output voltage is suppressed, the deterioration of the image quality of the output image can be suppressed. In addition, current consumption can be reduced as compared with the case where the current flowing through the output circuit is not changed.

  In particular, by reducing or stopping the current flowing through the output circuit during the vertical readout period, fluctuations in the amount of current flowing through the solid-state imaging device can be effectively suppressed, and fluctuations in the output voltage can also be effectively suppressed.

  The first current control circuit may further control the amount of current flowing from the vertical line driving current source to the signal amplification unit. In this case, it is possible to more effectively suppress fluctuations in the current supplied to the solid-state imaging device throughout one horizontal scanning period.

  Note that various amplifiers may be provided in the output circuit, and the first current control circuit may be configured to control the amount of current flowing through this amplifier.

  Further, the first current control circuit amplifies the amount of current flowing from the vertical line driving current source to the signal amplifying unit during the horizontal readout period, and the signal amplification from the vertical line driving current source during the vertical readout period. It may be configured to be smaller than the amount of current flowing through the section.

  Further, in one horizontal scanning period, a transition period in which readout of the signal accumulated in the row signal accumulation unit to the horizontal signal line is not performed between the vertical readout period and the horizontal readout period, The current control unit may reduce an amount of current flowing from the vertical line driving current source to the signal amplification unit between the transition period and the vertical readout period. In this case, even if the bias voltage fluctuates after the end of the vertical reading period, a signal can be read from the output circuit with the bias voltage being stable, which is preferable.

  The first current control circuit further includes a column amplifier provided for each vertical signal line, amplifying the signal input from the pixel via the vertical signal line and outputting the amplified signal to the row signal storage unit. The configuration may be such that the amount of current flowing through the column amplifier is controlled. In this case, for example, the first current control circuit supplies the solid-state imaging device by making the amount of current flowing through the column amplifier during the horizontal readout period smaller than the amount of current flowing through the column amplifier during the vertical readout period. The variation in the amount of current that is generated can be more effectively suppressed. The transistor constituting the solid-state imaging device of the present invention is preferably an N channel type or P channel type MISFET (MOSFET).

  The camera system of the present invention includes a photoelectric conversion unit and a signal amplification unit that amplifies the electric charge generated by the photoelectric conversion unit, and includes a plurality of pixels that are two-dimensionally arranged in a matrix, and the plurality of pixels. A vertical signal line wired for each column and connected in common to one column of pixels, and a vertical line driving current source connected to one end of each of the vertical signal lines and supplying a current to the signal amplifier A row signal accumulator that is connected to the vertical signal line and accumulates a signal from the pixel transmitted through the vertical signal line, and a horizontal signal from which the signal accumulated in the row signal accumulator is read out A solid-state imaging device having a line, an output circuit for outputting the signal read through the horizontal signal line, and a current control circuit for controlling an amount of current flowing through the output circuit, and the output circuit Processing the output signal, and A power supply voltage and current to the body imaging device, and a DSP that outputs the control signal for controlling the amount of current flowing to the solid-state imaging device, the current control circuit based on the control signal Controls the amount of current flowing through the output circuit.

  With this configuration, fluctuations in the amount of current supplied from the DSP to the solid-state imaging device can be suppressed, so that deterioration of the output image can be effectively suppressed.

  The solid-state imaging device driving method of the present invention includes a photoelectric conversion unit and a plurality of pixels that are two-dimensionally arranged in a matrix having a signal amplification unit that amplifies a charge generated by the photoelectric conversion unit. A vertical signal line that is wired for each of the plurality of pixels and connected in common to one column of pixels, and is connected to one end of each of the vertical signal lines, and supplies a current to the signal amplifier. Driving a solid-state imaging device having a vertical line driving current source, a row signal storage unit connected to the vertical signal line, a horizontal signal line, an output circuit connected to the horizontal signal line, and a current control circuit A method of reading a signal from a pixel in a selected row through each vertical signal line and outputting the signal to the row signal storage unit during a vertical readout period; and a horizontal readout period. Stored in the row signal storage section of each column A step (b) of inputting the signal to the output circuit via the horizontal signal line and sequentially outputting the signal for one row from the output circuit; and during the vertical readout period, the current control circuit However, the amount of current flowing through the output circuit is made smaller than the amount of current flowing through the output circuit during the horizontal readout period.

  With this method, the change in the current supplied from the power supply voltage supply unit (for example, DSP) to the solid-state imaging device can be reduced throughout one horizontal scanning period. Therefore, according to the driving method of the present invention, fluctuations in the power supply voltage and bias voltage can be suppressed, and fluctuations in the output voltage can be reduced. Furthermore, since the fluctuation of the output voltage is suppressed, the deterioration of the image quality of the output image can be suppressed. In addition, current consumption can be reduced as compared with the case where the current flowing through the output circuit is not changed.

  In the horizontal readout period, the current control circuit causes an amount of current flowing from the vertical drive current source to the signal amplifier to be smaller than an amount of current flowing to the signal amplifier in the vertical readout period. Is preferred.

  When the solid-state imaging device further includes a column amplifier provided for each of the vertical signal lines, the column amplifier amplifies the input signal and stores the row signal during the vertical readout period. In the horizontal readout period, the current control circuit preferably causes the amount of current flowing through the column amplifier to be smaller than the amount of current flowing through the column amplifier during the vertical readout period.

  According to the solid-state imaging device according to the present invention, the first current control circuit can change the current flowing through the output circuit. Therefore, the current flowing through the output circuit is stopped or reduced for a predetermined period, thereby supplying the power supply voltage. The change in the current supplied from the unit to the solid-state imaging device can be reduced throughout one horizontal scanning period. For this reason, in the solid-state imaging device of the present invention, fluctuations in the power supply voltage and bias voltage can be suppressed, and fluctuations in the output voltage can be reduced. Furthermore, since the fluctuation of the output voltage is suppressed, the deterioration of the image quality of the output image can be suppressed. In addition, current consumption can be reduced as compared with the case where the current flowing through the output circuit is not changed.

  In particular, by reducing or stopping the current flowing through the output circuit during the vertical readout period, fluctuations in the amount of current flowing through the solid-state imaging device can be effectively suppressed, and fluctuations in the output voltage can also be effectively suppressed. Furthermore, it is possible to effectively suppress fluctuations in the output voltage by stopping or reducing the current flowing through the signal amplifier and column amplifier during the horizontal readout period.

  As a result of studying various measures for stabilizing the power supply voltage of the bias voltage in the solid-state imaging device, the inventors of the present application have found that the current Ih supplied from the power supply terminal to the horizontal scanning circuit (FIG. 22B, 25) and the fluctuation I of the current Iv supplied to the pixel readout circuit for reading out the signal from the pixel via the vertical signal line, if the fluctuation in the bias I is suppressed through one horizontal scanning period, the fluctuation in the bias voltage can be reduced. I thought it would be effectively suppressed. For this purpose, it is effective to stop or reduce the current flowing through the circuit related to signal readout via the vertical signal line during the horizontal readout period and to stop or reduce the current flowing through the horizontal scanning circuit during the vertical readout period. I came up with it. In the following embodiments, a circuit for realizing such driving and details of the driving method will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a circuit configuration diagram showing a solid-state imaging device according to a first specific example of the first embodiment of the present invention.

  As shown in the figure, the solid-state imaging device of the present embodiment is commonly connected to a pixel array in which unit cells (pixels) are arranged two-dimensionally by n rows × m columns, and unit cells for one column, Also, vertical signal lines 8-1, 8-2,..., 8-m provided for each column, a vertical shift register 5, and a horizontal address line wired from the vertical shift register 5 in the horizontal direction (row direction). 6-n, vertical signal line reset transistors 15-1, 15-2,..., 15-m, and clamp capacitors 16-1, 16-2,. Sample hold transistors 18-1, 18-2, ..., 18-m, hold capacitors 19-1, 19-2, ..., 19-m, horizontal selection transistors 12-1, 12-2, ..., 12-m and an output reset transistor 46. Further, the solid-state imaging device includes a timing generator 71, a current control circuit 70, an output circuit 72, and a horizontal signal line 50 commonly connected to the horizontal selection transistors 12-1, 12-2, ..., 12-m. , 9-m are connected to one ends of the vertical signal lines 8-1, 8-2,..., 8-m of each column.

  Each unit cell includes a photodiode 1 that performs photoelectric conversion, and a floating diffusion unit (FD unit, signal charge storage unit; output unit of the photodiode 1) that stores charges photoelectrically converted by the photodiode (photoelectric conversion unit) 1. Vertical selection that selects a line from which the voltage signal is read out, and an amplification transistor (signal amplification unit) 2 that amplifies and outputs the charge signal accumulated in the FD unit as a voltage signal A transistor 3 and a reset transistor 4 for resetting the electric charge accumulated in the photodiode 1 are provided. FIG. 1 shows an example in which unit cells are arranged in a two-dimensional matrix with n rows × m columns. Here, photodiodes 1-1-1, 1-1-2, ..., 1-nm, amplification transistors 2-1-1, 2-1-2, ..., 2-nm, vertical selection transistors 3-1-1, 3-1-2,..., 3-nm, reset transistors 4-1-1, 4-1-2,. When there is no signal, they are expressed as a photodiode 1, an amplification transistor 2, a vertical selection transistor 3, and a reset transistor 4, respectively. Hereinafter, other components such as the vertical signal line 8, the horizontal address line 6, the vertical signal line reset transistor 15, the clamp capacitor 16, the sample hold transistor 18, the hold capacitor 19, and the horizontal selection transistor 12 are also expressed in the same manner.

  In the solid-state imaging device according to the present embodiment, the horizontal address lines 6 in each row are connected to the gates of the vertical selection transistors 3 in the corresponding rows, respectively, and determine lines from which signals are read. Further, the reset lines 7-1, 7-2,..., 7-n are connected to the gates of the reset transistors 4 in the corresponding rows, respectively. The source of the amplification transistor 2 in each column is connected to the vertical signal line 8 in the corresponding column, and a load transistor (vertical signal line driving auxiliary unit) 9 is provided at one end thereof. The load transistor 9 is arranged for each pixel column and functions as a current source for the amplification transistor 2 in one column.

  The other end of the vertical signal line 8 of each column is connected to a hold capacitor 19 that stores a signal for one line (one row) via a signal capturing transistor 18 that takes a signal for one line (one row) in FIG. And connected to the horizontal signal line 50 via the horizontal selection transistor 12 selected by the selection pulse supplied from the horizontal shift register 13.

  The timing generator 71 is a circuit that generates various pulses for driving the pixel readout circuit. Here, the “pixel readout circuit” includes the vertical shift register 5, the output reset transistor 46, the vertical signal line reset transistor 15, the clamp capacitor 16, the clamp transistor 17, the sample hold transistor 18, the hold capacitor 19, and the like. And The current control circuit 70 is a circuit for changing a current flowing through various amplifier circuits, and includes a bias circuit 74 that generates a bias voltage and a bias output control circuit 75 (see FIG. 3). The output circuit 72 amplifies the signal read out to the horizontal signal line 50. The output reset transistor 46 resets the state of the horizontal signal line 50 and the input terminal of the output circuit 72. SOUT indicates an output signal from the sensor output terminal (the output section of the output circuit 72).

  Next, FIG. 2 is a timing diagram of pulse signals for driving the solid-state imaging device of the present embodiment.

  As shown in the figure, for example, when an address pulse 101-1 for setting the horizontal address line 6-1 to a high level is applied, the vertical selection transistors 3-1-1, 3-1-2,. 1-m is turned ON, and the amplification transistors 2-1-1, 2-1-2,..., 2-1-m and the load transistors 9-1, 9-2,. A source follower circuit is formed for each unit cell, and gate voltages of the amplification transistors 2-1-1, 2-1-2,..., 2-1-m, that is, photodiodes 1-1-1, 1-1-2. ,..., 1-1-m appears on the vertical signal lines 8-1, 8-2,.

  At this time, by applying a clamp pulse 109 to the common gate 55 of the clamp transistor 17, the clamp transistors 17-1 and 17-2 are turned on, and the voltage on the clamp transistor side of the clamp capacitors 16-1 and 16-2 is set to the clamp transistor. After being fixed at the voltage VCL of the 17 common sources, it is turned OFF. Note that VCL is a clamp voltage of the noise canceling circuit and is also a reset voltage of the output circuit 72.

  Next, the signal reset pulse 102-1 is applied from the reset line 7-1 to the reset transistors 4-1-1, 4-1-2,... .., 8-m appears on the signal lines 8-1, 8-2,.

  At this time, the voltage on the clamp transistor side of the clamp capacitors 16-1 and 16-2 is the voltage change of the vertical signal line, that is, the noise-free signal voltage obtained by subtracting the noise voltage from the signal voltage is the voltage VCL of the common source of the clamp transistors. Appears superimposed on. The common source voltage is also free of noise.

  Next, the sample hold pulse 110 is applied to the common gate 56 of the sample hold transistor 18 with a slight delay from the clamp pulse 109, and the signal voltage without noise is applied to the sample hold transistors 18-1, 18-2,. , 19-m are transmitted to the hold capacitors 19-1, 19-2,. The above operation is performed within the vertical readout period 201.

  Next, in the horizontal readout period 202, horizontal selection pulses 104-1, 104-2,... Are sequentially applied from the horizontal shift register 13 to the horizontal selection transistors 12-1, 12-2, 12-3,. Output signals 105-1 and 105-2 for one row are sequentially taken out from the horizontal signal line 50.

  All the two-dimensional signals can be read out by sequentially repeating the above operations performed within one horizontal scanning period from the next line to the next line.

  In the above description, the current Iv flowing through the circuit related to vertical reading specifically indicates the total value of the current flowing through the source follower circuit of each unit cell (pixel) in the example of FIG. Furthermore, the current Ih flowing through the circuit related to horizontal reading specifically indicates the current flowing through the output circuit 72 in the example of FIG. As shown in FIG. 2, the solid-state imaging device according to the present embodiment is characterized in that the current Ih flowing through the output circuit 72 is reduced or stopped in the vertical readout period 201 and the pixel source follower circuit is used in the horizontal readout period 202. It is to reduce or stop the flowing current.

  With this feature, in the solid-state imaging device of the present embodiment, it is possible to suppress fluctuations in the value of the current I (I = Ih + Iv) supplied from the power supply circuit within one horizontal scanning period. Here, the power supply circuit means a circuit that supplies a reference voltage VCL, a power supply voltage, a bias voltage, and the like to a circuit related to vertical reading and a circuit related to horizontal reading.

  Furthermore, as a result of suppressing the current fluctuation, the fluctuation of the sensor output SOUT in the horizontal readout period 202 can be suppressed by suppressing the voltage fluctuation of the power supply voltage, the bias voltage, particularly the reference voltage VCL. As a result, it is possible to suppress the occurrence of problems on the output image such that the left side of the screen floats white or sinks black.

  Further, in order to reduce or stop the current flowing through the output circuit 72 during the vertical readout period 201, the total current consumption through one horizontal scanning period is suppressed as compared with the conventional driving method shown in FIG. Can do.

  Next, means for changing the current flowing in the source follower circuit and output circuit 72 of the pixel will be described with reference to FIG. FIG. 3 is a diagram illustrating a specific configuration example of the current control circuit 70 and the output circuit 72. The output circuit 72 shown in the figure includes a drain-coupled source follower circuit including an amplification transistor 45 and a load transistor 44 that supplies current in addition to the output reset transistor 46. The source follower circuit of each pixel has the same circuit configuration. In FIG. 3, φSIGRS is a reset pulse for the input terminal of the output circuit 72, and φBIASSW 2 is a current control pulse for the output circuit 72.

  As shown in FIG. 3, the current control circuit 70 includes a bias circuit 74 that generates a bias voltage using resistance division by the resistance components of the transistors 37 and 38, and a bias output control that receives an output from the bias circuit 74. The circuit 75 includes a capacitive element 39 connected to a wiring connecting the bias circuit 74 and the bias output control circuit 75.

  The bias circuit 74 stops or reduces the current by dropping the gate voltage of the load transistor 44 to the “Low” voltage of the ground voltage. The bias output control circuit 75 is means for switching the gate voltage of the load transistor 44, and is a circuit that electrically disconnects (impedance cut) the output BIASIN3 of the bias circuit 74.

  The bias output control circuit 75 includes a switching transistor 40 in which φBIASSW2 is input to the gate, and a switching transistor 42 in which the inverted signal of φBIASSW2 is input to the gate by the inverter 43.

  Next, the operation of the bias output control circuit will be described. First, when φBIASSW2 is at “High” level, the switching transistor 40 is turned on, and a bias voltage is supplied to the output amplifier circuit. On the other hand, when φBIASSW2 becomes a low level, the switching transistor 40 is turned OFF, and the supply of the bias voltage is stopped. At this time, the switching transistor 42 is turned ON, a low level voltage is supplied to the output circuit 72, and the current flowing through the output amplifier is stopped or reduced. Therefore, for example, the current flowing through the output circuit 72 by the bias circuit 74 and the bias output control circuit 75 during the vertical readout period can be reduced.

  Although the source voltage of the switching transistor 42 shown in FIG. 3 is ground, a current flowing through the output circuit 72 may be adjusted by connecting a bias voltage generation circuit lower than BIASIN3 to the source terminal.

  A characteristic of the switching transistor 40 is that the bias voltage can be switched at high speed. That is, when φBIASSW2 is switched from the high level to the low level, the bias charge is held in the capacitive element 39 in the high state. When φBIASSW2 is switched to the low level, the switching transistor 40 is turned off, so that the charge / discharge operation of the charge held in the capacitive element 39 becomes unnecessary, and thus the low level voltage is supplied to the load transistor 44 at a high speed. It becomes possible.

  In addition, when switching from the low state to the high state, the charge / discharge operation to the capacitive element 39 is not necessary, so that the bias voltage can be supplied at high speed.

  Note that in the solid-state imaging device of the present embodiment, a noise cancellation circuit that is connected to the vertical signal line 8 of each column and removes noise included in the signal may be provided. In this case, the current control circuit 70 controls the amount of current supplied to the noise cancellation circuit to be smaller in the horizontal readout period than in the vertical readout period.

-Other specific examples of this embodiment-
FIG. 4 is a circuit diagram illustrating configurations of a current control circuit and an output circuit in the solid-state imaging device according to the second specific example of the first embodiment. In the solid-state imaging device according to this example, circuits other than those shown in FIG. 4 are the same as those in the first example, and therefore only the characteristic part of this example will be described below.

  As shown in FIG. 4, in the solid-state imaging device of this example, the output circuit 72 has a plurality of load transistors for supplying current. Further, the load transistor 44-1 is connected to the bias output control circuit 75, and stops or reduces the current supply by the control by φBIASSW2 switched to the high level or the low level.

  On the other hand, the gate of the load transistor 44-2 is not connected to the bias output control circuit 75 but is connected to the output section of the bias circuit 74, so that a constant current is always supplied to the output circuit 72. That is, it is possible to arbitrarily adjust the current in the vertical readout period 201 and the horizontal readout period 202 by adjusting the sizes of the load transistors 44-1 and 44-2.

  In the present embodiment, a configuration is adopted in which two load transistors included in the output circuit 72 are provided in parallel, but three or more load transistors may be provided. For example, when there is individual variation in the impedance of a power line as a camera system, the current amount consumed by the solid-state imaging device is constant throughout one horizontal scanning period by controlling a plurality of load transistors as a camera system. It becomes possible to.

  FIG. 5 is a circuit diagram showing configurations of a current control circuit and an output circuit in the solid-state imaging device according to the third specific example of the first embodiment. Note that in the solid-state imaging device according to this example, circuits other than those shown in FIG. 5 are the same as those in the first example, and therefore only the features of this example will be described below. The solid-state imaging device according to this example is characterized in that a source-coupled single amplifier is provided as the output circuit 72.

  As shown in FIG. 5, the current control circuit 70 according to this specific example has the same basic configuration as the current control circuits according to the first and second specific examples, but is an n-channel type whose source is grounded. A difference is that a p-channel type switching transistor 41 in which a power supply voltage is supplied to the source is provided instead of the switching transistor 42.

  Further, the output circuit 72 according to this specific example includes a cascode connection to the amplification transistor 48 and the amplification transistor 48 in addition to the amplification transistor 45 to which an image signal is input to the gate and the load transistor 44 to which BIAS3 is input to the gate. Cascode transistor 49, a capacitive element C2 interposed between the source of the amplification transistor 45 and the gate of the amplification transistor 48, load transistors 47-1 and 47-2 for supplying current to the output circuit 72, and The output portion OUT connected to the drains of the load transistors 47-1 and 47-2 and the drain of the cascode transistor 49 and the gate and the output portion of the capacitive element C2 and the second amplification transistor are interposed in parallel. The capacitor C3 and the transistor 61 are included. The capacitive element C2 determines the gain of the output circuit 72. The transistor 61 is for resetting the input unit and output unit of the amplifier.

  As described above, even when a source-coupled single amplifier is provided as the output circuit 72, the gate voltage of the load transistor 47-1 is controlled in the same manner as in the solid-state imaging device according to the second specific example shown in FIG. The current consumption can be changed. Even when the load transistor 47-2 is not provided, it is possible to adjust the amount of current flowing through the output circuit 72.

  In this specific example, since the switching transistor 41 in the bias output control circuit 75 is a P-channel type, the configuration of the output circuit is changed so that the polarity is opposite to that of the first and second specific examples.

  Next, the operation of the bias output control circuit 75 will be described.

  First, when φBIASSW2 becomes a high voltage, the switching transistor 40 is turned on and a bias voltage is supplied to the output circuit 72.

  On the other hand, when φBIASSW2 becomes low level, the switching transistor 40 is turned off and the switching transistor 41 is turned on, whereby the power supply voltage VDD is supplied to the gate of the load transistor 47-1 of the output circuit 72 and flows to the load transistor 47-1. The current stops or decreases.

  Next, FIG. 6 is a circuit diagram illustrating configurations of a current control circuit and an output circuit in the solid-state imaging device according to the fourth specific example of the first embodiment. The solid-state imaging device according to the fourth specific example is characterized in that the current flowing through the output circuit 72 is stopped by controlling the gate voltage of the cascode transistor of the output circuit 72.

  As shown in FIG. 6, the circuit configuration of the current control circuit 70 of this example is the same as the current control circuit shown in FIG. 4, and the gate of the cascode transistor 49 in the output circuit 72 is connected to the switching transistor 40 and the switching transistor 42. The connection is different from the second specific example.

  Therefore, when φBIASSW2 becomes high level, the current control circuit 70 supplies a bias voltage to the output circuit 72, and a current flows through the output circuit 72.

  On the other hand, when φBIASSW2 becomes low level, the current control circuit 70 supplies a low-level output voltage to the output circuit 72, and the current flowing through the output circuit 72 is stopped or reduced.

  As described above, the characteristic difference between the output circuit according to the third specific example shown in FIG. 5 and the output circuit according to the fourth specific example shown in FIG. 6 is the output from the output unit OUT in the current stopped state. In the voltage state.

  That is, in the third specific example shown in FIG. 5, since the load transistor 47-1 is turned off when the current is stopped, the output voltage from the output unit OUT is at a low level. On the other hand, in the fourth specific example shown in FIG. 6, since the cascode transistor 49 is turned off when the current is stopped, the output voltage becomes a high level.

  Further, in the fourth specific example shown in FIG. 6, the gate voltage of the load transistor 47 is a fixed bias voltage, whereas in the third specific example shown in FIG. 5, the fixed voltage is applied to the gate terminal of the amplification transistor 48. Is not applied, and the impedance of the gate terminal becomes somewhat high. For this reason, in the output circuit according to the fourth specific example, the output fluctuation when the current is stopped is smaller than that of the output circuit according to the third specific example.

  On the other hand, the output circuit of the third specific example shown in FIG. 5 can facilitate current control by providing a plurality of load transistors as described above.

  Next, FIG. 7 is a circuit diagram showing configurations of a current control circuit and an output circuit in the solid-state imaging device according to the fifth specific example of the first embodiment.

  As shown in the figure, the solid-state imaging device of this example is characterized in that the output circuit 72 is configured by a source coupled differential amplifier. The current control circuit 70 has the same configuration as that in FIG. According to the output circuit 72 of this example, as in FIG. 4, a load transistor that supplies current to the output circuit 72 (that is, supplies current to a transistor that receives an input signal and a transistor that receives an inverted input signal). By controlling the bias voltage 62-1, the current flowing through the output circuit can be changed.

  It should be noted that the specific example of the solid-state imaging device of the present embodiment described above is such that in one horizontal scanning period, Ih is stopped or reduced during the vertical readout period, and Iv is stopped or reduced during the horizontal readout period. It is an example of the circuit structure for implement | achieving the drive method of invention, The circuit structure of the solid-state imaging device of this invention is not limited to the above-mentioned specific example.

(Second Embodiment)
FIG. 8A is a circuit diagram showing a configuration example of a camera system according to the second embodiment of the present invention.

  As shown in the figure, the camera system of this embodiment includes a DSP 92 and a solid-state imaging device 93 according to the first embodiment. Between the DSP 92 and the solid-state imaging device 93, a signal line for supplying a power supply voltage to the solid-state imaging device 93, a signal line 98 for giving a control signal from the DSP 92 to the solid-state imaging device 93, and the solid-state imaging device 93 And a signal line for sending an image signal output from the DSP 92 to the DSP 92. A wiring resistor 94 (R) exists on the signal line for supplying the power supply voltage, and a load capacitor 95 (C1) exists between the signal line and the ground. In addition, an external capacitor 96 is connected to the outside of the solid-state imaging device 93, and an internal capacitor 97 is provided inside the solid-state imaging device 93.

  In the camera system of the present embodiment, as shown in FIG. 8B, the current consumed by the solid-state imaging device 93 through one horizontal scanning period by applying a control signal to the solid-state imaging device via the signal line 98. I (t) is constant. For this reason, the power supply voltage VDD (t) and the bias voltage Bias (t) supplied to the solid-state imaging device 93 are also substantially constant throughout the horizontal scanning period.

  Further, the control signal may be input to the timing generator 71 shown in the embodiment of FIG. The timing generator 71 may include a register that generates a plurality of drive patterns for controlling at least one or more load transistors. Further, by writing a desired current control register pattern from the DSP 92 to the register of the solid-state image pickup device 93, the current consumed throughout one horizontal scanning period is made constant and performance is emphasized (screen whitening and blackening are reduced). It is possible to increase the degree of freedom in design, such as whether to focus on the total current consumption.

  Further, the control signal applied to the signal line 98 may be directly input to, for example, the current control circuit 70 (see FIGS. 3 and 4) shown in the embodiment of FIG. However, in this case, in order to control the load transistor in the solid-state imaging device 93, it is necessary to supply at least one drive pattern, preferably a plurality of drive patterns, directly from the DSP 92. Therefore, in general, the control signal supplied from the DSP 92 to the solid-state imaging device 93 is preferably applied to a register that generates a drive pattern in the timing generator 71 (see FIG. 1).

(Third embodiment)
The structure of the solid-state imaging device according to the third embodiment of the present invention is basically the same as that of the first embodiment shown in FIG. 1 except that the detailed circuit configuration of the timing generator 71 in FIG. 1 is different. This is the same as the solid-state imaging device. However, the driving method of the solid-state imaging device according to the present embodiment is partly different from the driving method of the solid-state imaging device according to the first embodiment.

  FIG. 9 is a timing diagram illustrating a driving method of the solid-state imaging device according to the third embodiment. This timing diagram shows a case where the current Iv flowing through the circuit related to vertical reading and the current Ih flowing through the circuit related to horizontal reading are not equal, and Iv> Ih.

  9, when the current flowing through the output circuit 72 is stopped in the vertical readout period 201 and the current flowing through the source follower circuit of the pixel is stopped in the horizontal readout period 202, the vertical readout period 201 and the horizontal readout period 202 are A current fluctuation of Iv + Ih occurs at the boundary, and the power supply voltage, the bias voltage, and the reference voltage VCL accompanying the current fluctuation fluctuate.

  Here, the current fluctuation in the conventional solid-state imaging device shown in FIG. 25 is Iv, and (Iv−Ih) <Iv.

  However, in the method for driving the solid-state imaging device according to the present embodiment, as can be seen from FIG. 9, the variation of the reference voltage VCL due to the current variation is smaller than that of the prior art (FIG. 25), and the entire circuit of the solid-state imaging device The current consumed by can be reduced.

  Furthermore, the driving method of the solid-state imaging device according to the present embodiment shown in FIG. 9 has a vertical readout period (first reading period) in order to suppress fluctuations in the output voltage from the current control circuit or the like due to slight fluctuations in VCL. A period (third period) 203 in which neither vertical reading nor horizontal reading is performed is provided between the (period) 201 and the horizontal reading period (second period) 202. That is, by providing the period 203 shown in FIG. 9, the horizontal reading operation is started after the output of the VCL is stabilized.

  By this operation, the voltage fluctuation of the reference voltage VCL is suppressed in the horizontal readout period 202, so that the output SOUT of the output circuit 72 can be more reliably suppressed from changing in the horizontal readout period. As a result, it is possible to suppress the occurrence of image defects such that the left side of the screen floats white or sinks black.

(Fourth embodiment)
FIG. 10 is a circuit configuration diagram showing a solid-state imaging device according to the fourth embodiment of the present invention. The solid-state imaging device of this embodiment is characterized in that a column amplifier 73 is provided for each column of unit cells, as compared with the solid-state imaging device according to the first embodiment shown in FIG.

  Next, details of the column amplifier 73 will be described with reference to FIG.

  FIG. 11 is a circuit configuration diagram showing a first specific example of the current control circuit 70 and the column amplifier 73 in the solid-state imaging device of the present embodiment. In the example shown in FIG. 5, one source-coupled single amplifier provided for all the pixel columns in the output circuit is provided for each pixel column in the solid-state imaging device of the present embodiment. In FIG. 11, φBIASSW1 indicates a current control pulse of the column amplifier 73.

  The column amplifier 73 includes an amplification transistor 31, a load transistor 32 that supplies a current into the column amplifier 73, a cascode transistor 33 interposed between the amplification transistor 31 and the load transistor 32, and a vertical signal line 8. The capacitor 35 connected to the gate of the amplifier transistor 31 and the capacitor 35 and the capacitor 36 provided in parallel with each other between the gate of the capacitor 35 and the amplifier transistor 31 and the output unit. And a transistor 34. The capacitive elements 35 and 36 determine an amplifier gain and form an inverting amplifier. The reset transistor 34 resets the input / output of the column amplifier.

  The current control circuit shown in FIG. 11 is the same as the circuit configuration shown in FIG. 5. When φBIASSW1 becomes high level, a bias voltage is supplied to the load transistor 32, current flows to the column amplifier 73, and the amplifier operation To do. On the other hand, when φBIASSW1 becomes low level, a low level voltage is supplied to the gate of the load transistor 32, and the current to the column amplifier 73 is stopped or reduced.

  FIG. 12 is a circuit configuration diagram showing a second specific example of the current control circuit 70 and the column amplifier 73 in the solid-state imaging device according to the fourth embodiment of the present invention. This is a configuration in which the current is changed by changing the gate voltage of the cascode transistor 33 of the column amplifier 73.

  From FIG. 12, when φBIASSW1 becomes a high level, a bias voltage is supplied to the gate of the cascode transistor 33, a current flows through the column amplifier 73, and the amplifier operates.

  On the other hand, when φBIASSW1 becomes low level, a low-level voltage is supplied to the gate of the cascode transistor 33, and the current flowing through the column amplifier 73 is stopped or reduced.

  Further, the characteristic difference between the current control configurations shown in FIGS. 11 and 12 is the same as the characteristic difference between the current control configurations shown in FIGS. Here, “the characteristic difference is the same” means that the characteristic difference between the configuration shown in FIG. 11 and the configuration shown in FIG. 12 is in the voltage state of the output part OUT in the current stopped state. That is, in the circuit shown in FIG. 11, since the load transistor 32 is turned off when the current is stopped, the output voltage becomes a low level, whereas in the circuit shown in FIG. 12, the cascode transistor 33 is turned off when the current is stopped. The voltage becomes high level. Further, in the column amplifier 73 shown in FIG. 12, the gate voltage of the load transistor 32 is a fixed bias voltage, whereas in the column amplifier 73 shown in FIG. 11, no fixed voltage is applied to the gate terminal of the amplification transistor 31. The impedance of the gate terminal becomes slightly higher. Therefore, according to the configuration shown in FIG. 12, the output fluctuation when the current is stopped has the effect of being smaller than that of the circuit of FIG.

  Next, the circuit operation of the solid-state imaging device when the column amplifier means is provided will be described with reference to FIG. FIG. 13 is a timing diagram illustrating a driving method of the solid-state imaging device according to the fourth embodiment.

  As shown in the figure, a clamp pulse 109 is applied to the common gate 55 of the clamp transistor 17, all the m clamp transistors 17 are turned ON, and the voltage of the clamp transistor side electrode of the clamp capacitor 16 is set to the common source of the clamp transistor 17. After being fixed at the voltage VCL, it is turned OFF.

  At this time, a reset pulse 111 is applied to a common reset gate of the column amplifiers 73, the reset transistors 34 in the column amplifiers 73 are turned on, and the output voltage of the column amplifiers 73 is fixed to the reset voltage of the column amplifiers 73 and then turned off. To do.

  Next, the signal reset pulse 102-1 is applied from the reset line 7-1 to the gates of the reset transistors 4-1-1, 4-1-2,..., 4-1-m, and the signal charge of the photodiode is discharged. Then, the noise voltage due to the threshold variation of the amplification transistors 2-1-1, 2-1-2, 2-1 -m on the vertical signal lines 8-1, 8-2,. Appears.

  At this time, the voltage of the clamp transistor side electrodes of the clamp capacitors 16-1, 16-2,..., 16-m is the amount of voltage change of the vertical signal lines 8-1, 8-2,. A noiseless signal voltage obtained by subtracting the noise voltage from the signal appears superimposed on the common source voltage VCL of the clamp transistor. The common source voltage is also free of noise.

  Next, the sample and hold pulse 110 is applied to the common gate 56 of the sample and hold transistor 18, and the signal voltage without noise is supplied to the hold capacitor 19- through the sample and hold transistors 18-1, 18-2,. 1, 19-2, ..., 19-m.

  The solid-state imaging device shown in FIG. 13 is different from the solid-state imaging device shown in FIG. 2 because the column amplifier 73 forms an inverting amplifier, so that the polarity of the signal held in the hold capacitor 19 is opposite (negative) polarity. It is to become.

  Next, horizontal selection pulses 104-1, 104-2,... Are sequentially applied from the horizontal shift register 13 to the horizontal selection transistors 12-1, 12-2, and output signals for one row are sequentially extracted from the horizontal signal line 50. .

  By repeating the above operation sequentially from the next line to the next line, all two-dimensional signals can be read out.

  Iv is a current flowing through a circuit related to vertical readout. In the example shown in FIG. 10, the total current flowing through the pixel source follower circuit and the column amplifier 73 is shown.

  Ih is a current flowing in a circuit related to horizontal reading, and in the example shown in FIG.

  As described above, in the solid-state imaging device and the driving method thereof according to the fourth embodiment described with reference to the drawings, the current flowing through the output circuit 72 is reduced or stopped in the vertical readout period 201, and the pixels of the solid-state imaging apparatus in the horizontal readout period 202 are stopped. This is characterized in that the current flowing through the source follower circuit and the column amplifier 73 is reduced or stopped.

  Therefore, as shown in FIG. 13, it is possible to suppress the current fluctuation of the total current I of the current flowing through the circuit related to horizontal reading and the current flowing through the circuit related to vertical reading through one horizontal scanning period.

  Further, as a result of suppressing the current fluctuation, it is possible to suppress the fluctuation of the output SOUT of the output circuit 72 within the horizontal readout period 202 by suppressing the voltage fluctuation of the power supply voltage and the bias voltage, particularly the reference voltage VCL. it can.

  As a result, it is possible to suppress the occurrence of image defects such that the left side of the screen floats white or sinks black. Also, by reducing or stopping the current flowing through the output circuit 72 during the vertical readout period 201, the overall current consumption through one horizontal scanning period can be suppressed.

  In particular, in the circuit configuration provided with the column amplifier means, the current flowing in the vertical readout period becomes large, so the effect of suppressing the current fluctuation in the solid-state imaging device of this embodiment is high.

  FIG. 14 is a circuit configuration diagram showing a configuration in which the output circuit 72 of the solid-state imaging device provided with the column amplifier described in the fourth embodiment is replaced with the differential amplification type output circuit shown in FIG. Also in the circuit shown in FIG. 14, as described in the third embodiment, the fluctuation in the voltage of VCL can be suppressed by suppressing the current fluctuation, and the output fluctuation of the output SOUT from the output unit can be suppressed.

  As a common precaution regarding the first to fourth embodiments, if the current flowing through the output circuit 72 is completely stopped in the vertical read period only when the current Ih is twice or more the current Iv, the vertical read period And the current fluctuation during the horizontal readout period becomes larger than Iv. In this case, it is preferable to reduce the current of the output circuit instead of stopping it. Ideally, control should be made so that Ih and Iv have the same value.

(Fifth embodiment)
FIG. 15 is a circuit configuration diagram showing a current control circuit and an output circuit in a solid-state imaging device according to the fifth embodiment of the present invention. The solid-state imaging device of the present embodiment has a plurality of current paths, and each of the plurality of current paths changes an output MOS transistor and an output impedance of at least one of the plurality of current paths. The output amplifier provided with the MOS transistor for making it provide.

  The difference from the solid-state imaging device shown in FIG. 5 is that the output circuit 72 of the present embodiment has a plurality of amplification transistors 48-1 and 48-2 and a plurality of cascode transistors 49-1 and 49 that change the output impedance of the output circuit 72. -2 and a plurality of cascode transistors 49-1, 49-2, and a current control circuit 70-2 for controlling the gate voltage of the cascode transistors 49-1, 49-2. .

  As an effect obtained with this configuration, fluctuations in the DC voltage of the output unit OUT may be suppressed when the currents of a plurality of current paths are changed. With respect to this effect, the fluctuation of the DC voltage value of the output from the output unit OUT when the current changes will be described by comparing with the solid-state imaging device shown in FIG.

  In the output circuit 72 shown in FIG. 5, when both of the plurality of load transistors 47-1 and 47-2 functioning as current sources are ON, the parallel resistance value of the load transistors 47-1 and 47-2 and the cascode transistor 49 and the voltage divided by the series resistance value of the amplification transistor 48 are obtained as the DC voltage of the output part OUT. On the other hand, when the load transistor 47-1 is turned OFF and the current value decreases, the voltage divided by the resistance value of only the load transistor 47-2 and the series resistance value of the cascode transistor 49 and the amplification transistor 48 is output from the output section OUT. Obtained as a DC voltage.

  (Resistance value of only the load transistor 47-2)> Since the parallel resistance value of the load transistors 47-1 and 47-2, the DC voltage of the output part OUT at the time of the current decrease somewhat decreases. On the other hand, in the output circuit 72 of the present embodiment, fluctuations in the DC voltage of the output unit OUT can be suppressed with high accuracy as follows.

In the output circuit 72 of the present embodiment shown in FIG. 15, the resistance value of the amplification transistor 48-1 is R _(48-1) and the resistance value of the amplification transistor 48-2 is R _(48-2). The resistance values of the cascode transistors 49-1 and 49-2 are respectively R _(49-1) and R _(49-2) , and the resistance values of the load transistors _{47-1 and 47-2} are respectively R _(47-1) and R. _(47-2) .

When both the load transistors 47-1 and 47-2 are ON, the DC voltage of the output part OUT is VDD * [{R _(48-1) + R _(49-1) } // {R _(48-2) + R _(49-2) }] / [R _(47-1) // R _(47-2) + {R _(48-1) + R _(49-1) } // {R _(48-2) + R _{( 49-2)} }].

If the various transistor sizes are designed to be constant (the gate width is constant without changing the gate length of the transistor), R _(47-1) = A * R _(47-2) , R _{(48- 1)} = A * R _(48-2) , R _(49-1) = A * R _(49-2) . Then, the DC voltage of the output part OUT can be expressed as VDD * {R _(48-2) + R _(49-2) } / {R _(47-2) + R _(48-2) + R _(49-2) }. .

On the other hand, even if the load transistor 47-1 is turned OFF and the current value is decreased, the DC voltage of the output unit OUT is VDD * {R _(48-2) + R _(49-2) } / {R _(47-2) + R. _(48-2) + R _(49-2) }, which is the same voltage as the DC voltage before the current change.

  Thus, by providing a plurality of amplification transistors and a plurality of output impedance control transistors (cascode transistors) for a plurality of current sources, it is possible to suppress the DC voltage fluctuation of the output unit OUT before and after the current change. it can. Therefore, if the solid-state imaging device of this embodiment is used, even when the current Ih flowing through the output circuit 72 is reduced in the vertical readout period compared to the horizontal readout period, fluctuations in the output voltage from the output circuit 72 can be suppressed to a smaller level. Can do.

  If the DC voltage fluctuation of the output unit OUT can be suppressed as a camera system (imaging device), for example, the output from the output unit OUT can be easily received directly by the transistor. This is because if the DC output value from the output OUT varies greatly, it is necessary to increase the input dynamic range of the transistor that receives the output in the camera system.

  When the fluctuation of the DC output value from the output unit OUT is large, in order to suppress the fluctuation of the DC output value from the output unit OUT, it is shown in FIG. 22A between the solid-state imaging device and the DSP including the analog front end. Although there is a method of providing the capacitive element 1099 and cutting the DC component by capacitive coupling, there are disadvantages such as an increase in the number of parts and area as a camera system.

  FIG. 16 is a circuit configuration diagram illustrating a first modification of the solid-state imaging device according to the present embodiment. In the solid-state imaging device of this modification, in the output circuit 72, amplification transistors 48-1 and 48-2 corresponding to a plurality of current paths, output impedance control transistors 63-1 and 63-2, and a cascode transistor 49 are provided. -1, 49-2 are provided. The difference between the solid-state imaging device shown in FIG. 15 and the solid-state imaging device according to the present modification is that the gate voltage of the load transistor 47-1 that functions as a current source is not changed, but the cascode transistor 49-1. This is due to the fluctuation of the gate voltage. Further, transistors 63-1 and 63-2 for controlling the output impedance are further provided.

Although detailed description is omitted, like the output circuit of the fifth embodiment shown in FIG. 15, in the output circuit 72 of this modification example, the size of various transistors is set to be a constant so that the current before and after the current change can be increased. Both DC output values are VDD * {R _(48-2) + R _(49-2) } / {R _(47-2) + R _(63-2) + R _(48-2) + R _(49-2) } Variations in the DC output value from the output unit OUT can be suppressed.

  The difference from FIG. 15 is that there is no need to provide a switch in the transmission path of the bias voltage BIASIN4 supplied to each gate of the current source (load transistors 47-1 and 47-2). As a result, fluctuations in the bias voltage due to switching can be suppressed, making it easy to realize a low-noise output amplifier.

  Note that the current control circuit, the pixel source follower circuit, the column amplifier circuit, and the output circuit of the present invention have a circuit configuration in which current is changed in each of the vertical readout period and the horizontal readout period. The circuit is not limited to the circuits shown in the third to fifth embodiments.

  For example, the bias output control circuits shown in the first to third embodiments have shown the configuration in which the bias output is switched by the MOS transistor. However, the circuit configuration shown in FIG.

  FIG. 17 is a circuit configuration diagram illustrating a second modification of the solid-state imaging device according to the present embodiment. In the example shown in the figure, the current control circuit 70 is not provided with the switching transistor 40 (see FIG. 15), and the switching transistor 42 is used to directly lower the bias output terminal to the ground low level voltage. At this time, the transistor 38 on the power supply side is controlled to be turned off so that a direct current does not flow.

  FIG. 18 is a circuit configuration diagram showing a third modification of the solid-state imaging device of the present embodiment. As shown in the figure, the power supply voltage VDD and the ground voltage may be switched instead of the bias voltage and the ground voltage for the cascode transistor 33 cascode-connected to the amplification transistor 31.

  Furthermore, in the solid-state imaging device of each embodiment of the present invention, the timing control is performed by the timing generator inside the imaging device shown in FIG. 1, but it may be controlled by a system outside the solid-state imaging device.

  Furthermore, although the solid-state imaging device according to the embodiment of the present invention has been described centering on a circuit configured with an N-channel MOS transistor, the N-channel MOS transistor may be replaced with a P-channel MOS transistor.

  For example, although the amplifier circuit shown in FIG. 3 is an N-channel type source follower circuit, it may be a P-channel type source follower circuit. In this case, it should be noted that the polarity of the bias output control circuit needs to be reversed. As a circuit for reversing the polarity, a bias output control circuit 75 shown in FIG. 5 may be used.

  Although the circuit shown in FIG. 1 has been described as a circuit constituting the pixel of the solid-state imaging device of each embodiment, for example, a circuit configuration for reading a signal to a floating diffusion (FD) unit as shown in FIG. May be. In this example, a read transistor 0-1-1 driven by a read signal line 112-1 is provided between the photodiode 1-1-1 and the FD portion. Further, a power pulse is supplied to the drain of the amplification transistor 2-1-1 through the power pulse signal line 113-1.

  In the case of this circuit configuration, the signal held in the hold capacitor 19-1 shown in FIG. 2 is read as shown in FIG. Since the signal is clamped to the reference voltage VCL only by becoming negative, the effect of the present invention can be similarly obtained even in the pixel circuit configuration shown in FIG.

  As described above, the solid-state imaging device and the driving method thereof according to the present invention are useful for imaging devices such as digital cameras and video cameras.

It is a circuit block diagram which shows the solid-state imaging device which concerns on the 1st specific example of 1st Embodiment. It is a timing diagram of a pulse signal for driving the solid-state imaging device according to the first specific example of the first embodiment. It is a circuit block diagram which shows the current control circuit and output circuit which concern on the 1st specific example of 1st Embodiment. It is a circuit block diagram which shows the current control circuit and output circuit in the solid-state imaging device which concerns on the 2nd specific example of 1st Embodiment. It is a circuit block diagram which shows the current control circuit and output circuit in the solid-state imaging device which concerns on the 3rd specific example of 1st Embodiment. It is a circuit block diagram which shows the current control circuit and output circuit in the solid-state imaging device which concerns on the 4th specific example of 1st Embodiment. It is a circuit block diagram which shows the current control circuit and output circuit in the solid-state imaging device which concerns on the 5th example of 1st Embodiment. (A) is a circuit diagram which shows the structural example of the camera system which concerns on the 2nd Embodiment of this invention, (b) is a timing diagram which shows the electric current and voltage supplied to the solid-state imaging device of the said camera system It is. FIG. 9 is a timing diagram illustrating a method for driving a solid-state imaging device according to a third embodiment. It is a circuit block diagram which shows the solid-state imaging device which concerns on 4th Embodiment. It is a circuit block diagram which shows the 1st specific example of the current control circuit and column amplifier in the solid-state imaging device which concerns on 4th Embodiment. FIG. 9 is a circuit configuration diagram illustrating a second specific example of a current control circuit and a column amplifier in a solid-state imaging device according to a fourth embodiment. It is a timing diagram which shows the drive method of the solid-state imaging device which concerns on 4th Embodiment. It is a circuit block diagram which shows what used the output circuit of the solid-state imaging device which provides the column amplifier demonstrated in 4th Embodiment as the output circuit of a differential amplification type. It is a circuit block diagram which shows the current control circuit and output circuit in the solid-state imaging device which concerns on 5th Embodiment. It is a circuit block diagram which shows the 1st modification of the solid-state imaging device of 5th Embodiment. It is a circuit block diagram which shows the 2nd modification of the solid-state imaging device of 5th Embodiment. It is a circuit block diagram which shows the 3rd modification of the solid-state imaging device of 5th Embodiment. (A) is a circuit block diagram which shows an example of the pixel circuit in the solid-state imaging device of this invention, (b) is a timing diagram which shows the various signals in the solid-state imaging device of 5th Embodiment. It is a circuit block diagram which shows an example of the conventional solid-state imaging device. It is a timing diagram which shows the pulse signal for driving the conventional solid-state imaging device. (A) is an example of the camera system using a solid-state imaging device, (b) is a figure for demonstrating the drive method of the conventional camera system. It is a timing chart of various signals in the conventional output circuit. 6 is a timing chart showing the timing of vertical readout and horizontal readout in a conventional solid-state imaging device. The power supply voltage VDD, Iv related to vertical reading, current Ih related to horizontal reading, current sum I, and φSIGRS are added to the timing chart shown in FIG.

Explanation of symbols

0-1-1 Read transistor 1, 1-1-1, 1-1-2,..., 1-nm photodiode 2, 2, 1-1, 1-2-2,. m amplification transistors 3, 3-1-1, 3-1-2, ..., 3-nm vertical selection transistors 4, 4-1-1, 4-1-2, ..., 4-2-2: reset Transistor 5 Vertical shift registers 6, 6-1, 6-2, ..., 6-n Horizontal address lines 7, 7-1, 7-2, ..., 7-n Reset lines 8, 8-1, 8-2, , 8-m Vertical signal lines 9, 9-1, 9-2, ˜, 9-m Load transistors 12, 12-1, 12-2, ˜, 12-m Horizontal selection transistor 13 Horizontal shift registers 15, 15 -1, 15-2,..., 15-m Vertical signal line reset transistors 16, 16-1, 16-2,. Quantity 17, 17-1, 17-2, ..., 17-m Clamp transistor 18, 18-1, 18-2, ..., 18-m Sample hold transistor 19, 19-1, 19-2, ..., 19- m Hold capacitor 31 Amplifying transistor 32 Load transistor 33 Cascode transistor 34 Reset transistors 35 and 36 Capacitor element 36: Column amplifier feedback capacitor element 37 Transistor 38 Transistor 39 Capacitor elements 40, 41 and 42 Switching transistor
44, 44-1, 44-2 Load transistor
45 Amplifier transistor
46 Reset transistor for output
47, 47-1, 47-2 Load transistor
48, 48-1, 48-2 Amplifying transistor
49 Cascode Transistor
50 horizontal signal lines
55 Common gate of clamp transistor
56 Common gate of sample hold transistor
61, 63-1, 63-2 transistor
62-1 and 62-2 load transistor
70 Current control circuit
71 Timing Generator
72 Output circuit
73 Column amplifier
74 Bias circuit
75 Bias output control circuit
92 DSP
93 Solid-state imaging device
94 Wiring resistance
95 Load capacity
96 External capacity
97 Internal capacity
98 signal line
101-1 Address pulse
102-1 Signal reset pulse
104-1 and 104-2 Horizontal selection pulse
105-1, 105-2 Output signal
109 Clamp pulse
110 Sample hold pulse
111 Reset pulse
112 Read signal line
113 Power pulse signal line
201 Vertical readout period
202 Horizontal readout period
203 Third period VDD Power supply voltage VCL Noise cancellation circuit clamp voltage SOUT Output circuit output signal φSIGRS Output circuit input terminal reset pulse φBIASSW2 Output circuit current control pulse φBIASSW1 Column amplifier circuit current control pulse

Claims (18)

A plurality of pixels that have a photoelectric conversion unit and a signal amplification unit that amplifies the charge generated by the photoelectric conversion unit, and is two-dimensionally arranged in a matrix;
A vertical signal line wired for each of the plurality of pixels and commonly connected to one column of pixels;
A vertical line driving current source connected to one end of each of the vertical signal lines and supplying a current to the signal amplifier;
A row signal storage unit that is connected to the vertical signal line and stores a signal from the pixel transmitted through the vertical signal line;
A horizontal signal line from which the signal stored in the row signal storage unit is read out;
An output circuit for outputting the signal read out through the horizontal signal line to the outside;
A solid-state imaging device comprising: a first current control circuit that controls an amount of current flowing through the output circuit.   The solid-state imaging device according to claim 1, wherein the first current control circuit further controls an amount of current flowing from the vertical line driving current source to the signal amplifying unit. The output circuit has an amplifier for amplifying the input signal,
The solid-state imaging device according to claim 2, wherein the first current control circuit controls an amount of current flowing through the amplifier. The amplifier includes a first amplification transistor that amplifies the signal input to a gate, and a first load transistor that supplies a current to the first amplification transistor.
The solid-state imaging device according to claim 3, wherein the first current control circuit adjusts an amount of current flowing through the output circuit by controlling an operation of the first load transistor.   The amplifier amplifies and outputs the input signal, a third load transistor that supplies current to the third amplification transistor, the third load transistor, and the third load transistor. The solid-state imaging device according to claim 3, wherein the solid-state imaging device is a source-coupled amplifier having a third cascode transistor provided between the first and second amplification transistors. The amplifier supplies current to the first MOS transistor to which the signal is input, the second MOS transistor to which a predetermined bias voltage is input, the first MOS transistor, and the second MOS transistor. , A differential amplifier having a fifth load transistor and a sixth load transistor connected in parallel with each other;
The first current control circuit controls the fifth load transistor to supply a constant current throughout one horizontal scanning period, and controls the operation of the sixth load transistor, thereby controlling the output circuit. The solid-state imaging device according to claim 3, wherein an amount of current flowing through the device is adjusted. One horizontal scanning period includes a vertical readout period in which the signal is read out through the vertical signal line, and a horizontal readout in which the signal accumulated in the row signal accumulation unit is read out to the horizontal signal line and output from the output circuit. Period and
7. The first current control circuit according to claim 2, wherein the amount of current flowing through the output circuit during the vertical readout period is made smaller than the amount of current flowing through the output circuit during the horizontal readout period. The solid-state imaging device as described in any one of them. A noise cancellation circuit connected to the vertical signal line and subtracting noise from the signal read out to the vertical signal line;
The solid-state imaging device according to claim 1, wherein the first current control circuit further controls the amount of current flowing through the noise cancellation circuit.   The solid-state imaging device according to claim 8, wherein the noise cancellation circuit subtracts noise from the signal by clamping the noise read out to the vertical signal line to a first reference voltage. A column amplifier provided for each vertical signal line, further amplifying the signal input from the pixel through the vertical signal line and outputting the amplified signal to the row signal storage unit;
The solid-state imaging device according to claim 1, wherein the first current control circuit controls an amount of current flowing through the column amplifier.   The column amplifier includes a fifth amplification transistor that amplifies the signal input to a gate, and a seventh load transistor that supplies a current to the fifth amplification transistor. The solid-state imaging device according to claim 10. A photoelectric conversion unit and a signal amplification unit that amplifies the charge generated by the photoelectric conversion unit, and a plurality of pixels that are two-dimensionally arranged in a matrix and wired to the plurality of pixels for each column A vertical signal line commonly connected to one column of pixels, a vertical line driving current source connected to one end of each of the vertical signal lines and supplying a current to the signal amplifier, and the vertical signal line A row signal accumulation unit that accumulates signals from the pixels that are connected and transmitted via the vertical signal line, a horizontal signal line from which the signal accumulated in the row signal accumulation unit is read, and the horizontal signal line A solid-state imaging device having an output circuit for outputting the signal read out via a current control circuit for controlling an amount of current flowing through the output circuit;
A DSP that processes the signal output from the output circuit, supplies a power supply voltage and current to the solid-state imaging device, and outputs the control signal for controlling the amount of current that flows through the solid-state imaging device. ,
The current control circuit is a camera system that controls an amount of current flowing through the output circuit based on the control signal.   The camera system according to claim 12, wherein the current control circuit causes an amount of current flowing through the output circuit during the vertical readout period to be smaller than an amount of current flowing through the output circuit during the horizontal readout period.   14. The camera system according to claim 13, wherein the current control circuit further controls the amount of current flowing from the vertical line driving current source to the signal amplification unit based on the control signal. The solid-state imaging device further includes a column amplifier that is provided for each vertical signal line and amplifies the signal input from the pixel via the vertical signal line and outputs the amplified signal to the row signal storage unit. ,
15. The camera system according to claim 14, wherein the current control circuit controls an amount of current flowing through the column amplifier based on the control signal. A photoelectric conversion unit and a signal amplification unit that amplifies the electric charge generated by the photoelectric conversion unit, and a plurality of pixels that are two-dimensionally arranged in a matrix and wired for each of the plurality of pixels for each column. A vertical signal line commonly connected to one column of pixels, a vertical line driving current source connected to one end of each of the vertical signal lines and supplying a current to the signal amplifier, and the vertical signal line A driving method of a solid-state imaging device having a connected row signal storage unit, a horizontal signal line, an output circuit connected to the horizontal signal line, and a current control circuit,
Reading a signal from each pixel in a selected row through each vertical signal line during a vertical readout period, and outputting the signal to the row signal storage unit;
A step of causing the signal accumulated in the row signal accumulation section of each column to be input to the output circuit via the horizontal signal line and sequentially outputting the signals for one row from the output circuit during a horizontal readout period; (B)
The solid-state imaging device driving method, wherein the current control circuit causes a current amount flowing through the output circuit to be smaller than a current amount flowing through the output circuit during the horizontal reading period in the vertical readout period.   In the horizontal readout period, the current control circuit causes an amount of current flowing from the vertical drive current source to the signal amplification unit to be smaller than an amount of current flowing in the signal amplification unit in the vertical readout period. The method for driving a solid-state imaging device according to claim 16. The solid-state imaging device further includes a column amplifier provided for each vertical signal line and connected to the vertical signal line,
In the vertical readout period, the column amplifier amplifies the input signal and outputs it to the row signal storage unit,
18. The solid state according to claim 17, wherein in the horizontal readout period, the current control circuit causes an amount of current flowing through the column amplifier to be smaller than an amount of current flowing through the column amplifier during the vertical readout period. Driving method of imaging apparatus.

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