JP2006121140A - Drive method of solid-state imaging apparatus, and imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drive method of a solid-state imaging apparatus which realizes a CDS function capable of dividedly transferring photo electric charges from a photoelectric conversion section and reading a noise component in advance. <P>SOLUTION: The drive method of the solid-state imaging apparatus configured with the arrangement of a plurality of unit pixels each including: a storage well 2 for storing optically generated electric charges; a floating diffusion 8 to which the optically generated electric charges are transferred; an amplifier means for outputting an amplified pixel signal on the basis of the optically generated electric charges transferred to the floating diffusion 8; and a transfer control element 4 with an electric charge storage region 6 for controlling a potential barrier of a transfer path between the storage well 2 and the floating diffusion 8 and storing the optically generated electric charges, includes a first transfer step of the transfer control element 4 for controlling the potential barrier of the transfer path for all the pixels at the same time to dividedly transfer the optically generated electric charges stored in the storage well 2 to the electric charge storage region. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for driving a solid-state imaging device and an imaging device.

Conventionally, as a solid-state imaging device mounted on a mobile phone, a digital camera or the like, a CMOS type image sensor (hereinafter referred to as a CMOS sensor) and a CCD (charge coupled device) type image sensor (hereinafter referred to as a CCD sensor) There is.
In order to expand the so-called dynamic range of the solid-state imaging device which is a CMOS sensor, in the CMOS sensor, the photoelectric charge from the photoelectric conversion unit is transferred to the floating diffusion, for example, twice, and the signal is read, for example, divided into two systems. For this reason, a technique has been proposed (see, for example, Patent Document 1).

  However, according to the technique according to this proposal, there is a problem that it takes a long time to read out a signal because the photoelectric charge from the photoelectric conversion unit is read out twice. Therefore, in order to perform correlated double sampling (hereinafter referred to as CDS) for noise reduction in such a solid-state imaging device, there is a problem that the circuit must be driven at high speed.

Further, according to the technique related to the proposal, since the output system is required for the number of times of signal reading, there is a problem that the entire circuit scale is increased.
Therefore, a technique has been proposed in which an output signal from the photoelectric conversion unit is output to one system so that the entire circuit scale is not increased (see, for example, Patent Document 2). According to the technique related to the proposal, the photoelectric charge is read from the photoelectric conversion unit into the floating diffusion region in two portions, and the charge accumulated in the floating diffusion region is read out in one system.
Japanese Patent Laid-Open No. 2001-17775 Japanese Patent Laid-Open No. 2003-219277

  However, in the case of the divided transfer technique according to the latter proposal, it is possible to output a signal to one system, but since the noise component readout is performed after resetting the signal charge transferred to the floating diffusion, the noise component is There is a problem that it does not correlate with the noise component included in the signal component. If a noise suppression function for pre-reading noise components is to be realized, a frame memory must be provided as a peripheral circuit to hold the signals of all pixels, resulting in an increase in the circuit scale as a whole. There is.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a driving method of a solid-state imaging device that realizes a CDS function that can divide and transfer photoelectric charges from a photoelectric conversion unit and read out a noise component in advance.

  The solid-state imaging device driving method of the present invention includes an accumulation well for accumulating photogenerated charges generated by photoelectric conversion elements in response to incident light, a floating diffusion region to which the photogenerated charges are transferred, and the floating diffusion region. Amplifying means for outputting a pixel signal amplified on the basis of the photogenerated charge transferred to the light source, controlling a potential barrier of a transfer path between the storage well and the floating diffusion region, and generating the light A solid-state imaging device configured by arranging a plurality of unit pixels each including a transfer control element having a charge holding region for holding charge, wherein all the pixels are simultaneously transferred by the transfer control element. A potential barrier of the path is controlled, and the photo-generated charge by the photoelectric conversion element is transferred to the charge via the transfer path. An accumulation procedure for accumulating in the accumulation well while preventing it from flowing through the holding region, and simultaneously controlling the potential barrier of the transfer path by the transfer control element for all the pixels, and the light accumulated in the accumulation well A first transfer procedure in which the generated charge is divided and transferred to the charge holding region; and a potential barrier of the transfer path is controlled by the transfer control element so that the photogenerated charge does not flow to the floating diffusion region. A noise component reading procedure for reading a noise component in the floating diffusion region and a potential barrier of the transfer path are controlled by the transfer control element to transfer the photogenerated charge accumulated in the charge holding region to the floating diffusion region. A second transfer procedure and the transfer process by the transfer control element; By controlling the potential barrier including a signal component read procedure for outputting a pixel signal corresponding to the light-generated charge from the floating diffusion region in a state of being held to the light-generated electric charges in the modulation well.

  According to such a configuration, it is possible to realize a driving method of a solid-state imaging device that realizes a CDS function that can divide and transfer photoelectric charges from the photoelectric conversion unit and read out noise components in advance.

In the driving method of the solid-state imaging device of the present invention, it is preferable that a reset procedure for resetting all pixels is further included before the accumulation procedure.
According to such a configuration, the collective electronic shutter function can be realized in the solid-state imaging device.

In the imaging device of the present invention, an accumulation well for accumulating photogenerated charges generated by photoelectric conversion elements in response to incident light, a floating diffusion region to which the photogenerated charges are transferred, and the floating diffusion region are transferred to the floating diffusion region Amplifying means for outputting a pixel signal amplified based on the photogenerated charge, a potential barrier of a transfer path between the storage well and the floating diffusion region, and holding the photogenerated charge A solid-state imaging device configured by arranging a plurality of unit pixels including a transfer control element having a charge holding region, and simultaneously controlling the potential barrier of the transfer path by the transfer control element for all the pixels, Do not let the photo-generated charge generated by the photoelectric conversion element flow to the charge holding region via the transfer path. The storage timing signal to be accumulated in the accumulation well and the potential barrier of the transfer path are simultaneously controlled by the transfer control element for all the pixels to divide the photogenerated charge accumulated in the accumulation well to A first transfer timing signal to be transferred to the charge holding region, and a noise component of the floating diffusion region in a state in which the transfer control element controls the potential barrier of the transfer path and does not flow the photogenerated charge to the floating diffusion region. And a second transfer timing for transferring the photogenerated charge accumulated in the charge holding region to the floating diffusion region by controlling the potential barrier of the transfer path by the transfer control element. Signal and the transfer control element A signal component readout timing signal for outputting a pixel signal corresponding to the photogenerated charge from the floating diffusion region while controlling the potential barrier of the transfer path and holding the photogenerated charge in the modulation well. A timing control circuit.
According to such a configuration, it is possible to realize an imaging apparatus that can divide and transfer photocharges from the photoelectric conversion unit and realize a CDS function that reads a noise component in advance.

In the imaging device of the present invention, it is preferable that the solid-state imaging device further includes a discharging unit that discharges the excess charge in the accumulation well.
According to such a configuration, surplus charges generated in the photoelectric conversion unit can be discharged.

In the imaging device of the present invention, the amplifying unit includes a modulation transistor that controls a channel threshold voltage by the charge held in the floating diffusion region and outputs the pixel signal corresponding to the charge. desirable.
According to such a configuration, in an image pickup apparatus using a so-called substrate modulation type solid-state image pickup apparatus, it is possible to realize a CDS function capable of dividing and transferring photocharges from the photoelectric conversion unit and reading out noise components in advance. it can.

Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a plan view showing a planar shape of the solid-state imaging device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. However, the cross section of the wiring and its upper layer structure is not shown.

  As shown in FIG. 1, the solid-state imaging device of the present embodiment has a sensor cell array in which a plurality of sensor cells are arranged in a two-dimensional matrix on a substrate plane. A range indicated by a broken line in FIG. 1 is one sensor cell C that is a unit pixel. The solid-state imaging device according to the present embodiment is a CMOS-APS (Active Pixel Sensor) type sensor. Each sensor cell accumulates photogenerated charges generated according to incident light and outputs a pixel signal at a level based on the accumulated photogenerated charges. A pixel signal of one screen can be obtained by arranging the sensor cells in a matrix.

  The solid-state imaging device according to the present embodiment achieves both the CDS function and the collective electronic shutter function. FIG. 1 shows only four sensor cells. Each of the four sensor cells has a photodiode formation region PD. Each sensor cell has the same structure. Note that this embodiment shows an example in which electrons are used as photogenerated charges. Even when holes are used as the photo-generated charges, the same configuration can be adopted.

  As shown in FIG. 2, the solid-state imaging device includes a photodiode formation region PD, a transfer transistor formation region TT, and a reset transistor formation region RST. Although not shown in FIG. 2, the amplification transistor TA formation region and the selection transistor Has a TS formation region.

  A floating diffusion 8 is formed in the reset transistor formation region RST. A charge holding region TCP is formed in the transfer transistor formation region TT. In the charge holding region TCP, an impurity region for temporarily holding the transferred photogenerated charge, that is, an impurity layer 6 is formed.

  In the present embodiment, the photogenerated charges accumulated in each photodiode formation region PD are divided into a plurality of times, that is, divided into a plurality of times in this case, all at once for all pixels (that is, all sensor cells at the same time). Is transferred to the charge holding region TCP and temporarily held in the impurity layer 6, and then transferred from the charge holding region TCP to the floating diffusion 8 in the reset transistor formation region RST for each selected line.

  The configuration of the solid-state imaging device according to the present embodiment will be described in more detail with reference to FIGS. 1 and 2. In FIG. 2 and the description thereof, the subscripts-and + of N and P indicate the state from the lighter portion (subscript-) to the darker portion (subscript ++) depending on the number. .

  As shown in FIG. 2, the sensor cell is formed on the P-type semiconductor region 1a. In the present embodiment, the P-type semiconductor region is a P-type semiconductor substrate. However, the present invention is not limited to this, and a P-type impurity region may be provided in the semiconductor substrate. In the photodiode formation region PD, an N-type impurity layer 2 is formed on a P-type substrate 1a. A photodiode is formed by the P-type semiconductor region 1 a and the N-type impurity layer 2. The photoelectric conversion element includes a P-type semiconductor region 1 a and an N-type impurity layer 2. The N-type impurity layer 2 constituting the photoelectric conversion element functions as an accumulation well 2 for accumulating photogenerated charges. A P-type impurity layer 3 electrically connected to the substrate 1a is formed on the substrate surface side of the photodiode formation region PD. The impurity layer 3 functions as a pinning layer. In the photodiode formation region PD, an opening region is formed on the substrate surface, and the accumulation well 2 is formed below the opening region. As shown in FIG. 1, the photodiode formation region PD is formed in a substantially L shape on the substrate surface.

  On the other hand, on the P-type substrate 1a in the reset transistor formation region RST, a pair of N-type impurity layers are formed on the substrate surface. Of these pair of impurity layers, the impurity layer on the photodiode formation region PD side forms a floating diffusion 8 as an impurity region, and the other impurity layer 10 is connected to a fixed potential point, for example, VDD.

  A reset gate (also simply referred to as a gate) 9 is formed on the substrate surface of the reset transistor formation region RST via a gate insulating film (not shown). A channel is formed on the substrate surface under the reset gate 9. By applying a predetermined voltage to the reset gate 9 via a terminal, the channel is made conductive, the charge in the floating diffusion 8 is discharged through the other impurity layer 10, and the potential of the floating diffusion 8 is initialized. Can be done.

  Below the opening region of the photodiode, a depletion layer extends from the boundary surface between the impurity layer 3 and the accumulation well 2 to the entire accumulation well 2 and its periphery. In the region of the depletion layer, photogenerated charges due to light incident through the opening region are generated. The generated photogenerated charges are collected in the accumulation well 2.

  The charges accumulated in the accumulation well 2 are transferred to and held in the floating diffusion 8 via a transfer transistor formation region TT described below. The floating diffusion 8 is connected to a gate TAg of an amplification transistor TA (described later). The drain of the amplification transistor TA is connected to the power supply terminal, and the output of the amplification transistor TA corresponds to the potential of the floating diffusion 8, that is, the incident light to the photodiode formation region PD functioning as a photodiode.

  The transfer transistor formation region TT will be described. As shown in FIG. 2, the transfer transistor formation region TT has a charge holding region TCP in the substrate 1a for temporarily holding photogenerated charges.

  Specifically, the transfer transistor region TT is formed on the substrate surface side between the photodiode formation region PD and the reset transistor formation region RST in one sensor cell. The transfer transistor region TT has a transfer gate 4 via a gate insulating layer 5 on the substrate surface so that a channel is formed on the substrate surface. A charge holding region TCP is provided below the transfer gate 4. In the charge holding region TCP, an impurity layer 6 is formed in the vicinity of the substrate surface. The N-type impurity layer 6 is capacitively coupled to the transfer gate 4. A transfer pulse is supplied to the transfer gate 4 via a terminal.

An N ⁻ impurity layer 7 as an impurity region is formed between the impurity layer 6 and the floating diffusion 8 in the reset transistor formation region RST. The channel of the transfer transistor region TT, that is, the transfer path is controlled by the voltage applied to the transfer gate 4. Thereby, the potential barrier of the impurity layer 7 formed between the impurity layer 6 under the transfer gate 4 and the floating diffusion 8 under the reset transistor can be effectively controlled.

As shown in FIG. 1, the transfer gate 4 in the transfer transistor region TT is formed in a substantially rectangular shape adjacent to the end of one side of the substantially L-shaped photodiode formation region PD.
In the present embodiment, an overflow drain region OFD is formed adjacent to the photodiode formation region PD for discharging charges overflowing from the photodiode formation region PD (excess charge). In the overflow drain region OFD, an N-type impurity layer 12 as an impurity region is formed on the substrate surface, and the impurity layer 12 is connected to a predetermined fixed potential point together with the other impurity layer 10 of the reset transistor formation region RST. Yes.

An N ⁻ impurity layer 11 as an impurity region is formed between the accumulation well 2 and the impurity layer 12 in the photodiode formation region PD. In a period in which the potential barrier in the transfer transistor formation region TT is set high, the potential barrier due to the N ⁻ impurity layer 11 is lower than the potential barrier in the transfer transistor formation region TT. As a result, the N ⁻ impurity layer 11 forms a surplus charge discharge path (hereinafter also referred to as an OFD path) for transferring surplus charges from the photodiode formation region PD, and the surplus charges generated in the photodiode formation region PD. Is discharged to the overflow drain region OFD.

That is, the N ⁻ impurity layer 11 is formed adjacent to a part of the edge of the storage well 2 not in contact with the transfer transistor formation region TT. The N ⁻ impurity layer 11 has a lower potential than the other edge of the storage well 2 so that surplus charges from the photodiode formation region PD do not flow into the transfer transistor region TT but flow into the overflow drain region OFD. It has become.

  FIG. 3 is a circuit diagram for explaining an equivalent circuit of the sensor cell of the solid-state imaging device according to the present embodiment. The sensor cell C is formed in the photodiode formation region PD, the photodiode Pd realized in the reset transistor formation region RST, the floating diffusion capacitor C2 and the reset transistor TRS constituting the capacitance, and the transfer transistor formation including the charge holding region TCP. The transfer accumulation unit Ts realized in the region TT, an amplification transistor TA as an amplification unit, and a selection transistor TS are included. The transfer storage unit Ts includes a transistor Tr that is a transfer control element formed in the transfer transistor formation region TT and a capacitor C1 for transfer storage provided under the transistor Tr. The capacitor C1 corresponds to the storage capacitor in the impurity layer 6 described above.

  A reset line 15a is connected to the gate 9 of the reset transistor TRS. A transfer line 15b is connected to the transfer gate 4 of the transistor Tr. The drain of the reset transistor TRS and the drain of the amplification transistor TA are connected to the VDD line 15c. For example, a voltage of 3.3 V is applied to the VDD line 15c. The source of the selection transistor TS is connected to the output line 15d. The output line 15 d is connected to the CDS circuit 16, and the output signal of the CDS circuit 16 is output to the horizontal scanning circuit 17. The gate TSg of the selection transistor TS is connected to the selection line 15e.

  The charge (photogenerated charge) generated in the photodiode Pd that performs photoelectric conversion is controlled in the capacitor C1 by controlling the transfer gate 4 of the transistor Tr connected to the transfer line 15b to a predetermined first voltage. Temporarily retained. The transfer of charge to the capacitor C1 is divided and performed here twice. Thereafter, the charge held in the capacitor C1 is transferred to the floating diffusion 8 of the reset transistor TRS by controlling the transfer gate 4 of the transistor Tr to have a predetermined second voltage.

  The reset transistor TRS changes the gate potential of the amplification transistor TA by holding the electric charge in the floating diffusion 8, and outputs an output corresponding to the gate potential based on the amount of charge in the floating diffusion 8 from the amplification transistor TA. Thus, the output voltage VO of the amplification transistor TA corresponds to the potential of the floating diffusion 8, that is, corresponds to the brightness of the incident light to the photodiode Pd. The output of the amplification transistor TA is output to the output line 15d via the selection transistor TS.

  When a predetermined voltage is applied to the gate of the reset transistor TRS, the reset transistor TRS becomes conductive, and the charge accumulated in the floating diffusion 8 flows to a fixed potential point. Thereby, discharge (initialization) of the photogenerated charges in the floating diffusion 8 is performed, and the potential of the floating diffusion 8 becomes a predetermined initial value.

  Accordingly, various timing signals having a predetermined voltage at a predetermined timing are supplied to the reset line 15a, the transfer line 15b, and the selection line 15e, whereby operations such as charge transfer are performed.

Further, although not shown in FIG. 3, an OFD resistor is connected to one end of the photodiode Pd. This OFD resistance corresponds to the N ⁻ impurity layer 11 constituting the OFD path. The other end of the resistor OFD is connected to a fixed potential point. Thereby, surplus charges generated in the photodiode formation region PD can be discharged via the resistor OFD.

  FIG. 4 is a potential diagram showing a potential state in each mode of the solid-state imaging device. FIG. 4 shows, from the top, the first accumulation mode (M1), the first batch transfer mode (M2), the second accumulation mode (M3), the second batch transfer mode (M4), the reset mode (M5), and the noise component readout. The potential in the mode (M6), the transfer mode (M7), and the signal component readout mode (M8) is shown. In FIG. 4, the potential relationship in each mode is shown with the positive direction being the direction in which the potential of an electron that is a photo-generated charge increases. When a predetermined timing signal is supplied from a timing control circuit (not shown) to the transfer line 15b or the like, the solid-state imaging device enters each mode state.

  In FIG. 4, the horizontal axis indicates the position along the line AA ′ in FIG. 1, and the vertical axis indicates the potential based on the electrons, and shows the potential relationship at each position. Yes. From the left side to the right side of FIG. 4, another impurity layer 10 of the reset transistor TRS, the gate 9, the floating diffusion 8, the impurity layer 7, the impurity layer 6 of the charge holding region TCP, the transfer gate 4, the storage well 2, and the OFD path The potential in the substrate at the position of the impurity layer 11 and the impurity layer 12 in the overflow drain region OFD is shown.

  In the first accumulation mode (M1), that is, the initial accumulation mode, a voltage is applied to the transfer gate 4 of the transfer transistor Tr so that a high potential barrier is formed between the accumulation well 2 and the charge holding region 6. Applied. The potential of the impurity layer 11 constituting the OFD path is lower than the potential of the transfer gate 4 region. This is because the charges overflowing from the accumulation well 2 are discharged to the impurity layer 12 in the OFD region. That is, as an accumulation procedure, the potential barrier of the transfer path is controlled by the gate voltage of the transfer transistor Tr at the same time for all the pixels, and the photo-generated charge by the photoelectric conversion element is at least transmitted through the impurity path 6 of the charge holding region TCP via the transfer path. The procedure of accumulating in the accumulation well 2 is performed while preventing the flow of the gas.

  In the first batch transfer mode (M2), that is, the first batch transfer mode, the transfer gate Tr of the transfer transistor Tr is high so that no potential barrier is formed between the accumulation well 2 and the impurity layer 6. A predetermined voltage is applied. At this time, since the potential of the impurity layer 6 is lower than that of the accumulation well 2, the charge accumulated in the accumulation well 2 flows into the impurity layer 6. That is, as a batch transfer procedure, a procedure for controlling the potential barrier of the transfer path by the gate voltage of the transfer transistor Tr and transferring the photogenerated charges accumulated in the accumulation well 2 to the impurity layer 6 is performed simultaneously for all pixels. .

  In the second accumulation mode (M3), that is, the second accumulation mode, an operation similar to that in the first accumulation mode (M1) is performed. As shown in FIG. 4, as the accumulation procedure, the potential barrier of the transfer path is controlled by the gate voltage of the transfer transistor Tr simultaneously for all the pixels, and the photo-generated charge by the photoelectric conversion element is at least charged through the transfer path. A procedure for accumulating in the accumulation well 2 while not flowing in the impurity layer 6 of TCP is performed.

In the second batch transfer mode (M4), that is, the second batch transfer mode, the same operation as in the first batch transfer mode (M2) is performed. As a batch transfer procedure, a procedure for controlling the potential barrier of the transfer path by the gate voltage of the transfer transistor Tr and transferring the photogenerated charges accumulated in the accumulation well 2 to the impurity layer 6 is performed simultaneously for all the pixels. As a result, as shown in FIG. 4, the charges transferred by both the first transfer and the second transfer are accumulated in the impurity layer 6.
Here, accumulation and batch transfer are divided and performed twice, but may be performed three or more times.

  In the reset mode (M5), a high potential barrier is formed between the accumulation well 2 and the impurity layer 6 in the transfer gate 4 of the transfer transistor Tr, and between the impurity layer 6 and the floating diffusion 8. In addition, a voltage is applied so that a high potential barrier is formed. Thereby, the charge flowing into the impurity layer 6 is held in the impurity layer 6. In this state, reset is performed as will be described later. The floating diffusion 8 may accumulate unnecessary charges during the above-described accumulation and transfer modes (M1 to M4) due to dark current or the like. Therefore, in the reset mode (M5), unnecessary charges in the floating diffusion 8 are transferred. Is called. That is, a predetermined voltage is applied to the gate 9 of the reset transistor TRS, the reset transistor RST becomes conductive, and the charge accumulated in the floating diffusion 8 flows to the fixed potential point. Therefore, the photogenerated charges in the floating diffusion 8 are discharged, and there are no charges in the floating diffusion 8 except for noise components.

  Also in the noise component readout mode (M6), a high potential barrier is formed between the accumulation well 2 and the impurity layer 6 in the transfer gate 4 of the transfer transistor Tr, and the impurity layer 6 and the floating diffusion 8 are A voltage is applied so that a high potential barrier is also formed between them. In this state, the noise component is read out. That is, as a noise component modulation procedure, a procedure is performed in which the potential barrier of the transfer path is controlled by the gate voltage of the transfer transistor Tr, and the noise component of the floating diffusion 8 is read in a state where no photo-generated charge flows through the floating diffusion 8. The noise component of the floating diffusion 8 is read out. This changes the gate potential of the amplifying transistor TA in accordance with the floating diffusion 8 in a state where there is no charge, so that the output voltage VO of the amplifying transistor TA corresponds to the state in which the floating diffusion 8 has no potential. It corresponds to the noise component. As for the signal of the noise component, the output of the amplification transistor TA is output to the output line 15d via the selection transistor TS.

  In the transfer mode (M7), a high predetermined voltage is applied to the transfer gate 4 of the transfer transistor Tr so as not to form a potential barrier between the impurity layer 6 and the floating diffusion 8. At this time, since the potential of the floating diffusion 8 is lower than that of the impurity layer 6, the charge accumulated in the impurity layer 6 flows into the floating diffusion 8. That is, as a transfer procedure for each line, a procedure is performed in which the potential barrier of the transfer path is controlled by the gate voltage of the transfer transistor Tr and the photogenerated charges accumulated in the impurity layer 6 are transferred to the floating diffusion 8.

  In the signal component readout mode (M8), a voltage is applied to the transfer gate 4 of the transfer transistor Tr so that a high potential barrier is formed between the impurity layer 6 and the floating diffusion 8. Thereby, the electric charge flowing into the floating diffusion 8 is held in the floating diffusion 8. Further, in this state, signal components are read out as described later. That is, as the signal component modulation procedure, there is a procedure for controlling the potential barrier of the transfer path by the gate voltage of the transfer transistor Tr and outputting a pixel signal corresponding to the photogenerated charge in a state where the photogenerated charge is held in the floating diffusion 8. Done.

  Next, a driving method for realizing the CDS function and the collective electronic shutter function in the solid-state imaging device according to the above configuration will be described according to an operation sequence.

  FIG. 5 is a timing chart showing a driving sequence of the solid-state imaging device according to the present embodiment. As shown in FIG. 5, in one frame period, the reset period R1, the first accumulation period A1, the first (initial) batch transfer period T1, the second accumulation period A2, the second batch transfer period T2, and the reading of the pixel signal Six periods of period S are included.

  The reset period R1 is an all-cell simultaneous reset period for simultaneously resetting all the pixels at the start of one frame, that is, all the sensor cells. The reset operation performed in this reset period is an operation for discharging remaining charges from the storage well 2, the impurity layer 6 as the temporary storage diffusion region, and the floating diffusion 8 for all pixels. After the reset operation, charge accumulation in the accumulation well 2 of each sensor cell is started.

  The accumulation period A1 subsequent to the reset period R1 is a period for storing each photocell generated in the photodiode formation region PD in the accumulation well 2 by receiving light in the accumulation mode (M1).

  During the collective transfer period T1 following the accumulation period A1, each sensor cell is in the collective transfer mode (M2), and the charges accumulated in the respective photodiode formation regions PD are simultaneously collected for all the pixels, that is, for all the sensor cells. This is a period in which batch transfer for transferring to the charge holding region TCP is performed. The batch transfer operation in this batch transfer period is performed by simultaneously applying a predetermined first voltage to the transfer gate 4 of the transfer transistor Tr described above.

When extremely intense light is incident on the photodiode formation region PD, an overflow charge may be generated in the accumulation period and the batch transfer period. Excess charge from the photodiode formation region PD is transferred to the overflow drain region OFD through the N ⁻ impurity layer 11 constituting the OFD path and discharged. That is, signal charges (photogenerated charges) are held in the charge holding region TCP, and at the same time, surplus charges are discharged through the overflow drain region OFD.

  After the batch transfer period T1, a second accumulation period A2 follows. Similar to the first accumulation period A1, the second accumulation period A2 is a period for accumulating photogenerated charges generated in the photodiode formation region PD in the accumulation well 2 upon receiving light.

  A second batch transfer period T2 follows the second accumulation period A2. In the second batch transfer period 2, as in the first batch transfer period T 1, each sensor cell enters the batch transfer mode, and the charges accumulated in each photodiode formation region PD are collectively transferred to all pixels, that is, all the sensor cells simultaneously. This is a period in which batch transfer for transferring to the charge holding region TCP of each sensor cell is performed.

  Up to this point, since the charge is held in the charge holding region TCP, as shown in FIG. 5, the pixel signal readout period S1 after the second batch transfer period T2 is the charge held in the charge holding region TCP. Is transferred to the floating diffusion 8 in the reset transistor formation region TRS for each selected line. That is, as shown in FIG. 5, in the pixel signal readout period, the horizontal blanking period occurs sequentially, that is, with a time lag, for the n lines from the first row L1 to the last row Ln. As shown in FIG. 6, the horizontal blanking period includes a reset period and a noise component / signal component readout period.

FIG. 6 is a timing chart showing the timing of reset, noise component readout, charge transfer, and signal component readout in the horizontal blanking period.
First, in the reset period R3, the charge in the floating diffusion 8 is discharged, and the potential of the floating diffusion 8 has an initial value. Subsequent to the reset period R3, a noise and signal component readout period S2 is provided.
At the noise component readout timing, first, the noise component is read out. Subsequently, charges are transferred from the impurity layer 6 to the floating diffusion 8 at the timing of charge transfer. Next, the signal component is read at the signal component read timing.

  Therefore, according to the solid-state imaging device according to the present embodiment, the photo-generated charge from the accumulation well in the photodiode formation region is divided and transferred to the impurity layer 6 below the transfer transistor Tr, so that the CMOS sensor The so-called dynamic range has been expanded. Furthermore, the solid-state imaging device according to the present embodiment reads out the noise component in the floating diffusion 8 before reading out the charge in the impurity layer 6, and then transfers the charge from the impurity layer 6 to the floating diffusion 8. Since the component is read out, the CDS function by the noise advance reading is realized. Furthermore, the solid-state imaging device according to the present embodiment resets all pixels before dividing and transferring the photogenerated charges from the accumulation well in the photodiode formation region to the impurity layer 6 below the transfer transistor Tr. Since the photo-generated charges are accumulated from the above, a batch electronic shutter function is also realized.

  Therefore, as a result, according to the solid-state imaging device according to the present embodiment, a high-quality image signal can be obtained.

(Second Embodiment)
First, the configuration of the solid-state imaging device according to the second embodiment of the present invention will be described. FIG. 7 is a plan view showing a planar shape of the solid-state image sensor device according to the present embodiment. FIG. 8 is a cross-sectional view taken along line A1-A1 ′ of FIG. However, the cross section of the wiring and its upper layer structure is not shown.

  As shown in FIG. 7, the solid-state imaging device according to the present embodiment also has a sensor cell array in which a plurality of sensor cells are arranged in a two-dimensional matrix on the substrate plane, similarly to the solid-state imaging device according to the first embodiment. It is. Each sensor cell accumulates photogenerated charges generated according to incident light and outputs a pixel signal at a level based on the accumulated photogenerated charges. A pixel signal of one screen can be obtained by arranging the sensor cells in a matrix. In FIG. 7, a range indicated by a dotted line is one sensor cell C which is a unit pixel. Each sensor cell has a photodiode formation region. The solid-state imaging device according to the present embodiment is a substrate modulation type sensor. In FIG. 7, four sensor cells are shown therein. Each of the four sensor cells has photodiode formation regions PDa, PDb, PDc, and PDd (hereinafter, each photodiode formation region is referred to as PD1 in the present embodiment). Since the structure of each sensor cell is the same, in the following description, the photodiode forming region PDa will be described. Note that this embodiment shows an example in which electrons are used as photogenerated charges. Even when holes are used as the photo-generated charges, the same configuration can be adopted.

  As shown in FIG. 8, a modulation transistor formation region TM1 is provided corresponding to the photodiode formation region PD1. Transfer transistor formation regions TT1 for transferring charges from the photodiode formation region PD1 to the modulation transistor formation region TM1 are provided between the photodiode formation region PD1 and the modulation transistor formation region TM1, respectively.

  In the present embodiment, the transfer transistor formation region TT1 has a carrier pocket region TCP1 as a charge holding region for temporarily holding charges. In the present embodiment, the charges (photogenerated charges) accumulated in each photodiode formation region PD1 are divided into all the pixels at once (that is, all sensor cells simultaneously) and divided into a plurality of times, here twice. Then, the data is transferred to the carrier pocket region TCP1 of each sensor cell and temporarily held, and then transferred from the carrier pocket region TCP1 to the modulation transistor formation region TM1 for each selected line.

  The configuration of the solid-state imaging device according to the present embodiment will be described in more detail with reference to FIGS. As shown in FIG. 7, the photodiode formation region PD1 has a substantially rectangular shape. The photodiode formation region PD1 is formed between the source line S and drain line D provided along the vertical direction of the two-dimensional matrix and the transfer gate line Tx and gate line G provided along the horizontal direction. ing. Although the gate line G is provided in a straight line in the lateral direction, the substantially ring-shaped gate 105 (described later) is bent along the shape of the gate 105.

As shown in FIG. 8, the sensor cell is formed on an N-type substrate 101a. On the N-type substrate 101a in the photodiode formation region PD1, a P ⁻ P-type well 2 is formed at a deep position of the substrate. On the other hand, on the N-type substrate 101a in the modulation transistor TM1 formation region, a P ⁻ P-type well 103 is formed at a relatively shallow position of the substrate. In FIG. 8 and the description thereof, the subscripts-and + of N and P indicate the state from the lighter portion (subscript-) to the darker portion (subscript ++) depending on the number. . This embodiment is a case where electrons are used as signal charges, but when holes are used as signal charges, this can be realized by reversing the polarities of the N-type and P-type.

On the P-type well 102 in the photodiode formation region PD1, an N layer is formed over substantially the entire surface of the photodiode formation region PD1, and the N layer functions as the storage well 104. A P ⁺ impurity layer 108 functioning as a pinning layer is formed on the substrate surface side of the photodiode formation region PD1 over substantially the entire surface. In the photodiode formation region PD1, an opening region is formed on the surface of the substrate 101, and an accumulation well 104 that is an N-type well in a region wider than the opening region is formed.

  A depletion region is formed in the boundary region between the P-type well 102 and the N-type accumulation well 104 formed on the substrate 101 below the photodiode formation region PD1 having the function of the photoelectric conversion element. In this depletion region, Photogenerated charges are generated by the light incident through the aperture region that receives light in the photodiode formation region. The generated photogenerated charge is accumulated in the accumulation well 104.

For example, a P-channel depletion MOS transistor is used as the modulation transistor Tm1 as amplification means formed in the modulation transistor formation region TM1. On the P-type well 103 in the modulation transistor formation region TM1, a substantially ring-shaped (octagonal in FIG. 7) gate (hereinafter also referred to as a ring gate or simply a gate) 105 is formed on the surface of the substrate 101 via a gate insulating film 110. Is formed. A P ⁺ impurity layer 111 constituting a channel is formed on the substrate surface under the ring gate 105. A P ⁺⁺ impurity layer is formed on the surface of the substrate at the center of the opening of the ring gate 105 to form a source region (hereinafter also simply referred to as a source) 112. An N layer is formed on the P-type well 103 in the modulation transistor formation region TM1 in accordance with the substantially outer peripheral shape of the ring gate 105 constituting the modulation transistor, and the N layer functions as the modulation well 106. In this modulation well 106, a ring-shaped carrier pocket 107 of an N type high concentration region which is a floating diffusion region by N ⁺ diffusion formed along the ring shape of the ring gate 105 is formed. A P ⁺ impurity layer is formed on the substrate surface around the ring gate 105 to form a drain region (hereinafter also simply referred to as a drain) 113. The P ⁺ impurity layer 111 constituting the channel is connected to the source region 112 and the drain region 113.

  The modulation well 106 controls the threshold voltage of the channel of the modulation transistor Tm1. The modulation transistor Tm1 includes a modulation well 106, a ring gate 105, a source region 112, and a drain region 113, and the channel threshold voltage changes according to the charge accumulated in the carrier pocket 107.

Further, as shown in FIG. 7, a P ⁺ layer gate contact region 105 a is formed near the surface of the substrate 101 at a predetermined position of the ring gate 105. At a predetermined position of the source region 112, a P ⁺ layer source contact region 112a is formed in the vicinity of the substrate 101 surface. At a predetermined position of the drain region 113, a drain contact region 113a of a P ⁺ layer is formed in the vicinity of the surface of the substrate 101.

  The charges accumulated in the accumulation well 104 are transferred to the modulation well 106 via the transfer transistor formation region TT1 described below and held in the carrier pocket 107. The source potential of the modulation transistor formation region TM1 functioning as the modulation transistor is in accordance with the amount of charge transferred to the modulation well 106, that is, incident light to the photodiode formation region PD1 functioning as a photodiode.

On the surface of the substrate 101 in the vicinity of the accumulation well 104, a diffusion region (hereinafter referred to as an OFD region) 114 for discharging unnecessary charges including overflow charges is formed by a high concentration N ⁺⁺ type impurity layer. The OFD region 114 serving as a discharging means for discharging unnecessary excess charges from the accumulation well overflows from the accumulation well 104 without being accumulated in the accumulation well 104 and does not contribute to the pixel signal (hereinafter referred to as unnecessary charge). Is an area for discharging to the substrate.

  The transfer transistor formation region TT1 will be described. As shown in FIG. 8, the transfer transistor formation region TT1 has a carrier pocket region TCP1 for temporarily holding charges in the substrate.

Specifically, the transfer transistor region TT1 is formed on the substrate surface side between the photodiode formation region PD1 and the modulation transistor formation region TM1 in one sensor cell. The transfer transistor region TT1 has a transfer gate 122 on the substrate surface via a gate insulating film 121 so that a channel is formed on the substrate surface. The channel of the transfer transistor region TT1, that is, the transfer path, is controlled by the voltage applied to the transfer gate 122 and the voltage applied to the P ⁺ impurity layer 125.

A carrier pocket region TCP1 is provided under the transfer gate 122. In the carrier pocket region TCP1, an N layer is formed on the P-type well 103 in the modulation transistor formation region TM1, and the N layer functions as a transfer accumulation well 123. In this transfer accumulation well 123, a transfer carrier pocket 124 is formed by N ⁺ diffusion.

  Further, the transfer gate 122 is formed on the surface side of the substrate, and a part of the transfer gate 122 covers the accumulation well 104 when viewed from the direction orthogonal to the surface of the substrate (shown by 104a in FIG. 8). ), And is provided on the surface via a gate insulating film 121.

Further, between the transfer accumulation well 123 and the modulation transistor formation region TM1, a P ⁺ impurity layer 125 is formed over the entire surface of the substrate. Under the P ⁺ impurity layer 125, an N-type impurity layer 126 is formed. This P ⁺ impurity layer 125 makes it possible to effectively control the potential barrier of the transfer path 126 formed between the carrier pocket 124 under the transfer gate 122 and the carrier pocket 107 under the modulation transistor. Since at the same time can be embedded impurity layer 126 under P ⁺ impurity layer 125, P ⁺ impurity layer 125 may exhibit a function as a pinning layer, suppress the generation of dark current.

  As shown in FIG. 7, the transfer gate 122 of the transfer transistor region TT1 has a substantially rectangular shape along one side of the rectangular photodiode formation region PD1. In the present embodiment, as shown in FIG. 7, since the ring gate 105 is provided in the vicinity of one corner of the photodiode formation region PD1, the ring gate 105 of the transfer gate 122 in the transfer transistor region TT1. The side portion has a shape that is partially cut off along the shape of the ring gate.

Further, when viewed from a direction perpendicular to the substrate surface, a carrier pocket 124 (not shown in FIG. 7) is formed inside the transfer gate 122 of FIG.
Further, as shown in FIG. 7, a P ⁺ layer gate contact region 122 a is formed near the surface of the substrate 101 at a predetermined position of the transfer gate 122.
Note that wiring layers such as the transfer gate line Tx and the source line S described above are formed on the substrate surface via an interlayer insulating film (not shown). The transfer gate 122, the source contact region 112a, and the like are electrically connected to each wiring in the wiring layer through a contact hole opened in the interlayer insulating film. Each wiring is made of a metal material such as aluminum.

  FIG. 9 is an equivalent circuit of the sensor cell of the solid-state imaging device according to the present embodiment. The sensor cell C includes a photodiode Pd1 realized in the photodiode formation region PD1, a modulation transistor Tm1 realized in the modulation transistor formation region TM1, and a transfer accumulation unit Ts1 realized in the transfer transistor formation region TT1. The transfer accumulation unit Ts1 includes a transistor Tr1 that is a transfer control element formed in the region TT1, and a capacitor C11 provided under the transistor Tr1. The capacitor C11 corresponds to the charge holding region corresponding to the carrier pocket 124 described above.

  The charge (photogenerated charge) generated in the photodiode Pd1 that performs photoelectric conversion is temporarily held in the capacitor C11 by controlling the transfer gate 122 of the transistor Tr1 to be a predetermined first voltage. Thereafter, the charge held in the capacitor C11 is transferred to the carrier pocket 107 of the modulation transistor Tm1 by controlling the transfer gate 122 of the transistor Tr1 to have a predetermined second voltage.

  The modulation transistor Tm1 is equivalent to a change in the back gate bias due to the charge held in the carrier pocket 107, and the channel threshold voltage changes according to the amount of charge in the carrier pocket 107. As a result, the output voltage VO1 of the modulation transistor Tm1 corresponds to the charge in the carrier pocket 107, that is, corresponds to the brightness of light incident on the photodiode Pd1.

  Further, FIG. 9 shows a variable resistor OFD1 connected to one end of the photodiode Pd1. The OFD region 114 is indicated by a variable resistor OFD1 in order to change the potential corresponding to the applied potential.

  FIG. 10 is a potential diagram illustrating a potential state in each mode of the solid-state imaging device. FIG. 10 shows, from the top, the first accumulation mode (M1), the first batch transfer mode (M2), the second accumulation mode (M3), the second batch transfer mode (M4), the reset mode (M5), and the noise component readout. The potential in the mode (M6), the transfer mode (M7), and the signal component readout mode (M8) is shown. In FIG. 10, the potential relationship in each mode is shown with the direction in which the potential of the electron becomes higher on the positive side. When a predetermined timing signal is supplied from a timing control circuit (not shown) to the transfer gate line Tx and the like, the solid-state imaging device enters each mode state.

  In FIG. 10, the horizontal axis indicates the position along the line A1-A1 ′ in FIG. 7 and the vertical axis indicates the potential based on the hole, and shows the potential relationship at each position. Yes. From the left side to the right side of FIG. 10, one end side of the ring gate 105, the source region 112, the other end side of the ring gate 105, the transfer gate 122 of the transfer transistor Tr1, the storage well 104, and the OFD region 114 are within the substrate. Shows the potential.

  In the accumulation mode (M1), a voltage is applied to the transfer gate 122 of the transfer transistor Tr1 so that a high potential barrier is formed between the accumulation well 104 and the carrier pocket 124. The potential of the OFD region 114 is lower than the potential of the transfer gate 122 region. This is because the electric charge overflowing from the accumulation well 104 is discharged to the OFD region 114. That is, as an accumulation procedure, the potential barrier of the transfer path is controlled by the gate voltage of the transfer transistor Tr for all the pixels at the same time so that the photo-generated charges due to the photoelectric conversion elements do not flow into the carrier pocket 124 through at least the transfer path. The procedure for accumulating in the accumulation well 104 is performed.

  In the first batch transfer mode (M2), that is, the first batch transfer mode, the transfer gate 122 of the transfer transistor Tr1 is low so that no potential barrier is formed between the storage well 104 and the carrier pocket 124. A predetermined first voltage is applied. At this time, since the potential of the carrier pocket 124 is lower than that of the accumulation well 104, the charge accumulated in the accumulation well 104 flows into the carrier pocket 124. That is, as a batch transfer procedure, a procedure for controlling the potential barrier of the transfer path by the gate voltage of the transfer transistor Tr1 and transferring the photogenerated charges accumulated in the accumulation well 104 to the carrier pocket 124 is performed simultaneously for all pixels. .

  In the second accumulation mode (M3), that is, the second accumulation mode, an operation similar to that in the first accumulation mode (M1) is performed. As shown in FIG. 10, as an accumulation procedure, the potential barrier of the transfer path is controlled by the gate voltage of the transfer transistor Tr1 at the same time for all the pixels, and the photo-generated charge by the photoelectric conversion element is at least charged through the transfer path. A procedure for accumulating in the accumulation well 104 while not flowing into the carrier pocket 124 of TCP1 is performed.

In the second batch transfer mode (M4), that is, the second batch transfer mode, the same operation as in the first batch transfer mode (M2) is performed. As a batch transfer procedure, a procedure for controlling the potential barrier of the transfer path by the gate voltage of the transfer transistor Tr1 and transferring the photogenerated charges accumulated in the accumulation well 104 to the carrier pocket 124 is performed simultaneously for all the pixels. As a result, as shown in FIG. 10, the charges transferred by both the first transfer and the second transfer are accumulated in the carrier pocket 124.
Here, the accumulation and batch transfer are divided into two, but may be divided into three or more.

  In the reset mode (M5), a high potential barrier is formed between the storage well 104 and the carrier pocket 124 in the transfer gate 122 of the transfer transistor Tr1, and between the carrier pocket 124 and the carrier pocket 107. In addition, a voltage is applied so that a high potential barrier is formed. Thereby, the electric charge flowing into the carrier pocket 124 is held in the carrier pocket 124. In this state, reset is performed as will be described later. The carrier pocket 107 may accumulate unnecessary charges during the above-described accumulation and transfer modes (M1 to M4) due to dark current or the like. Therefore, in the reset mode (M5), unnecessary charges in the carrier pocket 107 are transferred. Is called. That is, a predetermined voltage is applied to the transfer gate 122, the ring gate 105, the drain 113, and the source 112, and the charge accumulated in the carrier pocket 107 flows to a fixed potential point. Therefore, the photogenerated charges in the carrier pocket 107 are discharged, and there are no charges in the carrier pocket 107 except for noise components.

  Even in the noise component readout mode (M6), a high potential barrier is formed between the storage well 104 and the carrier pocket 124 in the transfer gate 122 of the transfer transistor Tr1, and the carrier pocket 124, the carrier pocket 107, A voltage is applied so that a high potential barrier is also formed between them. In this state, the noise component is read out. That is, as a noise component modulation procedure, a procedure is performed in which the potential barrier of the transfer path is controlled by the gate voltage of the transfer transistor Tr1 and the noise component in the carrier pocket 107 is read in a state where photogenerated charges do not flow into the carrier pocket 107.

  In the transfer mode (M7), a high predetermined voltage is applied to the transfer gate 122 of the transfer transistor Tr1 so as not to form a potential barrier between the carrier pocket 124 and the carrier pocket 107. At this time, since the potential of the carrier pocket 107 is lower than that of the carrier pocket 124, the charge accumulated in the carrier pocket 124 flows into the carrier pocket 107. That is, as a transfer procedure for each line, a procedure for controlling the potential barrier of the transfer path by the gate voltage of the transfer transistor Tr1 and transferring the photogenerated charges accumulated in the carrier pocket 124 to the carrier pocket 107 is performed.

  In the signal component read mode (M8), a voltage is applied to the transfer gate 122 of the transfer transistor Tr1 so that a high potential barrier is formed between the carrier pocket 124 and the carrier pocket 107. As a result, the electric charge flowing into the carrier pocket 107 is held in the carrier pocket 107. Further, in this state, signal components are read out as described later. That is, as a signal component modulation procedure, the potential barrier of the transfer path is controlled by the gate voltage and the drain voltage of the transfer transistor Tr1, and the photogenerated charge is held in the modulation well 106 according to the photogenerated charge from the carrier pocket 107. A procedure for outputting the obtained pixel signal is performed.

  Next, in the solid-state imaging device according to the above configuration, the driving method for realizing the CDS function and the collective electronic shutter function is the same as the operation sequence shown in FIG. 5 described in the first embodiment. That is, as shown in FIG. 5, one frame period includes a reset period R1, a first accumulation period A1, a first (initial) batch transfer period T1, a second accumulation period A2, a second batch transfer period T2, and a pixel signal. The six reading periods S are included.

  The reset period R1 is an all-cell simultaneous reset period for simultaneously resetting all the pixels at the start of one frame, that is, all the sensor cells. The reset operation performed in the reset period is an operation for discharging remaining charges from the storage well 104, the carrier pocket 124 and the carrier pocket 107, which are temporary storage diffusion regions, for all pixels. After the reset operation, charge accumulation in the accumulation well 104 of each sensor cell is started.

  The accumulation period A1 following the reset period R1 is a period for storing each photocell generated in the photodiode formation region PD1 in the accumulation well 104 by receiving light in the accumulation mode (M1).

  During the collective transfer period T1 following the accumulation period A1, each sensor cell enters the collective transfer mode (M2), and the charges accumulated in the respective photodiode formation regions PD1 are simultaneously collected for all the pixels, that is, for all the sensor cells. This is a period in which batch transfer for transferring to the charge holding region TCP1 is performed. The batch transfer operation in this batch transfer period is performed by simultaneously applying a predetermined first voltage to the transfer gate 122 of the transfer transistor Tr1 described above.

  When extremely intense light is incident on the photodiode formation region PD1, overflow charge may be generated in the accumulation period and the batch transfer period. Excess charge from the photodiode formation region PD1 is transferred to the overflow drain region OFD1 through the P impurity layer 11 constituting the OFD1 path and discharged. That is, signal charges (photogenerated charges) are held in the charge holding region TCP, and at the same time, surplus charges are discharged through the overflow drain region OFD1.

  After the batch transfer period T1, a second accumulation period A2 follows. Similar to the first accumulation period A1, the second accumulation period A2 is a period for accumulating photogenerated charges generated in the photodiode formation region PD1 in the accumulation well 104 upon receiving light.

  A second batch transfer period T2 follows the second accumulation period A2. In the second batch transfer period 2, as in the first batch transfer period T 1, each sensor cell is in the batch transfer mode, and the charges accumulated in each photodiode formation region PD 1 are collectively transferred to all the pixels, that is, all the sensor cells simultaneously. This is a period in which batch transfer for transferring to the charge holding region TCP1 of each sensor cell is performed.

Up to this point, since the charge is held in the charge holding region TCP1, as shown in FIG. 5, in the pixel signal readout period S1 after the second batch transfer period T2, the charge held in the charge holding region TCP1. Is transferred to the carrier pocket 107 in the modulation transistor formation region TM1 for each selected line. That is, as shown in FIG. 5, in the pixel signal readout period, the horizontal blanking period occurs sequentially, that is, with a time lag, for the n lines from the first row L1 to the last row Ln.
The horizontal blanking period is the same as that in FIG. 6 described in the first embodiment, and includes a reset period and a noise component / signal component readout period. That is, first, in the reset period R3, the charge in the carrier pocket 107 is discharged, and the potential of the carrier pocket 107 becomes the initial value. At the timing of the noise component readout in the noise and signal component readout period S2 following the reset period R3, the noise component is first read out. Subsequently, charges are transferred from the carrier pocket 124 to the carrier pocket 107 at the timing of charge transfer. Next, the signal component is read at the signal component read timing.

  FIG. 11 is a timing chart for explaining timing signals supplied to the transfer gate line Tx and the like in the horizontal blanking period of each cell. The horizontal blanking period (H) occurs for each selected line. FIG. 11 shows waveforms of timing signals applied to the transfer gate 122 of the transistor Tr1, the gate 105, the source 112, and the drain 113 of the modulation transistor Tm1 in the batch transfer period (T2) and the horizontal blanking period (H). .

  After the batch transfer period (T2), a predetermined voltage is applied to the transfer gate 122, the gate 105, the drain 113, and the source 112 in the reset period (R3). The charge in the carrier pocket 107 is discharged by the reset operation in the reset period (R3).

  In the noise component and signal component readout period (S2), first, a predetermined voltage is applied to the transfer gate 122, the gate 105, the drain 113, and the source 112 in order to read out the noise component (M6). Thereafter, by applying predetermined voltages to the transfer gate 122, the gate 105, the drain 113, and the source 112, charge transfer from the carrier pocket 124 to the carrier pocket 107 is performed (M7).

  Next, in order to read the signal component, a predetermined voltage is applied to the transfer gate 122, the gate 105, the drain 113, and the source 112, whereby the signal component is read from the charge amount of the carrier pocket 107 (M8).

  Therefore, according to the solid-state imaging device according to the present embodiment, the photo-generated charges from the accumulation well in the photodiode formation region are divided and transferred to the carrier pocket 124 below the transfer transistor Tr1, so that the substrate modulation type The so-called dynamic range of the sensor has been expanded. Furthermore, the solid-state imaging device according to the present embodiment reads the noise component in the carrier pocket 107 before reading the charge in the carrier pocket 124, and then transfers the charge from the carrier pocket 124 to the carrier pocket 107, Since the component is read out, the CDS function by the noise advance reading is realized. Furthermore, the solid-state imaging device according to the present embodiment resets all pixels before dividing and transferring the photo-generated charges from the accumulation well in the photodiode formation region to the carrier pocket 124 below the transfer transistor Tr1. Since the photo-generated charges are accumulated from the above, a batch electronic shutter function is also realized.

  Finally, the configuration when the solid-state imaging device according to the first and second embodiments described above is used in an imaging device such as a digital camera will be described. FIG. 12 is a partial configuration diagram illustrating a configuration example of an imaging device using the solid-state imaging device according to the first and second embodiments. The imaging device 51 is a digital still camera, for example, and performs imaging of a subject by operating a sensor 52 that is a solid-state imaging device in response to a user operation. As an input signal to the sensor 52, there is a timing signal supplied to the transfer gate line Tx and the like described above. The timing signal is supplied from the timing control circuit 53 to the sensor 52.

  The imaging device 51 includes a system control circuit (not shown) including a software program, a circuit, and the like for outputting various control signals such as a shutter control signal and a timing signal to the sensor 52 in accordance with a user operation. Have. Based on the control signal from the system control circuit, the timing control circuit 53 outputs various signals shown in FIG. 5, FIG. 6, FIG. 10 and FIG. The pixel signal from the sensor 52 is supplied to the signal processing circuit 54, and various signal processing such as gamma correction is performed. The image signal from the signal processing circuit 54 is supplied to recording and communication circuits.

  Therefore, as a result, according to the solid-state imaging device according to the present embodiment, a high-quality image signal can be obtained.

  The present invention is not limited to the above-described embodiment, and various changes and modifications can be made without departing from the scope of the present invention.

1 is a plan view showing a planar shape of a solid-state imaging device according to a first embodiment of the present invention. Sectional drawing along the AA 'line of FIG. The circuit diagram for demonstrating the equivalent circuit of the sensor cell which concerns on 1st this Embodiment. The potential diagram which shows the state of the potential in 1st this Embodiment. 6 is a timing chart showing a driving sequence of the solid-state imaging device. The timing chart which shows each timing in a horizontal blanking period. The top view which shows the planar shape of the solid-state image sensor device concerning 2nd Embodiment. Sectional drawing along the A1-A1 'line of FIG. The equivalent circuit of the sensor cell of the solid-state imaging device which concerns on 2nd this Embodiment. The potential diagram which shows the state of the potential in 2nd this Embodiment. The timing chart which shows each timing in a horizontal blanking period. FIG. 3 is a partial configuration diagram of an imaging apparatus using a solid-state imaging apparatus according to the first and second embodiments.

Explanation of symbols

1a, 101a substrate, 2,104 accumulation well, 3, 10, 11, 12, 108, 111, 125 impurity layer, 4,122 transfer gate, 5,110 gate insulating film, 6 impurity region, 7, 8 floating diffusion, 9 gate, 15a reset line, 15b transfer line, 15c VDD line, 15d output line, 15e select line, 102 P type well, 103 P type well, 105 ring gate, 106 modulation well, 107 carrier pocket, 112 source region, 113 drain region, 114 OFD, 124 carrier pocket for transfer

Claims (5)

Based on the accumulation well for accumulating the photogenerated charge generated by the photoelectric conversion element in response to the incident light, the floating diffusion region to which the photogenerated charge is transferred, and the photogenerated charge transferred to the floating diffusion region Transfer control having amplification means for outputting an amplified pixel signal, a charge holding region for controlling a potential barrier of a transfer path between the accumulation well and the floating diffusion region, and holding the photogenerated charge A solid-state imaging device driving method configured by arranging a plurality of unit pixels including an element,
At the same time for all the pixels, the transfer control element controls the potential barrier of the transfer path so that the photo-generated charge by the photoelectric conversion element does not flow to the charge holding region through the transfer path. An accumulation procedure for accumulating in the accumulation well;
A first transfer procedure for simultaneously controlling the potential barrier of the transfer path by the transfer control element to divide the photogenerated charge accumulated in the accumulation well and transfer it to the charge holding region for all the pixels simultaneously; ,
A noise component readout procedure for controlling the potential barrier of the transfer path by the transfer control element and reading the noise component of the floating diffusion region in a state where the photogenerated charge does not flow to the floating diffusion region;
A second transfer procedure for controlling the potential barrier of the transfer path by the transfer control element to transfer the photogenerated charge accumulated in the charge holding region to the floating diffusion region;
Signal component readout for outputting a pixel signal corresponding to the photogenerated charge from the floating diffusion region in a state where the photo control charge is held in the modulation well by controlling the potential barrier of the transfer path by the transfer control element. Procedure and
A method for driving a solid-state imaging device including:   The solid-state imaging device driving method according to claim 1, further comprising a reset procedure for resetting all pixels before the accumulation procedure. Based on the accumulation well for accumulating the photogenerated charge generated by the photoelectric conversion element in response to the incident light, the floating diffusion region to which the photogenerated charge is transferred, and the photogenerated charge transferred to the floating diffusion region Transfer control having amplification means for outputting an amplified pixel signal, a charge holding region for controlling a potential barrier of a transfer path between the accumulation well and the floating diffusion region, and holding the photogenerated charge A solid-state imaging device configured by arranging a plurality of unit pixels including an element;
At the same time for all the pixels, the transfer control element controls the potential barrier of the transfer path so that the photo-generated charge by the photoelectric conversion element does not flow to the charge holding region through the transfer path. An accumulation timing signal to be accumulated in the accumulation well and a potential barrier of the transfer path are simultaneously controlled by the transfer control element for all the pixels to divide the photogenerated charge accumulated in the accumulation well to hold the charge The first transfer timing signal to be transferred to the region and the transfer control element control the potential barrier of the transfer path to read out the noise component of the floating diffusion region without flowing the photogenerated charge to the floating diffusion region By the noise component readout timing signal and the transfer control element A second transfer timing signal for controlling the potential barrier of the transfer path to transfer the photogenerated charge accumulated in the charge holding area to the floating diffusion area; and the potential barrier of the transfer path by the transfer control element. A timing control circuit that outputs a signal component readout timing signal for outputting a pixel signal corresponding to the photogenerated charge from the floating diffusion region in a state where the photogenerated charge is held in the modulation well by controlling An imaging apparatus comprising:   The image pickup apparatus according to claim 3, wherein the solid-state image pickup apparatus further includes a discharge unit that discharges the excess charge in the accumulation well. 4. The amplifying unit includes a modulation transistor that controls a threshold voltage of a channel by the electric charge held in the floating diffusion region and outputs the pixel signal corresponding to the electric charge. 5. The imaging device according to 4.

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