JP2002134729A - Solid-state image pickup device and method for driving the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MOS-type image sensor that can take an image produced by an optical signal with the whole light-receiving surface, can convert the optical signal into an electrical signal, and can output the electrical signal as an image signal to the outside. SOLUTION: The MOS-type image sensor includes a light-receiving diode 111, having a light-receiving region that is formed on a substrate 11, and produces light-producing electric charges, when light is applied thereto; an insulating gate type field effect transistor 112 for detecting optical signals which is provided with a region 25 for accumulating the light-producing electric charges, outputs a threshold voltage modulated by the accumulation of the light-producing electric charges as an optical signal, and is formed on the substrate 11; an electric charge carrying path for carrying the light-producing electric charges produced in the light-receiving region to the region 25; an electric charge discharging path for discharging the light-producing electric charges produced in the light-receiving region to the substrate 11; and a means 42 for controlling a potential barrier with respect to the light-producing electric charges of the electric charge discharging path.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device and a method of driving the same, and more particularly, to a threshold voltage modulation type MOS image sensor used for a video camera, an electronic camera, an image input camera, a scanner or a facsimile. The present invention relates to a solid-state imaging device using the same and a driving method thereof.

[0002]

2. Description of the Related Art Semiconductor image sensors such as CCD type image sensors and MOS type image sensors are excellent in mass productivity, and have been applied to most image input device devices with the development of finer pattern technology. In particular,
In recent years, the power consumption is smaller than that of a CCD image sensor, and the sensor element and the peripheral circuit element are the same CMOS.
With the advantage that it can be created by technology, MOS
Type image sensors are being reviewed.

In view of such trends in the world, the present applicant has improved a MOS type image sensor, and has a sensor element having a carrier pocket (high concentration buried layer) 25 below a channel region of a MOS transistor for detecting an optical signal. (Japanese Patent Application No. 10-186453) has been filed to obtain a patent (registration number 2935492). That MOS
The type image sensor has a structure shown in FIG. 8 of the patent. In this structure, as shown in FIG. 8, the unit pixel is composed of a light receiving diode and a light signal detecting MOS transistor adjacent to the light receiving diode. The light receiving diode and the MOS transistor for detecting an optical signal are connected by a p-type well region. In the MOS transistor for detecting an optical signal, the gate electrode has a ring shape, an n-type source region is formed in the center, and an n-type drain region is formed so as to surround the outer periphery of the gate electrode. A p-type hole pocket is provided below the gate electrode and in the well region near the source region so as to surround the source region.

[0004] By the way, the CCD sensor releases the simultaneous shutter without a mechanical shutter, receives a video signal by a light receiving diode, reads the video signal to a transfer path, and then reads the signal read to the transfer path to the outside. It is possible to extract a stationary video signal without distortion. On the other hand, in the MOS image sensor, a focal plane shutter captures an image using a light receiving diode. Then, a video signal that has been photoelectrically converted by a series of repetitive operations is extracted. For example, a high reverse voltage is applied to each electrode during the initialization period to deplete each electrode, and light-emitting holes remaining in hole pockets are emitted. In the accumulation period, light-emitting holes are generated by light irradiation on the light receiving diode portion, transferred to the hole pockets and accumulated, and in the readout period, the electric field effect for light signal detection modulated in proportion to the amount of accumulated light-generated holes. An optical signal is detected by detecting a threshold value of the transistor.

[0005]

However, in the above-described image capturing system, when photographing a high-speed moving object or photographing with an image sensor having more pixels,
There is a problem that an image is distorted due to a time difference between the start of reading and the end of reading. The present invention has been made in view of the above-described problems of the related art, and takes in an image by an optical signal over the entire light receiving surface and simultaneously, converts the optical signal into an electric signal, and outputs the image as an image signal to the outside. An object of the present invention is to provide a MOS image sensor that can be taken out and a driving method thereof.

[0006]

In order to solve the above-mentioned problems, the present invention relates to a solid-state imaging device, and as a basic configuration of the solid-state imaging device, a light-receiving device that generates light-generated charges by irradiating light formed on a substrate. A light-receiving diode having a region, and a storage region for the photo-generated charges, and outputting a threshold voltage modulated by the accumulation of the photo-generated charges as an optical signal,
An insulated gate field effect transistor for optical signal detection formed on the substrate, a charge transfer path for transferring light generated charges generated in the light receiving region to the storage region, and a light generated charge generated in the light receiving region. A charge discharging path for discharging to the substrate; and a means for controlling a potential barrier of the charge discharging path for the photo-generated charges.

That is, FIG. 2A, FIG. 7A and FIG.
As shown in FIG. 1A, a unit pixel 101 including a light receiving diode 111 and an insulated gate field effect transistor (MOS transistor) 112 for detecting an optical signal adjacent to the light receiving diode 111 is provided. The light receiving diode 111 is formed in the p-type first well regions 15a and 43 formed in the n-type layer 32a on the p-type substrate 11, and the MOS transistor 112 is formed on the n-type layer 11 on the p-type substrate 11.
P-type second well region 15 formed in mold layer 32b
b. Also, the MOS transistor 112
A high concentration buried layer (carrier pocket: photo-generated charge accumulation region) 25 for accumulating photo-generated charges is formed in the second well region 15b below the channel region of FIG. ing.

Further, as shown in FIGS. 2 (a), 7 (a), 9 and 11 (a), n is located next to the p-type first well regions 15a, 43 of the light-receiving diode 111. Mold layer 3
A p-type overflow drain region 41 connected to the p-type substrate 11 with the interposition 2a therebetween is provided. Also, the overflow drain gates (OFDG: means for controlling a potential barrier for photo-generated charges) 42, 42a, 42b extend from above the end regions of the first well regions 15a, 43 to above the overflow drain region 41.
8a. Under the overflow drain gates 42, 42a, 42b, the surface layer and the n-type layer 32a in the end regions of the first well regions 15a, 43
A low-concentration n-type region or p-type region (surface region) 17c that connects the n-type impurity region 17 of the light-receiving diode 111 and the p-type overflow drain region 41 is formed in the surface layer. A path from the first well regions 15a and 43 to the p-type substrate 11 via the n-type layer 32a and the overflow drain region 41 constitutes a charge discharging path.
If necessary, overflow drain gates 42, 42a,
The potential barrier for the photo-generated charges in the charge discharging path is controlled by 42b.

In particular, as shown in FIGS. 8 and 10, the well regions 15a of the light-receiving diode 111 are held so as to be aligned in rows and columns, and in the column direction (or row direction).
A common overflow drain region 41 is provided for the first well region 15a which is obliquely adjacent to the first well region 15a. The overflow drain gates 42a and 42b pass over the overflow drain region 41 and are provided so as to bridge the adjacent first well regions 15a.

In the above configuration, the carrier pocket 2
In order to control the flow of the photo-generated charges to the photo-electric charges 5, the following characteristics are provided so that the potential barrier against the photo-generated charges can be controlled in the charge transfer path from the light receiving region to the carrier pocket 25. . First, as shown in FIG. 2A, the first and second well regions 15a and 15b are connected via a low-concentration p-type region 15c in the charge transfer path. .

Second, as shown in FIG. 7A, the first well region 43 of the light receiving diode 111 has a higher p-type impurity concentration than the second well region 15b of the MOS transistor 112. It is characterized by having.
Third, as shown in FIG. 11A, the first and second well regions 15a and 15b are arranged with the n-type layer 32a interposed therebetween, and the transfer gate 44 is provided in the first well region 15a. The second well region 15b is provided from above the end region to above the end region of the second well region 15b through above the n-type layer 32a. Under the transfer gate 44, a low concentration p-type region (surface region) 17d is formed on the surface of the n-type layer 32a.
Are formed. In some cases, the n-type layer 32a may be exposed on the surface without providing the p-type region 17d.

Next, a method of driving the solid-state imaging device of the present invention in the case where a solid-state imaging device having the above-described structure, in particular, holes (holes) are used as photo-generated charges will be described. First, an initialization operation is performed. In the initialization operation, an operation of discharging the photo-generated charges from at least the light receiving region and the carrier pocket 25 is performed for all the pixels. That is, the potential barrier of the charge discharging path is reduced with respect to the residual charge in the light receiving region, and the potential barrier of the path from the carrier pocket 25 to the substrate 11 is reduced with respect to the residual charge in the carrier pocket 25, so that the light receiving The residual charges in the region and the carrier pocket 25 are swept out.

Next, the operation proceeds to an accumulation operation. In the accumulation operation,
The operation of accumulating the photo-generated charges is performed in all the pixels. That is, a potential barrier is formed in the charge transfer path and the charge discharge path for the photo-generated charges in the light receiving region, and the light signal based on the image is taken in over the entire light receiving surface and simultaneously. As a result, photo-generated charges are generated in the light receiving region, and the photo-generated charges are accumulated in the light receiving region. Next, a potential barrier is formed in the charge discharge path for the photo-generated charges in the light receiving region and the potential barrier in the charge transfer path is lowered, and the photo-generated charges are transferred to the carrier pocket 25.

Next, the operation proceeds to a read operation. In the reading operation, the photoelectrically converted optical signals are read out line by line. Therefore, for all the pixels arranged in the row selected for reading the optical signal based on the photo-generated charges, and for all the pixels arranged in the row selected for reading the optical signal corresponding to the photo-generated charges, A potential barrier is formed in the charge transfer path for the photo-generated charges in the cell and the potential barrier in the charge discharge path is lowered, and a change in the threshold voltage corresponding to the amount of accumulated photo-generated charges is read. At this time, the photo-generated charges generated in the light receiving region when the light is continuously received in the light receiving region are discharged from the light receiving region to the substrate 11 through the charge discharging path. On the other hand, for all the pixels in the unselected row (non-selected row), a potential barrier is formed in the path from the carrier pocket 25 to the substrate 11 for the photogenerated charge in the carrier pocket 25, and the photogenerated charge is stored in the carrier pocket 25. In addition to the accumulation, a potential barrier is formed in the charge transfer path for the photo-generated charges generated in the light receiving area, and the potential barrier of the charge discharging path is lowered to transfer the photo-generated charges generated in the light receiving area to the charge discharging path. And the photo-generated charges in the carrier pocket 25 are prevented from leaking.

In this manner, the optical signals corresponding to the photo-generated charges are sequentially read out for each row. Note that the optical signal contains a noise signal component due to a residual carrier that causes noise. A special operation for removing a noise signal component may be performed. That is, as shown in FIG. 4, FIG. 5, and FIG. 6, in the read operation, following the read operation of the optical signal of the selected row, the potential applied state to the pixels of the non-selected row is kept as it is, and Are initialized in the same manner as described above, and subsequently, the threshold voltage in the initialized state is read out. Then, a signal of the difference between the threshold voltage corresponding to the amount of light generated charge and the threshold voltage in the initialized state is calculated, and a net optical signal component is output as a video signal.

The operation and effect achieved by the above configuration will be described below. The solid-state imaging device according to the present invention includes a charge discharging path for discharging the photo-generated charges generated in the light receiving region to the substrate 11, and means for controlling a potential barrier for the photo-generated charges in the charge discharging path. Specifically, the charge discharging path is the first well region 1 of the light receiving diode 111.
5a to n-type layer 32a and overflow drain region 4
1 is a path leading to the substrate 11. The means for controlling the potential barrier is the overflow drain gate 42 provided on the charge discharging path.

Therefore, when necessary, the flow of the photo-generated charges from the light receiving region toward the substrate 11 can be controlled. In the charge transfer path, the light receiving diode 111
A low-concentration p-type region 15c is interposed in a connection region between the first well region 15a of the MOS transistor portion and the second well region 15b of the MOS transistor portion.

The low-concentration p-type region 15c has a higher potential for holes than the surrounding first and second well regions 15a and 15b. In this case, by relatively adjusting the voltage applied to the gate electrode 19 and the voltage applied to the drain region 17a, the potential of the p-type region 15c can be adjusted so as to be a barrier against the photo-generated charges. Thus, when necessary, the flow of the photo-generated charges from the light receiving region toward the carrier pocket 25 can be controlled.

Further, the first well region 43 of the light receiving diode 111 has a higher p-type impurity concentration than the second well region 15b of the MOS transistor 112. Second well region 1 having a lower p-type impurity concentration
5b is a first well region 4 having a higher p-type impurity concentration.
The potential with respect to the photo-generated charges becomes higher than 3. In this case, the voltage applied to the gate electrode 19 and the drain region 17
By relatively adjusting the voltage applied to a, it is possible to adjust the potential difference so that the potential difference acts as a barrier to the photo-generated charges. This makes it possible to control the flow of the photo-generated charges from the light receiving region toward the carrier pocket 25.

The first well region 15a and the second well region 15b are connected via an n-type layer 32a, and a transfer gate 44 is provided on the connection region via an insulating film 18b. . In some cases, a low-concentration p-type region 17d may be formed below the transfer gate 44 in the surface layer of the n-type layer 32a. Transfer gate 4
The voltage applied to the region 4 can be adjusted so that the potential of the region becomes a barrier against photo-generated charges. This makes it possible to control the flow of the photo-generated charges from the light receiving region toward the carrier pocket 25.

In the driving method of the solid-state imaging device according to the present invention, the initialization period, the accumulation period, and the readout period are repeated in this order. In particular, initialization and accumulation in the carrier pocket 25 are performed for all the pixels in the initialization period and the accumulation period, and in the read operation, when the optical signal is read from the pixel in the selected row, the potential of the charge transfer path and the charge The potential of the discharge path is controlled to prevent the carriers accumulated in the carrier pockets 25 of the non-selected rows from leaking, and the photo-generated charges generated in the light receiving region during the read operation are moved to the carrier pockets 25. Instead, it can be discharged to the substrate 11.

Thus, an image based on an optical signal can be taken into the solid-state imaging device over the entire light receiving surface and simultaneously, the optical signal can be converted into an electric signal, and can be taken out of the solid-state imaging device as a video signal. When the first and second well regions 15a, 15b and the like are of the opposite conductivity type, that is, when the high-concentration buried layer 25 is an n-type, the high-concentration buried layer 25 becomes an electron pocket (carrier pocket). And the photo-generated electrons are accumulated.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a plan view showing an element layout in a unit pixel of a MOS image sensor according to a first embodiment of the present invention. FIG. 2 (a)
FIG. 2 is a sectional view taken along line II of FIG. 1.

As shown in FIGS. 1 and 2A, a light receiving diode 111 and an optical signal detecting M
The OS transistor 112 is provided adjacent to the OS transistor 112.
As the MOS transistor 112, an n-channel depletion MOS transistor (hereinafter sometimes simply referred to as a MOS transistor) is used. Unit pixel 1
Numeral 01 has a substantially rectangular shape and is oblique to the column or row direction. The unit pixels 101 are not particularly separated in one row, but are separated by a p-type overflow drain region 41.

The light-receiving diode 111 and the MOS transistor 112 are formed in different well regions, that is, a first well region 15a and a second well region 15b.
They are connected to each other via the mold region 15c. The first well region 15a in the portion of the light receiving diode 111 forms a part of a charge generation region by light irradiation. The second well region 15b in the portion of the MOS transistor 112 forms a gate region in which the threshold voltage of the channel can be changed by the potential applied to this region 15b.

In the part of the light receiving diode 111, FIG.
As shown in (a), an n-type layer 32a is formed on a p-type substrate 11.
Is formed, and the first well region 15a is formed on the n-type layer 32a. Further, an n-type impurity region (opposite conductivity type region) 17 is formed in the surface layer of the first well region 15a. MOS transistor 11
2, as shown in FIG. 2A, the p-type substrate 1
1 includes a high concentration p-type layer 11a,
It is thicker than 11 parts. An n-type layer (opposite conductivity type layer) 32b is formed on the p-type layer 11a, and the well region 15b is formed on the n-type layer 32b. On the surface of the semiconductor substrate above the well region 15b, a gate electrode 19 is formed via a gate insulating film 18.

The gate electrode 19 has a ring shape.
A source region 16 is formed in the surface layer of the well region 15b so as to be surrounded by the inner edge of the ring-shaped gate electrode 19. A drain region 17a is formed on the surface of the ring-shaped gate electrode 19 so as to surround the outer edge and extend from the well region 15b to the n-type layer 32a. On the light receiving diode 111 side, the drain region 17a extends to form the impurity region 17 of the light receiving diode 111. That is, the impurity region 17 and the drain region 17a are connected to the first and second well regions 15a and 15b.
Are formed integrally so as to cover most of the surface layer. In the following description, the term “drain region” may refer to a region including the impurity region 17 even if the reference numeral 17a is used to indicate the drain region.

A region between the source region 16 and the drain region 17a becomes a channel region. At a normal operating voltage, in order to keep the channel region in a depletion state, an appropriate concentration of n-type impurity is introduced into the channel region to form an n-type channel doped layer 17b. That n
In the well region 15b under the channel dope layer 17b, a carrier pocket (high-concentration buried layer; a photo-generated charge accumulation region) 25 is formed so as to surround the source region 16. In the carrier pocket 25, the carrier pocket 2
Since the p-type impurity concentration is higher than that of the first and second well regions 15a and 15b at the periphery of the photovoltaic element 5, the potential inside the carrier pocket 25 with respect to the photogenerated holes in the photogenerated charges is low. Become. Thus, light-generated holes can be collected in the carrier pocket 25.

The low-concentration p-type region (one conductivity type region) 15c interposed between the first and second well regions 15a and 15b is a drain region 1 on the light-receiving diode 111 side.
It is formed in a region corresponding to a boundary portion between 7a and the channel dope layer 17b. The path from the light receiving area to the carrier pocket 25, which is composed of the first well region 15a, the low concentration p-type region 15c, and the second well region 15b, is a charge transfer path.

Further, next to the p-type overflow drain region 41 separating the rows as described above, the n-type layer 3
A first well region 15a of the light receiving diode 111 is provided via the second well 2a. The overflow drain region 41 is connected to the substrate 11 and has a function of separating rows and discharging excess photo-generated charges to the substrate 11.

From the first well region 15a to the n-type layer 32a
A path leading to the substrate via the overflow drain region 41 is a charge discharging path. Further, in the charge discharging path, an overflow drain gate 42 is provided from above the end region of the first well region 15a to above the overflow drain region 41 via the gate insulating film 18a. Below the overflow drain gate 42, the n-type layer 32 from the surface of the end region of the first well region 15a is formed.
Low concentration n-type region (surface region) 17 over the surface layer of a
c is formed. That is, the n-type region 17c connects the overflow drain region 41 and the impurity region 17. In some cases, a low-concentration p-type region may be used instead of the low-concentration n-type region 17c.

The above elements are covered with an insulating film 26, and regions other than the light receiving window 24 of the light receiving diode 111 are shielded from light by a metal layer (light shielding film) 23 formed on the insulating film 26. Next, referring to FIG. 2B, the state of the change of the valence band (Ev) along one direction in a plane parallel to the surface from the overflow drain region to the carrier pocket 25, and the carrier pocket The state of the change of the valence band (Ev) along the depth direction from 25 to the substrate 11 will be described. FIG. 2 (b) is a cross-sectional view of FIG.
It is a figure which shows the mode of the change of the top of a valence band (Ev) along the II line. A path that is slightly deeper than the source region 16, the drain region 17a, and the impurity region 17 and that reaches the carrier pocket 25 on the left side with the light receiving region shown in the drawing as a center indicates how the valence band (Ev) in the charge transfer path changes. The path to the overflow drain region 41 on the right side shows how the valence band (Ev) in the charge discharging path changes.

On the left side of the first well region 15 as a light receiving region, a first well region 15a below the impurity region 17, a low concentration p-type region 15c, which constitutes a charge transfer path,
Second well region 15b below drain region 17a and channel region 17b, carrier pocket 25, second well region 15b below source region 16, carrier pocket 2
5, a second well region 15b below the channel region 17b and the drain region 17a is arranged. Further, a charge discharging path is formed on the right side of the first well region 15.
First well region 15a below impurity region 17, n-type layer 3
2a, overflow drain regions 41 are arranged. In this case, a state is shown in which no voltage is applied to any electrode or region. Also, the first and second well regions 15a
And the top of the valence band (Ev) at 15b is the reference level.

Between the light receiving area and the carrier pocket 25,
Due to the low concentration p-type region 15c and between the light receiving region and the overflow drain region 41, the n-type layer 32a
Each region has an energy level lower than the reference level. The region having a low energy level serves as a barrier to light-generated holes. Further, in the high-concentration p-type carrier pocket 25, the level is higher than the reference level, so that light generation holes are easily collected.

The height of the potential barrier is adjusted by adjusting the voltage applied to the gate 19, the overflow drain gate 42 and other regions to control the movement of the photo-generated holes to the carrier pocket 25 and the overflow drain region 41. Can be. Next, an overall configuration of a MOS image sensor using the unit pixels having the above structure will be described with reference to FIG. FIG. 3 is a circuit configuration diagram of the MOS image sensor according to the first embodiment of the present invention.

As shown in FIG. 3, the MOS image sensor has a two-dimensional array sensor configuration, and the unit pixels 101 having the above-described structure are arranged in a matrix in the column direction and the row direction. In addition, the vertical scanning signal (VS
Drive scan circuit 102 and the drain voltage (VD
D) The drive scanning circuit 103 is disposed on the left and right sides of the pixel area.

Vertical scanning signal supply line (VSCAN supply line)
.. Are provided one by one from the drive scanning circuit 102 for the vertical scanning signal for each row. The vertical scanning signal supply lines 59a, 59b,... Are connected to the gate electrodes 19 of the MOS transistors 112 in all the unit pixels 101 arranged in the row direction. Also, one drain voltage supply line (VDD supply line) 61a, 61b,... Is provided for each row from the drive scanning circuit 103 of the drain voltage (VDD). Each drain voltage supply line 61a, 61b,.
Is connected to the drain regions 17a of the optical signal detection MOS transistors 112 in all the unit pixels 101 arranged in the row direction.

The vertical output lines 60a, 60b,.
Are output one by one per column, and each vertical output line 60a, 60
b,... are M in all the unit pixels 101 arranged in the column direction.
Each of them is connected to the source region 16 of the OS transistor 112. The source region 16 of the MOS transistor 112 is connected to the boosted voltage supply lines 73a, 73b,.
Are connected to the step-up scanning circuit 108 through. First and second well regions 15 in carrier pocket 25
a, a high voltage for discharging the electric charge remaining in 15b is supplied.

Further, the source region 16 of the MOS transistor 112 has vertical output lines 60a, 60b,.
To the signal output circuit 105. And
The source region 16 is connected to a pair of first and second line memories including a capacitor (not shown) in the signal output circuit 105. The first line memory stores a first source potential when the photo-generated charges are accumulated in the carrier pocket 25, and the second line memory stores the photo-generated charges after the photo-generated charges are discharged from the carrier pocket 25. The second source potential is stored. Then, a voltage having a difference between the first and second source potentials is output as an optical signal through a differential amplifier or the like (not shown). In this embodiment, no active load such as a constant current source is connected to the source region 16.

Horizontal scanning signal (HSCAN) supply line 72
a and 72b are output one by one from the horizontal scanning signal (HSCAN) input scanning circuit 104 for each column. Each horizontal scanning signal (HSCAN) supply line 72a, 72b is a signal output circuit 1
05. The horizontal scanning signal (HSCAN) input scanning circuit 104 supplies a horizontal scanning signal to the signal output circuit 105 through each horizontal scanning signal (HSCAN) supply line 72a, 72b, and controls the timing of outputting an optical signal.

In accordance with the vertical scanning signal (VSCAN) and the horizontal scanning signal (HSCAN), the MOS transistor 112 of each unit pixel 101 is successively driven to produce an image which does not include a noise component due to residual charges, which is proportional to the amount of incident light. The signal (Vout) is read from the signal output circuit 105. Next, a light detection operation of a series of solid-state imaging devices will be briefly described with reference to FIGS.

FIG. 4 is a timing chart of each input / output signal for operating the MOS image sensor according to the present invention. FIG. 5 and FIG.
FIG. 9 is a schematic diagram showing a state of a change in an energy level (Ev) at an energy band of a light receiving diode 111, well regions 15a and 15b, a carrier pocket 25, an overflow drain region 41 and a peripheral portion thereof, particularly, a top of a valence band.

In this case, an n-channel depletion type MOS transistor formed in the p-type second well region 15b is used as the optical signal detecting MOS transistor 112. In the light detection operation, a series of processes including an initialization period (sweep period), an accumulation period, and a readout period are repeatedly performed. Here, for convenience, the description starts from the initialization period.
During the series of operations, the overflow drain region 4
It is assumed that 1 is grounded.

First, an initialization operation is performed. In the initialization operation, for all pixels,
The charge remaining in the first and second well regions 15a and 15b is discharged. That is, as shown in FIG. 4, the potential (Vp) of the drain region 17a (impurity region 17) is set for all the pixels.
d) is set to about 5 V, and the potential (Vg) of the gate electrode 19 is set.
Is approximately 7V. The potential (Vofdg) of the overflow drain gate 42 is set to the ground potential (zero potential). The potential of the drain region 17a extends to the source region 16 through the channel region.

At this time, the pn junction of the drain region 17a, the source region 16, and the impurity region 17 and the p
A voltage is applied to the n-junction, and the channel region 17b is kept conductive by the voltage applied to the gate electrode 19,
The voltage applied to the source region 16 and the drain region 17a is applied to the second well region 15b and the hole pocket 25. As a result, the upper region of the substrate 11 is depleted,
The high electric field generated at this time causes the light receiving diode 111
The remaining holes in the first well region 15a of the portion are directly discharged to the substrate 11, and the remaining holes are surely discharged from the second well region 15b including the carrier pocket 25. Further, as shown in FIG. 5B, the light receiving diode 1 is also passed through the overflow drain region 41 having a low potential.
Residual holes in the eleven well regions 15a are discharged.

Next, an accumulation operation is performed. Also in this case, for all pixels, light-generated holes are generated in the light receiving region, and transferred to the carrier pocket 25 for accumulation. For all the pixels, a voltage, for example, about 0.5 V (Vpd) is applied to the drain region 17 a of the optical signal detection MOS transistor 112.
Is applied. In addition, the drain potential (V
A gate voltage (Vg), for example, about 2 V, is applied so that the channel region is not depleted with respect to pd) and the source potential (Vps) and electrons are accumulated with a sufficient electron density. As a result, electrons having a sufficient electron density are accumulated in the channel region, and the source region 16 becomes the drain region 17.
a through the channel region, and the source region 16 has the same voltage (Vpd) as the voltage (Vpd) of the drain region 17a.
s) About 0.5V is applied. Further, 3 V (Vofdg) is applied to the overflow drain gate 42.

In the accumulation period, a gate voltage (Vg), for example, about 2 V, at which electrons are accumulated with a sufficient electron density without applying any depletion to the channel region, is applied to the gate insulating film 18 and the channel region. The hole generation center of the interface state at the interface is deactivated, and the emission of holes from the interface state, that is, the leak current is suppressed. Thus, accumulation of holes other than the photo-generated charges in the carrier pocket 25 is suppressed, and so-called white flaws can be prevented from occurring on the image screen.

Subsequently, light is applied to the light receiving surfaces of all the pixels and simultaneously to the light receiving diode 111. When the electron-hole pairs (photo-generated charges) are generated by light irradiation, as shown in FIG. 5C, the positive side of the p-type region 15c in the path (charge transfer path) from the light receiving area to the carrier pocket 25 is formed. Since the potential barrier for the holes and the potential barrier for the holes of the n-type layer 32a in the path (charge discharging path) from the light receiving region to the overflow drain region 41 are high, the light generated holes are accumulated in the light receiving diode 111. Will be.

Next, FIGS. 4 and 5 (d), (e),
As shown in (f), for all the pixels, the light-generated holes in the light receiving diode 111 are transferred to the carrier pocket 25 in three stages.
Transfer to and accumulate. Therefore, first, as shown in FIG. 5D, the potential (Vpd) of the drain region 17a of the optical signal detecting MOS transistor 112 is set to about 0.5 V and the potential (Vofdg) of the overflow drain gate 42 for all the pixels. ) Is maintained at 3 V, the potential (Vg) of the gate electrode 19 is set to the ground potential, and the potential of the well region 15b having the carrier pocket 25 is lowered with respect to the well region 15a of the light receiving portion.

Subsequently, the gate electrode 19 and the source region 1
6. The potential of the overflow drain gate 42 (Vg, V
ps, Vofdg), the potential (Vpd) of the drain region 17a is set to 3 V, and the potential of the second well region 15b having the carrier pocket 25 is changed with respect to the first well region 15a of the light receiving region. And lower it relatively further.

Finally, while maintaining the potential (Vg) of the gate electrode 19 in the previous state, the potential (Vpd) of the drain region 17a is set to 5 V, and the overflow drain gate 4
The potential (Vofdg) of 5 is set to 5 V, and the carrier pocket 2
The potential of the second well region 15b having the fifth region 5 is further lowered relatively to the first well region 15a of the light receiving region.

Next, a read operation is performed. In this readout period, the threshold voltage of each pixel, that is, the photoelectrically converted optical signal is read out for each row and stored in the storage device in the signal output circuit 105, and subsequently the horizontal output line 7
1 is output. First, for all pixels in the first row, V
From the SCAN drive scanning circuit 102, the gate electrode 1 of the selected row
9 to about 2V. The ground potential is output to an output line 59b to the gate electrode 19 of the non-selected row.
On the other hand, the VDD drive scanning line 61 is used for both the selected row and the unselected row.
a is kept at approximately 3 V (becomes the drain potential of the MOS transistor 112). The overflow drain gate 42 is set to the ground potential for both the selected and unselected rows.

At this time, a low electric field inversion region is formed in a part of the channel region above the carrier pocket 25 in the pixel of the selected row, and a high electric field region is formed in the remaining part of the channel region. The drain voltage-current characteristic of the MOS transistor 112 shows a saturation characteristic. As a result, the first line memory is charged, and when the charging is completed,
The light-modulated threshold voltage (source potential VoutS) is stored in the first line memory. Further, as shown by the solid line in FIG. 6G, since the potential of the overflow drain gate 42 is low, there is no barrier against the photo-generated holes in the charge discharging path. Therefore, light-generated holes generated by light irradiation in the light receiving region are discharged to the substrate 11 through the overflow drain region 41.

On the other hand, in the pixels in the non-selected rows, the energy level changes as shown by the dotted line in FIG. 6G, and the potential of the carrier pocket 25 becomes lower. Therefore, the light-generated holes stored in the carrier pocket 25 do not leak during the read operation of the selected row. Further, since the potential of the overflow drain gate 42 is low, light-generated holes generated by light irradiation in the light receiving region are discharged to the substrate 11 through the overflow drain region 41.

As described above, the read threshold voltage includes not only the voltage due to the light-generated holes but also the voltage due to the charges not due to the light-generated holes (ie, the noise voltage (VoutN)). I have. In order to remove this noise voltage from the optical signal, for the selected row on which the read operation was performed,
An operation of reading only the noise voltage (VoutN) is performed. That is, about 7 V is output to the output line 59a from the VSCAN drive scanning circuit 102 to the gate electrode 19 of the selected row. The output line 59b to the gate electrode 19 in the non-selected row is held at the ground potential. In addition, the VDD drive scanning line 61a is kept at about 5 V in both the selected row and the non-selected row. The overflow drain gate 42 holds the selected row and the unselected row at the ground potential. As a result, the energy level changes as shown by the solid line in FIG.
As in the case of the initialization operation shown in (b), residual charges are discharged from the semiconductor.

On the other hand, in the pixels in the non-selected rows, the energy level changes as shown by the dotted line in FIG. 6 (h), and the potential of the carrier pocket 25 becomes lower. Therefore, the light-generated holes stored in the carrier pocket 25 do not leak during the read operation of the selected row. Further, since the potential of the overflow drain gate 42 is low, light-generated holes generated by light irradiation in the light receiving region are discharged to the substrate 11 through the overflow drain region 41.

Next, as in the case of FIG. 6 (g), the energy level of the pixel in the selected row is changed as shown by the solid line in FIG. 6 (i), and the MOS transistor 112 is operated. As a result, the second line memory is charged, and when the charging is completed, the threshold voltage (source potential VoutN) in a state where the photo-generated holes are not accumulated in the carrier pocket 25 is stored in the second line memory. It is memorized. On the other hand, in the non-selected row, as in the case of FIG.
The energy level is changed as shown by the dotted line in (i) to prevent the light-generated holes stored in the carrier pocket 25 from leaking during the read operation of the selected row.

Thereafter, as shown by the solid line in FIG. 6 (j), the energy level is changed to change the source potentials VoutS and VoutN.
An operation of outputting a voltage having a difference between the two is performed. Thus, a video signal (Vout = VoutS-VoutN) proportional to the light irradiation amount
Can be taken out. Thereafter, FIGS. 6 (g) to 6
The operation of (j) is repeated to perform the read operation for each row. In the meantime, the state in which the light-generated holes are accumulated in the carrier pocket 25 is maintained in the non-selected row where the reading has not been performed yet.

By reading the photoelectrically converted optical signals from the pixels in all rows in this manner, one image can be displayed on the screen. As described above, the first aspect of the present invention
In the method of driving the solid-state imaging device according to the embodiment, the initialization period, the accumulation period, and the readout period are repeated in this order. In particular, initialization and accumulation in the carrier pocket 25 are performed for all the pixels in the initialization period and the accumulation period, and in the read operation, when the optical signal is read from the pixel in the selected row, the potential of the charge transfer path and the charge The potential of the discharge path is controlled so that the photo-generated charges stored in the carrier pockets 25 of the non-selected rows do not leak, and the photo-generated charges generated in the light receiving region during the read operation are transferred to the carrier pockets 25. It is possible to discharge from the overflow drain region 41 without moving.

As a result, the image based on the optical signal can be taken into the image sensor over the entire light receiving surface and at the same time, and the optical signal can be converted into an electric signal and taken out of the image sensor as a video signal. Further, since the charge generation region and the charge transfer region have a buried structure, in a series of accumulation operation-read operation-initialization operation (sweeping operation), when the photo-generated holes move, the semiconductor surface and the channel are removed. An ideal photoelectric conversion mechanism that does not interact with a noise source in the region can be realized.

(Second Embodiment) FIG. 7A is a sectional view of a solid-state imaging device according to a second embodiment. FIG.
FIG. 7B is a diagram showing how the energy level (Ev) at the top of the valence band changes along the line III-III in FIG. FIG. 7A is different from FIG. 2A in that the first well region 15a and the second well region 15b are different.
Without providing a low-concentration p-type region between the first well region 15a and the p-type impurity concentration of the second well region 15b.
Is higher than the p-type impurity concentration. In the figure, the other reference numerals are the same as those shown in FIG. 2A, and the description thereof is omitted because they are the same as those of FIG. 2A.

As a result, as shown in FIG. 7 (b), the light generation positive direction from the light receiving region toward the carrier pocket 25 is formed at the boundary between the first well region 15a and the second well region 15b in the charge transfer path. It is possible to form a potential barrier for holes such that the energy level is low for the holes, that is, the potential is high. Therefore, in the operation of accumulating the light-generated holes shown in FIG. 5C, the movement of the light-generated holes to the carrier pocket 25 and the overflow drain region 41 is prevented, and the light-generated holes are accumulated in the light receiving region. It is possible.

Thus, similarly to the first embodiment,
A series of operations consisting of an initialization operation, a storage operation, and a read operation is repeated to capture an image by an optical signal over the entire light receiving surface and simultaneously to an image sensor, convert the optical signal into an electric signal, and convert the image signal into an image signal. Can be taken out of the image sensor. (Third Embodiment) FIG. 8 is a plan view showing an element layout in a unit pixel of a MOS image sensor according to a third embodiment. FIG. 9 is a cross-sectional view of FIG.
It is sectional drawing which follows the IV line.

The third embodiment differs from the first embodiment in that the first well regions 15a of the light receiving diode 111 are aligned in rows and columns as shown in FIG. The first well regions 15a of the light receiving diodes 111 adjacent to each other in the column direction (or the row direction) are provided close to each other while being held, and the overflow drain region 4 common to the first well regions 15a is provided.
1 is provided. The overflow drain gate (OFDG) 42a passes over the overflow drain region 41 and is located between the adjacent well regions 15a.
This is a point provided over the gate insulating film 18a so as to bridge the line a.

As shown in FIG. 9, the structure below the overflow drain gate 42a is different from the structure below the overflow drain gate 42 in FIG. 2A from the overflow drain region 41 to the impurity region 17 of the light receiving diode 111. A feature is that two of the same configurations are combined in two directions with the square overflow drain region 41 as the center.

As shown in FIG. 8, the unit pixel has a substantially rectangular shape, and the direction of arrangement of the first well region 15a of the light receiving diode 111 and the gate electrode 19 of the MOS transistor 112 is the column direction or the row direction. The oblique direction with respect to the direction is the same as in the first embodiment. On the other hand, in order to satisfy the above condition, the first well region 15a of the light receiving diode 111 portion in the unit pixel and the gate electrode 19 of the MOS transistor 112 are arranged in the opposite direction in the adjacent pixel. Is different from the embodiment of the present invention.

In the figure, the other reference numerals are the same as those shown in FIG. 2A, and the description thereof is omitted because they are the same as those in FIG. 2A. In the third embodiment, the light receiving diodes 111 adjacent to each other in the column direction (or row direction) are held while the first well regions 15a of the light receiving diode 111 are aligned in rows and columns. The first well regions 15a are provided close to each other, and a common overflow drain region 41 is provided between the first well regions 15a.

As a result, unlike the first embodiment,
In particular, there is no need to provide a strip-shaped overflow drain region 41 that also functions as a diffusion isolation region, connecting the first well regions 15a with each other, across the rows. Other configurations are the same as those of the first embodiment, so that the second embodiment can also provide the same operation and effects as those of the first embodiment.

(Fourth Embodiment) FIG. 10 is a plan view showing an element layout in a unit pixel of a MOS image sensor according to a fourth embodiment. FIG.
FIG. 1A is a sectional view taken along the line VV in FIG. FIG.
FIG. 1B is a diagram showing a state of a change in energy level (Ev) at the top of the valence band along the line VI-VI in FIG. 11A. The first well regions 15a of the adjacent light receiving diodes 111 are provided close to each other while the first well regions 15a are held so as to be aligned in rows and columns, and the first well regions 15a are provided. The point that a common overflow drain region 41 is provided for each other is the same as in the third embodiment.

On the other hand, the fourth embodiment is different from the third embodiment in that, as shown in FIG. 11A, the light receiving diode 11 adjacent to the channel region 17b is different from the third embodiment.
The transfer gate (TG) 44 is provided at the boundary between the drain region 17a on the first side and the impurity region 17 of the light receiving diode 111 via the insulating film 18b. In this case, the first and second well regions 15a,
15b are located below the transfer gate 44 and in the n-type layer 32.
a, and the transfer gate 44 is provided from above the end region of the first well region 15a to above the end region of the second well region 15b. The first and second well regions 15a and 15b
It is connected by a low-concentration p-type region (surface region) 17d formed in the surface layer of the n-type layer 32a under the transfer gate 44.

Another configuration of the fourth embodiment is different from that of the third embodiment in that the pixels sharing the overflow drain region 41 are arranged obliquely to the column or row direction. The point is that they are the same.
Another difference is that the first well region 15a has an octagonal shape. In the figure, the other reference numerals are the same as those shown in FIG. 2A, and the description thereof is omitted because they are the same as those of FIG. 2A.

In the above description, the first and second well regions 15a and 15b correspond to the low-concentration p-type region 17 formed on the surface of the n-type layer 32a under the transfer gate 44.
Although connected by d, as shown in FIG. 12, the first well region 15a and the second well region 15b may be formed so as to sandwich the n-type layer 32a. As described above, in the fourth embodiment of the present invention, the first well region 15a and the second well region 1 in the charge transfer path.
The transfer gate 44 is provided on the connection region with the gate 5b via the insulating film 18b.

Therefore, the potential of the connection region can be adjusted by the voltage applied to the transfer gate 44 so that the potential of the connection region becomes a barrier against the photo-generated charges. Thus, when necessary, the flow of the photo-generated charges from the light receiving region toward the carrier pocket 25 can be controlled. Next, a method of driving the MOS image sensor having the configuration shown in FIG. 11 will be described with reference to FIGS. The same can be applied to a MOS image sensor having a configuration around the transfer gate 44 shown in FIG.

FIG. 13 is a timing chart of each input / output signal for operating the MOS type image sensor shown in FIG. 14 and 15 show the light receiving diode 111 and the well regions 15a and 15a in each operation.
FIG. 7B is a schematic diagram showing a state of changes in the energy level (Ev) at the top of the valence band, especially at the energy band at b, the carrier pocket 25, the overflow drain region 41, and the periphery thereof.

In this case, an n-channel depletion type MOS transistor formed in the p-type second well region 15b is used as the optical signal detecting MOS transistor 112. Next, the light detection operation of a series of solid-state imaging devices will be briefly described with reference to FIGS. In the light detection operation, a series of processes including an initialization period (sweep period), an accumulation period, and a readout period are repeatedly performed. Here, for convenience, the description starts from the initialization period.
During the series of operations, the overflow drain region 4
It is assumed that 1 is grounded.

First, an initialization operation is performed. In the initialization operation, the charges remaining in the carrier pocket 25 and the first and second well regions 15a and 15b are discharged for all the pixels through the operations of FIGS. 14A to 14D. As shown in FIG. 14A, the residual charges in the light receiving region are transferred to the carrier pocket 25. That is, as shown in FIG. 13, the potential of the drain region 17a (the impurity region 17) (V
pd) is set to about 3 V, and the potential (V
g) is set to approximately 0 V, and the transfer gate (TG) 44
Is set to about 0V, and the potential (Vofdg) of the overflow drain gate 42 is set to about 3V.

Next, as shown in FIG. 14B, the residual charges in the charge transfer path are transferred to the carrier pocket 25. That is, as shown in FIG.
(Impurity region 17) potential (Vpd), gate electrode 19
While the potential (Vg) of the overflow drain gate 42 and the potential (Vofdg) of the overflow drain gate 42 are maintained in the previous state, the potential of the transfer gate (TG) 44 is set to approximately 3V.

Subsequently, as shown in FIG. 14C, the potential (Vofdg) of the overflow drain region 41 is lowered.
Next, as shown in FIG. 14D, the charges remaining in the carrier pocket 25 and the first and second well regions 15a and 15b are discharged. That is, as shown in FIG. 13, the potential (Vpd) of the drain region 17a (impurity region 17) is set to about 6 V and the potential (Vg) of the gate electrode 19 is set to about 8 V for all the pixels. Further, the potential (Vtg) of the transfer gate (TG) 44 is set to about 8V. Further, the potential of the overflow drain gate 42 (Vofdg)
Is the ground potential (zero potential). The potential (Vpd) of the drain region 17a extends to the source region 16 through the channel region.

At this time, the pn junction of the drain region 17 a, the source region 16, the impurity region 17 and the p
A voltage is applied to the n-junction, and a voltage (Vg) applied to the gate electrode 19 is applied to the second well region 15b and the n-type layer 32b below the second well region 15b. As a result, the upper region of the substrate 11 is depleted, and the high electric field generated at this time causes the residual holes in the first well region 15a of the light receiving diode 111 to be directly discharged to the substrate 11 and the carrier to be removed. Residual holes are reliably discharged from the second well region 15b including the pocket 25. Further, as shown in FIG. 14D, the residual holes in the first well region 15a of the light receiving region are also discharged through the overflow drain region 41 having a low potential.

Next, an accumulation operation is performed. In the accumulation operation, as shown in FIGS. 14 (e) and (f), and FIGS. 15 (a) and (b), for all pixels, light-generated holes are generated in the light receiving region and transferred to the carrier pocket 25. And accumulate. A voltage (Vpd), for example, about 1 V is applied to the drain region 17a of the MOS transistor 112 for detecting an optical signal. In addition, a gate voltage (Vg) such that the channel region is not depleted with respect to the drain potential (Vpd) and the source potential (Vps) in the gate electrode 19 and electrons are accumulated with a sufficient electron density, for example, Apply about 2V.
As a result, electrons having a sufficient electron density are accumulated in the channel region, the source region 16 is connected to the drain region 17a through the channel region, and the source region 16 has the same voltage (Vps) as the voltage (Vpd) of the drain region 17a. 1
V is applied. Further, 3 V (Vofdg) is applied to the overflow drain gate 42.

Subsequently, light is applied to the light receiving surfaces of all the pixels and simultaneously to the light receiving diodes 111. When electron-hole pairs (photo-generated charges) are generated by light irradiation, FIG.
As shown in (2), since the potential barrier for the holes of the n-type layer 32a in the path (charge discharging path) from the light receiving region to the overflow drain region 41 is high, the light generated holes are accumulated in the light receiving diode 111. become. Since the potential barrier for holes in the n-type layer 32b in the path (charge transfer path) from the light receiving region to the carrier pocket 25 is somewhat lower, some of the potential starts to be transferred to the carrier pocket 25. .

Next, as shown in FIGS. 14 (f) and 15 (a), the light-generated holes of the light-receiving diode 111 are transferred to the carrier pocket 25 and accumulated in two steps for all the pixels. Therefore, first, as shown in FIG.
For all the pixels, while keeping the potential (Vtg) of the transfer gate 44 at the ground potential and the potential (Vofdg) of the overflow drain gate 42 at 3 V, the drain region 17a of the MOS transistor 112 for detecting an optical signal is maintained. The potential (Vpd) is increased to about 3 V, the potential (Vg) of the gate electrode 19 is set to the ground potential, and the potential of the second well region 15b having the carrier pocket 25 is changed with respect to the first well region 15a of the light receiving region. Lower. As a result, a potential distribution is formed in which the generated charges in the light receiving region are directed from the light receiving region to the carrier pocket 25 via the charge transfer region, and the photo-generated holes are formed in the carrier pocket 25.
It is led toward.

Subsequently, the potential of the drain region 17a (Vp
d), potential of gate electrode 19 (Vg), source region 16
The potential (Vtg) of the transfer gate 44 is increased to 3 V while the potential (Vofdg) of the overflow drain gate 42 and the potential (Vofdg) of the overflow drain gate 42 are maintained in the previous state, and the photo-generated holes in the charge transfer path are removed from the carrier pocket. The electric field directed to 25 is further strengthened.

Finally, as shown in FIG. 13, the potential (Vpd) of the drain region 17a and the potential (V
g), the potential (Vtdg) of the overflow drain gate 42 while keeping the potential (Vtg) of the transfer gate 44 and the potential (Vps) of the source region 16 in the previous state.
Is the ground potential. As shown in FIG. 15 (b), the photo-generated charges remaining in the light receiving region
After that, the light is discharged to the substrate 11 side.

Next, after the charge transfer, as shown in FIG. 13, the potential (Vtg) of the transfer gate 44, the potential (Vps) of the source region 16, and the potential (Vofdg) of the overflow drain gate 42 were held in the previous state. As it is, the potential (Vpd) of the drain region 17a is set to about 1V, and the potential (Vg) of the gate electrode 19 is set to about 2V. Next, a read operation is performed. In this readout period, the threshold voltage of each pixel, that is, the photoelectrically converted optical signal is read out for each row, stored in the storage device in the signal output circuit 105, and subsequently output to the horizontal output line 71 as a video signal.

First, as shown in FIG. 13, for all the pixels, the potential (Vpdg) of the transfer gate 44 and the potential (Vofdg) of the overflow drain gate 42 are maintained in the previous state, and the potential (Vpg) of the drain region 17a is maintained.
d) is set to 3V. Further, the potential (Vg) of the gate electrode 19 is set for all pixels in the selected first row (selected row).
Is maintained at about 2 V, and the gate electrode 1 in a non-selected row is
The potential (Vg) of No. 9 is a ground potential.

At this time, a low electric field inversion region is formed in a part of the channel region above the carrier pocket 25 in the pixel in the selected row, and a high electric field region is formed in the remaining part of the channel region. The drain voltage-current characteristic of the MOS transistor 112 shows a saturation characteristic. As a result, the first line memory is charged, and when the charging is completed,
The light-modulated threshold voltage (source potential VoutS) is stored in the first line memory. Further, as shown by the solid line in FIG. 15D, since the potential of the overflow drain gate 42 is low, there is no barrier against the photo-generated holes in the charge discharging path. Therefore, light-generated holes generated by light irradiation in the light receiving region are discharged to the substrate 11 through the overflow drain region 41.

On the other hand, in the pixels in the non-selected rows, FIG.
As shown by the dotted line, the energy level changes, and the potential of the carrier pocket 25 becomes lower. For this reason,
The light-generated holes stored in the carrier pocket 25 do not leak during the read operation of the selected row. Further, since the potential of the overflow drain gate 42 is low, light-generated holes generated by light irradiation in the light receiving region are discharged to the substrate 11 through the overflow drain region 41.

Thereafter, the operation of changing the energy level and outputting the source voltage (VoutS) is performed as shown by the solid line in FIG. In this way, a video signal (Vout = VoutS) proportional to the light irradiation amount can be extracted. Thereafter, the operation of FIGS. 15D to 15E is repeated to perform the read operation for each row. In the meantime, the state in which the light-generated holes are accumulated in the carrier pocket 25 is maintained in the non-selected row where the reading has not been performed yet.

By reading the photoelectrically converted optical signals from the pixels in all rows in this manner, one image can be displayed on the screen. In the above, unlike the first embodiment, the noise signal (VoutS) is converted from the optical signal (VoutS).
No operations except for N) are performed, but if necessary,
Similarly to the embodiment, after the operation of reading the optical signal by the light-generated holes shown in FIG. 15D, the operation of initializing the carrier pocket 25 and the source potential in the initialized state, that is, the noise voltage Only the operation of reading out is performed. Then, in the operation of reading an optical signal from the line memory shown in FIG. 15E, an operation of outputting a voltage having a difference between the source potentials VoutS and VoutN is performed. In this way, a video signal (Vout = VoutS-VoutN) proportional to the light irradiation amount can be extracted.

As described above, also in the fourth embodiment, as in the first embodiment, the initialization period, the accumulation period, and the read period are repeated in this order. In particular, initialization and accumulation in the carrier pocket 25 are performed for all the pixels in the initialization period and the accumulation period, and in the read operation, when the optical signal is read from the pixel in the selected row, the potential of the charge transfer path and the charge The potential of the discharge path is controlled to prevent the carriers accumulated in the carrier pockets 25 of the non-selected rows from leaking, and the photo-generated charges generated in the light receiving region during the read operation are moved to the carrier pockets 25. Instead of the substrate 1 through the overflow drain region 41,
1 can be discharged.

As a result, an image based on an optical signal can be taken into the image sensor over the entire light receiving surface and simultaneously, and the optical signal can be converted into an electric signal and taken out of the image sensor as a video signal. In addition, since other configurations of the fourth embodiment are the same as those of the first embodiment, the fourth embodiment has the same operation and effects as those of the first embodiment. be able to.

(Fifth Embodiment) FIG. 16 is a plan view showing an element layout in a unit pixel of a MOS image sensor according to a fifth embodiment. Fifth
In the fourth embodiment, the point that the transfer gate 44a and the overflow drain region 41 are provided is the same as that of the fourth embodiment, but the point that the overflow drain region 41 is provided for each pixel is the same as that of the fourth embodiment. This embodiment is different from the embodiment.

In the figure, reference numeral 42C denotes an overflow drain gate provided from the end region of the first well region 15a to the overflow drain region 41, and 17C denotes an overflow drain gate 42c.
Is a low-concentration n-type region or a p-type region provided on the surface layer of a region from the end region of the first well region 15a to the overflow drain region 41.

As described above, the fifth embodiment has the same configuration as the fourth embodiment except that the overflow drain region 41 is provided for each pixel. In this embodiment, the same operation and effect as those of the fourth embodiment can be obtained. As described above, the present invention has been described in detail by the embodiment. However, the scope of the present invention is not limited to the example specifically shown in the embodiment, and the scope of the present invention is not limited to the scope of the present invention. Modifications of the form are included in the scope of the present invention.

For example, in the above embodiment, the line memory consisting of the input capacitor is directly connected to the source region 56 in the signal output circuit, but a constant current source is connected in parallel to the line memory, and the source follower connection is made. Is also good. In this case, the switched capacitor circuit need not be provided.
Although the first and second well regions 15a and 15b are formed in the n-type layers 32a and 32b on the p-type substrate 11, instead of the n-type layers 32a and 32b, a p-type epitaxial layer is formed. To form an n-type layer, and the first and second well regions 15a and 15b may be formed in the n-type layer.

Further, although the p-type substrate 11 is used,
Instead, an n-type substrate may be used. In this case, in order to obtain the same effect as in the above embodiment, the conductivity type of each layer and each region described in the above embodiment and the like may be all reversed. In this case, carriers to be accumulated in the carrier pocket 25 are electrons out of electrons and holes.

[0098]

As described above, in the solid-state imaging device according to the present invention, the charge discharging path for discharging the photo-generated charges generated in the light receiving region to the substrate and the potential barrier of the charge discharging path for the photo-generated charges are controlled. Means. Therefore,
When necessary, it is possible to control the flow of the photo-generated charges from the light receiving region toward the substrate.

Further, the charge transfer path for transferring the photo-generated charges generated in the light receiving region to the storage region of the MOS transistor for detecting a light signal has a means for controlling a potential barrier for the photo-generated charges. Thereby, when necessary, the flow of the photo-generated charges from the light receiving region to the accumulation region can be controlled. In the method for driving the solid-state imaging device according to the present invention, the initialization operation, the accumulation operation, and the read operation are repeated in this order. In particular, in the initialization operation and the accumulation operation, initialization and accumulation in the accumulation region are performed for all the pixels, and in the read operation, when the optical signal is read from the pixel in the selected row, the potential of the charge transfer path and the charge discharge By controlling the potential of the path and preventing the carriers accumulated in the accumulation region of the non-selected row from leaking, without moving the photo-generated charges generated in the light receiving region during the reading operation toward the accumulation region, It can be made to discharge to the substrate.

As a result, an image based on an optical signal can be taken into the solid-state imaging device over the entire light-receiving surface and simultaneously, the optical signal can be converted into an electric signal, and can be taken out of the solid-state imaging device as a video signal.

[Brief description of the drawings]

FIG. 1 is a plan view showing an element layout in a unit pixel of a MOS image sensor according to a first embodiment of the present invention.

FIG. 2A is a cross-sectional view taken along the line II of FIG. (B) is along the line II-II in FIG.
FIG. 9 is a diagram illustrating a state of a change at the top of a valence band (Ev).

FIG. 3 is a diagram illustrating an overall circuit configuration of the MOS image sensor of FIG. 1;

FIG. 4 is a timing chart of each input / output signal for operating the MOS image sensor according to the first embodiment of the present invention.

FIG. 5 is a schematic diagram showing a state of a change in an energy level (Ev) at an energy band of a light-receiving diode, a well region, a carrier pocket, an overflow drain region and a peripheral portion thereof, particularly a top of a valence band, in each period of FIG. (Part 1).

FIG. 6 is a schematic diagram showing a state of a change in an energy level (Ev) at an energy band of a light receiving diode, a well region, a carrier pocket, an overflow drain region and a peripheral portion thereof, particularly a valence band at each period in FIG. (Part 2).

FIG. 7 (a) is a diagram showing an M according to a second embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along line II of FIG. 1, illustrating a structure of an element in a unit pixel of the OS-type image sensor. FIG. 3B is a diagram showing a state of a change in the top of the valence band (Ev) along the line III-III in FIG.

FIG. 8 is a plan view showing an element layout in a unit pixel of a MOS image sensor according to a third embodiment of the present invention.

FIG. 9 is a sectional view taken along the line IV-IV of FIG. 8;

FIG. 10 is a plan view showing an element layout in a unit pixel of a MOS image sensor according to a fourth embodiment of the present invention.

11 is a cross-sectional view along the line VV in FIG.

FIG. 12 is also a cross-sectional view showing another configuration of the transfer gate and its peripheral portion.

FIG. 13 is a timing chart of input / output signals for operating the MOS image sensor shown in FIGS. 10 and 11;

FIG. 14 is a schematic diagram showing a change in energy level (Ev) at the energy band of a light-receiving diode, a well region, a carrier pocket, an overflow drain region and its surroundings, particularly the top of a valence band, in each period of FIG. (Part 1).

FIG. 15 is a schematic diagram showing changes in the energy level (Ev) at the energy band of the light-receiving diode, well region, carrier pocket, overflow drain region and its surroundings, particularly at the top of the valence band, in each period of FIG. (Part 2).

FIG. 16 is a plan view showing an element layout in a unit pixel of a MOS image sensor according to a fifth embodiment of the present invention.

[Explanation of symbols]

11, 11a Substrate 15a, 43 First well region 15b Second well region 15cp p-type region (one conductivity type region) 16 Source region 17 Impurity region (opposite conductivity type region) 17a Drain region 17b Channel dope layer 17c, 17d Surface layer region 18, 18a, 18b Gate insulating film 19 Gate electrode 25 Carrier pocket (high concentration buried layer; storage region for photogenerated charge) 32a, 32b N-type layer (opposite conductivity type layer) 41 Overflow drain region 42, 42a, 42b, 42c Overflow drain gate 44, 44a Transfer gate 59a, 59b VSCAN supply line 60a, 60b Vertical output line 61a, 61b VSCAN supply line 62a, 62b VDD supply line 71 Horizontal output line 72a, 72b HSCAN supply line 73a, 73b Boost voltage Supply Reference Signs List 101 unit pixel 102 VSCAN drive scan circuit 103 VDD drive scan circuit 104 HSCAN input scan circuit 105 signal output circuit 107 video signal output terminal 108 boost scan circuit 111 light receiving diode 112 optical signal detection insulated gate field effect transistor (for optical signal detection MOS transistor)

Continued on front page F-term (reference) 4M118 AA10 AB01 BA14 CA04 CA20 FA06 FA14 FA19 FA34 FA39 FA40 FA42 5C024 AX01 CX11 CX17 CY16 GX03 GX16 GY31 GZ04 HX35 HX40 HX41 HX47 JX21

Claims (17)

[Claims] 1. A light-receiving diode having a light-receiving region formed on a substrate and generating light-generated charges by light irradiation, and a threshold voltage provided with a storage region for the light-generated charges and modulated by the accumulation of the light-generated charges. An optical signal detection insulated gate field effect transistor formed on the substrate, a charge transfer path for transferring light generated charges generated in the light receiving region to the storage region, A charge discharging path for discharging the photo-generated charges generated in step (c) to the substrate; and a means for controlling a potential barrier of the charge discharging path for the photo-generated charges. 2. The light-receiving diode is formed in a first well region of one conductivity type formed in an opposite conductivity type layer formed on the substrate of one conductivity type, and in a surface layer of the first well region. The opposite conductivity type region, the insulated gate field effect transistor for optical signal detection is a second well region of one conductivity type formed in the opposite conductivity type layer, and a ring-shaped gate electrode. A source region formed in the second well region surrounded by an inner edge of the ring-shaped gate electrode, and a drain formed in the second well region surrounding an outer edge of the ring-shaped gate electrode A region, a channel region between the drain region and the source region, and the first and second regions formed in a second well region below the channel region and surrounding the source region. Higher than the well area of A lightly doped region having a high impurity concentration, the light receiving region includes the first well region, the photogenerated charge accumulation region is the high concentration buried layer, and the charge transfer path is The first well region and the second well region;
2. The solid-state imaging device according to claim 1, further comprising: 3. An overflow drain region of one conductivity type, which is adjacent to the first well region via the opposite conductivity type layer and is connected to the substrate, and an end region of the first well region. An overflow drain gate formed over the overflow drain region via a gate insulating film, wherein the charge discharging path extends from an end region of the first well region to the overflow drain region through the opposite conductivity type layer. 3. The solid-state imaging device according to claim 2, further comprising a path that leads to the charge drain path, and a unit that controls a potential barrier against light generated charges in the charge discharge path is the overflow drain gate. 4. A one-conductivity-type region is formed at least in a surface layer of a path from the first well region to the overflow drain region through the opposite-conductivity-type layer in the charge discharging path. The solid-state imaging device according to claim 3, wherein: 5. The semiconductor device according to claim 5, wherein an opposite conductivity type region is formed at least in a surface layer of a path from the first well region to the overflow drain region through the opposite conductivity type layer in the charge discharging path. The solid-state imaging device according to claim 3, wherein: 6. The charge transfer path by interposing a one conductivity type region having a lower concentration than the first well region and the second well region between the first well region and the second well region. The solid-state imaging device according to any one of claims 2 to 5, wherein a potential barrier for the photo-generated charges is formed therein. 7. The first well region and the second well region are connected to each other, and the impurity concentration of the first well region is made higher than the impurity concentration of the second well region. The solid-state imaging device according to claim 2, wherein a potential barrier for the photo-generated charge is formed in the charge transfer path. 8. A device for controlling a potential barrier for the photo-generated charges in a region connecting the first well region and the second well region in the charge transfer path. 6. The solid-state imaging device according to any one of 2 to 5. 9. A region connecting the first well region and the second well region is the opposite conductivity type layer, and the means for controlling a potential barrier for the photo-generated charge includes the first well region. An edge of the drain region from an edge of the opposite conductivity type region formed on a surface layer of the region through an edge region of the first well region, an edge region of the opposite conductivity type layer and an edge region of the second well region; 9. The solid-state imaging device according to claim 8, wherein the transfer gate is a transfer gate provided on a path leading to a gate insulating film. 10. A one conductivity type region is formed at least in a surface layer of a path from the first well region to the second well region via the opposite conductivity type layer in the charge transfer path. The solid-state imaging device according to claim 9, wherein: 11. An opposite conductivity type region is formed in a surface layer of a path from at least the first well region to the second well region via the opposite conductivity type layer in the charge transfer path. The solid-state imaging device according to claim 9, wherein: 12. The solid-state imaging device according to claim 1, wherein the configuration of the solid-state imaging device according to claim 1 is one pixel, and a plurality of pixels are arranged on the substrate. 13. Each of the charge discharging paths of the plurality of adjacent pixels extends from each of the first well regions and is connected to the substrate at one location, and the photo-generated charges are provided in each of the charge discharging paths. The solid-state imaging device according to claim 12, further comprising a unit that controls a potential barrier with respect to the solid-state imaging device. 14. The solid-state imaging device according to claim 12, wherein the plurality of pixels are arranged in columns and rows. 15. The solid-state imaging device, further comprising: a vertical scanning signal drive scanning circuit that supplies a scanning signal to a gate electrode of the insulated gate field effect transistor for detecting an optical signal; A drain voltage drive scanning circuit that supplies a drain voltage; a signal output circuit that stores a voltage of a source region of the insulated gate field effect transistor, and further outputs an optical signal corresponding to the voltage of the source region; 14. The solid-state imaging device according to claim 13, further comprising: a horizontal scanning signal input scanning circuit for supplying a scanning signal for controlling a timing of reading the data. 16. A driving method for a solid-state imaging device, wherein the solid-state imaging device according to claim 14 reads out an optical signal based on the photo-generated charges and outputs the signal as a video signal, wherein (a) all the pixels About, lowering the potential barrier of the charge discharging path with respect to the residual charges in the light receiving region,
And lowering the potential barrier of the path from the accumulation region to the substrate with respect to the residual charge in the photo-generated charge accumulation region, so that at least the residual charge in the light-receiving region and the photo-generated charge accumulation region is reduced. (B) forming a potential barrier between the charge transfer path and the charge discharge path for the photo-generated charges in the light receiving area for all the pixels, Generating and accumulating the photo-generated charges by irradiation; (c) forming a potential barrier in the charge discharge path for the photo-generated charges in the light receiving region and lowering a potential barrier in the charge transfer path; Transferring the photo-generated charges to the storage region through the charge transfer path and accumulating the photo-generated charges; (d) arranging the photo-generated charges in the row selected for reading the optical signal corresponding to the photo-generated charges For all of the elements, a potential barrier is formed in the charge transfer path for the photo-generated charges in the light-receiving region, and the potential barrier of the charge discharge path is lowered, so that a threshold corresponding to the amount of accumulated photo-generated charges is obtained. A voltage change is read out, and the photo-generated charges generated in the light receiving region are discharged from the light receiving region to the substrate through the charge discharging path, while all of the pixels in the other rows than the selected row are discharged. Forming a potential barrier on the path from the light-generated charge storage region to the substrate for the light-generated charge in the storage region and storing the light-generated charge in the storage region; A potential barrier is formed in the charge transfer path for the generated photo-generated charges, and the potential barrier of the charge discharging path is lowered to reduce the generated photo-generated charges in the light receiving region to the charges. And (e) repeating the operation of (d) to sequentially read out the optical signals taken in by the pixels for all the rows. . 17. Before the operation of (e) and after the operation of reading out the change in the threshold voltage corresponding to the accumulation amount of the photo-generated electric charges in (d), for all the pixels arranged in the row (D1) discharging the photo-generated charges accumulated in the photo-generated charge storage region; and (d2) changing the threshold voltage when the photo-generated charges are discharged from the photo-generated charge storage region. (D3) Next, a signal representing a difference between a change in the threshold voltage corresponding to the amount of accumulation of the photo-generated charges and a change in the threshold voltage in a state where the photo-generated charges are discharged from the accumulation region of the photo-generated charges. 17. The method for driving a solid-state imaging device according to claim 16, wherein