JP2007142218A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device in which picked-up images are not distorted even when moving images are picked up. <P>SOLUTION: The solid-state imaging device is provided with a global shutter function of transferring charges stored by simultaneously exposing the photoelectric conversion region 49 of all pixels with light from an object to a p-type region 47 near the source of a transistor for signal output having an annular gate electrode 45 simultaneously for all the pixels, under the control of a transfer gate electrode 51, and then successively outputting imaging signals from the transistor for the signal output of each pixel. The p-type region 47 near the source and the photoelectric conversion region 49 are formed by ion implantation using boron as acceptor impurities. Since the boron which does not easily cause defects compared to BF<SB>2</SB>is used for an ion implantation kind, crystal defects are not easily generated and low noise constitution is attained. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device using a transistor having a ring-shaped gate electrode as a signal output transistor in a pixel.

  As a typical solid-state image sensor used in an imaging apparatus, there is a CCD (Charge Coupled Device) type image sensor. However, due to the problem of power consumption, it has become difficult to meet the recent demand for rapid increase in the number of pixels and high-speed readout. On the other hand, CMOS (Complementary Metal-Oxide Semiconductor) type image pickup devices (hereinafter also referred to as CMOS sensors) can be driven at a low voltage, and can easily meet the demands for increasing the number of pixels and reading at high speed. . In addition, a CMOS process can be used in the manufacturing process, and peripheral circuits such as a drive circuit and a processing circuit can be mixedly mounted in the same chip, which is advantageous for downsizing. For this reason, CMOS type image sensors are attracting attention as high-performance image sensors that replace CCDs for digital cameras and video cameras.

  The CMOS sensor will be described in more detail. This is a conventionally known rolling shutter type CMOS sensor (see, for example, Patent Document 1). FIG. 8 shows an equivalent circuit diagram of an example of the conventional CMOS sensor. In the CMOS sensor shown in the figure, for simplicity, the unit pixel 1 has a 2 × 2 pixel arrangement in which two horizontal pixels and two vertical pixels are arranged. The unit pixel 1 includes a photodiode (PD) 2 for photoelectrically converting a subject image, a signal charge amplification MOS field effect transistor (hereinafter referred to as MOSFET) 3, a charge transfer MOSFET 4, a reset MOSFET 5, and a selection. The power supply line 6 is connected to the drains of the MOSFETs 3 and 5, and the source of the amplification MOSFET 3 is connected to the drain of the selection MOSFET 7.

  The gate electrode of the amplification MOSFET 3 is in a floating diffusion (FD), and the charge of the photodiode 2 is transferred to the gate electrode (FD) of the amplification MOSFET 3 through the drain-source of the charge transfer MOSFET 4. The potential of the gate electrode (FD) of the amplification MOSFET 3 is reset by the reset MOSFET 5.

  When the selection MOSFET 7 is turned on, the source of the amplification MOSFET 3 is conducted to the pixel output line 8 through the drain and source of the selection MOSFET 7. The pixel output line 8 is connected to the drain of the constant current supply MOSFET 9. The constant current supply MOSFET 9 acts as a load of the source follower circuit of the amplification MOSFET 3. The constant current supply MOSFET 9 is controlled by the gate potential of the gate potential supply line 13.

  The reset control line 10, the charge transfer control line 11, and the pixel selection control line 12 are connected to the gate electrodes of the reset MOSFET 5, the charge transfer MOSFET 4, and the selection MOSFET 7, respectively. It is supplied from the pulse supply terminals 15, 14, 16 through the drains and sources of the MOSFETs 19, 20, 21.

  The vertical shift register 17 is a circuit for selecting a 2 × 2 pixel row for row sequential scanning, and the vertical shift register output lines 18-1 and 18-2 are connected to the gate electrodes of the MOSFETs 19, 20, and 21 in each row. It is connected and determines which row of pixels is controlled by the pulse supplied to the terminals of the pulse supply terminals 15, 14, 16.

  The read block 22 is connected to a capacitor 23 for holding a reset signal output, a capacitor 24 for holding an optical signal output, switching MOSFETs 25 and 26 for selecting which one to hold, and horizontal output lines 27 and 28. Switch MOSFETs 29 and 30. The switching MOSFETs 25 and 26 are switching-controlled by pulses supplied from the terminals 37 and 38 to the gate electrodes.

  The horizontal shift register 34 is a horizontal shift register output line 35-connected to the gates of the MOSFETs 29 and 30 for switching which column of the 2 × 2 pixels is to be output to the horizontal output lines 27 and 28. 1 and the output potential to 35-2. In addition, a potential for resetting the horizontal output lines 27 and 28 is supplied from the terminal 33, and the reset timing is performed by switching the switching MOSFETs 31 and 32 with a pulse supplied from the terminal 36. The horizontal output lines 27 and 28 are connected to the input terminal of the differential amplifier 39. The differential amplifier 39 takes the difference between the reset signal output and the optical signal output, and outputs the difference signal from the amplifier output terminal 40 to the outside of the sensor.

  Next, the operation of the conventional CMOS sensor shown in FIG. 8 will be described with reference to the timing chart of FIG. Note that all the MOSFETs in FIG. 8 are N-type, and therefore the MOSFETs are turned on when the gate potential is high (High) and turned off when the gate potential is Low.

  First, as shown in FIG. 9D, the potential of the vertical shift register output line 18-1 becomes High at time t1, thereby selecting the pixel 1 in the first row. Subsequently, as shown in FIG. 9C, the input pulse of the pulse supply terminal 16 becomes High at time t2, and the selection MOSFET 7 of the pixel 1 in the first row is turned on. The source of the amplification MOSFET 3 of the pixel 1 is connected to the constant current supply MOSFET 9 through the drain / source of the selection MOSFET 7 and the pixel output line 8 to form a source follower circuit.

  In this state, first, a high-level pulse is supplied to the pulse supply terminal 15 as shown in FIG. 9B, and the gate electrode of the amplification MOSFET 3 passes through the drain and source of the reset MOSFET 5 of the pixel 1 in the first row. (FD) is reset. Thereafter, at time t3, the input pulse of the pulse supply terminal 37 becomes High as shown in FIG. 9I, the switching MOSFET 25 is turned on, and the capacitor 23 outputs from the source follower circuit of the pixel 1 in the first row. The reset signal output is held.

  Next, when a high pulse is applied to the pulse supply terminal 14 at time t4 as shown in FIG. 9A, the charge transfer MOSFET 4 in the pixel 1 in the first row is turned on, and the pixel 1 in the first row. The charge accumulated in the photodiode 2 is transferred to the gate electrode (FD) of the amplification MOSFET 3 through the drain / source of the charge transfer MOSFET 4. At time t5, when a high pulse is applied to the pulse supply terminal 38 as shown in FIG. 9 (J), the optical signal output output from the source follower circuit of the pixel 1 in the first row is held in the capacitor 24. Is done. Subsequently, as shown in FIG. 9C, since the input pulse of the pulse supply terminal 16 becomes Low at time t6, the selection MOSFET 7 in the pixel 1 in the first row is turned off, and the pixel in the first row The output from 1 disappears.

  During this time, the input signal of the terminal 36 is High as shown in FIG. 9H, and the horizontal output lines 27 and 28 are in a reset state. However, at time t6, the input signal at the terminal 36 becomes Low as shown in FIG. 9 (H), and when the High pulse shown in FIG. 9 (F) is applied to the horizontal shift register output line 35-1 in this state. Since the switching MOSFETs 29 and 30 in the first column are turned on, the signals of the capacitors 23 and 24 in the first column are output to the horizontal output lines 27 and 28 through the switching MOSFETs 29 and 30 in the first column, respectively. And supplied to the differential amplifier 39. The differential amplifier 39 calculates the difference between each signal of the capacitors 23 and 24 in the first column, that is, the reset signal output and the optical signal output, and removes the optical signal from which the noise caused by the threshold variation of the amplification MOSFET 3 is removed. Output from the output terminal 40.

  Next, when a high pulse is applied to the terminal 36 at time t7 shown in FIG. 9 (H), the horizontal output lines 27 and 28 are reset again, and then to the horizontal shift register output line 35-2, as shown in FIG. 9 (G). As shown, the high pulse is applied at time t8, and the switching MOSFETs 29 and 30 in the second column are turned on, so that the signals of the capacitors 23 and 24 in the second column are switched to the switching MOSFETs 29 and 30 in the second column. Are output to the horizontal output lines 27 and 28, supplied to the differential amplifier 39, and the second column signal is output from the differential amplifier 39 to the output terminal 40 in the same manner as the first column.

  After that, at time t9 shown in FIG. 9D, the potential of the vertical shift register output line 18-1 becomes Low, and the processing for the first row is completed. Next, at time t10, as shown in FIG. 9E, the potential of the vertical shift register output line 18-2 becomes High, and processing similar to that in the first row is performed, and reading of all pixels is completed.

  Therefore, in the case of this CMOS sensor, the timing of photoelectric conversion by the photodiodes 2 in the first and second rows is different. Such an imaging method is called a rolling shutter or a focal plane.

JP 2003-17677 A

  Such a conventional rolling shutter type CMOS sensor reads out one row at a time, and the timing of reading out is different between the upper part and the lower part of the pixel area. Therefore, when a moving object is imaged, the captured image is distorted.

  As a method of avoiding this problem, a method of providing a mechanical shutter in front of the incident light side of the rolling shutter type CMOS sensor is conceivable. In this method, the exposure process and the signal reading process are performed by providing an exposure period of one frame period for all lines corresponding to the mechanical shutter open period, and sequentially reading one line at a time during the mechanical shutter close period. In particular, when the subject is a still image, the above-described distortion of the captured image can be avoided.

  However, in this case, the mechanical shutter increases the size of the apparatus by providing a mechanical shutter, and it is necessary to perform opening / closing control of the mechanical shutter for each frame. There are problems such as increased complexity and increased power for driving the shutter, making it difficult to apply to moving image shooting.

  In the above CMOS sensor, when a buried photodiode is formed by forming a diffusion region having a conductivity type opposite to the well in the well formed on the substrate surface, impurities having a conductivity type opposite to that of the well are formed. When the diffusion region is formed by applying the ion implantation method used, if a shallow diffusion region is formed using heavy impurities to increase the photoelectric conversion efficiency, crystal defects are likely to occur. Noise due to dark current is greatly generated.

  The present invention has been made in view of the above points, and it is an object of the present invention to provide a solid-state imaging device in which a captured image is not distorted even when a moving image is captured.

  Another object of the present invention is to provide a solid-state imaging device that realizes low noise while suppressing dark current by applying an ion implantation method using a predetermined impurity when forming a photodiode.

  To achieve the above object, the present invention provides a signal output transistor having a ring-shaped gate electrode formed on a substrate with an insulating film interposed therebetween, and a photoelectric conversion device that converts light accumulated in the substrate into electric charges and accumulates it. A plurality of pixels including a conversion region and charge transfer means for transferring the charge accumulated in the photoelectric conversion region to the signal output transistor are two-dimensionally arranged, and light from the subject is applied to the photoelectric conversion regions of all the plurality of pixels. A global exposure that simultaneously exposes the charge accumulated in the photoelectric conversion area during the exposure period to the signal output transistors all at once via the charge transfer means, and then sequentially outputs the imaging signals from the signal output transistors of each pixel. A solid-state imaging device having a shutter function, wherein the photoelectric conversion region is formed by ion implantation using boron as an acceptor impurity or arsenic as a donor impurity. And said that you are.

  In order to achieve the above object, the present invention provides a ring-shaped gate electrode formed on a substrate with an insulating film interposed therebetween, and a source provided at the position of the substrate corresponding to the central opening of the ring-shaped gate electrode. A signal output transistor comprising a region, a source region surrounding the source region, and a source vicinity region provided on the substrate so as not to reach the outer periphery of the ring-shaped gate electrode, and converting the light provided on the substrate into an electric charge A plurality of pixels including a photoelectric conversion region to be accumulated and charge transfer means for transferring charges accumulated in the photoelectric conversion region to a source vicinity region of the signal output transistor are two-dimensionally arranged, and photoelectric conversion of all the plurality of pixels is performed. The area is exposed to light from the subject at the same time, and the charges accumulated in the photoelectric conversion area during the exposure period are transferred to the signal output transistors all at once through the charge transfer means, and then each pixel A solid-state imaging device having a global shutter function that sequentially outputs imaging signals from a signal output transistor, wherein a source vicinity region is formed by ion implantation using boron as an acceptor impurity or arsenic as a donor impurity. Features.

The present invention is a solid-state imaging device having a global shutter function including a signal output transistor having a ring-shaped gate electrode in a pixel, and the photoelectric conversion region or the source vicinity region is boron or donor impurity as an acceptor impurity. Formed by ion implantation using arsenic as an acceptor, and using boron which is less likely to cause crystal defects than BF ₂ as an acceptor impurity, or lattice distortion or stress as compared with phosphorus as a donor impurity. It is formed by ion implantation using arsenic that is difficult to generate.

  According to the present invention, since it has a global shutter function, image distortion at the time of moving image shooting can be prevented, and a shot image without image distortion can be obtained without using a mechanical shutter mechanism at the time of still image shooting.

According to the present invention, the photoelectric conversion region and the source vicinity region of the signal output transistor are formed by ion implantation using boron, which is less likely to have a crystal defect than BF ₂ as an acceptor impurity, or a donor impurity As described above, since arsenic, which is less susceptible to lattice distortion and stress than phosphorus, is formed by ion implantation, dark current can be reduced, and as a result, a solid-state imaging device having a low noise configuration can be realized.

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1A is a plan view of one pixel of an embodiment of a solid-state imaging device according to the present invention, and FIG. 1B is a longitudinal sectional view taken along line XX ′ in FIG. . As shown in FIG. 1B, the substrate used in the present embodiment has a p ⁻ type epitaxial layer 42 grown on a p ⁺ substrate 41. An n-well 43 is provided in the p ⁻ -type epitaxial layer 42, and a ring-shaped gate electrode 45 is formed on the n-well 43 as a first gate electrode with a gate oxide film 44 interposed therebetween.

As shown in FIG. 1B, an n ⁺ -type source region 46 is provided on the surface of the n-well 43 in the central opening of the ring-shaped gate electrode 45 so as to surround the source region 46 adjacent to the source region 46. A p-type source vicinity region 47 is formed. The source vicinity p-type region 47 does not reach the outer peripheral portion of the ring-shaped gate electrode 45. There is an n ⁺ -type drain region 48 on the surface of the n-well 43 that is separated from the source region 46 and the p-type region 47 near the source.

Further, as shown in FIG. 1B, a p ⁻ type region 49 is formed in the n-well 43 outside the outer peripheral portion of the ring-shaped gate electrode 45, and the buried photodiode shown in FIG. 50 is formed. A transfer gate electrode 51 is formed on the substrate between the p ⁻ -type region 49 constituting the embedded photodiode 50 and the ring-shaped gate electrode 45 as a second gate electrode with the gate insulating film 44 interposed therebetween.

  Metal wirings 52, 53, 54, and 55 are connected to the drain region 48, the ring-shaped gate electrode 45, the source region 46, and the transfer gate electrode 51, respectively. Further, as shown in FIG. 1B, the upper part of each component is covered with an insulating layer, and a light shielding film 56 is further formed thereon. An opening 57 is formed at a position corresponding to the upper portion of the light shielding film 56 in the vertical direction of the photodiode 50. The light shielding film 56 is formed of a metal or an organic film. The light reaches the embedded photodiode 50 through the opening 57 and is photoelectrically converted.

  Next, the pixel structure of the CMOS sensor and the entire structure of the image sensor will be described with reference to FIG. In the figure, first, pixels are arranged in a pixel spread area 61 in m rows and n columns. In FIG. 2, one pixel 62 of s rows and t columns among these m rows and n columns is represented by an equivalent circuit. The pixel 62 includes a ring-shaped gate MOSFET 63, a photodiode 64, and a transfer gate MOSFET 65. The drain of the ring-shaped gate MOSFET 63 is the n-side terminal of the photodiode 64 and the drain electrode wiring 66 (corresponding to 52 in FIG. 1). , The source of the transfer gate MOSFET 65 is connected to the p-side terminal of the photodiode 64, and the drain is connected to the back gate of the ring-shaped gate MOSFET 63.

In FIG. 1B, the ring-shaped gate MOSFET 63 has a p-type region 47 near the source directly below the ring-shaped gate electrode 45 as a gate region, and an n ⁺ -type source region 46 and an n ⁺ -type drain region 48. An n-channel MOSFET. In FIG. 1B, the transfer gate MOSFET 65 has an n well 43 just below the transfer gate electrode 51 as a gate region, a p ⁻ type region 49 embedded with a photodiode 50 as a source region, and a p-type region 47 near the source. A p-channel MOSFET serving as a drain region.

  In FIG. 2, in order to read a signal for one frame from each pixel of m rows and n columns, there is a circuit 67 for generating a frame start signal for giving a signal to start reading. The frame start signal may be given from outside the image sensor. This frame start signal is supplied to the vertical shift register 68. The vertical shift register 68 outputs a signal indicating which row of pixels is read out from each pixel of m rows and n columns.

  The pixels in each row are connected to a control circuit that controls the potential of a ring gate electrode such as the ring gate MOSFET 63, a transfer gate electrode such as the transfer gate MOSFET 65, and a drain electrode such as the ring gate MOSFET 63. The output signal of the vertical register 68 is supplied. For example, the ring-shaped gate electrode of each pixel in the s-th row is connected to the ring-shaped gate potential control circuit 70 via the ring-shaped gate electrode wiring 69 (corresponding to 53 in FIG. 1), and the transfer gate electrode of each pixel is Are connected to the transfer gate potential control circuit 72 via the transfer gate electrode wiring 71 (corresponding to 55 in FIG. 1), and the drain electrode of each pixel is drained via the drain electrode wiring 66 (corresponding to 52 in FIG. 1). It is connected to the potential control circuit 73. Each control circuit 70, 72, 73 is supplied with an output signal from the vertical shift register 68.

  Since the ring-shaped gate electrode is controlled for each row, wiring is performed in the horizontal direction. However, since the transfer gate electrode is controlled simultaneously for all pixels, the wiring direction is not limited and the vertical direction may be used. Here, it is expressed as wiring in the horizontal direction. The drain potential control circuit 73 controls all the pixels at the same time, but may be controlled for each row. Therefore, the drain potential control circuit 73 is represented by being connected to both the frame start signal and the vertical register 68.

  The source electrode of the ring-shaped gate MOSFET 63 of the pixel 62 is branched into two via a source electrode wiring 74 (corresponding to 54 in FIG. 1), and one of the source electrodes is supplied to a source potential control circuit 75 that controls the source electrode potential via a switch SW1. The other is connected to the signal readout circuit 76 via the switch SW2. When reading the signal, the switch SW1 is turned off and the switch SW2 is turned on. When the source potential is controlled, the switch SW1 is turned on and the switch SW2 is turned off. Since the signal is output in the vertical direction, the wiring direction of the source electrode is set to be vertical.

  The signal readout circuit 76 is configured as follows. The output of the pixel 62 is performed from the source of the ring-shaped gate MOSFET 63, and a load, for example, a current source 77 is connected to the output line 74. Therefore, it is a source follower circuit. One end of each of the capacitor C1 and the capacitor C2 is connected to the current source 77 via the switch sc1 and the switch sc2. One end of each of the capacitors C1 and C2 whose other ends are grounded is connected to the inverting input terminal and the non-inverting input terminal of the differential amplifier 78, and the potential difference between the capacitors C1 and C2 is output from the differential amplifier 78. It is like that.

  Such a signal readout circuit 76 is called a CDS circuit (correlated double sampling circuit), and various circuits other than the method described here have been proposed, and the circuit is not limited to this circuit. The signal output from the signal readout circuit 76 is output via the output switch swt. The output switches swt in the same column are subjected to switching control by a signal output from the horizontal shift register 79.

Next, a method for driving the CMOS sensor shown in FIG. 2 will be described with reference to the timing chart of FIG. First, in the period shown in FIG. 3A, light is incident on the embedded photodiode (50 in FIG. 1A, 64 in FIG. 2, etc.), and an electron / hole pair is generated due to the photoelectric conversion effect. Holes are accumulated in the buried p ⁻ -type region 49 of the diode. At this time, the potential of the transfer gate electrode 51 is the same as the drain potential Vdd, and the transfer gate MOSFET 65 is off. These accumulations are performed at the same time as the previous frame read operation is being performed.

  In the subsequent period shown in FIG. 3 (2), when the reading of the previous frame is completed, a new frame start signal is transmitted as shown in FIG. First, all the pixels are performed simultaneously from the photodiode (50 in FIG. 1A, 64 in FIG. 2 etc.) to the p-type region (47 in FIG. 1) near the source of the ring-shaped gate electrode (45 in FIG. 1). It is to transfer the hole. Therefore, as shown in FIG. 3B, the transfer gate control signal output from the transfer gate potential control circuit 72 falls from Vdd to Low2, the potential of the transfer gate electrode (51 in FIG. 1) becomes Low2, and the transfer gate MOSFET 65 Turns on.

  At this time, the potential of the ring-shaped gate electrode wiring 69 controlled by the ring-shaped gate potential control circuit 70 changes from Low to Low1 as shown in FIG. 3C, but Low2 is larger than Low1. Low1 may be the same as Low. Most simply, Low1 = Low = 0 (V) is set.

  On the other hand, the source potential of all the pixels including the source potential supplied from the source potential control circuit 75 to the source of the ring-shaped gate MOSFET 63 from the source electrode wiring 74 through the switch SW1 is as shown in FIG. The potential is set to S1. S1> Low1, which keeps the ring-shaped gate MOSFET 63 off and prevents current from flowing. As a result, charges (holes) accumulated in the photodiodes of all the pixels are transferred all at once under the ring-shaped gate electrodes of the corresponding pixels.

  In the region below the ring-shaped gate electrode 45 shown in FIG. 1B, the p-type region 47 in the vicinity of the source has the lowest potential, so the holes accumulated in the photodiode are the source that is the back gate of the ring-shaped gate MOSFET 63. It reaches the nearby p-type region 47 and accumulates there. As a result of the accumulation of holes, the potential of the p-type region 47 near the source rises.

Subsequently, in the period shown in FIG. 3 (3), the transfer gate electrode becomes Vdd again and the transfer gate MOSFET 65 is turned off as shown in FIG. 3 (B). As a result, in the photodiode (50 in FIG. 1A, 64 in FIG. 2, etc.), electron-hole pairs are generated again due to the photoelectric conversion effect, and holes start to accumulate in the buried p ⁻ -type region 49 of the photodiode. This accumulation operation is continued until the next charge transfer.

  On the other hand, since the reading operation is sequentially performed in units of rows, the potential of the ring-shaped gate electrode is low as shown in FIG. 3C in the period (3) in which the first to (s−1) th rows are read. In this state, a standby state is entered with holes accumulated in the p-type region 47 near the source. The source potential can take various values depending on the value of the signal from the pixel while the signal is read from another row. The ring-shaped gate electrode potential can take various values for each row, but is set to Low in the s-th row, and the ring-shaped gate MOSFET 63 is in an off state.

  In the subsequent period shown in FIGS. 3 (4) to (6), pixel signal readout is performed. This signal readout operation will be described representatively for the pixel 62 in the s-th row and the t-th column. First, in a state where holes are accumulated in the p-type region 47 near the source, the vertical shift register 68 shown in FIG. In the period (4) in which the output signal is at a low level as shown in FIG. 5H, the ring-shaped gate electrode 45 is controlled by the control signal output from the ring-shaped gate potential control circuit 70 to the ring-shaped gate electrode wiring 69. Is increased from Low to Vg1, as shown in FIG.

Here, the potential Vg1 is between the potentials Low, Low1, and Vdd described above.
Low ≦ Low1 ≦ Vg1 ≦ Vdd (where Low <Vdd)
Is an electric potential that holds the inequality. In the period (4), the switch SW1 is turned off as shown in FIG. 3I, the switch SW2 is turned on as shown in FIG. 3J, and the switch sc1 is turned on as shown in FIG. The switch sc2 is turned off as shown in FIG. As a result, the source follower circuit connected to the source of the ring-shaped gate MOSFET 63 works, and the source potential of the ring-shaped gate MOSFET 63 is S2 (= Vg1-Vth1) in the period (4) as shown in FIG. Become. Here, Vth1 is a threshold voltage of the ring-shaped gate MOSFET 63 in a state in which there is a hole in the back gate (p-type region 47 near the source). The source potential S2 is stored in the capacitor C1 through the switch sc1 that is turned on.

  In the subsequent period shown in FIG. 3 (5), the potential of the ring-shaped gate electrode 45 is set as shown in FIG. 3 (K) by the control signal output from the ring-shaped gate potential control circuit 70 to the ring-shaped gate electrode wiring 69. At the same time as raising to High1, the switch SW1 is turned on and the switch SW2 is turned off as shown in FIGS. 1I and 1J, and the source potential output from the source potential control circuit 75 is shown in FIG. Raise to Highs as shown. Here, High1 and Highs> Low1.

  The values of the potentials High1 and Highs may be the same or different, but High1 and Highs ≦ Vdd are desirable for simplicity of design. In a simple setting, High1 = Highs = Vdd. Further, it is desirable to set the potential so that the ring-shaped gate MOSFET 63 is turned on and no current flows. As a result, the potential of the p-type region 47 near the source rises, and holes are discharged to the epitaxial layer 42 beyond the barrier of the n-well 43 (reset).

  In the subsequent period shown in FIG. 3 (6), the same signal readout state as in the period (4) is set again. However, unlike the period (4), as shown in FIGS. 3M and 3N, the switch sc1 is turned off and the switch sc2 is turned on. The ring-shaped gate electrode has the same Vg1 as that in the period (4) as shown in FIG. However, in this period (6), holes are discharged to the substrate in the immediately preceding period (5), and no holes are present in the p-type region 47 near the source, so the source potential of the ring-shaped gate MOSFET 63 is as shown in FIG. L), the period (6) is S0 (= Vg1-Vth0). Here, Vth0 is the threshold voltage of the ring-shaped gate MOSFET 63 in a state where there is no hole in the back gate (p-type region 47 near the source).

  The source potential S0 is stored in the capacitor C2 through the switch sc2 that is turned on. The differential amplifier 78 outputs the potential difference between the capacitors C1 and C2. That is, the differential amplifier 78 outputs (Vth0−Vth1). This output value (Vth0-Vth1) is a change in threshold value due to hole charge. Thereafter, among the pulses shown in FIG. 3F output from the horizontal shift register 79, the output switch swt shown in FIG. 2 is turned on based on the output pulse in the t-th column shown in FIG. During the ON period, as schematically shown by hatching in FIG. 3P, the threshold value change due to the Hall charge from the differential amplifier 78 is output to the outside of the sensor as the output signal Vout of the pixel 62.

  Subsequently, in the period indicated by (7) in FIG. 3, the potential of the ring-shaped gate electrode 45 is set to low again as shown in FIG. 3 (B), and all of the p-type region 47 near the source has no holes. It waits until the signal processing of the next row is completed (until the readout of the pixels of the s + 1 row to the nth row is completed). During these readout periods, the photodiode 64 is accumulating holes due to the photoelectric conversion effect. Thereafter, the process returns to the period (1) and repeats from the hole transfer. As a result, the output signal shown in FIG. 3G is read from each pixel.

In the solid-state imaging device having the configuration shown in FIGS. 1A and 1B, the ring-shaped gate MOSFET 63 having the ring-shaped gate electrode 45 is an amplification MOSFET. As shown in FIG. It is a kind of CMOS sensor in the sense that it has an amplifying MOSFET. In this CMOS sensor, the charges (holes) accumulated in the buried p ⁻ type region 49 are transferred all at once to the p-type region 47 near the source under the ring-shaped gate electrode 45 of the corresponding pixel. By doing so, a global shutter is realized.

  Note that the potential supply of the source electrode wiring 74 at the time of resetting in the period (5) of FIG. That is, in the period (5), both the switches SW1 and SW2 are turned off, and the source electrode wiring 74 is floated. Here, when the potential of the ring-shaped gate electrode wiring 69 is High1, the ring-shaped gate MOSFET 63 is turned on, current is supplied from the drain to the source electrode, and the source electrode potential rises. As a result, the potential of the p-type region 47 in the vicinity of the source is raised, and holes are discharged to the p-type epitaxial layer 42 beyond the barrier of the n-well 43 (reset). The source electrode potential when the holes are completely discharged becomes High1-Vth0. This method can reduce the number of transistors that supply Highs in the source potential control circuit 75, and as a result, the chip area can be reduced.

  As described above, according to the solid-state imaging device of the present embodiment having the structure shown in FIG. 1, the charges generated by the light incident on the photodiodes 50 of all the pixels and simultaneously accumulated in all the pixels are transferred to the transfer gates of all the pixels. By turning on the MOSFETs 65 all at once, the MOSFET 65 is transferred to the p-type region 47 near the source below the central opening of the ring-shaped gate MOSFET 63 (the back gate of the ring-shaped gate MOSFET 63). At this time, since charges can be transferred simultaneously in all pixels, a collective shutter (global shutter) is possible.

  Then, the charge transferred to the p-type region 47 in the vicinity of the source of the ring-shaped gate MOSFET shifts the threshold voltage of the ring-shaped gate MOSFET 63 according to the amount of charge. At this time, the ring-shaped gate of the ring-shaped gate MOSFET 63 An optical output signal can be obtained as a change in threshold voltage corresponding to the amount of charge by setting the electrode to an appropriate potential, passing a current through the source / drain, and connecting a load to the source. Further, the charge accumulated in the p-type region 47 near the source of the ring-shaped gate MOSFET 63 is discharged to the substrate 42 by overcoming the potential of the n-well region 43 immediately below by raising the source potential. Can do. At this time, since all the charges accumulated in the p-type region 47 near the source of the ring-shaped gate MOSFET 63 are discharged to the substrate 42, the occurrence of reset noise can be suppressed.

  In addition, since this embodiment has a global shutter function, a captured image without image distortion can be obtained even when a moving subject is imaged. That is, the exposure to the solid-state imaging device of this embodiment is performed in the same one frame period without shifting the timing for each line. This corresponds to the period (1) in FIG.

  After exposure for a certain period, the transfer gates (transfer gate MOSFET 65, etc. in FIG. 2) simultaneously charge all the pixels in a predetermined region of each pixel (back gate of the ring-shaped gate MOSFET 63 in FIG. 2, p-type near the source in FIG. Transferred to area 47). This corresponds to the period (2) in FIG. Thereafter, signals from each pixel are sequentially read out by the readout circuit within the readout period. This corresponds to the periods (3) to (7) in FIG.

  As a result, even when a moving subject is imaged, the captured image is an image exposed at the same time without using a mechanical shutter in the present embodiment, so image distortion different from that of the subject image does not occur. Therefore, according to the present embodiment, even when a fast-moving subject is captured, an accurate image can be obtained without distortion or deformation.

FIG. 4 is a longitudinal sectional view for one pixel of another embodiment of the solid-state imaging device according to the present invention. In the figure, the same components as those in FIG. A top view of this embodiment is the same as FIG. This embodiment has a global shutter function as in the embodiment shown in FIG. 1, but the difference in structure between this embodiment and the embodiment shown in FIG. In this embodiment, a ring-shaped p ⁺ region 81 is formed inside the source vicinity p-type region 47 as shown in FIG. The p ⁺ region 81 is provided to concentrate the charge transferred to the p-type region 47 in the vicinity of the source in the p ⁺ region 81 to increase the effect of threshold change due to the charge and improve the sensitivity.

Further, the p ⁺ region 81 in the source vicinity p-type region 47 is provided not inside the ring-shaped gate electrode 45 but inside the central opening of the ring-shaped gate electrode 45. In this way, as will be described later, the p ⁺ region 81 can be formed by self-alignment using the ring-shaped gate electrode 45, and the area variation is significantly smaller than when the p ⁺ region 81 is formed using a mask. Variations in characteristics can be reduced.

  The above is the description of the embodiment relating to the structure of the solid-state imaging device according to the present invention. However, the present invention is characterized by the manufacturing method of the photodiode 50 and the source vicinity p-type region 47 of the solid-state imaging device having the above-described structure. . Then, next, the manufacturing method of the solid-state image sensor shown in FIG. 4 is demonstrated with FIG. 5 thru | or FIG. First, a manufacturing method of the source vicinity p-type region 47 and its peripheral structure will be described with reference to FIGS. Here, for simplicity, it is assumed that the n-well 43 has already been formed. In this state, as shown in FIG. 5A, the portion 84 for forming the p-type region is removed by the photo process of the resist 83, and ion implantation of acceptor impurities is performed through the oxide film 82 into the n-well 43, and the source p A mold area 47 is created.

Next, after removing the oxide film 82 on the substrate surface, a gate oxide film 85 (corresponding to 44 in FIG. 4) is newly formed as shown in FIG. A ring-shaped gate electrode 86 (corresponding to 45 in FIG. 4) is formed. Subsequently, as shown in FIG. 5C, using the ring-shaped gate electrode 86 as a mask, ion implantation of an acceptor impurity indicated by 87 is performed at a location shallower than the p-type region 47 in the vicinity of the source, thereby forming a p ⁺ region 88. Form.

Subsequently, using the ring-shaped gate electrode 86 as a mask, as shown in FIG. 6A, an n ⁺ layer 90 is formed on the substrate surface by ion implantation of a donor impurity 89, which is shallower than the p ⁺ region 88. . Next, as shown in FIG. 6B, an LDD side spacer 91 is formed on the inner wall of the ring-shaped gate electrode 86 by a known method.

Then, as shown in FIG. 6C, a high concentration donor implantation 92 is performed through the LDD side spacer 91 to form an n ⁺ -type source region 93 (corresponding to 46 in FIG. 4). As a result, a ring-shaped p ⁺ region 94 (corresponding to 81 in FIG. 4) is formed in the p-type region 47 near the source. As described above, in this embodiment, the ring-shaped p ⁺ region 94 (81) can be formed inside the p-type region 47 near the source by self-alignment of the gate oxide film 85 and the LDD side spacer 91. High-precision manufacturing is possible.

Now, boron (B: boron) and boron fluoride (BF ₂ ) are ion-implanted species of acceptor impurities (p-type impurities) used in the source vicinity p-type region 47 and the p ⁺ region 94 (81) in the inside thereof. Conceivable. When these are compared, since BF ₂ is heavier, there is an advantage that BF ₂ can be implanted shallower as an acceptor impurity. In particular, if the p ⁺ region 94 (81) can be made shallow, the conversion efficiency for converting the accumulated holes into an electric signal is improved.

However, on the other hand, there is a problem that BF ₂ is more likely to have crystal defects than boron. It cannot be said that quantitative examination has been sufficiently conducted on the ease of occurrence of this crystal defect. However, for example, in Japanese Patent Laid-Open No. 10-242071, simulation of impurity diffusion is compared with actual measurement by SIMS (Secondary Ionization Mass Spectrometer) analysis, and it is estimated that BF ₂ is approximately three times as likely to be defective as boron. ing. Since the p-type region 47 in the vicinity of the source accumulates holes for a maximum of one frame, it is preferable to prevent crystal defects as much as possible.

Therefore, in this embodiment, boron is used as the ion implantation species of the acceptor impurity (p-type impurity) used for the p-type region 47 near the source and the p ⁺ region 94 (81) inside the source, without using BF _2. Is injected at low energy. For example, the p ⁺ type region 94 (81) is ion-implanted with a low energy of 5 to 30 KeV. Regarding the ion implantation of the acceptor impurity in the entire p-type region 47 in the vicinity of the source, the acceleration energy may be boron, for example, 50 to 150 KeV, and a commonly used range is used.

On the other hand, arsenic (As) is better than phosphorus (P) as a donor impurity (n-type impurity) implanted into a region shallower than the p ⁺ region 94 (81). This is because when phosphorus is used, lattice distortion and stress are generated, and defects are likely to occur (see, for example, JP-A-2004-47985). Therefore, in order to form the n ⁺ region 93 (46) in direct contact with the p ⁺ region 94 (81) where holes are concentrated by applying the ion implantation method, it is better to use arsenic as a donor impurity.

On the other hand, in the n-well 43 outside the ring-shaped gate electrode 45, a p ⁻ -type region 49 constituting the embedded photodiode 50 is formed in a process different from the formation of the p ⁺ region 94 (81). The A method for manufacturing this photodiode will be described with reference to FIG.

  In FIG. 7, in the state where the ring-shaped gate electrode 45 and the transfer gate electrode 51 are not yet present, the sacrificial oxide film 96 is coated on the entire surface of the substrate with a film thickness of, for example, 10 nm instead of the gate oxide film. The region I is exposed to form an opening in the region I, and donor impurities are ion-implanted into the region I implantation range through the opening to form the region I of the n-well 43. Since the region I of the n-well 43 is deep from the substrate surface, phosphorus (P) is used as a donor impurity, and high-energy ion implantation of about 500 keV to 2 MeV is performed.

  Subsequently, the region II in FIG. 7 is exposed to form an opening in the region II of the resist, and donor impurities are ion-implanted into the region II implantation region through the opening to form the region II of the n-well 43. To do. Since the portion of the region II of the n-well 43 is widely distributed in the depth direction, ion implantation is not performed once but is performed a plurality of times while changing energy. As in the region I, ion implantation is performed at high energy in the deep part of the region II.

  Subsequently, the region III in FIG. 7 is exposed to form an opening in the region of the resist region III, and donor impurities are ion-implanted into the region III implantation region through the opening to thereby form the region III of the n-well 43. After the formation, the region IV in FIG. 7 is exposed to form an opening in the region IV of the resist, and donor impurities are ion-implanted into the region IV implantation region through the opening to form a portion of the region IV in the n-well 43. Form.

Thereafter, the entire surface of the resist is coated, and the buried p-implanted region range in FIG. 7 of the resist is exposed to form an opening, and acceptor impurities are implanted at a low concentration through the opening to form a buried p ⁻ region 49. create. As the implantation conditions, for example, boron is performed at an acceleration energy of 20 to 100 keV and in a dose range of 1E12 cm ^{−2 to} 2E13 cm ⁻² . That is, in this embodiment, the p ⁻ region 49 forming the embedded photodiode 50 is formed by ion implantation using boron instead of BF ₂ as an acceptor impurity, and as a result, A low noise photodiode is formed.

Thereafter, arsenic is ion-implanted as a donor impurity in the buried p ⁻ region 49 to form an n ⁺ type drain region 48. The n ⁺ -type drain region 48 is formed by ion implantation using arsenic and has low noise.

Note that the present invention also holds true when the conductivity type of the above-described embodiment is reversed. In that case, boron is used as an acceptor impurity when forming a p-type well or drain region by ion implantation, and arsenic is ion-implanted when forming an n ⁻ -type buried region. As arsenic implantation conditions at this time, for example, acceleration energy of 50 to 200 keV and a dose amount of 1E12 cm ^{−2 to} 2E13 cm ⁻² are used. Thereby, a low noise photodiode can be formed.

It is the top view and sectional drawing explaining the structure of one pixel of the solid-state image sensor of this invention. It is the figure which showed the whole structure of one Embodiment of the solid-state image sensor of this invention with the electrical equivalent circuit. 3 is a timing chart for explaining the operation of the solid-state imaging device in FIG. 2. It is sectional drawing of other embodiment of the solid-state image sensor of this invention. FIG. 5 is an element cross-sectional view (No. 1) for explaining the method of manufacturing the p-type region near the source in FIG. 4 and the structure around it. FIG. 5D is a device cross-sectional view (part 2) illustrating the method for manufacturing the p-type region near the source in FIG. 4 and the structure around it. It is an element cross-sectional schematic diagram explaining the manufacturing method of the embedded photodiode of the solid-state image sensor of this invention. It is a figure explaining the whole structure of the conventional rolling shutter type | mold CMOS sensor with an electrical equivalent circuit. It is a timing chart explaining operation | movement of the CMOS sensor of FIG.

Explanation of symbols

43 n well 45 ring-shaped gate electrode 46, 93 n ⁺ type source region 47 near source p type region 48 n ⁺ type drain region 49 buried p ⁻ type region 50, 64 photodiode 51 transfer gate electrode 52, 66 drain electrode wiring 53 , 69 Ring-shaped gate electrode wiring 54, 74 Source electrode wiring (output line)
55, 71 Transfer gate electrode wiring 61 Pixel covering area 62 Pixel 63 Ring-shaped gate MOSFET
65 Transfer gate MOSFET
81, 94 p ⁺ region

Claims (2)

A signal output transistor having a ring-shaped gate electrode formed on a substrate with an insulating film interposed therebetween, a photoelectric conversion region for converting light stored in the substrate into electric charge and storing it, and stored in the photoelectric conversion region A plurality of pixels including a charge transfer means for transferring the charge to the signal output transistor, the light from the subject is simultaneously exposed to the photoelectric conversion regions of all the pixels, and an exposure period is set. A global shutter function for sequentially outputting the imaging signal from the signal output transistor of each pixel after transferring the charge accumulated in the photoelectric conversion region to the signal output transistor all at once via the charge transfer means A solid-state imaging device comprising:
The photoelectric conversion region is formed by ion implantation using boron as an acceptor impurity or arsenic as a donor impurity. A ring-shaped gate electrode formed on the substrate with an insulating film interposed therebetween, a source region provided at a position of the substrate corresponding to a central opening of the ring-shaped gate electrode, surrounding the source region, and A signal output transistor including a source vicinity region provided on the substrate so as not to reach an outer periphery of the ring-shaped gate electrode, a photoelectric conversion region configured to convert light stored in the substrate into an electric charge, and A plurality of pixels including a charge transfer means for transferring the charge accumulated in the photoelectric conversion region to the source vicinity region of the signal output transistor is two-dimensionally arranged, and a subject is placed in the photoelectric conversion region of all the plurality of pixels. The light accumulated in the photoelectric conversion region during the exposure period is simultaneously applied to all the pixels to the signal output transistor via the charge transfer means. After feeding, a solid-state imaging device having a global shutter function which sequentially outputs an imaging signal from the signal output transistor of each pixel,
The solid-state imaging device, wherein the source vicinity region is formed by ion implantation using boron as an acceptor impurity or arsenic as a donor impurity.

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