JP2007019681A - Method of driving solid-state imaging element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a signal deteriorates since a dark current generated owing to a crystal defect or the gate oxide film interfacial potential of a solid-state imaging element is not discharged and accumulated in a well before and superposed on the signal as electric charges of a photodiode are transferred to the well thereafter. <P>SOLUTION: Disclosed is the method of driving the solid-state imaging element where a plurality of pixels are regularly arrayed each of which comprises: a ring-shaped gate electrode; a source diffusion area formed at a center opening of the ring-shaped gate electrode; a source nearby area formed surrounding the source diffusion area and not reaching the outer periphery of the ring-shaped gate electrode; a photoelectric conversion area in which light is converted into electric charges and accumulated; and a transfer means of transferring the electric charges accumulated in the photoelectric conversion area to the vicinity of the source. In the method, resetting is carried out by discharging electric charges in the vicinity of sources of all the pixels together to a substrate in a period (1') right before a period (2) wherein electric charges of all the pixels are transferred to the source nearby areas. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for driving a solid-state imaging device, and in particular, realizes a global shutter by transferring charges stored in a photodiode all at once to a source vicinity region provided near a source region of a ring-shaped gate electrode opening. The present invention relates to a method for driving a solid-state imaging device.

  2. Description of the Related Art Conventionally, a driving method is known in which a CMOS image sensor, which is a solid-state imaging device, is operated with an electronic shutter that simultaneously starts and ends the accumulation of all pixels (see, for example, Patent Document 1).

  FIG. 5 shows an equivalent circuit diagram of an example of one pixel of the conventional solid-state imaging device described in Patent Document 1. In the figure, a pixel 1 is a transfer transistor 3 composed of a photodiode 2 that photoelectrically converts incident subject light and stores it as charges, and a P-channel MOS field effect transistor that transfers charges stored in the photodiode 2. A reset transistor 4 composed of a P-channel MOS field effect transistor, and an amplification composed of an N-channel MOS field effect transistor that amplifies the charge transferred by the transfer transistor 3 and outputs it to the pixel signal output line 16 Transistor 5.

  The gates of the transistors 5 and 3 are connected to the gate lines 12 and 13, and the source of the reset transistor 4 is connected to the reset supply line 14. Further, the pixel signal output line 16 is connected to the load 10 and is grounded through the switch 6 and the capacitor 7 in series, and is grounded through the switch 8 and the capacitor 9 in series. That is, the load 10 is connected to the pixel signal output line 16, and the capacitors 7 and 9 can store the load voltage at the time of optical signal output and reset signal output.

  The pixel 1 constituting this CMOS image sensor transfers the charges accumulated in the photodiode 2 all at once to the well diffusion layer 15 of the amplifying transistor 5 through the transfer transistor 3, and in accordance with the transferred charge amount, Since the potential changes, it is extracted as an electrical signal as a change in threshold voltage or a change in on-resistance.

  Here, as the characteristics of each MOS field effect transistor, the transfer transistor 3 is turned off when the potential of the gate wiring 13 is at a high level, and is turned on when the potential of the gate wiring 12 is at a low level. The threshold voltage is set so that the transistor 5 is turned off when it is on, middle level, and high level, and the transistor 5 is turned off when the potential of the gate wiring 12 is low level and middle level. It shall be.

  A driving method of this conventional CMOS image sensor will be described with reference to the timing chart of FIG. First, as shown in FIGS. 6B and 6A, the potentials of the gate wirings 12 and 13 of all the pixels are both set to the low level at the time t1, and thereby the drain and source of the reset transistor 4 which is turned on. The charges in both the photodiode 2 and the well 15 are discharged via the via and reset. After that, at time t2, as shown in FIG. 6A, the potential of the gate wiring 13 of all the pixels becomes high level, and as shown in FIG. 6B, the potential of the gate wiring 12 becomes middle level at time t3. Accumulation of optical signal charges is started simultaneously in the photodiodes 2 of all the pixels.

  After a predetermined accumulation time, the potentials of the gate wirings 13 of all the pixels become low level at time t4 shown in FIG. 6A, and the transfer transistors 3 are turned on. The charge is transferred to the well diffusion layer 15 of the amplifying transistor 5 through the transfer transistor 3 in the on state, and the potential of the gate wiring 13 becomes high level at time t5 after the transfer is completed.

  Thereafter, the readout process is sequentially performed for every row from all pixels. Here, when the potential of the gate wiring 12 is set to a high level at time t6 as shown in FIG. 6B, the amplifying transistor 5 is turned on, and an output corresponding to the optical signal charge is output to the pixel signal output line 16, The data is stored in the capacitor 7 through the switch 6 in the ON state (switch 8 is OFF at this time) schematically shown at a high level in FIG. Subsequently, as shown in FIG. 6B, at time t7, the potential of the gate wiring 12 becomes low level, and the charge in the well 15 is discharged.

  Thereafter, when the potential of the gate wiring 12 is set to the high level again at time t8, a signal output at the reset time is output to the pixel signal output line 16, and the switch in the ON state schematically shown in FIG. 6C at the high level. 8 (at this time, the switch 6 is off) and stored in the capacitor 9. This completes the reading process from the pixel 1, and subtracts the signals stored in the capacitors 7 and 9 using a subtracting means (not shown), and outputs it to the outside of the sensor.

JP 2003-17677 A

  However, in the conventional method for driving the solid-state imaging device, the potential of the gate wiring 12 is set to the middle level at time t3 when the signal of the photodiode 2 is accumulated, and the reset transistor 4 is turned off. As a result, the dark current generated at the interface of the crystal defects or the gate oxide film interface is not discharged in the well 15 but is accumulated in the well 15. When the potential of the gate wiring 13 then becomes low level at time t4 and the charge of the photodiode 2 is transferred to the well 15, the dark current component overlaps with the signal, thereby degrading the signal.

  Further, the conventional driving method of the solid-state imaging device has a problem that the signal cannot be accumulated by the photodiode 2 during signal readout. Further, since the reset transistor 4 is provided, the number of transistors in the pixel is increased to three, which causes a problem that the aperture ratio is deteriorated.

  The present invention has been made in view of the above points, and provides a driving method of a solid-state imaging device capable of preventing signal degradation due to dark current by adding an operation of resetting a transfer destination diffusion layer in all pixels immediately before transfer. For the purpose.

  Another object of the present invention is to provide a driving method of a solid-state imaging device capable of accumulating signals in a photodiode even during signal readout.

  Furthermore, another object of the present invention is to provide a method for driving a solid-state imaging device that requires only two transistors in a pixel.

  In order to achieve the above object, the present invention provides a ring-shaped gate electrode, a source diffusion region provided in a central opening of the ring-shaped gate electrode, and the outer periphery of the ring-shaped gate electrode surrounding the source diffusion region. An optical signal output transistor that outputs the amount of input charge as a change in threshold value, a photoelectric conversion region that converts light into charge and accumulates, A method for driving a solid-state imaging device in which a plurality of pixels having a transfer means for transferring charges accumulated in a photoelectric conversion region to a region near the source are arranged in a matrix, and light having ring-shaped gate electrodes of all pixels The signal output transistors are turned on at the same time, the first step of resetting all the pixels at the same time to discharge the charges near the source to the substrate, and the transfer means for all the pixels are turned on at the same time. In addition, the optical signal output transistors having the ring-shaped gate electrode are turned off, and the charges accumulated in the photoelectric conversion regions of the pixels are all simultaneously applied to the substrate immediately below the ring-shaped gate electrode of the same pixel. A second step of transferring and accumulating in the source vicinity region, and a third step of starting accumulation of charges obtained by photoelectrically converting incident light into the photoelectric conversion region again with the transfer means turned off, The optical signal output transistors having the ring-shaped gate electrodes of a plurality of pixels are sequentially controlled to operate, and the potential change due to the electric charge accumulated in the source vicinity region of each pixel is changed to the threshold value of the optical signal output transistor. And a fourth step of reading out a signal as a change in.

  In the present invention, all-pixel charge transfer is performed in which charges accumulated in the photoelectric conversion region of each pixel are transferred all at once to a substrate immediately below the ring-shaped gate electrode of the same pixel and accumulated in a region near the source. Immediately before, the reset for discharging the charges in the vicinity of the source of all the pixels to the substrate is performed all at once, so that the period of the reset state in which there is no charge in the vicinity of the source can be made constant.

  According to the present invention, the region near the source of the transfer destination to which the charges of all the pixels are transferred all at once is reset immediately before the charge transfer, and the time for which the reset state without charge is continued is made constant for all the pixels. The dark current accumulated in the region near the source due to crystal defects or the like can be discharged, there is no variation in image quality, and signal reading with less noise can be performed.

  In addition, according to the present invention, charges obtained by photoelectrically converting light can be accumulated in the photoelectric conversion region of a pixel that is not performing signal readout even during signal readout. Since the number of the optical signal output transistors and the transistors constituting the transfer means are driven, the aperture ratio of the photoelectric conversion region is improved as compared with a solid-state imaging device having three transistors in the pixel. be able to.

  Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a pixel structure of an example of a solid-state image sensor to which the driving method of the solid-state image sensor according to the present invention can be applied, and an electric circuit expressing the entire image sensor. The pixel structure itself of this solid-state imaging device is the one previously disclosed by the present inventor in Japanese Patent Application No. 2004-21895.

As shown in a top view of FIG. 1A and a longitudinal sectional view taken along line XX ′ of FIG. 1A shown in FIG. 1B, this solid-state image sensor is formed on a p ⁺ type substrate 21. A p ⁻ type epitaxial layer 22 is grown on the surface of the epitaxial layer 22, and an n well 23 is formed on the surface of the epitaxial layer 22. On the n-well 23, a gate electrode 25 having a ring shape as a first gate electrode is formed with a gate oxide film 24 interposed therebetween.

An n ⁺ -type source region 26 is formed on the surface of the n-well 23 corresponding to the center portion of the ring-shaped gate electrode 25, and a source vicinity p-type region 27 is formed adjacent to the source region 26. . The source vicinity p-type region 27 does not reach the outer peripheral portion of the ring-shaped gate electrode 25. An n ⁺ -type drain region 28 is formed on the surface of the n-well 23 at a position outside the source region 26 and the p-type region 27 near the source. Further, there is a buried p ⁻ -type region 29 in the n-well 23 under the drain region 28 outside the ring-shaped gate electrode 25. The buried p ⁻ -type region 29 and the drain region 28 constitute the buried photodiode 30 shown in FIG.

  Metal wirings 32, 33, 34, and 35 are connected to the drain region 28, the ring-shaped gate electrode 25, the source region 26, and the transfer gate electrode 31, respectively. In addition, a light shielding film 36 is formed above each of the above-described components as shown in FIG. 1B, and an opening 37 is formed at a position corresponding to the embedded photodiode 30 of the light shielding film 36. Has been. The light shielding film 36 is formed of a metal or an organic film. The light reaches the embedded photodiode 30 through the opening 37 and is photoelectrically converted.

  The solid-state imaging device having the structure shown in FIG. 1 is a CMOS sensor (meaning that a transistor having a ring-shaped gate electrode 25 is an amplifying MOS field effect transistor (FET) and an amplifying MOSFET is provided in each pixel). It can be said to be a kind of CMOS image sensor.

  Next, the pixel structure of the solid-state image sensor (CMOS sensor) in FIG. 1 and the entire structure of the image sensor will be described with reference to FIG. 2 expressed by an electric circuit. In the figure, first, pixels are arranged in a pixel spread area 41 in a two-dimensional matrix of m rows and n columns. In FIG. 2, one pixel 42 of s rows and t columns among these m rows and n columns pixels is represented by an equivalent circuit. The pixel 42 includes a MOSFET 43 having a ring-shaped gate electrode (hereinafter referred to as a ring-shaped gate MOSFET) 43, a photodiode 44, and a transfer gate MOSFET 45. The drain of the ring-shaped gate MOSFET 43 is a photodiode. 44 is connected to the n-side terminal 44 and the drain electrode wiring 46 (corresponding to 32 in FIG. 1), the source of the transfer gate MOSFET 45 is connected to the p-side terminal of the photodiode 44, and the drain is the back gate of the ring-shaped gate MOSFET 43 (FIG. 1 near the source p-type region 27).

In FIG. 1B, the ring-shaped gate MOSFET 43 has a p-type region 27 near the source directly below the ring-shaped gate electrode 25 as a gate region, and an n ⁺ -type source region 26 and an n ⁺ -type drain region 28. It has N channel MOSFET. In addition, in FIG. 1B, the transfer gate MOSFET 45 has an n well 23 just below the transfer gate electrode 31 as a gate region, a p ⁻ type region 29 embedded with a photodiode 30 as a source region, and a p-type region 27 near the source. A P-channel MOSFET serving as a drain.

  In FIG. 2, there is a frame start signal generation circuit 47 for generating a frame start signal for giving a signal to start reading in order to read a signal for one frame from each pixel of m rows and n columns. The frame start signal may be given from outside the image sensor. This frame start signal is supplied to the vertical shift register 48. The vertical shift register 48 outputs a signal indicating which row of pixels is read out from each pixel of m rows and n columns.

  The pixels in each row are connected to a control circuit that controls the potentials of the ring-shaped gate electrode, transfer gate electrode, and drain electrode, and the output signal of the vertical register 48 is supplied to these control circuits. For example, the ring-shaped gate electrode of each pixel in the s-th row is connected to the ring-shaped gate potential control circuit 50 via the ring-shaped gate electrode wiring 49, and the transfer gate electrode of each pixel is connected via the transfer gate electrode wiring 51. Are connected to the transfer gate potential control circuit 52, and the drain electrode of each pixel is connected to the drain potential control circuit 53 via the drain electrode wiring 46. Each control circuit 50, 52, 53 is supplied with an output signal of the vertical shift register 48.

  Since the ring-shaped gate electrode is controlled for each row, wiring is performed in the horizontal direction. However, since the transfer gate electrode is controlled simultaneously for all pixels, the wiring direction is not limited and the vertical direction may be used. Here, it is expressed as wiring in the horizontal direction. Although the drain potential control circuit 53 controls all the pixels at the same time, there is a possibility that the drain potential control circuit 53 is controlled for each row.

  The source electrode of the ring-shaped gate MOSFET 43 of the pixel 42 is branched into two via a source electrode wiring 54 (corresponding to 34 in FIG. 1), and one of the source electrodes is supplied to a source potential control circuit 55 that controls the source electrode potential via a switch SW1. The other is connected to the signal readout circuit 56 via the switch SW2. When reading the signal, the switch SW1 is turned off and the switch SW2 is turned on. When the source potential is controlled, the switch SW1 is turned on and the switch SW2 is turned off. Since the signal is output in the vertical direction, the wiring direction of the source electrode is set to be vertical.

  The signal readout circuit 56 is configured as follows. The output of the pixel 42 is performed from the source of the ring-shaped gate MOSFET 43, and a load, for example, a current source 27 is connected to the output line 24. Therefore, it is a source follower circuit. One end of each of the capacitor C1 and the capacitor C2 is connected to the current source 27 via the switch sc1 and the switch sc2. One end of each of the capacitors C1 and C2 whose other ends are grounded is connected to the inverting input terminal and the non-inverting input terminal of the differential amplifier 58, and the potential difference between the capacitors C1 and C2 is output from the differential amplifier 58. It is like that. The signal output from the signal readout circuit 56 is output via the output switch swt. The output switches swt in the same column are controlled by a signal output from the horizontal shift register 59.

  By the way, in the CMOS sensor having such a structure, since the source vicinity p-type region 27 in FIG. 1 has a lower potential than the peripheral region, a depletion layer spreads in the periphery. When crystal defects exist in this depletion layer, hole electron pairs are generated by heat, and holes accumulate in the p-type region 27 near the source, resulting in noise. The lower the potential of the p-type region 27 in the vicinity of the source, the greater the influence of the depletion layer spreading to the peripheral region and collecting more noise charges. That is, the influence is greater in the reset state where there is no charge.

  This is shown in the schematic diagram of FIG. In FIG. 4, for the sake of simplicity, the photoelectric conversion region and the transfer gate electrode are ignored. FIG. 4A shows a state in which the hole 61 is present in the p-type region 27 near the source, and the spread of the depletion layer 60 is limited. Therefore, since the crystal defect 62 in FIG. 4A is not in the depletion layer 60, even if an electron hole pair is generated here, it is recombined and does not go to the p-type region 27 near the source.

  On the other hand, FIG. 4B is reset and there is no hole. When the depletion layer 63 expands to a region including the crystal defect 62 and an electron hole pair is generated at the crystal defect 62, the hole falls into the p-type region 27 near the source as indicated by 64. 4A and 4B show only a depletion layer that affects the p-type region 27 near the source. Therefore, a depletion layer due to the diffusion potential between the N well 23 and the P substrate 22 is ignored. Further, the potentials of the ring-shaped gate electrode 25, the source 26, and the drain 28 are not changed in FIGS. 4A and 4B, and the expansion of the depletion layer depends only on the influence of the potential of the p-type region 27 near the source. It is drawn as being.

  In the CMOS sensor having such a structure, when the reset of the p-type region 27 in the vicinity of the source (discharge of electric charges to the substrate) is different for each line, the amount of noise differs for each line (the pixel in the first row is the final pixel). As a result, the image quality varies from line to line. Further, the well diffusion layer 15 of the conventional solid-state imaging device described in Patent Document 1 shown in FIG. 5 corresponds to the p-type region 27 in the vicinity of the source in FIG. Problems with the described conventional solid-state imaging device arise.

Therefore, in one embodiment of the present invention, the problem of the conventional driving method of the solid-state imaging device described in Patent Document 1 described above is solved, and the image quality variation for each line is not generated as shown in FIG. Next, a driving method according to an embodiment of the present invention will be described with reference to the timing chart of FIG. First, in the period shown in FIG. 3A, light enters an embedded photodiode (30 in FIG. 1A, 44 in FIG. 2, etc.), and an electron / hole pair is generated by the photoelectric conversion effect. Holes are accumulated in the buried p ⁻ type region 29. At this time, the potential of the transfer gate electrode 31 is the same as the drain potential Vdd, and the transfer gate MOSFET 45 is off. These accumulations are performed at the same time as the previous frame read operation is being performed.

  Subsequently, when the reading of the previous frame is completed, a new frame start signal, which is a pulse having a constant width, is output from the frame start signal generation circuit 47 as shown in FIG. In the period indicated by (1 ′) immediately after the output of the frame start signal, the potentials of the ring-shaped gate electrode wirings 33 of all the pixels are set to High 1 as shown in FIG. 3C, and FIG. As shown, the potential of the source electrode wiring 34 is set to Highs, and the charges in the p-type region 27 near the source of all the pixels are simultaneously discharged (reset) to the substrate. As a result, the time for which the reset state without charge is continued in the source vicinity p-type region 27 is made constant for all pixels.

  Subsequently, in the period shown in FIG. 3 (2), the p-type region in the vicinity of the source of the ring-shaped gate electrode (25 in FIG. 1) from the photodiode (40 in FIG. 1A, 44 in FIG. 2 etc.) from all the pixels simultaneously. In order to transfer holes to (27 in FIG. 1), transfer gate electrodes (31 in FIG. 1) of all pixels are transferred by a transfer gate control signal output from the transfer gate potential control circuit 52 as shown in FIG. 3 (B). The transfer gate MOSFETs of all the pixels including the transfer gate MOSFET 45 are simultaneously turned on.

  This potential Low2 is higher than the potential Low1 of the control signal shown in FIG. 3C that is output from the ring-shaped gate potential control circuit 50 and applied to the ring-shaped gate electrode 25 of the ring-shaped gate MOSFET 43 at this time. A potential gradient is provided under the transfer gate electrode 31 and the ring-shaped gate electrode 25. The ring-shaped gate electrode potential Low1 may be 0V, but may be another value higher than 0V.

  On the other hand, the source potential of all the pixels including the source potential supplied from the source potential control circuit 55 to the source of the ring-shaped gate MOSFET 43 from the source electrode wiring 54 via the switch SW1 is as shown in FIG. The potential S1 (S1> Low1) is set so that the ring-shaped gate MOSFET 43 is turned off and no current flows. As a result, charges accumulated in the photodiodes of all the pixels are transferred all at once under the ring-shaped gate electrodes of the corresponding pixels.

  In the region below the ring-shaped gate electrode 25 shown in FIG. 1B, the source vicinity p-type region 27 has the lowest potential, so that the holes accumulated in the photodiode 30 (44) are near the source p-type region 27. Reach and accumulate there. As a result of the accumulation of holes, the potential of the p-type region 27 near the source rises.

Subsequently, in the period shown in FIG. 3 (3), as shown in FIG. 3 (B), the potential of the transfer gate electrode becomes Vdd, and the transfer gate MOSFETs of all the pixels are simultaneously turned off. As a result, again in the embedded photodiode (30 in FIG. 1A, 44 in FIG. 2, etc.), an electron-hole pair is generated by the photoelectric conversion effect, and the photodiode (30 in FIG. 1A, 44 in FIG. 2) is generated. Etc.), holes begin to accumulate in the buried p ⁻ -type region 29. This accumulation operation is continued until the next charge transfer.

  On the other hand, pixel signal readout is performed in order for each row, so that the potential of the ring-shaped gate electrode is Low as shown in FIG. As shown in (D), it is s1, and the ring-shaped gate MOSFET is in an off state, and enters a standby state with holes accumulated in the p-type region 27 near the source. Note that 0 (GND) ≦ Low ≦ Low1. The source potential can take various values depending on the value of the signal from the pixel while the signal is read from another row. Further, the ring-shaped gate electrode potential can take various potentials for each row.

  In the subsequent period shown in FIGS. 3 (4) to (6), pixel signal readout is performed. This signal readout operation will be described representatively for the pixel 42 in the s-th row and the t-th column. First, in the state where charges are accumulated in the p-type region 27 near the source, the vertical shift register 48 shown in FIG. In the period (4) in which the output signal is at a low level as shown in FIG. 3H, the potential of the ring-shaped gate electrode 25 is changed by the control signal output from the ring-shaped gate potential control circuit 50 as shown in FIG. As shown in FIG. 4, the voltage is raised from Low to Vg1.

Here, the potential Vg1 is between the potentials Low, Low1, and Vdd described above.
Low ≦ Low1 ≦ Vg1 ≦ Vdd (where Low <Vdd)
Is an electric potential that holds the inequality. In the period (4), the switch SW1 is turned off as shown in FIG. 3I, the switch SW2 is turned on as shown in FIG. 3J, and the switch sc1 is turned on as shown in FIG. The switch sc2 is turned off as shown in FIG.

As a result, the source follower circuit connected to the source of the ring-shaped gate MOSFET 43 works, and the source potential of the ring-shaped gate MOSFET 43 is S2 (= Vg1-Vth1) in the period (4) as shown in FIG. Become. Here, Vth1 is a threshold voltage of the ring-shaped gate MOSFET 43 in a state where there is a hole in the back gate (the p-type region 27 near the source) of the ring-shaped gate MOSFET 43. This source potential S2 is stored in the capacitor C1 through SW2 that is turned on and the switch sc1. In this period (4), holes accumulated in the buried p ⁻ -type region 29 of the photodiode are increased from those in the period (3) due to the photoelectric conversion effect.

  In the subsequent period shown in FIG. 3 (5), the control signal output from the ring-shaped gate potential control circuit 50 raises the potential of the ring-shaped gate electrode 25 to High 1 as shown in FIG. As shown in (I) and (J), the switch SW1 is turned on and the switch SW2 is turned off, and the source potential output from the source potential control circuit 55 is raised to Highs as shown in FIG. Here, High1 and Highs> Low1.

The values of the potentials High1 and Highs may be the same or different, but High1 and Highs ≦ Vdd are desirable for simplicity of design. Further, it is desirable to set the potential so that the ring-shaped gate MOSFET 43 is turned on and no current flows. As a result, the potential of the p-type region 27 near the source in FIG. 1 rises, and holes are discharged to the epitaxial layer 22 beyond the barrier of the n-well 23. In this period (5), the number of holes accumulated in the p ^- type region 29 embedded in the photodiode is increased compared to the period (4) due to the photoelectric conversion effect.

  In the subsequent period shown in FIG. 3 (6), the same signal readout state as in the period (4) is set again. However, unlike the period (4), as shown in FIGS. 3M and 3N, the switch sc1 is turned off and the switch sc2 is turned on. The potential of the ring-shaped gate electrode 25 is set to Vg1 which is the same as that in the period (4) as shown in FIG. However, in this period (6), holes are discharged to the substrate (epitaxial layer 22) in the immediately preceding period (5) and no holes exist in the p-type region 27 near the source, so the source potential of the ring-shaped gate MOSFET 43 is As shown in FIG. 3L, in the period (6), S0 (= Vg1-Vth0). Here, Vth0 is a threshold voltage in a state where there is no hole in the back gate (the source vicinity p-type region 27) of the ring-shaped gate MOSFET 43. The source potential S0 is stored in the capacitor C2 via the turned-on SW2 and the switch sc2.

  The differential amplifier 58 outputs the potential difference between the capacitors C1 and C2. That is, the differential amplifier 58 outputs (Vth0−Vth1). This output value (Vth0-Vth1) is a change in threshold value due to hole charge. Thereafter, among the pulses shown in FIG. 3F output from the horizontal shift register 59, the output switch swt shown in FIG. 2 is turned on based on the output pulse in the t-th column shown in FIG. As schematically shown by hatching in FIG. 3P during the ON period, the threshold change due to the hole charge from the differential amplifier 58 is output as the output signal Vout of the pixel 42.

  Subsequently, in the period indicated by (7) in FIG. 3, the potential of the ring-shaped gate electrode 25 is set to Low again as shown in FIG. 3 (B), and all of the p-type region 27 near the source has no holes. Wait until the signal processing for the next row is completed. Even during this period (7), holes continue to accumulate in the photodiode due to the photoelectric conversion effect. Thereafter, the process returns to the period (1) and repeats from the hole transfer. Thereby, the output signal Vout shown in FIG. 3G is sequentially read from all the pixels. When signals are read from all pixels, the next frame is started again.

  Strictly speaking, the circuit of the pixel 42 is provided with a switch linked to each potential of the ring-shaped gate electrode wiring 49 and the transfer gate electrode wiring 51 between the source of the transfer gate MOSFET 45 and the back gate of the ring-shaped gate MOSFET 43. It is the structure which is made. This switch is turned on when there is a relationship Low1 ≦ Low2 between the potential Low1 of the ring-shaped gate electrode wiring 49 and the potential Low2 of the transfer gate electrode wiring 51, and when there is a relationship Low1> Low2. Turns off. However, at the time of transfer, the above condition of Low1 ≦ Low2 is always satisfied by the potential control circuits 50, 52, etc., and therefore this switch is omitted in FIG.

  Note that the source potential at the time of reset in period (5) in FIG. That is, in the period (5), both the switches sw1 and sw2 shown in FIG. 2 are turned off, and the source electrode wiring 54 is floated. Here, when the potential of the ring-shaped gate electrode 25 is High1, the ring-shaped gate MOSFET 43 is turned on, current is supplied from the drain to the source of the ring-shaped gate MOSFET 43, and the source electrode potential rises, thereby causing a p-type in the vicinity of the source. The potential of the region 27 is raised, and holes are discharged (reset) into the p-type epitaxial layer 22 beyond the barrier of the n-well 23.

  The source electrode potential when the holes are completely discharged becomes (High1-Vth0). In this method, the number of transistors supplying Highs in the source potential control circuit 55 can be reduced, and the chip area can be reduced.

  As described above, according to the present embodiment, the charges in the p-type region 27 near the source of all the pixels are simultaneously applied to the substrate (1 ′) in the period shown in FIG. By discharging (resetting) to the p-type epitaxial layer 22), the time for which the reset state without charge in the p-type region 27 near the source continues to be constant for all the pixels, and thus accumulated in the n-well 23. It is possible to prevent a phenomenon in which dark current is accumulated in a signal and overlapped with the signal.

  In this embodiment, as shown in FIG. 2, the number of transistors in one pixel 52 is two in total, that is, a ring-shaped gate MOSFET 43 and a transfer gate MOSFET 45, and the number of transistors in the pixel is three. The aperture ratio of the photodiode 30 can be improved as compared with the image pickup device, and charges (holes) can be accumulated in the photodiode even during signal readout.

1 is a top view illustrating a structure of an example of a solid-state imaging device to which the present invention is applied and a cross-sectional view taken along line X-X ′. It is the figure which expressed the pixel structure of the solid-state image sensor of FIG. 1, and the whole image sensor with the electric circuit. It is a timing chart for operation explanation of one embodiment of the method of the present invention. It is a figure which shows each example of how the depletion layer spreads in the solid-state image sensor of FIG. It is an equivalent circuit diagram of an example for 1 pixel of the conventional solid-state image sensor. 6 is a timing chart for explaining the operation of FIG. 5.

Explanation of symbols

25 n-type gate electrode 26 n ⁺ type source region 27 p-type region in the vicinity of the source 28 n ⁺ type drain region 29 buried p ⁻ type region 30, 44 photodiode 31 transfer gate electrode 41 pixel padding region 42 pixel 43 ring shape Gate MOSFET
45 Transfer gate MOSFET
47 frame start signal generation circuit 48 vertical shift register 50 ring-shaped gate potential control circuit 52 transfer gate potential control circuit 53 drain potential control circuit 56 signal readout circuit 58 differential amplifier 59 horizontal shift register C1, C2 capacitor

Claims (1)

A ring-shaped gate electrode; a source diffusion region provided in a central opening of the ring-shaped gate electrode; and a source vicinity provided so as to surround the source diffusion region and not to reach an outer periphery of the ring-shaped gate electrode An optical signal output transistor that outputs the amount of input charge as a change in threshold value, a photoelectric conversion region that converts light into electric charge and accumulates, and is stored in the photoelectric conversion region A solid-state imaging device driving method in which a plurality of pixels each having a transfer means for transferring charges to the source vicinity region are arranged in a matrix,
A first step of performing a reset by simultaneously turning on the optical signal output transistors having the ring-shaped gate electrodes of all the pixels and discharging the charges in the vicinity of the source to the substrate all at once;
The transfer means of all the pixels is turned on at the same time, and the optical signal output transistor having the ring-shaped gate electrode is turned off, and the charges accumulated in the photoelectric conversion regions of the pixels are A second step of transferring all of the pixels all at once to the substrate immediately below the ring-shaped gate electrode and storing them in the source vicinity region;
A third step of turning off the transfer means and starting accumulation of charges obtained by photoelectrically converting incident light in the photoelectric conversion region again;
The optical signal output transistors having the ring-shaped gate electrodes of the plurality of pixels are sequentially controlled to be in an operating state, and potential changes due to the charges accumulated in the source vicinity region of each pixel are output to the optical signal. And a fourth step of reading out a signal as a change in the threshold value of the transistor for a solid-state image sensor.

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