JP2007124070A - Image transmission apparatus using solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem in the conventional image transmission apparatus with high definition, wherein since a rolling shutter CMOS sensor is employed for its solid-state imaging device, superior image coding processing cannot be performed, when receiving image signal with a large motion, and efficiency is low. <P>SOLUTION: An image transmission apparatus disclosed herein uses a global shutter CMOS sensor 201 to image an object, resulting in that when a moving object is imaged, no image distortion which makes the image of the object different from the original will be caused in a picked-up image. Thus, both the correlation in the spatial direction and the correlation in the temporal direction of the image signal of even the object with a large motion can be ensured and image information can be coded efficiently, resulting in that a transmission band when the image signal is transmitted can efficiently be used and a high-definition image signal can be transmitted through a transmission path with a small transmission bandwidth. Furthermore, since deviations will not be caused in the imaged time of the signal by each image frame, the quality of the image as a still picture and the coding efficiency of the coded image can also be improved. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an image transmission apparatus using a solid-state image sensor, and more particularly to an image transmission apparatus using a solid-state image sensor that transmits a video signal obtained by imaging with a solid-state image sensor.

  In recent years, techniques for distributing digitized image signals through transmission lines such as satellite waves, terrestrial waves, telephone lines, and optical fibers have been realized. With such technology, interactive video transmission services such as live broadcast broadcasting from a remote location using a satellite or the like, and a video conference over a long distance are provided.

  A configuration of a conventional image transmission apparatus necessary for such a video transmission service will be described. FIG. 5 is a block diagram showing an example of a conventional image transmission apparatus. In the figure, first, there is a CMOS sensor 101 that converts a formed subject image into an electrical signal, and there is an optical lens 102 that forms an optical image of a subject (not shown) on the imaging surface of the CMOS sensor 101. The electrical signal output from the CMOS sensor 101 enters the input signal processing device 103, undergoes processing such as gamma correction and contour correction, and is sent to the image encoding device 104 as a digital image signal (video signal).

  In the image encoding device 104, the digital image signal is compressed using the time-direction correlation and the spatial-direction correlation of the image signal, which will be described later, and converted into encoded data having an information amount suitable for the transmission band of the transmission path. Then, the encoded data is supplied to the multiplexer 105. The multiplexing apparatus 105 superimposes (multiplexes) the encoded data supplied from the image encoding apparatus 104 and information to be transmitted other than an image, and outputs a signal superimposed on the modulation apparatus 106. In the modulation device 106, the input information is modulated in accordance with the electrical signal of the transmission path and the format. The modulated signal is output to the transmission path 107. The transmission path 107 may be a wired network such as an optical fiber or a telephone line, or may be a broadcasting or wireless network such as a satellite wave, a terrestrial wave, or a wireless LAN (local area network).

  In recent years, HDTV (High Definition Television) and image transmission apparatuses using high-definition image signals exceeding the number of pixels of HDTV have been developed. When inputting such a high-definition image, a CMOS sensor 101 capable of reading a signal at high speed is used as an image sensor. Further, the image encoding device 104 performs information compression processing for reducing the information amount of the input image signal and outputting it to the transmission path.

  As a high-efficiency encoding method for moving images and audio in an image transmission apparatus, international standards such as MPEG (Moving Picture Experts Group phase 2) 2, MPEG4 ASP, MPEG4 AVC and the like are used. Regarding the image coding of these standards, a method of compressing the amount of information using the correlation between adjacent pixels (spatial direction) of the image signal and the correlation between adjacent frames or adjacent fields (time direction) is used. .

  For example, an image encoding device in the MPEG2 standard performs encoding processing using the following algorithm. First, temporally continuous image frames are divided into a reference frame and a prediction frame. By encoding the reference frame using only the correlation in the spatial direction, it is possible to restore only the encoded data of the frame. By encoding the prediction frame using both the correlation in the time direction and the correlation in the spatial direction from the reference frame, the encoding efficiency can be further increased with respect to the reference frame. The encoded data of the prediction frame is restored from the restored reference frame and the encoded data of the prediction frame.

  A specific encoding system used in MPEG2 image encoding will be described with reference to FIG. An I picture (I frame), which is a reference frame indicated by I in FIG. 6A, periodically exists and is an intra-frame encoded image that serves as a reference for decoding processing. In addition, the prediction frame includes a P picture (P frame) encoded only by prediction from a temporally previous (past) reference frame indicated by P in FIG. There is a B picture (B frame) that is predictively encoded from two (future) reference frames. An arrow in FIG. 6A indicates a prediction direction.

  A P picture is an inter-frame forward prediction encoded image that is a prediction frame and also serves as a reference frame for the subsequent B picture and P picture. A B picture is a bidirectional predictive encoded image and is a prediction frame. An intra-frame coded image signal of an I picture is divided into processing units called macroblocks of horizontal 16 pixels × vertical 16 pixels by a luminance signal. The divided macroblock data is further divided into two-dimensional blocks of horizontal 8 pixels × vertical 8 pixels, and a DCT (Discrete Cosine Transform) process, which is a kind of orthogonal transform, is performed.

  Since the signal after the DCT conversion shows a value according to the frequency component of the two-dimensional block, the component is concentrated in a low band in a general image. In addition, information degradation of high frequency components has a property that is visually less noticeable than information degradation of low frequency components. Therefore, the amount of information is compressed by finely quantizing the low frequency components and coarsely quantizing the high frequency components, and variable length coding the coefficient components and the continuous length of coefficient 0 having no components.

  An image signal of a P picture is divided into macroblock units of 16 horizontal pixels × 16 vertical pixels by a luminance signal in the same manner as an I picture. In the P picture, a motion vector between the reference frame is calculated for each macroblock. Motion vector detection is generally obtained by block matching. In this block matching, the difference absolute value of each pixel obtained by blocking the reference frame of the position where the horizontal / vertical position where the macroblock exists by the motion vector value and the pixel of the macroblock are moved into 16 horizontal pixels × 16 vertical pixels. The sum (or the sum of squared differences) is obtained, and the value of the motion vector taking the minimum value is output as the detected motion vector.

  Each pixel of the macroblock is compared with each pixel of the two-dimensional block cut out by the motion vector. When an accurate motion vector is detected, the information amount of the difference block is significantly smaller than the information amount of the original macroblock, so that coarser quantization processing than that of the I picture is possible. Actually, it is selected whether to encode a differential block or a non-differential block (Intra block) (prediction mode determination), and DCT / variable length encoding similar to that of an I picture is performed on the selected block. Processing is performed and the amount of information is compressed.

  The B picture is processed in the same manner as the P picture. However, since the I and P pictures that are reference frames exist before and after in time, a motion vector is detected between each reference frame. In the B picture, there are three types of prediction options: prediction from the previous reference frame (Forward prediction), prediction from the subsequent reference frame (Backward prediction), and average value for each pixel of two prediction blocks (Average prediction), Prediction mode determination is performed from four types of intra blocks combined.

  B pictures can be predicted from temporally preceding and following reference frames, so that prediction efficiency is further improved than P pictures. Therefore, the quantization is generally coarser than that of the P picture. The selected block is subjected to encoding processing similar to that for I and P pictures.

  Since the B picture is decoded, a prediction process from a reference frame that is later in time is performed, so that the reference frame is encoded prior to the B picture. Therefore, as shown in FIG. 6B, the input picture signal is rearranged in the order after the I picture or P picture, which is the reference frame, and encoded.

  In the decoding process, as shown in FIG. 6C, by performing the reverse rearrangement of FIG. 6B and outputting, the decoded images are reproduced in the order of the input image signals. The transmission process is a process of converting the encoded image information into a signal format or characteristics of the transmission path and outputting the signal. As an example, an ATM (Asynchronous Transfer Mode) used for information transmission through a network such as various optical fibers will be described.

  In ATM, information such as voice, image, and data is divided and transmitted in units of fixed-length information called cells. The cell is composed of a portion for storing 48-byte information to be transmitted and a portion for storing a transfer destination of 5-byte information. The transmission apparatus divides the encoded information to be input every 48 bytes, and then assigns a number indicating the transfer destination to each division information and sends it to the network. In the network, the transfer destination in the cell is read, the communication partner is recognized, and information is sent to the communication partner. In the receiving apparatus, a plurality of arrived cells are combined to restore the transmitted information.

  As described above, in the image transmission apparatus that transmits a high-definition image signal, the CMOS sensor 101 that can read out the signal at high speed is used as an imaging element that captures the image signal for transmission. The CMOS sensor 101 will be described in more detail. This is a conventionally known rolling shutter type CMOS sensor (see, for example, Patent Document 1).

  FIG. 7 shows an equivalent circuit diagram of an example of the conventional CMOS sensor. In the CMOS sensor shown in the figure, for simplicity, the unit pixel 1 has a 2 × 2 pixel arrangement in which two horizontal pixels and two vertical pixels are arranged. The unit pixel 1 includes a photodiode (PD) 2 for photoelectrically converting a subject image, a signal charge amplification MOS field effect transistor (hereinafter referred to as MOSFET) 3, a charge transfer MOSFET 4, a reset MOSFET 5, and a selection. The power supply line 6 is connected to the drains of the MOSFETs 3 and 5, and the source of the amplification MOSFET 3 is connected to the drain of the selection MOSFET 7.

  The gate electrode of the amplification MOSFET 3 is in a floating diffusion (FD), and the charge of the photodiode 2 is transferred to the gate electrode (FD) of the amplification MOSFET 3 through the drain-source of the charge transfer MOSFET 4. The potential of the gate electrode (FD) of the amplification MOSFET 3 is reset by the reset MOSFET 5.

  When the selection MOSFET 7 is turned on, the source of the amplification MOSFET 3 is conducted to the pixel output line 8 through the drain and source of the selection MOSFET 7. The pixel output line 8 is connected to the drain of the constant current supply MOSFET 9. The constant current supply MOSFET 9 acts as a load of the source follower circuit of the amplification MOSFET 3. The constant current supply MOSFET 9 is controlled by the gate potential of the gate potential supply line 13.

  The reset control line 10, the charge transfer control line 11, and the pixel selection control line 12 are connected to the gate electrodes of the reset MOSFET 5, the charge transfer MOSFET 4, and the selection MOSFET 7, respectively. It is supplied from the pulse supply terminals 15, 14, 16 through the drains and sources of the MOSFETs 19, 20, 21.

  The vertical shift register 17 is a circuit for selecting a 2 × 2 pixel row for row sequential scanning, and the vertical shift register output lines 18-1 and 18-2 are connected to the gate electrodes of the MOSFETs 19, 20, and 21 in each row. It is connected and determines which row of pixels is controlled by the pulse supplied to the terminals of the pulse supply terminals 15, 14, 16.

  The read block 22 is connected to a capacitor 23 for holding a reset signal output, a capacitor 24 for holding an optical signal output, switching MOSFETs 25 and 26 for selecting which one to hold, and horizontal output lines 27 and 28. Switch MOSFETs 29 and 30. The switching MOSFETs 25 and 26 are switching-controlled by pulses supplied from the terminals 37 and 38 to the gate electrodes.

  The horizontal shift register 34 is a horizontal shift register output line 35-connected to the gates of the MOSFETs 29 and 30 for switching which column of the 2 × 2 pixels is to be output to the horizontal output lines 27 and 28. 1 and the output potential to 35-2. In addition, a potential for resetting the horizontal output lines 27 and 28 is supplied from the terminal 33, and the reset timing is performed by switching the switching MOSFETs 31 and 32 with a pulse supplied from the terminal 36. The horizontal output lines 27 and 28 are connected to the input terminal of the differential amplifier 39. The differential amplifier 39 takes the difference between the reset signal output and the optical signal output, and outputs the difference signal from the amplifier output terminal 40 to the outside of the sensor.

  Next, the operation of the conventional CMOS sensor shown in FIG. 7 will be described with reference to the timing chart of FIG. Note that all the MOSFETs in FIG. 7 are N-type, and therefore, the MOSFET is turned on when the gate potential is high (High) and turned off when the gate is low (Low).

  First, as shown in FIG. 8D, the potential of the vertical shift register output line 18-1 becomes High at time t1, thereby selecting the pixel 1 in the first row. Subsequently, as shown in FIG. 8C, the input pulse at the pulse supply terminal 16 becomes High at time t2, and the selection MOSFET 7 of the pixel 1 in the first row is turned on. The source of the amplification MOSFET 3 of the pixel 1 is connected to the constant current supply MOSFET 9 through the drain / source of the selection MOSFET 7 and the pixel output line 8 to form a source follower circuit.

  In this state, first, a high-level pulse is supplied to the pulse supply terminal 15 as shown in FIG. 8B, and the gate electrode of the amplification MOSFET 3 passes through the drain and source of the reset MOSFET 5 of the pixel 1 in the first row. (FD) is reset. Thereafter, at time t3, the input pulse of the pulse supply terminal 37 becomes High as shown in FIG. 8 (I), the switching MOSFET 25 is turned on, and the capacitor 23 outputs from the source follower circuit of the pixel 1 in the first row. The reset signal output is held.

  Next, when a high pulse is applied to the pulse supply terminal 14 at time t4 as shown in FIG. 8A, the charge transfer MOSFET 4 in the pixel 1 in the first row is turned on, and the pixel 1 in the first row. The charge accumulated in the photodiode 2 is transferred to the gate electrode (FD) of the amplification MOSFET 3 through the drain / source of the charge transfer MOSFET 4. At time t5, when a high pulse is applied to the pulse supply terminal 38 as shown in FIG. 8 (J), the optical signal output output from the source follower circuit of the pixel 1 in the first row is held in the capacitor 24. Is done. Subsequently, as shown in FIG. 8C, the input pulse at the pulse supply terminal 16 becomes Low at time t6, so that the selection MOSFET 7 in the pixel 1 in the first row is turned off, and the pixel in the first row. The output from 1 disappears.

  During this time, the input signal at the terminal 36 is High as shown in FIG. 8H, and the horizontal output lines 27 and 28 are in the reset state. However, at time t6, the input signal at the terminal 36 becomes Low as shown in FIG. 8 (H), and when the High pulse shown in FIG. 8 (F) is applied to the horizontal shift register output line 35-1 in this state. Since the switching MOSFETs 29 and 30 in the first column are turned on, the signals of the capacitors 23 and 24 in the first column are output to the horizontal output lines 27 and 28 through the switching MOSFETs 29 and 30 in the first column, respectively. And supplied to the differential amplifier 39. The differential amplifier 39 calculates the difference between each signal of the capacitors 23 and 24 in the first column, that is, the reset signal output and the optical signal output, and removes the optical signal from which the noise caused by the threshold variation of the amplification MOSFET 3 is removed. Output from the output terminal 40.

  Next, when a high pulse is applied to the terminal 36 at time t7 shown in FIG. 8 (H), the horizontal output lines 27 and 28 are reset again, and then to the horizontal shift register output line 35-2 in FIG. 8 (G). As shown, the high pulse is applied at time t8, and the switching MOSFETs 29 and 30 in the second column are turned on, so that the signals of the capacitors 23 and 24 in the second column are switched to the switching MOSFETs 29 and 30 in the second column. Are output to the horizontal output lines 27 and 28, supplied to the differential amplifier 39, and the second column signal is output from the differential amplifier 39 to the output terminal 40 in the same manner as the first column.

  Thereafter, at time t9 shown in FIG. 8D, the potential of the vertical shift register output line 18-1 becomes Low, and the processing of the first row is completed. Next, at time t10, as shown in FIG. 8E, the potential of the vertical shift register output line 18-2 becomes High, and processing similar to that in the first row is performed, and reading of all pixels is completed.

  Therefore, in the case of this CMOS sensor, the timing of photoelectric conversion by the photodiodes 2 in the first and second rows is different. Such an imaging method is called a rolling shutter or a focal plane.

JP 2003-17677 A

  As an image transmission apparatus, in order to effectively transmit information to a transmission path, it is necessary to improve the compression efficiency of information in the image encoding apparatus 104. In an image encoding method such as MPEG, an image is cut out in a two-dimensional block in the spatial direction, and compression processing using correlation in the spatial direction such as DCT conversion or compression using time direction correlation such as motion compensation prediction is performed in units. Processing is performed. In such a case, the correlation between the pixels of the blocked image data that is input at the same time is higher, and the difference in input time between the pixels is larger for an image with a large movement. Will worsen.

  The conventional rolling shutter type CMOS sensor 101 shown in FIG. 7 reads out one row at a time, and charges are stored in the photodiode 2 until the reading is completed. Accordingly, when considering a two-dimensionally divided image block, the exposure timing differs by the vertical line of the two-dimensional block at the upper end (first line) and the lower end (final line) of the block. For this reason, when an image signal with a large motion is input, the correlation in the spatial direction and the correlation in the time direction tend to be impaired, and good image coding processing cannot be performed, resulting in inefficient image transmission. The device is configured.

  The present invention has been made in view of the above points, and provides an image transmission apparatus capable of maintaining the correlation of image signals even for a subject with large movements and efficiently compressing a transmission band when transmitting an image. The purpose is to provide.

  In order to achieve the above object, the image transmission apparatus according to the present invention performs image processing on an imaging signal obtained by photoelectrically converting a subject light image by a solid-state imaging device, and then encodes and transmits the transmission path. In the device, an optical system that forms a subject light image on the imaging area of the solid-state image sensor, and the charge obtained by photoelectrically converting the subject light image to the photodiodes of all the pixels and accumulating them in all the pixels are stored. After that, the charge accumulated during the exposure period is sequentially output from each pixel as an imaging signal, and a predetermined signal is output for the global shutter type CMOS sensor as a solid-state imaging device and the imaging signal output from the global shutter type CMOS sensor. A signal processing unit that performs processing and outputs an image signal, and converts the image signal output from the signal processing unit into encoded data having an information amount suitable for the transmission band of the transmission path Encoding means, and an outputting means for outputting into a signal to be output to the transmission path encoded data output from the encoding means.

  In this invention, even when a moving subject is imaged by using a global shutter type CMOS sensor as a solid-state image sensor, the captured image does not cause image distortion different from the image of the subject. Both image signal correlation and temporal correlation can be ensured, and image information can be efficiently encoded and transmitted.

  Here, the global shutter type CMOS sensor includes a ring-shaped gate electrode on the substrate, a source region provided at a position of the substrate corresponding to the central opening of the ring-shaped gate electrode, surrounding the source region, and A signal output transistor comprising a source vicinity region provided on the substrate so as not to reach the outer periphery of the ring-shaped gate electrode, a photodiode for converting light to charge and storing, and a charge stored in the photodiode as a source A plurality of pixels including a charge transfer means for transferring to a neighboring area, and the charge transfer means in each pixel has a corresponding source neighboring area in the same pixel. All the pixels are transferred all at once, and the signal output transistor outputs the amount of input charge as a change in threshold value.

The global shutter CMOS sensor according to the present invention is a solid-state imaging device in which a plurality of pixels including a light-signal output transistor having a ring-shaped gate electrode and a photodiode are two-dimensionally arranged on a first conductivity type substrate. Where each of the pixels
An insulating film is provided on the second conductivity type well region provided on the surface of the substrate, the photoelectric conversion region of the first conductivity type photodiode provided in the well region, and the well region other than the photoelectric conversion region. A ring-shaped gate electrode provided between the ring-shaped gate electrode on the insulating film and the photoelectric conversion region, a transfer gate electrode provided on the well region with the insulating film interposed therebetween, and a surface of the well region A high-concentration second conductivity type drain region electrically integrated with the well region, provided in at least a part of a portion excluding the region corresponding to the ring-shaped gate electrode and the transfer gate electrode; A source region of the second conductivity type provided at a position in the well region corresponding to the central opening of the gate electrode, and provided in the well region so as to surround the source region and not reach the drain region And having a source region near the first conductivity type.

  Here, in the global shutter type CMOS sensor, the number of pixels equal to or larger than the number of pixels of the HDTV image is arranged in the imaging region in a two-dimensional matrix. The present invention is characterized in that the image signal is compression-encoded by a high-efficiency compression encoding method that compresses the amount of information using the correlation in the time direction.

  According to the present invention, since the global shutter CMOS sensor is used, the spatial correlation of the image signal and the correlation in the time direction are both ensured even for a subject with large movement, and the image can be efficiently encoded. Therefore, it is possible to provide an image transmission apparatus that can efficiently use a transmission band for transmitting image information and can transmit a high-definition image signal through a small number of transmission paths.

  In addition, according to the present invention, since there is no deviation in the imaging time of the signal for each frame of the image, when the input information is handled as a still image, the deviation of the image for each line does not occur. It is possible to improve the quality of the image and the encoding efficiency when it is encoded.

  Next, the best mode for carrying out the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of an image transmission apparatus using a solid-state imaging device according to the present invention. In the figure, the same components as those in FIG. Compared with the conventional image transmission apparatus shown in FIG. 5, the image transmission apparatus of the present embodiment shown in FIG. 1 uses a global shutter type CMOS sensor 201 as a solid-state imaging device instead of the rolling shutter type CMOS sensor 101. There is a feature in the point. In this global shutter type CMOS sensor 201, pixels having the same number of pixels as the number of pixels of a high-definition television (HDTV) image such as a high-definition image are arranged in a two-dimensional matrix in the imaging region.

Next, an embodiment of the global shutter type CMOS sensor 201 will be described. FIG. 2 shows a configuration diagram of an embodiment of a global shutter type CMOS sensor. FIG. 2A is a plan view, and FIG. 2B is a longitudinal sectional view taken along line XX ′ in FIG. Indicates. As shown in FIGS. 2A and 2B, the global shutter type CMOS sensor which is the solid-state imaging device 111 of the present embodiment grows a p ⁻ type epitaxial layer 42 on a p ⁺ type substrate 41, and There is an n-well 43 on the surface of the epitaxial layer 42. On the n-well 43, a gate electrode 45 having a ring shape as a first gate electrode is formed with a gate oxide film 44 interposed therebetween.

An n ⁺ -type source region 46 is formed on the surface of the n-well 43 corresponding to the center portion of the ring-shaped gate electrode 45, a source vicinity p-type region 47 is formed adjacent to the source region 46, and An n ⁺ -type drain region 48 is formed at a position spaced outside the source region 46 and the p-type region 47 near the source. In addition, there is a buried p ⁻ type region 49 in the n well 43 below the drain region 48. The buried p ⁻ type region 49 and the n well 43 constitute the buried photodiode 50 shown in FIG.

  Between the embedded photodiode 50 and the ring-shaped gate electrode 45, there is a transfer gate electrode 51 which is a second gate electrode. The drain region 48, the ring-shaped gate electrode 45, the source region 46, and the transfer gate electrode 51 include a drain electrode wiring 52, a ring-shaped gate electrode wiring 53, a source electrode wiring (output line) 54, and a transfer gate electrode, which are metal wirings, respectively. A wiring 55 is connected. Further, as shown in FIG. 2B, a light shielding film 56 is formed above each of the above components, and an opening 57 is formed at a position corresponding to the embedded photodiode 50 in the light shielding film 56. Has been. The light shielding film 56 is formed of a metal or an organic film. The light reaches the embedded photodiode 50 through the opening 57 and is photoelectrically converted.

  Next, the pixel structure of the CMOS sensor and the structure of the entire image sensor will be described with reference to FIG. In the figure, first, pixels are arranged in a pixel spread area 61 in m rows and n columns. In FIG. 3, one pixel 62 of s rows and t columns among these m rows and n columns pixels is represented by an equivalent circuit. The pixel 62 includes a ring-shaped gate MOSFET 63, a photodiode 64, and a transfer gate MOSFET 65. The drain of the ring-shaped gate MOSFET 63 is the n-side terminal of the photodiode 64 and the drain electrode wiring 66 (corresponding to 52 in FIG. 2). , The source of the transfer gate MOSFET 65 is connected to the p-side terminal of the photodiode 64, and the drain is connected to the back gate of the ring-shaped gate MOSFET 63.

In FIG. 2B, the ring-shaped gate MOSFET 63 has a p-type region 47 near the source directly below the ring-shaped gate electrode 45 as a gate region, and an n ⁺ -type source region 46 and an n ⁺ -type drain region 48. An n-channel MOSFET. In FIG. 2B, the transfer gate MOSFET 65 has an n well 43 just below the transfer gate electrode 51 as a gate region, a p ⁻ type region 49 embedded with a photodiode 50 as a source region, and a p-type region 47 near the source. A p-channel MOSFET serving as a drain.

  In FIG. 3, in order to read a signal for one frame from each pixel of m rows and n columns, there is a circuit 67 for generating a frame start signal for giving a signal to start reading. The frame start signal may be given from outside the image sensor. This frame start signal is supplied to the vertical shift register 68. The vertical shift register 68 outputs a signal indicating which row of pixels is read out from each pixel of m rows and n columns.

  The pixels in each row are connected to a control circuit that controls the potentials of the ring-shaped gate electrode, transfer gate electrode, and drain electrode, and these control circuits are supplied with the output signal of the vertical register 68. For example, the ring-shaped gate electrode of each pixel in the s-th row is connected to the ring-shaped gate potential control circuit 70 via the ring-shaped gate electrode wiring 69 (corresponding to 53 in FIG. 2), and the transfer gate electrode of each pixel is Are connected to the transfer gate potential control circuit 72 via the transfer gate electrode wiring 71 (corresponding to 55 in FIG. 2), and the drain electrode of each pixel is drained via the drain electrode wiring 66 (corresponding to 52 in FIG. 2). It is connected to the potential control circuit 73. Each control circuit 70, 72, 73 is supplied with an output signal from the vertical shift register 68.

  Since the ring-shaped gate electrode is controlled for each row, wiring is performed in the horizontal direction. However, since the transfer gate electrode is controlled simultaneously for all pixels, the wiring direction is not limited and the vertical direction may be used. Here, it is expressed as wiring in the horizontal direction. The drain potential control circuit 73 controls all the pixels at the same time, but may be controlled for each row. Therefore, the drain potential control circuit 73 is represented by being connected to both the frame start signal and the vertical register 68.

  The source electrode of the ring-shaped gate MOSFET 63 of the pixel 62 is branched into two via a source electrode wiring 74 (corresponding to 54 in FIG. 2), one of which is supplied to a source potential control circuit 75 that controls the source electrode potential via a switch SW1. The other is connected to the signal readout circuit 76 via the switch SW2. When reading the signal, the switch SW1 is turned off and the switch SW2 is turned on. When the source potential is controlled, the switch SW1 is turned on and the switch SW2 is turned off. Since the signal is output in the vertical direction, the wiring direction of the source electrode is set to be vertical.

  The signal readout circuit 76 is configured as follows. The output of the pixel 62 is performed from the source of the ring-shaped gate MOSFET 63, and a load, for example, a current source 77 is connected to the output line 74. Therefore, it is a source follower circuit. One end of each of the capacitor C1 and the capacitor C2 is connected to the current source 77 via the switch sc1 and the switch sc2. One end of each of the capacitors C1 and C2 whose other ends are grounded is connected to the inverting input terminal and the non-inverting input terminal of the differential amplifier 78, and the potential difference between the capacitors C1 and C2 is output from the differential amplifier 78. It is like that.

  Such a signal readout circuit 76 is called a CDS circuit (correlated double sampling circuit), and various circuits other than the method described here have been proposed, and the circuit is not limited to this circuit. The signal output from the signal readout circuit 76 is output via the output switch swt. The output switches swt in the same column are subjected to switching control by a signal output from the horizontal shift register 79.

Next, a method for driving the CMOS sensor shown in FIG. 3 will be described with reference to the timing chart of FIG. First, in the period shown in FIG. 4A, light is incident on the embedded photodiode (50 in FIG. 2A, 64 in FIG. 3, etc.), and an electron / hole pair is generated due to the photoelectric conversion effect. Holes accumulate in the buried p ^- type region 49 of the diode. At this time, the potential of the transfer gate electrode 51 is the same as the drain potential Vdd, and the transfer gate MOSFET 65 is off. These accumulations are performed at the same time as the previous frame read operation is being performed.

  In the subsequent period shown in FIG. 4 (2), when the reading of the previous frame is completed, a new frame start signal is transmitted as shown in FIG. First, all the pixels are performed simultaneously from the photodiode (50 in FIG. 2A, 64 in FIG. 3) to the p-type region (47 in FIG. 2) near the source of the ring-shaped gate electrode (45 in FIG. 2). It is to transfer the hole. Therefore, as shown in FIG. 4B, the transfer gate control signal output from the transfer gate potential control circuit 72 falls from Vdd to Low2, the potential of the transfer gate electrode (41 in FIG. 2) becomes Low2, and the transfer gate MOSFET 65 Turns on.

  At this time, the potential of the ring-shaped gate electrode wiring 69 controlled by the ring-shaped gate potential control circuit 70 changes from Low to Low1 as shown in FIG. 4C, but Low2 is larger than Low1. Low1 may be the same as Low. Most simply, Low1 = Low = 0 (V) is set.

  On the other hand, the source potential of all the pixels including the source potential supplied from the source potential control circuit 75 to the source of the ring-shaped gate MOSFET 63 from the source electrode wiring 74 through the switch SW1 is as shown in FIG. The potential is set to S1. S1> Low1, which keeps the ring-shaped gate MOSFET 63 off and prevents current from flowing. As a result, charges (holes) accumulated in the photodiodes of all the pixels are transferred all at once under the ring-shaped gate electrodes of the corresponding pixels.

  In the region below the ring-shaped gate electrode 45 shown in FIG. 2 (B), the p-type region 47 near the source has the lowest potential, so the holes accumulated in the photodiode reach the p-type region 47 near the source. Accumulated in. As a result of the accumulation of holes, the potential of the p-type region 47 near the source rises.

Subsequently, in the period shown in FIG. 4 (3), as shown in FIG. 4 (B), the transfer gate electrode becomes Vdd again, and the transfer gate MOSFET 65 is turned off. As a result, in the photodiode (50 in FIG. 2A, 64 in FIG. 3, etc.), electron-hole pairs are generated again due to the photoelectric conversion effect, and holes start to accumulate in the buried p ⁻ -type region 49 of the photodiode. This accumulation operation is continued until the next charge transfer.

  On the other hand, since the read operation is performed in units of rows, the potential of the ring-shaped gate electrode is low as shown in FIG. 4C in the period (3) in which the first to (s−1) th rows are read. In this state, a standby state is entered with holes accumulated in the p-type region 47 near the source. The source potential can take various values depending on the value of the signal from the pixel while the signal is read from another row. The ring-shaped gate electrode potential can take various values for each row, but is set to Low in the s-th row, and the ring-shaped gate MOSFET 63 is in an off state.

  In the subsequent period shown in FIGS. 4 (4) to (6), pixel signal readout is performed. This signal readout operation will be described representatively for the pixel 62 in the s-th row and the t-th column. First, in the state where holes are accumulated in the p-type region 47 near the source, the vertical shift register 68 shown in FIG. In the period (4) in which the output signal is at a low level as shown in FIG. 5H, the ring-shaped gate electrode 45 is controlled by the control signal output from the ring-shaped gate potential control circuit 70 to the ring-shaped gate electrode wiring 69. Is raised from Low to Vg1, as shown in FIG.

Here, the potential Vg1 is between the potentials Low, Low1, and Vdd described above.
Low ≦ Low1 ≦ Vg1 ≦ Vdd (where Low <Vdd)
Is an electric potential that holds the inequality. In the period (4), the switch SW1 is turned off as shown in FIG. 4I, the switch SW2 is turned on as shown in FIG. 4J, and the switch sc1 is turned on as shown in FIG. The switch sc2 is turned off as shown in FIG.

  As a result, the source follower circuit connected to the source of the ring-shaped gate MOSFET 63 works, and the source potential of the ring-shaped gate MOSFET 63 is S2 (= Vg1-Vth1) in the period (4) as shown in FIG. Become. Here, Vth1 is a threshold voltage of the ring-shaped gate MOSFET 63 in a state in which there is a hole in the back gate (p-type region 47 near the source). The source potential S2 is stored in the capacitor C1 through the switch sc1 that is turned on.

  In the subsequent period shown in FIG. 4 (5), the potential of the ring-shaped gate electrode 45 is set as shown in FIG. 4 (K) by the control signal output from the ring-shaped gate potential control circuit 70 to the ring-shaped gate electrode wiring 69. At the same time as raising to High1, the switch SW1 is turned on and the switch SW2 is turned off as shown in FIGS. 1I and 1J, and the source potential output from the source potential control circuit 75 is shown in FIG. Raise to Highs as shown. Here, High1 and Highs> Low1.

  The values of the potentials High1 and Highs may be the same or different, but High1 and Highs ≦ Vdd are desirable for simplicity of design. In a simple setting, High1 = Highs = Vdd. Further, it is desirable to set the potential so that the ring-shaped gate MOSFET 63 is turned on and no current flows. As a result, the potential of the p-type region 47 near the source rises, and holes are discharged to the epitaxial layer 42 beyond the barrier of the n-well 43 (reset).

  In the subsequent period shown in FIG. 4 (6), the same signal readout state as in the period (4) is set again. However, unlike the period (4), as shown in FIGS. 4M and 4N, the switch sc1 is turned off and the switch sc2 is turned on. The ring-shaped gate electrode is set to Vg1 which is the same as that in the period (4) as shown in FIG. However, in this period (6), holes are discharged to the substrate in the immediately preceding period (5), and no holes are present in the p-type region 47 near the source. Therefore, the source potential of the ring-shaped gate MOSFET 63 is as shown in FIG. L), the period (6) is S0 (= Vg1-Vth0). Here, Vth0 is the threshold voltage of the ring-shaped gate MOSFET 63 in a state where there is no hole in the back gate (p-type region 47 near the source).

  The source potential S0 is stored in the capacitor C2 through the switch sc2 that is turned on. The differential amplifier 78 outputs the potential difference between the capacitors C1 and C2. That is, the differential amplifier 78 outputs (Vth0−Vth1). This output value (Vth0-Vth1) is a change in threshold value due to hole charge. Thereafter, among the pulses shown in FIG. 4F output from the horizontal shift register 79, the output switch swt in FIG. 3 is turned on based on the output pulse in the t-th column shown in FIG. During the ON period, as schematically shown by hatching in FIG. 4 (P), the threshold value change due to the Hall charge from the differential amplifier 78 is output to the outside of the sensor as the output signal Vout of the pixel 62.

  Subsequently, in the period indicated by (7) in FIG. 4, the potential of the ring-shaped gate electrode 45 is set to low again as shown in FIG. It waits until the signal processing of the next row is completed (until the readout of pixels of the s + 1 row to the nth row is completed). During these readout periods, the photodiode 64 is accumulating holes due to the photoelectric conversion effect. Thereafter, the process returns to the period (1) and repeats from the hole transfer. As a result, the output signal shown in FIG. 4G is read from each pixel. When signals are read from all pixels, the next frame is started again.

  2A and 2B, the ring-shaped gate MOSFET 63 having the ring-shaped gate electrode 45 is an amplifying MOSFET, and as shown in FIG. It is a kind of CMOS sensor in the sense that it has an amplifying MOSFET. In this CMOS sensor, the charge (hole) accumulated in the photodiode is transferred to the p-type region 47 in the vicinity of the source under the ring-shaped gate electrode of the corresponding pixel at the same time. Is realized.

  Note that the potential supply of the source electrode wiring 74 at the time of resetting in the period (5) of FIG. That is, in the period (5), both the switches SW1 and SW2 are turned off, and the source electrode wiring 74 is floated. Here, when the potential of the ring-shaped gate electrode wiring 69 is High1, the ring-shaped gate MOSFET 63 is turned on, current is supplied from the drain to the source electrode, and the source electrode potential rises. As a result, the potential of the p-type region 47 in the vicinity of the source is raised, and holes are discharged to the p-type epitaxial layer 42 beyond the barrier of the n-well 43 (reset). The source electrode potential when the holes are completely discharged becomes High1-Vth0. This method can reduce the number of transistors that supply Highs in the source potential control circuit 75, and as a result, the chip area can be reduced.

  Note that the circuit configuration of the pixel 62 in FIG. 3 is simplified. Strictly speaking, the circuit of the pixel 62 is provided with a switch linked to each potential of the ring-shaped gate electrode wiring 69 and the transfer gate electrode wiring 71 between the source of the transfer gate MOSFET 65 and the back gate of the ring-shaped gate MOSFET 63. It is a configuration. This switch is turned on when there is a relationship of Low1 ≦ Low2 between the potential Low1 of the ring-shaped gate electrode wiring 69 and the potential Low2 of the transfer gate electrode wiring 71, and when there is a relationship of Low1> Low2. Turns off.

  By providing this switch, the substrate potential under the ring-shaped gate electrode 45 (potential Low1) is higher than the substrate potential under the transfer gate electrode 61 (potential Low2), and the ring-shaped gate electrode 45 (potential). The phenomenon that the substrate potential under Low 1) functions as a barrier and the holes cannot reach the p-type region 47 near the source can be expressed in a circuit form. However, at the time of transfer, the above condition of Low1 ≦ Low2 is always satisfied by the potential control circuits 70, 72, etc., and therefore this switch is omitted in FIG.

  As described above, in the global shutter type CMOS sensor 201 used as the solid-state imaging device, as described with reference to FIGS. 2 to 4, the exposure is performed in the same one frame period without shifting the timing for each line, and for a certain period. After the exposure, the transfer gates (transfer gate MOSFET 65, etc. in FIG. 3) in the global shutter CMOS sensor transfer the charges of all the pixels all at once to the readout circuit at the timing of the charge transfer period. Thereafter, signals from each pixel are sequentially read out by the readout circuit within the readout period. Thus, even when a moving subject is imaged, the captured image does not generate image distortion different from the image of the subject.

  Therefore, according to the present embodiment, it is possible to ensure both the correlation of the image signal and the correlation in the time direction even for a subject with large motion, and to efficiently encode the image information. The transmission band at the time of transmission can be used efficiently, and a high-definition image signal can be transmitted with few transmission paths. Also, since there is no deviation in the image capturing time of the signal for each frame of the image, when the input information is handled as a still image, there is no deviation of the image for each line, and the quality and code of the image as the still image Therefore, the coding efficiency is improved.

  In the image transmission apparatus shown in FIG. 1, the encoding algorithm of the image encoding apparatus 104 is an encoding method that uses correlation in the time direction and correlation in the spatial direction. Since the images are input at the same time, the correlation is high, and even for images with large movements, there is no shift in the input time between pixels, and a large correlation can be obtained. . Further, the modulation device 106 and the transmission path 107 are also effective regardless of their types.

It is a block diagram of one embodiment of an image transmission device of the present invention. FIG. 2 is a plan view of an element structure for one pixel of a global shutter type CMOS sensor that is the solid-state image pickup element of FIG. 1 and a cross-sectional view taken along line X-X ′. It is the figure which showed the whole structure of the global shutter type | mold CMOS sensor used by this invention with the electrical equivalent circuit. 3 is a timing chart for explaining the operation of the CMOS sensor of FIG. 2. It is a block diagram of an example of the conventional image transmission apparatus. It is a schematic diagram explaining the encoding system used by MPEG2 image encoding. It is a circuit diagram of an example of the rolling shutter type CMOS sensor used with the conventional image transmission apparatus. 8 is a timing chart for explaining the operation of FIG.

Explanation of symbols

43 n well 45 ring-shaped gate electrode 46 n ⁺ type source region 47 near source p type region 48 n ⁺ type drain region 49 buried p ⁻ type region 50, 64 photodiode 51 transfer gate electrode 52, 66 drain electrode wiring 53, 69 Ring-shaped gate electrode wiring 54, 74 Source electrode wiring (output line)
55, 71 Transfer gate electrode wiring 61 Pixel covering area 62 Pixel 63 Ring-shaped gate MOSFET
65 Transfer gate MOSFET
DESCRIPTION OF SYMBOLS 103 Input signal processing apparatus 104 Image coding apparatus 105 Multiplexing apparatus 106 Modulation apparatus 107 Transmission path 201 Global shutter type CMOS sensor

Claims (4)

In an image transmission apparatus that performs signal processing on an imaging signal obtained by photoelectrically converting a subject light image with a solid-state imaging device, and then encodes and transmits the transmission path.
An optical system that forms an image of the subject light image on an imaging region of the solid-state imaging device;
After the object light image is simultaneously exposed to photodiodes of a plurality of pixels and photoelectrically converted and accumulated in all pixels, the charges accumulated during the exposure period are sequentially output from each pixel as the imaging signal. A global shutter type CMOS sensor as the solid-state image sensor;
Signal processing means for performing predetermined signal processing on the imaging signal output from the global shutter type CMOS sensor and outputting an image signal;
Encoding means for converting the image signal output from the signal processing means into encoded data having an information amount suitable for a transmission band of a transmission path;
An image transmission apparatus comprising: output means for converting the encoded data output from the encoding means into a signal to be output to a transmission path and outputting the signal. The global shutter CMOS sensor is
A ring-shaped gate electrode on the substrate; a source region provided at a position of the substrate corresponding to a central opening of the ring-shaped gate electrode; and surrounding the source region and reaching an outer periphery of the ring-shaped gate electrode A signal output transistor comprising a source vicinity region provided on the substrate so as not to
The photodiode for converting light into electric charge and storing it;
A plurality of two-dimensionally arranged pixels including charge transfer means for transferring the charge accumulated in the photodiode to the source vicinity region;
The charge transfer means in each pixel transfers the charge accumulated in the photodiode all at once to the corresponding source vicinity region in the same pixel, and the signal output transistor receives the input charge. The image transmission apparatus according to claim 1, wherein the amount of output is output as a change in threshold value. The global shutter type CMOS sensor is a solid-state imaging device in which a plurality of pixels including an optical signal output transistor having a ring-shaped gate electrode and a photodiode are two-dimensionally arranged on a first conductive type substrate,
Each of the pixels
A well region of a second conductivity type provided on the surface of the substrate;
A photoelectric conversion region of the photodiode of the first conductivity type provided in the well region;
The ring-shaped gate electrode provided on the well region other than the photoelectric conversion region with an insulating film interposed therebetween;
Between the ring-shaped gate electrode on the insulating film and the photoelectric conversion region, a transfer gate electrode provided on the well region with the insulating film interposed therebetween,
A high concentration second electrically integrated with the well region provided in at least a part of the surface of the well region excluding the region corresponding to the ring-shaped gate electrode and the transfer gate electrode. A drain region of a conductivity type of
A source region of a second conductivity type provided at a position in the well region corresponding to the central opening of the ring-shaped gate electrode;
The image transmission apparatus according to claim 1, further comprising: a first conductivity type source vicinity region provided in the well region so as to surround the source region and not reach the drain region. In the global shutter type CMOS sensor, the number of pixels equal to or larger than the number of pixels of an HDTV image is arranged in an imaging region in a two-dimensional matrix, and the encoding means uses a correlation in a spatial direction and a correlation in a time direction. 2. The image transmission apparatus according to claim 1, wherein the image transmission apparatus compresses and encodes the image signal by a high-efficiency compression encoding method for compressing information.

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