JP2002057316A - Solid-state image sensing device and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image sensing device having structure which is suitable for micronizing the unit picture element. SOLUTION: A source region 56 is arranged inside the inner periphery of a ring type gate electrode 59 of an insulated gate field-effect transistor 112 for optical signal detection adjacent to a light receiving diode 111 in the unit picture element 101. A drain region 57a is arranged outside the outer periphery of a gate electrode 59. A high concentration buried layer which stores light generating charges is arranged in a well region under a channel region in the vicinity of the source region. The unit picture element 101 is surrounded by an element isolation region 53 where a series of diffusion isolation region having the same conductivity as the drain region 57a is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device and a method of driving the same, and more particularly, to a threshold voltage modulation type MOS image sensor used for a video camera, an electronic camera, an image input camera, a scanner or a facsimile. The present invention relates to a solid-state imaging device using the same and a driving method thereof.

[0002]

2. Description of the Related Art Semiconductor image sensors such as CCD type image sensors and MOS type image sensors are excellent in mass productivity, and are applied to almost all image input device devices with the development of finer pattern technology. In particular,
In recent years, the power consumption is smaller than that of a CCD image sensor, and the sensor element and the peripheral circuit element are the same CMOS.
With the advantage that it can be created by technology, MOS
Type image sensors are being reviewed.

In view of such trends in the world, the present applicant has improved a MOS type image sensor, and has a sensor element having a carrier pocket (high concentration buried layer) 25 below a channel region of a MOS transistor for detecting an optical signal. (Japanese Patent Application No. 10-186453) has been filed to obtain a patent (registration number 2935492). This MOS
The type image sensor has a structure shown in FIGS. 12 is a plan view, and FIG. 13 is a sectional view taken along line II of FIG. In the structure, as shown in FIGS. 12 and 13, the unit pixel 101 includes a light receiving diode 111 and an optical signal detecting field effect transistor 112 adjacent to the light receiving diode 111. The light receiving diode 111 and the optical signal detecting field effect transistor 112 are connected by p-type well regions 15a and 15b. In the optical signal detecting field-effect transistor 112, the gate electrode 19 has a ring shape, and n-type source regions 16a and 16b are formed in the center.
An n-type drain region 17a is formed so as to surround the outer periphery of. A p-type hole pocket 25 is provided below the gate electrode 19 and in the well region 15b near the source region so as to surround the source regions 16a and 16b. Adjacent unit pixels 101 are separated by element separation regions. The element isolation region is LOCOS (LOCcal Oxidation
It comprises an insulating isolation region 14 formed on the substrate surface by the (Silicon) method and a p-type diffusion isolation region 13 formed on the semiconductor substrate thereunder.

Using this MOS type image sensor, a high reverse voltage is applied to each electrode during the initialization period to deplete each electrode,
The light-generated holes remaining in the hole pockets 25 are emitted. During the accumulation period, light-generating holes are generated by irradiating light to the light-receiving diode 111 portion, transferred to the hole pocket 25 and accumulated, and used for detecting an optical signal modulated in proportion to the accumulation amount of the light-generating holes during the reading period. An optical signal is detected by detecting a threshold value of the field effect transistor 112.

[0005]

However, in the structure of the solid-state imaging device, the structure of the element isolation region and the structure of the field effect transistor for detecting an optical signal are not suitable for miniaturization, and the high definition of a future image will be required. There is a problem in that it is difficult to cope with the demand for miniaturization of unit pixels, which is required with the development of the semiconductor device.

The present invention has been made in view of the above-mentioned problems of the prior art, and provides a solid-state imaging device having a structure suitable for miniaturization of a unit pixel and a driving method thereof.

[0007]

In order to solve the above-mentioned problems, the present invention relates to a solid-state imaging device, and as a basic configuration of the solid-state imaging device, as shown in FIG. Each unit pixel 101 includes an insulated gate type field effect transistor (MOS transistor) 112 for detecting an optical signal.
Well region 54 interconnected with transistor 112
a, a high concentration buried layer (carrier pocket) 55 for accumulating photo-generated charges in the well region 54b around the source region of the MOS transistor 112.

The gate electrode of the insulated gate field effect transistor 112 has a ring shape, the source region 56 is provided inside the inner periphery of the gate electrode, and the drain region 57a is provided outside the outer periphery of the gate electrode. Is provided, and the light receiving diode 111 and the insulated gate field effect transistor 112 are characterized in that the diffusion isolation region 53 having the same conductivity type as the drain region 57a is surrounded by a series of element isolation regions. .

The diffusion isolation region 53 has well regions 54a and 54b having the same conductivity type as the drain region 57a.
It is characterized in that a deeper conductivity type impurity region is connected to the drain region 57a. Further, a plurality of unit pixels are arranged in rows and columns, and further, in a planar arrangement of the unit pixels in the solid-state imaging device, the direction from the gate electrode to the light receiving diode in the unit pixel is a row direction or It is characterized by being oblique to or parallel to the column direction. Further, the gate electrodes of the insulated gate field effect transistors in the same row are connected to each other, and the source regions of the insulated gate field effect transistors in the same column are connected to each other.

The operation and effect provided by the above configuration will be described below. By the way, the selective oxidation method (LOCOS method)
Is disadvantageous for miniaturization because the formation region of the isolation insulating film is wider than the mask width due to the generation of bird's beak. In the present invention, the adjacent unit pixel 10
1 is formed of a diffusion isolation region 53 having the same conductivity type as the drain region 57a and a conductivity type impurity region deeper than the well regions 54a and 54b connected to the drain region 57a. Have been. That is, since element isolation is performed only in the diffusion isolation region 53 without using an isolation insulating film by the LOCOS method, a bird's beak is not generated and the element isolation region does not extend beyond the mask width. Thereby, the unit pixel 101 can be miniaturized. In this case, the drain region 57a is
Region 52 of the same conductivity type as the drain region below 4a and 54b
a and 52b and between the adjacent unit pixels 101, but no problem occurs in the operation of the solid-state imaging device. Note that no problem occurs because the source region 56 and the drain region 57a are separated by the ring-shaped gate electrode 59 in the unit pixel 101.

When the well regions 54a, 54b and the like are of the opposite conductivity type, that is, when the high concentration buried layer is n-type,
The high concentration buried layer becomes an electron pocket (carrier pocket) and accumulates photo-generated electrons.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a plan view showing an element layout in a unit pixel of a MOS image sensor according to a first embodiment of the present invention.

As shown in FIG. 1, in a unit pixel 101,
The light receiving diode 111 and the optical signal detecting MOS transistor 112 are provided adjacent to each other. An n-channel MOS (nMOS) is used as the MOS transistor 112. The unit pixel 101 has a rectangular shape, and the unit pixel 1
Numeral 01 is surrounded by an element isolation region in which the diffusion isolation region 53 is a series.

The light receiving diode 111 and the MOS transistor 112 are formed in different well regions, that is, a first well region 54a and a second well region 54b, and the well regions 54a and 54b are connected to each other. The first well region 54a in the portion of the light receiving diode 111 forms a part of a charge generation region by light irradiation. The second well region 54b in the portion of the MOS transistor 112 forms a gate region in which the threshold voltage of the channel can be changed by the potential applied to this region 54b.

The gate electrode 59 of the MOS transistor 112 has a square ring shape and a band shape.
The source region 56 is provided inside the inner periphery of the gate electrode 59, and the drain region 5 is provided outside the outer periphery of the gate electrode 59.
7a is provided. An n-type impurity is introduced into a surface layer of the second well region 54b below the gate electrode 59, and serves as a channel region.

The impurity region 57 of the light receiving diode 111 is formed by extending the drain region 57a. That is,
The impurity region 57 and the drain region 57a are integrally formed so that most of the region covers the surface layer of the first and second well regions 54a and 54b connected to each other. Further, the impurity region 57 and the drain region 57a extend to the periphery of the unit pixel 101 and are connected to the diffusion isolation region 53 surrounding the unit pixel 101.

Further, a carrier pocket (high-concentration buried layer) 55, which is a feature of this MOS image sensor, is a part of the region from the drain region 57a to the source region 56 in the channel length direction. And over the entire area in the channel width direction. The gate electrode 59 is connected to vertical scanning signal (VSCAN) supply lines 59a, 59b,..., And the source region 56 is connected to vertical output lines (or source electrodes) 60a, 60b,.
···It is connected to the. Vertical scanning signal (VSCAN)
The supply lines 59a, 59b,... And the vertical output lines (or source electrodes) 60a, 60b,. The diffusion isolation region 53 connected to the drain region 57a also serves as a drain voltage (VDD) supply line (or drain electrode) 61a, 61b,.

The above-mentioned components are covered with an insulating film 64 such as a silicon oxide film, and a region other than the light receiving window 63 of the light receiving diode 111 is a metal layer (light shielding film) formed on the insulating film 64. ) 62 to shield light. In the element operation for detecting an optical signal in the MOS image sensor described above, an accumulation period, a readout period, an initialization period (sweep period), an accumulation period,...
A series of processes of an accumulation period, a reading period, and an initialization period (sweep period) are repeated. In this embodiment,
A blanking period is provided between the initialization period and the accumulation period.

In the accumulation period, carriers are generated by light irradiation, and holes of the photogenerated carriers are moved in the first and second well regions 54a and 54b and accumulated in the carrier pocket 55. In this case, a positive voltage of approximately +1.6 V is applied to the drain region 57a, and the source region 56 is disconnected from the external circuit. A positive voltage of about +2 V is applied to gate electrode 59 so that sufficient electrons are accumulated in the channel region of MOS transistor 112. As a result, the source region 56 also becomes the drain region 57a.
And a positive voltage of approximately +1.6 V is applied. The accumulation period is a period during which a voltage of a difference between the first source potential modulated by the optical signals stored in the first and second line memories and the second source potential before the optical signal is applied is output. But also.

In the reading period, a change in the threshold voltage of the MOS transistor 112 due to the photo-generated charges accumulated in the carrier pocket 55 is read as a change in the source potential, and stored in the first line memory. MOS transistor 1
12 operates in a saturated state so that the drain region 57a
A positive voltage of approximately + 2-3V is applied to the gate electrode 59, and a positive voltage of approximately + 2-3V is applied to the gate electrode 59.

In the initialization period, before the photo-generated electric charges (photo-generated carriers) are accumulated, the remaining photo-generated electric charges, acceptors, donors, etc., which have been read out, are neutralized or captured by surface states. Residual charges, such as holes and electrons, before reading the optical signal are discharged from the semiconductor to empty the carrier pocket 55. A positive high voltage of about +5 V or more is applied to the source region 56, the drain region 57a, and the gate electrode 59.

The blanking period is a period necessary for turning back horizontal scanning between the initialization period and the accumulation period. The blanking period is the second period in which the photo-generated charges are swept out of the carrier pocket 55 by using this period. The source potential is stored in the second line memory. In this period, the same voltage as that in the above-described reading period is applied to the light receiving diode 111 and the MOS transistor 112.

Next, the device structure of the MOS type image sensor according to the embodiment of the present invention will be described with reference to sectional views. FIG. 2A is a cross-sectional view corresponding to a cross-sectional view taken along line II-II of FIG. 1 and illustrating a device structure of the MOS image sensor according to the embodiment of the present invention. FIG.
(B) is a diagram showing a state of a potential along the surface of the semiconductor substrate. FIG. 3 is a sectional view taken along line III-III in FIG.

As shown in FIG. 2A, the impurity concentration is 1 ×
N-type silicon having an impurity concentration of about 1 × 10 ¹⁵ cm ⁻³ is epitaxially grown on a substrate 51 made of p-type silicon of 10 ¹⁸ cm ⁻³ or more. Then, the thick n-type layer 52 is formed on the light receiving diode 111 by selective ion implantation or the like.
Then, a thin n-type layer 52b is formed in the MOS transistor 112.

A plurality of unit pixels 101 each including a light receiving diode 111 and an optical signal detecting MOS transistor 112 are formed on the n-type layers 52a and 52b. Then, adjacent unit pixels 1 are separated so that each unit pixel 101 is separated.
01 on the surface of the n-type layers 52a and 52b.
3 are formed. The element isolation region 53 is formed as shown in FIG.
As shown in FIG. 3 and FIG. The diffusion isolation region 53 has the same conductivity type as the drain region 57, and is formed by connecting a conductivity type impurity region deeper than the well regions 54a and 54b to the drain region 57.

Next, the details of the light receiving diode 111 will be described with reference to FIGS. The light-receiving diode 111 includes an n-type layer 52a, a p-type first well region 54a formed on the surface of the n-type layer 52a, and extends from the surface of the first well region 54a to the surface of the n-type layer 52a. Do n
And an impurity region 57 of a mold type. The n-type layer 52a under the first well region 54a is thickened so as to effectively react to light having a long wavelength and generate photo-generated charges.

The impurity region 57 extends from the drain region 57a of the MOS transistor 112 for detecting an optical signal and is formed integrally with the drain region 57a. In the storage period described above, the impurity region 57 is connected to the drain voltage supply lines 61a, 61b,... And is biased to a positive potential. At this time, the depletion layer extends from the boundary between the impurity region 57 and the first well region 54a to the entire first well region 54a and reaches the n-type layer 52a. on the other hand,
The depletion layer extends from the interface between the substrate 51 and the n-type layer 52a to the n-type layer 52a and reaches the first well region 54a.

Since the first well region 54a and the n-type layer 52a are connected to the gate region 54b of the MOS transistor 112, the light generation holes
Can be effectively used as charges for threshold voltage modulation. In other words, the entire first well region 54a and the entire n-type layer 52a become a carrier generation region by light. Also,
In the light receiving diode 111 described above, the impurity region 57
The light-receiving diode 111 has a structure in which light-generating holes are buried in that a carrier generation region by light is disposed under the light-emitting diode. Accordingly, noise can be reduced without being affected by the surface of the semiconductor layer having many trap levels.

Next, the optical signal detecting MOS transistor 1
Details of 12 will be described with reference to FIG. MOS
The transistor 112 has, in order from the bottom, a p-type substrate 51, an n-type layer 52b on the substrate 51, and a p-type second well region 54b formed in the n-type layer 52b. ing. The n-type layer 52b has a high impurity concentration and a low impurity concentration in order to effectively apply an electric field to the second well region 54b thereon during the initialization period.

The MOS transistor 112 has a square ring-shaped and band-shaped gate electrode 59, an n-type source region 56 inside the inner periphery thereof, and an n-type drain region 57a outside the outer periphery thereof. Is provided on the outside.
The n-type drain region 57a extends to
11 and are integrated with the n-type impurity region 57. A source electrode (vertical output line) 60 is provided in the source region 56.
are connected to each other, and drain electrodes (VDD supply lines) 61a, 61b,.
Is connected.

The gate electrode 59 is formed on the second well region 54b between the drain region 57a and the source region 56 via a gate insulating film 58. Gate electrode 59
The surface layer of the lower second well region 54b becomes a channel region. Further, in order to keep the channel region in an inversion state or a depletion state at a normal operating voltage, an appropriate concentration of n-type impurity is introduced into the channel region to form a channel dope layer 54c.

Below the channel region below the gate electrode 59,
In the second well region 54b near the source region 56,
A band-like p + -type carrier pocket (high-concentration buried layer) 55 is formed in a part of the region in the channel length direction and the entire region in the channel width direction. The p + type carrier pocket 55 can be formed by, for example, an ion implantation method. The carrier pocket 55 is formed in the second well region 54b below the channel region generated on the surface. It is desirable that the carrier pocket 55 be formed so as not to cover the channel region.

In the p + type carrier pocket 55 described above, the well region 54a around the carrier pocket 55,
54b, the impurity concentration is higher than that of the carrier pocket 54b.
5 Carrier pocket 55 compared to peripheral potential
Has a lower potential. Thereby, the light generation holes can be collected in the carrier pocket 55.

FIG. 2B is a potential diagram showing a state in which light-generating holes are accumulated in the carrier pocket 55 and electrons are induced in the source-side channel region to generate an inversion region. The MOS transistor 112
Threshold voltage changes. Therefore, the detection of the optical signal can be performed by detecting the change in the threshold voltage.

By the way, in the above-described carrier sweeping period, a high voltage is applied to the gate electrode 59, and the electric field generated thereby sweeps out the carriers remaining in the second well region 54b to the substrate 51 side. in this case,
By the applied voltage, the depletion layer spreads from the boundary between the channel dope layer 54c in the channel region and the second well region 54b to the second well region 54b, and the p-type substrate 51 and the n-type layer 52b The depletion layer spreads from the interface to the n-type layer 52b below the second well region 54b. Therefore,
The range of the electric field affected by the voltage applied to the gate electrode 59 mainly covers the second well region 54b and the n-type layer 52b below the second well region 54b.

Next, another configuration different from the configurations shown in FIGS. 1 and 2 will be described. FIG. 4 is a plan view showing another structure different from the structure shown in FIG. 1, and FIG.
It is sectional drawing which follows the IV line. For the structure shown in FIG.
, Which extend in parallel with the VSCAN supply lines 59a, 59b,...
The drain region 5 of each unit pixel 101 is newly provided above.
7a. 4 and 5, the same reference numerals as those shown in FIGS. 1 and 2 denote the same components as those in FIGS.

By adopting a structure as shown in FIGS.
The operation of the solid-state imaging device can be made uniform by minimizing the potential difference of the drain voltage between the unit pixels 101. As described above, according to the first embodiment of the present invention, the adjacent unit pixels 101 are separated only by the diffusion separation region 53 without using the insulating film by the LOCOS method.
No extra area such as bird's beak is taken, and unit pixel 10
1 can be miniaturized.

(Second Embodiment) FIG. 6 is a plan view showing an element layout in a unit pixel of a MOS image sensor according to a second embodiment of the present invention. The difference from the first embodiment is that the planar shape of the outer periphery of the gate electrode 59 of the insulated gate field effect transistor (MOS transistor) 112 for detecting an optical signal is 8
This is a point having a square shape. A diffusion isolation region (element isolation region) 53 having the same conductivity type as the drain region 57a is formed in a series, and the first and second well regions 54 are formed.
As in the first embodiment, the unit pixel 101 is surrounded by the diffusion isolation region 53 formed deeper than a and 54b. In FIG. 6, the unit pixel 10 at the center is shown.
1, the boundary between the element isolation region 53 and the first well region 54a and the impurity region 57, the element isolation region 53 and the second well region 54b, and the drain region 5
7a is indicated by a dotted line, and the unit pixel 101 in another portion is indicated.
Are omitted from the illustration.

In FIG. 6, the unit pixels 101 are arranged so that one side of the octagonal gate electrode 59 is opposed between adjacent unit pixels 101. Light receiving diode 111
Are provided in a space in the diagonally adjacent direction in which the octagonal gate electrodes 59 are arranged and adjacent to one side of the octagon. The vertical output lines 60a, 60b, 60c,.
The SCAN supply lines 59a, 59b, 59c,...
They extend in directions that intersect each other. In FIG. 6, FIG.
1 are the same as those shown in FIG. 1 and the description thereof is omitted.

FIG. 7 is a sectional view taken along the line IV-IV in FIG. As shown in FIG. 7, the cross-sectional structure has substantially the same structure as FIG. 7, the same reference numerals as those shown in FIG. 2 denote the same components as those in FIG. 2, and a description thereof will be omitted.
According to the second embodiment of the present invention, the same effect as in the first embodiment can be obtained.

Next, another configuration different from the configurations shown in FIGS. 6 and 7 will be described. FIG. 8 shows that the periphery shown in FIG.
FIG. 9 is a plan view showing another configuration of the gate electrode structure having a square shape, and FIG. 9 is a cross-sectional view along the line V-V in FIG. 8. The VSCAN supply lines 59a, 59b, 59c,... Are different from the gate electrode structure shown in FIG.
, VDD supply lines 61a, 61b,.
Is newly provided above the diffusion isolation region 53 connected to the drain region 57a, and the drain region 57a of each unit pixel 101 is provided.
It is characterized by being connected to. 8 and 9
6 and 7 indicate the same components as those in FIGS.

8 and 9, similarly to FIG. 6, the element isolation region 53, the first well region 54a, and the impurity region 57 are provided only in the peripheral portion of the unit pixel 101 in the central portion.
, The element isolation region 53 and the second well region 54b
The boundary with the drain region 57a is indicated by a dotted line, and the other portions around the unit pixel 101 are omitted.

With the structure shown in FIGS. 8 and 9,
As in the case of FIG. 4 of the first embodiment, the unit pixel 10
The operation of the solid-state imaging device can be made uniform by minimizing the potential difference of the drain voltage between the two. In the above description, the shape of the outer peripheral portion of the gate electrode is an octagon, but the shape may be a polygon of four or more sides having four or more sides.

(Third Embodiment) Next, an overall configuration of a MOS image sensor using unit pixels having the above structure will be described with reference to FIG. FIG. 10 shows a circuit configuration diagram of a MOS image sensor according to the third embodiment of the present invention. As shown in FIG. 10, this MOS image sensor has a two-dimensional array sensor configuration, and the unit pixel 101 having the structure described in the first and second embodiments is arranged in the column direction and the row direction. Are arranged in a matrix.

A drive scanning circuit 102 for the vertical scanning signal (VSCAN) and a drive scanning circuit 103 for the drain voltage (VDD) are arranged on the left and right sides of the pixel region. Vertical scanning signal supply lines (VSCAN supply lines) 59a,
.. Are provided one by one from the drive scanning circuit 102 of the vertical scanning signal for each row. Each vertical scanning signal supply line 59
a, 59b,... represent all the unit pixels 1 arranged in the row direction.
01 is connected to the gate electrode 59 of the MOS transistor 112.

The drain voltage supply lines (VDD supply lines) 61a, 61b,...
, One for each row. The drain voltage supply lines 61a, 61b,... Are connected to the drain regions 57a of the optical signal detection MOS transistors 112 in all the unit pixels 101 arranged in the row direction.

The vertical output lines 60a, 60b,.
Are output one by one per column, and each vertical output line 60a, 60
b,... are M in all the unit pixels 101 arranged in the column direction.
Each is connected to the source region 56 of the OS transistor 112. The source region 56 of the MOS transistor 112 is connected to the boosted voltage supply lines 73a, 73b,.
Are connected to the step-up scanning circuit 108 through. First and second well regions 54 in carrier pocket 55
a, a high voltage for discharging the charges remaining in 54b is supplied.

Further, the source region 56 of the MOS transistor 112 has vertical output lines 60a, 60b,.
To the signal output circuit 105. And
The source region 56 is connected to a pair of first and second line memories including a capacitor (not shown) in the signal output circuit 105. The first line memory stores a first source potential when the photo-generated charges are accumulated in the carrier pocket 55, and the second line memory stores the photo-generated charges after the photo-generated charges are discharged from the carrier pocket 55. The second source potential is stored. Then, a voltage having a difference between the first and second source potentials is output as an optical signal through a differential amplifier or the like (not shown). In this embodiment, an active load such as a constant current source is not connected to the source region 56.

Horizontal scan signal (HSCAN) supply line 72
a and 72b are output one by one from the horizontal scanning signal (HSCAN) input scanning circuit 104 for each column. Each horizontal scanning signal (HSCAN) supply line 72a, 72b is a signal output circuit 1
05. The horizontal scanning signal (HSCAN) input scanning circuit 104 supplies a horizontal scanning signal to the signal output circuit 105 through each horizontal scanning signal (HSCAN) supply line 72a, 72b, and controls the timing of outputting an optical signal.

In accordance with the vertical scanning signal (VSCAN) and the horizontal scanning signal (HSCAN), the MOS transistor 112 of each unit pixel 101 is successively driven to produce an image free from noise components due to residual charges, which is proportional to the amount of incident light. The signal (Vout) is read from the signal output circuit 105. FIG. 11 shows a timing chart of each input / output signal for operating the MOS image sensor according to the present invention.

In this case, the present invention is applied to the case where the p-type first and second well regions 54a and 54b are used and the optical signal detecting MOS transistor 112 is an nMOS. Next, the light detection operation of a series of solid-state imaging devices will be briefly described with reference to FIG. As described above, the light detection operation repeatedly performs a series of processes including an accumulation period, a readout period, an initialization period (sweep period), and a blanking period. Here, for convenience, the description starts from the accumulation period.

First, during the accumulation period, the optical signal detection M
The drain region 57a and the source region 56 of the OS transistor 112 are higher than the ground potential and the drain region 5
A voltage, for example, about 1.6 V (Vpd) is applied to the drain region 57a so that the pn junction formed by the source region 7a and the source region 56 and the second well region 54b is reverse-biased, and the source region 56 is It is maintained in a high impedance state, for example, a state cut off from an external circuit.
In addition, a gate voltage at which a channel region is not depleted with respect to a drain potential and a source potential in the gate electrode 59 and electrons are accumulated with a sufficient electron density, for example, 2.2.
V is applied. Thus, electrons having a sufficient electron density are accumulated in the channel region, the source region 56 is connected to the drain region 57a through the channel region, and the source region 5
6 has a voltage of about 1.6 V, which is the same as the voltage of the drain region 57a.
(Vps) is applied.

At this time, the first well region 54a and the second well
In the well region 54b and the n-type layers 52a and 52b. Then, the first and second well regions 54a, 5a
An electric field directed toward the carrier pocket 55 is generated in the carrier pocket 55 due to a difference in impurity concentration between the carrier pocket 55 and the well regions 54a and 54b around the carrier pocket 55. Subsequently, the light receiving diode 111 is irradiated with light to generate electron-hole pairs (photo-generated charges).

Due to the electric field, light-generating holes of the light-generated charges are injected into the gate region 54 b of the MOS transistor 112 for detecting a light signal, and the carrier pocket 55
Is accumulated in Thus, the width of the depletion layer extending from the channel region to the gate region 54b thereunder is limited, and the potential near the source region 56 is modulated, so that the threshold voltage of the MOS transistor 112 changes.

In the accumulation period, the channel region is inverted so that sufficient electrons are accumulated, so that the gate insulating film 5 is formed.
The hole generation center of the interface state at the interface between the channel 8 and the channel region is inactivated, and the emission of holes from the interface state, that is, the leak current is suppressed. Thereby, accumulation of holes other than the photo-generated charges in the carrier pocket 55 is suppressed, and so-called white flaws can be prevented from occurring on the video screen.

In the accumulation period, the first period
And the voltage of the difference between the source potentials stored in the second line memory is output to the video signal output terminal 107. This operation will be described after the blanking period. Next, in the period at the start of the reading period, VSCA
The output (Vpg) of the N drive scanning circuit 102 is connected to the ground potential (M
(It becomes the gate potential of the OS transistor 112).
On the other hand, the VDD supply lines 61a, 61b,.
It is kept at 3V.

Next, in the period after the end of the readout period, the output of the VSCAN drive scanning circuit 102 (V
pg) is approximately 2.2 V (becomes the gate potential of the MOS transistor 112). On the other hand, the VDD supply lines 61a,
61b are approximately 3.3 V (MOS transistor 1
12 drain potential). That is, a gate voltage (Vpg) of about 2.2 V at which the MOS transistor 112 can operate in a saturated state is applied to the gate electrode 59, and a voltage (Vpd) of about 3.3 V at which the MOS transistor 112 can operate at the drain region 57a. Is applied. Thus, a low electric field inversion region is formed in a part of the channel region above the carrier pocket 55, and a high electric field region is formed in the remaining part of the channel region. At this time, MOS
The drain voltage-current characteristics of the transistor 112 show saturation characteristics.

As a result, the first line memory is charged, and when the charging is completed, the threshold voltage (source potential VoutS) light-modulated is stored in the first line memory. The threshold voltage includes not only the voltage due to the photo-generated charges but also the voltage due to the charges not due to the photo-generated charges (that is, a noise voltage (VoutN)). Next, the process proceeds to an initialization operation. In the initialization operation, the inside of the carrier pocket 55, the first and second well regions 54a, 54b
Drain the charge remaining inside. That is, a high voltage of approximately 5 V is applied from the boosting scanning circuit 108 to the source region 56. As a result, the source potential (Vps) becomes approximately 5 V, and the voltage is applied to the gate electrode 59 through the gate insulating film 58, so that the potential (Vpg) of the gate electrode 59 is stepped up to approximately 5 to 6V. Then, the potential (Vpd) of the drain also becomes approximately 5V.

At this time, the voltage applied to the gate electrode 59 depends on the second well region 54b and the second well region 54b.
Over the n-type layer 52b below. Carriers can be reliably swept out of the second well region 54b by the high electric field generated at this time. After discharging the photo-generated charges accumulated in the carrier pocket 55, the output (Vpg) of the VSCAN drive scanning circuit 102 is changed to the ground potential (the gate potential of the MOS transistor 112) during the blanking period before the accumulation period. And at the same time, the output (Vpd) of the VDD drive scanning circuit 103 is 3.3 V (MOS
The drain potential of the transistor 112).

Next, during the period after the end of the period at the start of the blanking period, the output (Vpg) of the VSCAN drive scanning circuit 102 is set to about 2.2 V (the MOS transistor 1).
12 gate potential). On the other hand, the VDD supply lines 61a, 61b,... Are maintained at about 3.3V. Thus, a low electric field inversion region is formed in a part of the channel region above the carrier pocket 55, and a high electric field region is formed in the remaining part of the channel region. At this time,
A drain current flows to the source of the MOS transistor 112, and the drain voltage-current characteristic shows a saturation characteristic according to the threshold voltage. As a result, the second line memory is charged, and when the charging is completed, the noise voltage (VoutN) due to the residual charge not due to the photo-generated charge is stored in the second line memory.

Next, returning to the accumulation period, the accumulation operation is performed at this time, and the operation of outputting the voltage of the difference between the source potentials VoutS and VoutN stored in the first and second line memories is performed. At this time, the output timing is H
It is controlled by a horizontal scanning signal from the SCAN input scanning circuit 104. In this way, a video signal (Vout = VoutS-VoutN) proportional to the light irradiation amount can be extracted.

As described above, according to the third embodiment of the present invention, when the light-generating hole moves in a series of steps of the accumulation operation, the read operation, and the initialization operation (sweep operation), An ideal photoelectric conversion mechanism that does not interact with a noise source in a semiconductor surface or in a channel region can be realized.
The present invention has been described in detail by the embodiment.
The scope of the present invention is not limited to the examples specifically shown in the above embodiments, and modifications of the above embodiments that do not depart from the gist of the present invention are included in the scope of the present invention.

For example, in the above embodiment, in order to form the inversion state of the channel region during the accumulation period, the pn junction formed by the drain region 57a and the source region 56 and the second well region 54b is particularly formed. A voltage is applied to the drain region 57a and the source region 56 so as to be reverse-biased.
A ground voltage may be applied to a and the source region 56.

Although a line memory composed of an input capacitor is connected to the source region 56 in the signal output circuit, a constant current source may be connected in parallel with the line memory, and a source follower connection may be used. In this case, the switched capacitor circuit need not be provided. Although the first and second well regions 54a and 54b are formed in the n-type layers 52a and 52b on the p-type substrate 51, the n-type layers 52a and 52b are formed.
Instead of b, an n-type impurity is introduced into the p-type epitaxial layer to form an n-type layer, and the first and second layers are formed in the n-type layer.
Well regions 54a and 54b may be formed.

Further, various modifications are conceivable as the structure of the solid-state image pickup device to which the present invention is applied. An element isolation region 53 in which a unit pixel 101 is formed adjacent to the MOS transistor 112 and the unit pixel 101 is a series of diffusion isolation regions 53 having the same conductivity type as the drain region 57a.
It just needs to be surrounded by.

Further, although the p-type substrate 51 is used,
Instead, an n-type substrate may be used. In this case, in order to obtain the same effect as in the above embodiment, the conductivity type of each layer and each region described in the above embodiment and the like may be all reversed. In this case, carriers to be accumulated in the carrier pocket 55 are electrons out of electrons and holes.

[0067]

As described above, according to the present invention, the element isolation region for separating adjacent unit pixels performs element isolation only in the diffusion isolation region without using an isolation insulating film by the LOCOS method. The unit pixel can be miniaturized without taking an unnecessary area necessary for the LOCOS method.

[Brief description of the drawings]

FIG. 1 is a plan view showing an element layout in a unit pixel of a solid-state imaging device used in a solid-state imaging device according to a first embodiment of the present invention.

FIG. 2A is a cross-sectional view along the line II-II in FIG. (B) is a diagram showing a state of potential in a state where light generation holes are accumulated in a carrier pocket and electrons are induced in a channel region to generate an inversion region.

FIG. 3 is a sectional view taken along the line III-III of FIG. 1;

FIG. 4 is a plan view showing an element layout in a unit pixel of a solid-state imaging device used in another solid-state imaging device according to the first embodiment of the present invention.

5 is a cross-sectional view taken along the line IV-IV of FIG.

FIG. 6 is a plan view showing an element layout in a unit pixel of a solid-state imaging device used in a solid-state imaging device according to a second embodiment of the present invention.

7 is a cross-sectional view taken along the line VV of FIG. 6;

FIG. 8 is a plan view showing an element layout in a unit pixel of a solid-state imaging device used in another solid-state imaging device according to a second embodiment of the present invention.

FIG. 9 is a cross-sectional view taken along the line VI-VI of FIG.

FIG. 10 is a diagram showing the overall circuit configuration of a solid-state imaging device having the solid-state imaging device of the present invention.

FIG. 11 is a timing chart illustrating a driving method of the solid-state imaging device according to the embodiment of the present invention;

FIG. 12 is a plan view showing an element layout in a unit pixel of a solid-state imaging device used in a solid-state imaging device according to a conventional example.

13 is a cross-sectional view taken along the line II of FIG.

[Explanation of symbols]

53 Diffusion separation region (element separation region) 54a First well region 54b Second well region 54c Channel dope layer 55 Carrier pocket (high concentration buried layer) 56 Source region 57 Impurity region 57a Drain region 58 Gate insulating film 59 Gate Electrodes 59a, 59b, 59c VSCAN supply line 60a, 60b, 60c Vertical output line 61a, 61b VDD supply line 71 Horizontal output line 72a, 72b HSCAN supply line 73a, 73b Boost voltage supply line 101 Unit pixel 102 VSCAN drive scan circuit 103 VDD Drive scan circuit 104 HSCAN input scan circuit 105 Signal output circuit 107 Video signal output terminal 108 Boost scan circuit 111 Light receiving diode 112 Insulated gate type field effect transistor for light signal detection (MOS transistor for light signal detection)

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H04N 5/335 H01L 21/76 J31 / 10 HG F term (Reference) 4M118 AA05 AA10 AB01 BA14 CA04 CA19 CA20 DB01 DD02 DD09 FA06 FA26 FA28 FA33 GB11 5C024 GX03 GX06 GY31 GZ02 GZ42 JX05 5C051 AA01 BA03 DA06 DB01 DB08 DC02 DC03 DC07 DE02 EA00 5F032 AB01 AB05 BB03 BB06 CA15 CA17 5F049 MA02 NB05 QA15 RA03 RA08 SE09 SE11 SE20

Claims (11)

[Claims] A unit pixel in which a light receiving diode and an insulated gate field effect transistor for detecting an optical signal adjacent to the light receiving diode are formed in a well region, and the portion of the insulated gate field effect transistor is formed in the well region A drain region and a source region provided therein, a channel region between the drain region and the source region,
A gate electrode formed on the channel region via a gate insulating film, and light generation generated by light irradiation by the light-receiving diode provided in a well region near the source region and below the channel region. A solid-state imaging device comprising: a solid-state imaging device having a high-concentration buried layer that accumulates electric charges; storing the photo-generated electric charges in the high-concentration buried layer; The gate electrode of the insulated gate field effect transistor has a ring shape, the source region is provided inside an inner peripheral portion of the gate electrode, and the drain region is provided outside an outer peripheral portion of the gate electrode. A solid-state imaging device, wherein the unit pixel is surrounded by an element isolation region in which a diffusion isolation region having the same conductivity type as the drain region is formed as a series. 2. The semiconductor device according to claim 1, wherein the diffusion isolation region has the same conductivity type as the drain region, and is formed by connecting a conductivity type impurity region deeper than the well region to the drain region. The solid-state imaging device according to claim 1. 3. The solid-state imaging device according to claim 1, wherein a planar shape of an outer peripheral portion of the gate electrode is a polygonal shape having four or more sides or a circular shape. 4. The light receiving diode according to claim 1, wherein said light receiving diode is provided adjacent to at least one side of a polygon of said gate electrode or adjacent to a part of a circular circumference. The solid-state imaging device according to any one of the above. 5. The solid-state imaging device according to claim 1, wherein a plurality of the unit pixels are arranged in rows and columns. 6. The device according to claim 5, wherein a direction from the gate electrode to the light receiving diode in the unit pixel is oblique to or parallel to the row direction or the column direction. The solid-state imaging device according to claim 1. 7. The gate electrodes of the insulated gate field effect transistors in the same row are connected to each other,
7. The solid-state imaging device according to claim 5, wherein the source regions of the insulated gate field effect transistors in the same column are connected to each other. 8. The solid-state imaging device according to claim 1, wherein a gate electrode of the insulated gate field effect transistor and its periphery are shielded from light. 9. The vicinity of the source region where the high-concentration buried layer is formed is a partial region in the channel length direction from the drain region to the source region and is close to the source region. The solid-state imaging device according to claim 1. 10. The high-concentration buried layer is formed over the entire region in the channel width direction.
10. The solid-state imaging device according to any one of claims 9 to 9. 11. The solid-state imaging device according to claim 1, wherein the first and second vertical scanning signals are supplied to a first gate electrode and a second gate electrode of the insulated gate field effect transistor for detecting an optical signal, respectively. A signal driving scanning circuit; a drain voltage driving scanning circuit for supplying a drain voltage to a drain region of the insulated gate field effect transistor; and a horizontal scanning signal input scanning for supplying a horizontal scanning signal for controlling a timing of outputting the optical signal. The solid-state imaging device according to claim 1, further comprising: a circuit; and a video signal output terminal that outputs the optical signal.