JP3313683B2 - Solid-state imaging device and solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device and a solid-state image pickup device, and more particularly to a threshold voltage modulation type MOS image sensor used for a video camera, an electronic camera, an image input camera, a scanner or a facsimile. The present invention relates to a solid-state imaging device and a solid-state imaging device using the same.

[0002]

2. Description of the Related Art Semiconductor image sensors such as CCD type image sensors and MOS type image sensors are excellent in mass productivity, and have been applied to most image input device devices with the development of finer pattern technology. In particular,
In recent years, the power consumption is smaller than that of a CCD image sensor, and the sensor element and the peripheral circuit element are the same CMOS.
With the advantage that it can be created by technology, MOS
Type image sensors are being reviewed.

In view of such trends in the world, the present applicant has improved a MOS type image sensor, and has applied for a patent application for a sensor element having a carrier pocket (high-concentration buried layer) below a channel region (Japanese Patent Application No. Hei 10 (1998) -108). 186453
To obtain a patent (registration number 2935492). In this MOS image sensor, an optical signal is displayed as an image by repeating a series of processes of an initialization period, an accumulation period, a readout period, an initialization period, and so on.

[0004]

By the way, the above MOS
There is room for improvement in the following problems in the type image sensor. That is, the light-generated carriers generated in the light-receiving diode portion are not accumulated in the carrier pocket at one time during the accumulation period and remain there. After the accumulation period, the light-emitting carriers move from the light-receiving diode portion gradually toward the carrier pocket and accumulate in the carrier pocket. Will be done. This is observed on the screen as a so-called afterimage.

Further, when a very small amount of light is incident on the light-receiving diode portion, the photo-generated carriers generated in the light-receiving diode portion are not sent to the carrier pocket during the accumulation period but remain in the light-receiving diode portion, and the MOS transistor Does not change. This is observed on the screen as so-called black crush. The present invention has been made in view of the problems of the related art, and provides a solid-state imaging device and a solid-state imaging device capable of preventing so-called afterimages and blackouts.

[0006]

In order to solve the above-mentioned problems, the present invention relates to a solid-state image pickup device, and as a basic configuration thereof, as shown in FIG. Insulated gate field effect transistor (MOS transistor) 1 for detecting an optical signal
12 and a light receiving diode 111 and an insulated gate field effect transistor (M
The OS transistor (112) is formed in the first well region 15a and the second well region 15b, respectively, and the photo-generated electric charge is stored in the second well region 15b around the source region of the MOS transistor 112 for optical signal detection. It has a high concentration buried layer (carrier pocket) 25 for accumulation.

Then, the first well region 1 of the opposite conductivity type is formed.
It is characterized in that the 5a and the second well region 15b are connected as follows. That is, a connection region having a high impurity concentration is formed between these regions, or their ends overlap each other, and the overlap region is a connection region. For this reason, as shown in FIG. 5B, in the connection region, the potential for electrons or holes to be accumulated in the carrier pockets of the photo-generated carriers in order to change the threshold voltage of the optical signal detection MOS transistor. Can be lowered.

By lowering this potential, the first well region 15a to the second well region 15b of the photogenerated carriers to be accumulated in the carrier pocket in order to change the threshold voltage of the MOS transistor for detecting an optical signal.
To the carrier pocket 25 in the second well region 15b.

As a result, it is possible to suppress image degradation such as afterimages and blackouts caused by the photogenerated carriers remaining in the light receiving diode portion beyond the accumulation period.
When the first and second well regions and the like are of the opposite conductivity type, that is, when the high concentration buried layer is n-type, the high concentration buried layer becomes an electron pocket and accumulates photogenerated electrons. become. In the initialization period and the accumulation period, the first well region 15a and the second well region 15b
In the overlapping region between the end portions of the photo-generated carriers, the potential for electrons or holes to be accumulated in the carrier pocket in order to change the threshold voltage of the photo-signal detection MOS transistor can be reduced.

[0010] By lowering the potential, the movement of the photo-generated carriers to be accumulated in the carrier pocket from the first well region 15a to the second well region 15b is further promoted, and the photo-generated carriers are transferred to the second well region. It becomes easier to move toward the carrier pocket 25 in the region 15b.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing an element layout in a unit pixel of a MOS image sensor according to an embodiment of the present invention. FIG.
As shown in FIG.
11 and an optical signal detection MOS transistor 112 are provided adjacent to each other. As the MOS transistor 112, an n-channel MOS (nMOS) having a low concentration drain structure (LDD structure) is used.

The light receiving diode 111 and the MOS transistor 112 are formed in different well regions, that is, a first well region 15a and a second well region 15b, and the well regions 15a and 15b are connected to each other. The first well region 15a in the portion of the light receiving diode 111 forms a part of a charge generation region by light irradiation. The second well region 15b in the portion of the MOS transistor 112 forms a gate region in which the threshold voltage of the channel can be changed by the potential applied to this region 15b.

The MOS transistor 112 has a lightly doped drain (LDD) structure. The low-concentration drain region 17a extends to form the impurity region 17 of the light-receiving diode 111 having substantially the same impurity concentration as the low-concentration drain region 17a. That is, the impurity region 17
And the low-concentration drain region 17a are connected to each other by a first
And the second well regions 15a and 15b are formed integrally with each other so that most of the region covers the surface layer. Further, a high-concentration drain region 17b as a contact layer is formed around the outer periphery of the impurity region 17 and the low-concentration drain region 17a so as to connect to the low-concentration drain region 17a while avoiding the light receiving portion.

The drain regions 17a and 17b are formed so as to surround the outer periphery of the ring-shaped gate electrode 19, and the source regions 16a and 16b are formed so as to be surrounded by the inner periphery of the ring-shaped gate electrode 19. Furthermore, this M
The carrier pocket (high-concentration buried layer) 25 which is a feature of the OS type image sensor is provided in the second well region 15b below the gate electrode 19, and in the peripheral portion of the source region 16a, the source regions 16a and 16b are formed. It is formed so as to surround it. The drain regions 17a and 17b are connected to a drain voltage (VDD) supply line 22 through a low-resistance contact layer 17b, and the gate electrode 19 is connected to a vertical scanning signal (VS).
CAN) supply line 21 and the source regions 16a, 1
6b is connected to the vertical output line 20 through the low resistance contact layer 16b.

The light receiving window 24 of the light receiving diode 111
The other area is shielded from light by the metal layer (light shielding film) 23. In the element operation for detecting an optical signal in the MOS image sensor described above, a sweep period (initialization), an accumulation period, a readout period, a sweeping period (initialization), and so on. A series of processes of (initialization) -accumulation period-readout period is repeated.

In the sweep period (initialization), before accumulating the photo-generated charges (photo-generated carriers), the photo-generated charges remaining after reading out, the acceptors and donors are neutralized, or the surface state is changed. The residual charge before reading the optical signal, such as holes and electrons, trapped in the semiconductor is discharged from the semiconductor,
Empty the carrier pocket 25. Source region 16a,
16b, drain regions 17a and 17b, and gate electrode 19
, A positive high voltage of about +5 V or more, usually about 7 to 8 V is applied.

In the accumulation period, carriers are generated by light irradiation, and holes of the carriers are converted into the first and second carriers.
Are moved in the well regions 15a and 15b to accumulate in the carrier pocket 25. Drain regions 17a, 17b
A positive voltage of approximately +2 to 3 V is applied to the gate electrode 19 and a low positive or negative voltage that keeps the MOS transistor 112 in a cut-off state is applied to the gate electrode 19.

In the read period, a change in the threshold voltage of the MOS transistor 112 due to the photo-generated charges stored in the carrier pocket 25 is read as a change in the source potential. M
In order for the OS transistor 112 to operate in a saturated state,
A positive voltage of approximately +2 to 3 V is applied to the drain regions 17a and 17b, and approximately +2 to 3 V is applied to the gate electrode 19.
A positive voltage of V is applied.

Next, the device structure of the MOS type image sensor according to the embodiment of the present invention will be described with reference to sectional views. FIG. 2A is a cross-sectional view corresponding to a cross-sectional view taken along line AA of FIG. 1 and illustrating a device structure of the MOS image sensor according to the embodiment of the present invention. FIG.
(B) is a diagram showing a state of a potential along the surface of the semiconductor substrate.

FIG. 3 is a sectional view taken along line BB of FIG. 1, and FIG. 4 is a sectional view taken along line CC of FIG. FIG.
(A) shows the first well region 15a and the second well region 1
FIG. 5B is a detailed cross-sectional view showing the vicinity of the overlapping region 5b, and FIG. 5B is a graph showing a potential distribution near the overlapping region.

As shown in FIG. 2A, an impurity concentration of 1 ×
An epitaxial layer (third semiconductor layer) 31 is formed by epitaxially growing p-type silicon with an impurity concentration of about 1 × 10 ¹⁵ cm ⁻³ on a substrate 11 made of p-type silicon of 10 ¹⁸ cm ⁻³ or more. The light receiving diode 111 and the optical signal detecting MOS transistor 1 are provided on the epitaxial layer 31.
12 are formed. The light receiving diode 111 and the optical signal detecting MOS transistor 112 are respectively connected to the first well region 15a and the second well region 15a.
Are formed in the well regions 15a and 15b. FIG.
As shown in (a), the first well region 15a and the second well region 15b are formed such that their ends overlap, and are connected to each other. In the overlapping region, a high concentration, that is, a total of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ^{−3 is used.}
About a p-type impurity is introduced. With such a structure, the potential of the overlapping region can be reduced as shown by the solid line in FIG. The width of the overlapping region is at least 0.3 μm
is necessary. When the width of the overlapping area is small, FIG.
As shown by the dotted line, a potential peak occurs at the boundary.

The epitaxial layer 31 between adjacent unit pixels 101 is separated so that each unit pixel 101 is separated.
A field insulating film (element isolation insulating film) 14 is formed on the surface. Further, the n-type well layer (one conductivity type region) 12 is formed below the field insulating film 14 and above the substrate 11 so as to include the entire interface between the epitaxial layer 31 and the field insulating film 14 and to separate the n-type well layer (one conductivity type region) 12. Is formed.

Next, the details of the light receiving diode 111 will be described with reference to FIGS. The light receiving diode 111 includes an n-type buried layer (one conductivity type buried layer) 3 embedded in the epitaxial layer 31 and in contact with the substrate 11.
2, a low-concentration n-type well layer (one conductivity type region) 12 formed on the n-type buried layer 32, and a p-type first well region 15a formed on the surface of the n-type well layer 12. And an n-type impurity region 17 extending from the surface layer of the first well region 15a to the surface layer of the n-type well layer 12. p
The substrate 11 of the mold forms a first semiconductor layer of the opposite conductivity type to the light receiving diode 111 portion. The n-type buried layer 32 and the low-concentration n-type well layer 12 formed thereon form a second semiconductor layer of the same conductivity type.

The impurity region 17 has a low concentration drain (LD
D) Optical signal detecting MOS transistor 11 having structure
2 is formed to extend from the low-concentration drain region 17a, and has substantially the same impurity concentration as the low-concentration drain region 17a. Since the impurity concentration of the impurity region 17 is low, a shallower impurity region 17 is formed. Therefore, blue light having a short wavelength and rapidly attenuating near the surface can be received with sufficient intensity.

In the storage period described above, the impurity region 17 is connected to the drain voltage supply line 22 and is biased to a positive potential. At this time, the depletion layer extends from the boundary between the impurity region 17 and the first well region 15a to the entire first well region 15a and reaches the n-type well layer 12. On the other hand, a depletion layer extends from the interface between the substrate 11 and the n-type buried layer 32 to the n-type buried layer 32 and the n-type well layer 12 thereon.
It spreads over the whole and reaches the first well region 15a.

The first well region 15a and the n-type layer 12 /
In No. 32, the potential distribution is such that the potential gradually decreases from the substrate 11 side to the surface side.
The holes generated by light in the well region 15a and the n-type layer 12/32 do not flow out to the substrate 11 side but stay in these regions 15a and the n-type layer 12/32. These regions 15a and n-type layers 12/32 are MO
Since the holes are connected to the gate region 15b of the S transistor 112, these holes generated by light can be effectively used as charges for threshold voltage modulation of the MOS transistor 112. In other words, the first well region 1
5a and the entire n-type layer 12/32 become a carrier generation region by light.

As described above, the presence of the n-type buried layer 32 increases the total thickness of the carrier generation region of the light receiving diode 111. Thus, when light is applied to the light receiving diode 111, the carrier generation region becomes a light receiving portion having high sensitivity to light having a long wavelength reaching deep inside the light receiving portion, such as red light. Further, the light receiving diode 111
Is that a light-generating region is arranged below the impurity region 17 in that
Numeral 1 has an embedded structure for holes generated by light. Accordingly, noise can be reduced without being affected by the surface of the semiconductor layer having many trap levels.

Next, the optical signal detecting MOS transistor 1
Details of 12 will be described with reference to FIGS. The portion of the MOS transistor 112 is p
Substrate 11, a p-type epitaxial layer 31 formed on the substrate 11, a p-type buried layer (buried layer of the opposite conductivity type) 33 and a p-type buried layer 33 formed in the epitaxial layer 31. An n-type well layer 12 immediately above the type buried layer 33;
And a p-type second well region 15b formed in the mold well layer 12. The p-type substrate 11 and the epitaxial layer 31 including the p-type buried layer 33 form a first semiconductor layer of the opposite conductivity type to the MOS transistor 112, and
The type well layer 12 also forms a second semiconductor layer of one conductivity type, and the epitaxial layer 31 including the p-type buried layer 33 forms a third semiconductor layer.

This MOS transistor 112 has a structure in which an outer periphery of a ring-shaped gate electrode 19 is surrounded by an n-type low-concentration drain region 17a. The n-type low concentration drain region 17 a is formed integrally with the n-type impurity region 17. The outer peripheral portion of the impurity region 17 extending from the low concentration drain region 17a is
And a high-concentration drain region 17b extending to the element isolation region 13 and the element isolation insulating film 14 is formed. The high concentration drain region 17b becomes a contact layer for the drain electrode 22. As shown in FIG. 2A, the drain electrode 22 includes the element isolation region 13 and the element isolation insulating film 14.
Is connected to the high-concentration drain region 17b.

Further, n-type source regions 16a and 16b are formed so as to be surrounded by a ring-shaped gate electrode 19. The source regions 16a and 16b have a high concentration at the center and a low concentration at the periphery. The source electrode 20 is connected to a high-concentration source region 16b as a contact layer. The gate electrode 19 is formed on the second well region 15b between the drain region 17a and the source region 16a via the gate insulating film 18.
The surface layer of the second well region 15b below the gate electrode 19 becomes a channel region. Furthermore, at normal operating voltage,
In order to maintain the channel region in an inversion state or a depletion state, an appropriate concentration of n-type impurity is introduced into the channel region to form a channel dope layer 15c.

In the second well region 15b below the channel region, a part of the region in the channel length direction, that is, a peripheral portion of the source regions 16a and 16b, so as to surround the source regions 16a and 16b. , P + -type carrier pockets (high-concentration buried layer) 25 are formed. The p + type carrier pocket 25 can be formed by, for example, an ion implantation method. The carrier pocket 25 is formed in the second well region 15 below the channel region formed on the surface.
b. It is desirable that the carrier pocket 25 be formed so as not to cover the channel region.

In the above p + -type carrier pocket 25, the potential of the photo-generated charges with respect to the photo-generated holes becomes lower. When a voltage higher than the gate voltage is applied to the drain regions 17a and 17b, the photo-generated holes are removed. It can be collected in the carrier pocket 25. FIG.
FIG. 5B shows a potential diagram in a state where light generation holes are accumulated in the carrier pocket 25 and electrons are induced in the channel region to generate an inversion region. The threshold voltage of the MOS transistor 112 changes due to the accumulated charge.
Therefore, the detection of the optical signal can be performed by detecting the change in the threshold voltage.

By the way, during the above-described carrier sweeping period, a high voltage is applied to the gate electrode 19, and the electric field generated thereby sweeps out the carriers remaining in the second well region 15b to the substrate 11 side. in this case,
The applied voltage causes the depletion layer to spread from the boundary between the channel dope layer 15c in the channel region and the second well region 15b to the second well region 15b, and the p-type buried layer 33 and the n-type well layer 12 Depletion layer from the interface with
To the n-type well layer 12 below the well region 15b.

Therefore, the range of the electric field by the voltage applied to the gate electrode 19 mainly depends on the second well region 15.
b and n-type well layer 12 under second well region 15b
Over. In this case, n under the second well region 15b
A high-concentration p-type buried layer 33 is formed adjacent to the n-type well layer 12 on the substrate 11 side with a small thickness. In the sweeping period, the p-type buried layer 33 suppresses the spread of the depletion layer extending from the interface between the p-type buried layer 33 and the n-type well layer 12. The spreading depletion layer becomes thinner.

That is, the voltage from the gate electrode 19 is mainly applied to the second well region 15b. In other words, since a strong electric field that causes a sudden potential change in the second well region 15b and sweeps holes toward the substrate 11 is mainly applied to the second well region 15b, the carrier pocket 25 and the second well region Carriers accumulated in 15b can be more reliably swept out therefrom with a low reset voltage, thereby improving reset efficiency.

In the MOS image sensor according to the above embodiment, the lower surface of the element isolation insulating film 14 is included on the p-type substrate 11 below the element isolation insulating film 14 and the n-type well layer 12 is isolated. Thus, a p-type element isolation region 13 is formed. That is, defects generated at the interface between the element isolation insulating film 14 and the element isolation region 13 are surrounded by the element isolation region 13.

Therefore, when a positive voltage is applied to the n-type drain regions 17a and 17b during the initialization period and the accumulation period, the p-type well regions 15a and 15b
Since the depletion layer extending from the mold substrate 11 only reaches the outer peripheral portion of the element isolation region 13 and does not spread inside the element isolation region 13, the defect generated at the interface is not covered by the depletion layer. . Therefore, it is possible to prevent the charge trapped in the defect from being released into the depletion layer, thereby suppressing fixed pattern noise caused by accumulation of the charge in the hole pocket 25 due to the defect. .

Further, as shown in FIG. 2A, a drain electrode 22 is provided near the element isolation insulating film 14 and the element isolation region 13. In this case, when a positive voltage is applied to the n-type drain regions 17a and 17b in the initialization period and the accumulation period, the n-type well layer 12 is depleted from the p-type well regions 15a and 15b or the p-type substrate 11 into the n-type well layer 12. The layer spreads, resulting in a potential distribution as shown in FIG. That is, the drain electrode 22 has the highest potential, and the substrate 11 and the element isolation region 13 connected to the substrate 11 have the lowest potential. Thereby, even if the element isolation insulating film 1
In the vicinity of the substrate 4, even if a defect occurs due to thermal distortion or the like due to selective oxidation and the charge trapped by the defect is released, the substrate 1 is immediately discharged.
It flows to one side, and hardly flows to the well regions 15a and 15b, and thus to the hole pocket 25.

As a result, defects generated at the interface between the element isolation region 13 and the element isolation insulating film 14 and the element isolation insulating film 1
The fixed pattern noise due to the accumulation of charges in the hole pockets 25 due to defects caused by thermal distortion or the like in the vicinity of 4 can be further suppressed. Next, a method of manufacturing the MOS image sensor will be described with reference to FIGS. In this description, in particular, the first well region 1
A description will be given centering on a step of forming an overlapping region of 5a and the second well region 15b.

FIG. 6A shows the n-type buried layer 32 of the light-receiving diode 111 and the p-type first well region 1 thereabove.
It is sectional drawing which shows the state after forming 5a. In the figure, reference numeral 11 denotes a p-type substrate, and 31 denotes an epitaxial layer formed on the substrate 11. The first well region 15a is formed on the surface of the epitaxial layer 31. The n-type buried layer 32 is formed in the epitaxial layer 31 under the first well region 15a and separated from the first well region 15a. Reference numeral 51 denotes a gate insulating film formed on the surface of the epitaxial layer 31, and reference numeral 52 denotes a resist mask having an opening 52a for ion implantation used for forming the n-type buried layer 32 and the first well region 15a. .

Next, after removing the resist mask 52,
As shown in FIG. 6B, a new resist mask 53 having an opening 53a is formed over the entire formation region of the unit pixel. N-type impurities are ion-implanted through the opening 53a,
The n-type well layer 12 is formed so as to be in contact with the n-type buried layer 32 and to include the first well region 15a. Next, after removing the resist mask 53, as shown in FIG.
A new resist mask 54 having an opening 54a in the OS transistor 112 is formed. In this case, the opening 5
4a is formed such that the opening end overlaps the end of the first well region 15a. Opening 5 of resist mask 52
The overlap width between 2a and the end of the opening 54a of the resist mask 54 is set to be at least 0.3 μm.

Subsequently, the p-type impurity is passed through the opening 54a.
Is deeply implanted into the epitaxial layer 31 to form a p-type
The embedded layer 33 is formed. No p-type through the same opening 54a
A pure substance is shallowly ion-implanted, and p
A second well region 15b of the mold is formed. Furthermore, the same
Ion injection of n-type impurity very shallow through opening 54a
And channel doping is performed on the surface of the second well region 15b.
The layer 15c is formed. At this time, the second well region 15
b and the end of the first well region 15a overlap each other.
And the p-type impurity concentration in the overlap region is 1 × 10¹⁶~
1 × 10¹⁷/ Cm ^-3About p-type impurities are introduced
You. Due to such a structure, the solid line in FIG.
Like the potential shown, the potential of the overlap region
Can be reduced. The width of the overlap area is small.
At least 0.3 μm is required.

Next, as shown in FIG. 7A, an opening 5 is formed in a rectangular annular region where a carrier pocket 25 is to be formed.
A resist mask 55 having 5a is formed. continue,
A p-type impurity is ion-implanted through the opening 55a to form a rectangular annular carrier pocket 25 in the second well region 15b immediately below the channel dope layer 15c. Next, as shown in FIG. 7B, a square annular gate electrode 19 is formed on the gate insulating film 18 so as to cover the square annular carrier pocket 25. At this time, the carrier pocket 25 is arranged below the gate electrode 19 from the inside.

Subsequently, n is set using the gate electrode 19 as a mask.
A type impurity is ion-implanted to form a lightly doped drain region and a lightly doped source region. Subsequently, after an insulating film covering the gate electrode 19 is formed, the insulating film is anisotropically etched to form a sidewall on the side wall of the gate electrode 19. Next, after forming a resist mask 56 covering the light-receiving diode 111, n-type impurities are ion-implanted using the gate electrode 19 and the sidewall as a mask, and a high-concentration drain region serving as a contact layer to the drain region and the source region is formed. And a high concentration source region is formed. As a result, a MOS transistor 112 having a low concentration drain (LDD) structure is formed.

Thereafter, through a predetermined process, a MOS image sensor as shown in FIG. 2A is completed. next,
With reference to FIG. 9, the overall configuration of a MOS image sensor using the unit pixels having the above structure will be described. FIG.
1 shows a circuit configuration diagram of a MOS image sensor according to an embodiment of the present invention.

As shown in FIG. 9, the MOS image sensor has a two-dimensional array sensor configuration, and the unit pixels having the above-described structure are arranged in a matrix in the column direction and the row direction. Also, a vertical scanning signal (VSCAN)
And a drive scanning circuit 103 for drain voltage (VDD) are disposed on the left and right sides of the pixel region. The vertical scanning signal supply lines 21a and 21b are provided one by one from the driving scanning circuit 102 of the vertical scanning signal (VSCAN) for each row. Each vertical scanning signal supply line 21a, 21
b is connected to the gates of the MOS transistors 112 in all the unit pixels 101 arranged in the row direction.

The drain voltage supply lines (VDD supply lines) 22a and 22b are provided one by one from the drive scanning circuit 103 of the drain voltage (VDD) for each row. The drain voltage supply lines (VDD supply lines) 22a and 22b are connected to the drains of the optical signal detection MOS transistors 112 in all the unit pixels 101 arranged in the row direction. Also,
Different vertical output lines 20a and 20b are provided for each column,
Each of the vertical output lines 20a and 20b is connected to the source of the MOS transistor 112 in each of the unit pixels 101 arranged in the column direction.

Further, M as a switch different for each column
OS transistors 105a and 105b are provided, and each of the vertical output lines 20a and 20b is connected to one of drains (light detection signal input terminals) 28a and 29a of each of the MOS transistors 105a and 105b. Gates (horizontal scanning signal input terminals) 28b and 29b of the switches 105a and 105b are connected to a driving scanning circuit 104 for horizontal scanning signals (HSCAN).

The sources (light detection signal output terminals) 28c and 29c of the switches 105a and 105b are connected to a video signal output terminal 1 through a common constant current source (load circuit) 106.
07. That is, M in each unit pixel 101
The source of the OS transistor 112 is connected to the constant current source 106 to form a source follower circuit for each pixel. Therefore, the potential difference between the gate and the source and the potential difference between the bulk and the source of each MOS transistor 112 are determined by the connected constant current source 106.

The vertical scanning signal (VSCAN) and the horizontal scanning signal (HSCAN) are used to sequentially turn on the MOS of each unit pixel.
By driving the transistor 112, a video signal (Vout) proportional to the amount of incident light is read out. FIG. 10 shows a timing chart of each input / output signal for operating the MOS image sensor according to the present invention. This is applied to the case where the p-type first and second well regions 15a and 15b are used and the optical signal detection transistor 112 is an nMOS.

Next, the light detection operation of a series of solid-state imaging devices will be briefly described with reference to FIGS.
As described above, the light detection operation is performed during the sweep period (initialization)-
A series of processes consisting of an accumulation period and a readout period is repeated. First, the carrier pocket 25 is initialized by the initialization operation.
The charge remaining in the first and second well regions 15a and 15b is discharged. That is, a high positive voltage of approximately 7 to 8 V is applied to the drain of the optical signal detection MOS transistor 112 through the VDD supply lines 22a and 22b and to the gate through the VSCAN supply lines 21a and 21b, respectively.

At this time, the thickness of the n-type well layer 12 under the second well region 15b is small, and
Since the high-concentration p-type buried layer 33 is in contact with the substrate 11 side, the voltage applied to the gate electrode 19 is applied only to the second well region 15b and a region very close to the second well region 15b. In other words, a strong electric field that sweeps holes toward the substrate 11 due to a sudden potential change in the second well region 15b is mainly applied to the second well region 15b, so that carriers can be more reliably swept with a low reset voltage. Therefore, the reset efficiency can be improved.

Next, a low gate voltage is applied to the gate electrode 19 of the MOS transistor 112 for detecting an optical signal, and a voltage (VDD) of about 2 to 3 V required for the operation of the transistor is applied to the drain regions 17a and 17b. At this time,
The first well region 15a, the n-type well layer 12 and the n-type buried layer 32 are depleted, and the second well region 15a
b is depleted. Then, the drain regions 17a, 17b
, An electric field is generated toward the source regions 16a and 16b.

Next, the light receiving diode 111 is irradiated with light. At this time, since the carrier generation region of the portion of the light receiving diode 111 is formed near the surface, the wavelength is short, such as blue light, and the sensitivity to light that is easily attenuated near the surface is improved. Since the total thickness is increased, the sensitivity is improved even for light having a long wavelength reaching deep inside the light receiving portion, such as red light. Therefore, electron-hole pairs (photo-generated charges) can be efficiently generated. In the overlap region 40 of the first well region 15a and the second well region 15b, a high concentration of p-type impurity is introduced to lower the potential.
Therefore, the light generation holes can easily move from the first well region 15a to the second well region 15b.

As described above, the light-generating holes are injected into the gate region of the MOS transistor 112 for light signal detection and are accumulated in the carrier pocket 25. Thus, the width of the depletion layer extending from the channel region to the gate region 15b thereunder is limited, and the source region 16
The potentials near a and 16b are modulated, and the threshold voltage of the MOS transistor 112 changes.

In the above initialization period and accumulation period, n
When a positive voltage is applied to the drain regions 17a and 17b, the interface between the element isolation insulating film 14 and the semiconductor layer is covered by the element isolation region 13, so that the interface becomes a depletion layer extending from the well region. Therefore, the charge trapped by the defect at the interface can be prevented from being released into the depletion layer. Thereby, fixed pattern noise due to accumulation of charges in the hole pocket 25 due to defects can be suppressed.

Further, n-type drain regions 17a and 17
When a positive voltage is applied to the drain electrode 22b, the drain electrode 22 is connected near the element isolation insulating film 14, so that even if the charge is released from a defect near the element isolation insulating film 14, the charge remains in the hole. The flow toward the pocket 25 can be suppressed. As a result, fixed pattern noise caused by accumulation of charges in the hole pockets 25 due to defects can be further suppressed.

Next, a gate voltage of about 2 to 3 V at which the MOS transistor 112 can operate in a saturated state is applied to the gate electrode 19, and a voltage VDD of about 2 to 3 V at which the MOS transistor 112 can operate at the drain regions 17a and 17b.
Is applied. As a result, a low electric field inversion region is formed in a part of the channel region above the carrier pocket 25, and a high electric field region is formed in the remaining part. At this time, MOS
The drain voltage-current characteristics of the transistor 112 are shown in FIG.
As shown in FIG.

Further, a constant current source 106 is connected to the source regions 16a and 16b of the MOS transistor 112 so that a constant current flows. Thereby, the MOS transistor 112
Forms a source follower circuit, so that the source potential changes following the fluctuation of the threshold voltage of the MOS transistor 112 due to the light-generating holes, resulting in a change in the output voltage.

In this way, a video signal (Vout) proportional to the amount of light irradiation can be obtained. As described above, according to the embodiment of the present invention, in the overlapping region between the first well region 15a and the second well region 15b,
Since the potential is lowered by introducing a high concentration of p-type impurities, the light-generating holes can easily move from the first well region 15a to the second well region 15b. Thereby, afterimages and underexposure can be suppressed.

In the initialization period and the accumulation period,
It is possible to further suppress fixed pattern noise due to accumulation of charges in the hole pockets 25 due to defects generated at the interface between the element isolation insulating film 14 and the element isolation region 13. Furthermore, an ideal photoelectric conversion mechanism that does not interact with a noise source in a semiconductor surface or a channel region when a light generation hole moves in a series of processes of a sweep operation (initialization), an accumulation operation, and a read operation. Can be realized.

Further, due to the charge accumulation in the carrier pocket 25, as shown in FIG.
Can be operated in a saturated state, and since a source follower circuit is formed, a change in threshold voltage due to photo-generated charges can be detected as a change in source potential. Therefore, photoelectric conversion with good linearity can be performed.

Next, another embodiment of the present invention will be described below with reference to FIG. FIG. 11 is a cross-sectional view showing a state near a connection region between a first well region and a second well region of a solid-state imaging device according to another embodiment of the present invention. The difference from the above-described embodiment shown in FIG. 5A is that the p-type first well region 15a and the p-type second well region 15b are first provided separately from each other, and the first well region 15a and the second well region 15b are connected by a p-type high-concentration region 15d (connection region 40). The impurity concentration of the connection region 40 is higher than the impurity concentration of the first well region 15a and the second well region 15b. A range of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ^-3 is desirable.

This connection region 40 is formed in the first well region 1
It can be formed by ion implantation or the like before or after forming the 5a or the second well region 15b. According to this other embodiment, similar to the above embodiment shown in FIG.
In the connection region 40, the potential for electrons or holes to be accumulated in the carrier pocket in order to change the threshold voltage of the optical signal detection MOS transistor among the photo-generated carriers can be reduced.

By lowering the potential, the first of the carriers to be accumulated in the carrier pocket in order to change the threshold voltage of the MOS transistor for detecting an optical signal.
The movement from the well region 15a to the second well region 15b is further promoted, and the carrier is
It becomes easy to move to the carrier pocket 25 in 5b.

As a result, it is possible to suppress image degradation such as afterimages and blackouts caused by the photogenerated carriers remaining in the light receiving diode 111 over the accumulation period. As described above, the present invention has been described in detail with reference to the embodiments. However, the scope of the present invention is not limited to the examples specifically shown in the embodiments, and the scope of the present invention is not limited to the scope of the present invention. Modifications of the embodiment are included in the scope of the present invention.

For example, the impurity concentration of the overlap region which is the connection region 40 between the first well region 15a and the second well region 15b, or the connection between the first well region 15a and the second well region 15b The impurity concentration of the high concentration region 15d, which is the region 40 to be changed, is set to 1 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm.
^-3, but not limited to this. The impurity concentration is higher than the impurity concentrations of the first well region 15a and the second well region 15b, and the drain voltage or the gate voltage applied during the initialization period and the accumulation period causes p.
The impurity concentration may be such that the entire region of the well regions 15a, 15b, and 15d of the mold is depleted.

Although the p-type substrate 11 is used, an n-type substrate may be used instead. In this case, in order to obtain the same effect as in the above embodiment, the conductivity type of each layer and each region described in the above embodiment and the like may be all reversed. In this case, carriers to be accumulated in the carrier pocket 25 are electrons out of electrons and holes.

[0069]

As described above, according to the present invention, there is provided a unit pixel including a light receiving diode and an insulated gate field effect transistor (MOS transistor) adjacent to the light receiving diode for detecting an optical signal. And an insulated gate field effect transistor (MOS transistor) for detecting an optical signal are formed in a first well region and a second well region, respectively, and a second portion around a source region of the MOS transistor for detecting an optical signal is formed. The well region has a high concentration buried layer (carrier pocket) for accumulating photo-generated charges. And a first well region of the opposite conductivity type and a second well region.
A connection region having a high impurity concentration for connecting these regions is formed between these well regions, or their end portions are overlapped with each other, and the overlap region is a connection region.

Therefore, in the connection region, the potential for electrons or holes to be accumulated in the carrier pocket in order to change the threshold voltage of the photo-signal detection MOS transistor among the photo-generated carriers can be reduced. For this reason, the movement of the photo-generated carriers from the first well region to the second well region is further promoted, and the photo-generated carriers are more likely to move toward the carrier pocket in the second well region. Accordingly, it is possible to suppress image degradation such as an afterimage and blackout caused by the photogenerated carriers remaining in the light receiving diode portion beyond the accumulation period.

[Brief description of the drawings]

FIG. 1 is a plan view showing an element layout in a unit pixel of a solid-state imaging device according to an embodiment of the present invention.

FIG. 2A is a cross-sectional view taken along the line AA of FIG. 1, showing a structure of a device in a unit pixel of the solid-state imaging device according to the embodiment of the present invention. (B) is a diagram showing a state of potential in a state where light generation holes are accumulated in a carrier pocket and electrons are induced in a channel region to generate an inversion region.

FIG. 3 is a cross-sectional view taken along the line BB of FIG. 1, showing a structure of a light-receiving diode in a unit pixel of the solid-state imaging device according to the embodiment of the present invention;

FIG. 4 is a cross-sectional view taken along the line CC of FIG. 1, showing a structure of an optical signal detecting MOS transistor in a unit pixel of the solid-state imaging device according to the embodiment of the present invention;

FIG. 5A is a cross-sectional view illustrating a state near a connection region between a first well region and a second well region of the solid-state imaging device according to the embodiment of the present invention. (B) is a diagram showing the state of the potential along the line FF in the vicinity of the connection region.

FIG. 6 is a cross-sectional view (part 1) illustrating a method for manufacturing a solid-state imaging device according to an embodiment of the present invention.

FIG. 7 is a sectional view (part 2) illustrating the method for manufacturing the solid-state imaging device according to the embodiment of the present invention.

FIG. 8 is a graph showing a drain current-voltage characteristic of an optical signal detection MOS transistor of the solid-state imaging device according to the embodiment of the present invention.

FIG. 9 is a diagram showing an overall circuit configuration of the solid-state imaging device according to the embodiment of the present invention.

FIG. 10 is a timing chart when the solid-state imaging device of FIG. 9 is operated.

FIG. 11 is a cross-sectional view showing a state near a connection region between a first well region and a second well region of a solid-state imaging device according to another embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 11 substrate (first semiconductor layer) 12 n-type well layer (one conductivity type region, second semiconductor layer) 12a epitaxial layer (one conductivity type region, second semiconductor layer) 13 element isolation region 14 element isolation insulating film Reference Signs List 15a First well region 15b Second well region 15c Channel doped layer 15d High concentration region 16a Low concentration source region 16b High concentration source region (contact layer) 17 Impurity region 17a Low concentration drain region 17b High concentration drain Region (contact layer) 18 Gate insulating film 19 Gate electrode 25 Carrier pocket (high concentration buried layer) 31 Epitaxial layer (third semiconductor layer) 32 n-type buried layer (buried layer of one conductivity type, second Semiconductor layer) 33 p-type buried layer (buried layer of opposite conductivity type, third semiconductor layer) 40 connection region 101 unit pixel 106 constant current source Load circuit) 107 video signal output terminal 111 receiving diode 112 for optical signal detection insulated gate field effect transistor (detection optical signal MOS transistor)

Claims (17)

(57) [Claims] 1. A solid-state imaging device having a unit pixel including a light receiving diode and an insulated gate field effect transistor for detecting an optical signal adjacent to the light receiving diode, wherein the light receiving diode part is a one conductivity type region. A first well region of the opposite conductivity type formed in the one conductivity type region, and an impurity region of one conductivity type formed in a surface layer of the first well region; The transistor portion includes the one conductivity type region, a second well region of the opposite conductivity type formed in the one conductivity type region, and a source of the one conductivity type formed on the surface layer of the second well region. A region and a drain region, a channel region between the source region and the drain region, a gate electrode formed on the channel region via a gate insulating film, and a source region below the channel region. A high-concentration buried layer of the opposite conductivity type formed inside the second well region nearby, wherein the first well region and the second well region are connected to each other, and the connection region is A solid-state imaging device having an impurity concentration higher than that of the first and second well regions, wherein the impurity region and the drain region are connected. 2. An impurity of the same conductivity type as that of the first well region and the second well region is introduced into a connection region between the first well region and the second well region. The solid-state imaging device according to claim 1, wherein 3. The first well region and the second well region are formed such that their ends are overlapped with each other, and the connection region is formed by the first well region and the second well region. 2. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is an overlapping region with the well region. 4. The solid-state imaging device according to claim 1, wherein a plurality of the unit pixels are formed, and the device includes an element isolation region that separates the unit pixels adjacent to each other. . 5. The solid-state imaging device according to claim 4, wherein an element isolation insulating film is formed on the element isolation region so that the entire lower surface of the element isolation region is included. 6. The semiconductor device according to claim 6, wherein the impurity region or the drain region is formed to extend near the element isolation region.
The solid-state imaging device according to claim 4, wherein a drain electrode is formed near the element isolation region and connected to the impurity region or the drain region. 7. The insulated gate electric field, wherein the light receiving diode portion comprises a substrate of an opposite conductivity type semiconductor, a buried layer of one conductivity type, and a one conductivity type region in which the first well region is formed. The effect transistor section includes the substrate of the opposite conductivity type semiconductor, a semiconductor layer of the opposite conductivity type including a buried layer of the opposite conductivity type formed on the substrate, and the one conductivity type in which the second well region is formed. The solid-state imaging device according to claim 1, comprising a mold region. 8. The vicinity of the source region where the high-concentration buried layer is formed is a partial region in the channel length direction from the drain region to the source region and is closer to the source region. The solid-state imaging device according to claim 1. 9. The solid-state imaging device according to claim 1, wherein the high-concentration buried layer is formed over an entire region in a channel width direction. 10. A gate electrode of the insulated gate field effect transistor has a ring shape, the source region is formed in a surface layer of the well region surrounded by the gate electrode, and the drain region is connected to the gate electrode. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is formed on a surface layer of the well region so as to surround the solid-state imaging device. 11. The insulated gate field effect transistor has a low-concentration drain (LDD) structure, wherein the low-concentration drain region extends to have the same impurity concentration as the low-concentration drain region. The solid-state imaging device according to claim 1, wherein a region is formed. 12. The solid-state imaging device according to claim 1, wherein a gate electrode of the insulated gate field effect transistor and its periphery are shielded from light. 13. The source follower circuit according to claim 1, wherein a load circuit is connected to a source region of said insulated gate field effect transistor.
The solid-state imaging device according to any one of the above. 14. The solid-state imaging device according to claim 13, wherein a source output of said source follower circuit is connected to a video signal output terminal. 15. A solid-state imaging device comprising the solid-state imaging device according to claim 1. Description: 16. A step of introducing an impurity of the opposite conductivity type into the one conductivity type region of the surface layer of the semiconductor substrate using the first mask to form a first well region of the opposite conductivity type in the surface layer of the one conductivity type region. An impurity of an opposite conductivity type is introduced into a surface layer of the one conductivity type region by a second mask having an opening formed so that an opening end overlaps with an end of the first well region; A second well region of the opposite conductivity type is formed so as to overlap an end portion of the region, and an overlap region having an impurity concentration higher than that of the first well region and the second well region is formed. A step of introducing one conductivity type impurity into a surface layer of the second well region by the second mask to form a channel doping layer of one conductivity type; and a step of forming the second well region by a third mask. Opposite conductive inside Forming a high-concentration buried layer having an impurity concentration higher than that of the second well region and having the opposite conductivity type inside the second well region below the channel dope layer; Forming a gate insulating film by thermally oxidizing a surface of the semiconductor substrate; and forming the gate insulating film so as to cover the high-concentration buried layer and so that the high-concentration buried layer is close to the source region side. Forming a gate electrode on the film, introducing one conductivity type impurity into the surface layer of the semiconductor substrate, and forming one conductivity type source region and drain region in the second well region surface layer on both sides of the gate electrode. Forming a one conductivity type impurity region in the surface layer of the first well region at the same time as the formation. 17. A step of introducing an impurity of an opposite conductivity type into a region of one conductivity type of a surface layer of a semiconductor substrate by using a first mask to form a first well region of an opposite conductivity type in a surface layer of the one conductivity type region. A step of introducing an impurity of the opposite conductivity type into the surface layer of the one conductivity type region using a second mask to form a second well region of the opposite conductivity type; and the first well region and the second well region Forming an opposite conductivity type connection region having an impurity concentration higher than that of the first well region and the second well region in a region between the first well region and the second well region. Connecting a region, introducing a one-conductivity-type impurity into a surface layer of the second well region by using the second mask, and forming a one-conductivity-type channel dope layer; Inside the second well area Introducing an impurity of the opposite conductivity type to form a high-concentration buried layer having an impurity concentration higher than that of the second well region and of the opposite conductivity type inside the second well region below the channel dope layer. Forming a gate insulating film by thermally oxidizing a surface of the semiconductor substrate; and covering the high-concentration buried layer so that the high-concentration buried layer is close to the source region side. Forming a gate electrode on a gate insulating film; introducing one conductivity type impurity into a surface layer of the semiconductor substrate; and forming a source region and a drain of one conductivity type on a surface layer of a second well region on both sides of the gate electrode. Forming a region and simultaneously forming an impurity region of one conductivity type in a surface layer of the first well region.